1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/interrupt.h> 15 16 #include "util.h" 17 18 #define RTW_MAX_MAC_ID_NUM 32 19 #define RTW_MAX_SEC_CAM_NUM 32 20 #define MAX_PG_CAM_BACKUP_NUM 8 21 22 #define RTW_MAX_PATTERN_NUM 12 23 #define RTW_MAX_PATTERN_MASK_SIZE 16 24 #define RTW_MAX_PATTERN_SIZE 128 25 26 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 27 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 #define TX_PAGE_SIZE_SHIFT 7 31 32 #define RTW_CHANNEL_WIDTH_MAX 3 33 #define RTW_RF_PATH_MAX 4 34 #define HW_FEATURE_LEN 13 35 36 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 37 38 extern bool rtw_bf_support; 39 extern unsigned int rtw_fw_lps_deep_mode; 40 extern unsigned int rtw_debug_mask; 41 extern const struct ieee80211_ops rtw_ops; 42 extern struct rtw_chip_info rtw8822b_hw_spec; 43 extern struct rtw_chip_info rtw8822c_hw_spec; 44 45 #define RTW_MAX_CHANNEL_NUM_2G 14 46 #define RTW_MAX_CHANNEL_NUM_5G 49 47 48 struct rtw_dev; 49 50 enum rtw_hci_type { 51 RTW_HCI_TYPE_PCIE, 52 RTW_HCI_TYPE_USB, 53 RTW_HCI_TYPE_SDIO, 54 55 RTW_HCI_TYPE_UNDEFINE, 56 }; 57 58 struct rtw_hci { 59 struct rtw_hci_ops *ops; 60 enum rtw_hci_type type; 61 62 u32 rpwm_addr; 63 u32 cpwm_addr; 64 65 u8 bulkout_num; 66 }; 67 68 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 69 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 70 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 71 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 72 73 #define IS_CH_5G_BAND_MID(channel) \ 74 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 75 76 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 77 #define IS_CH_5G_BAND(channel) \ 78 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 79 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 80 81 enum rtw_supported_band { 82 RTW_BAND_2G = 1 << 0, 83 RTW_BAND_5G = 1 << 1, 84 RTW_BAND_60G = 1 << 2, 85 86 RTW_BAND_MAX, 87 }; 88 89 /* now, support upto 80M bw */ 90 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 91 92 enum rtw_bandwidth { 93 RTW_CHANNEL_WIDTH_20 = 0, 94 RTW_CHANNEL_WIDTH_40 = 1, 95 RTW_CHANNEL_WIDTH_80 = 2, 96 RTW_CHANNEL_WIDTH_160 = 3, 97 RTW_CHANNEL_WIDTH_80_80 = 4, 98 RTW_CHANNEL_WIDTH_5 = 5, 99 RTW_CHANNEL_WIDTH_10 = 6, 100 }; 101 102 enum rtw_net_type { 103 RTW_NET_NO_LINK = 0, 104 RTW_NET_AD_HOC = 1, 105 RTW_NET_MGD_LINKED = 2, 106 RTW_NET_AP_MODE = 3, 107 }; 108 109 enum rtw_rf_type { 110 RF_1T1R = 0, 111 RF_1T2R = 1, 112 RF_2T2R = 2, 113 RF_2T3R = 3, 114 RF_2T4R = 4, 115 RF_3T3R = 5, 116 RF_3T4R = 6, 117 RF_4T4R = 7, 118 RF_TYPE_MAX, 119 }; 120 121 enum rtw_rf_path { 122 RF_PATH_A = 0, 123 RF_PATH_B = 1, 124 RF_PATH_C = 2, 125 RF_PATH_D = 3, 126 }; 127 128 enum rtw_bb_path { 129 BB_PATH_A = BIT(0), 130 BB_PATH_B = BIT(1), 131 BB_PATH_C = BIT(2), 132 BB_PATH_D = BIT(3), 133 134 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 135 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 136 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 137 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 138 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 139 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 140 141 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 142 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 143 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 144 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 145 146 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 147 }; 148 149 enum rtw_rate_section { 150 RTW_RATE_SECTION_CCK = 0, 151 RTW_RATE_SECTION_OFDM, 152 RTW_RATE_SECTION_HT_1S, 153 RTW_RATE_SECTION_HT_2S, 154 RTW_RATE_SECTION_VHT_1S, 155 RTW_RATE_SECTION_VHT_2S, 156 157 /* keep last */ 158 RTW_RATE_SECTION_MAX, 159 }; 160 161 enum rtw_wireless_set { 162 WIRELESS_CCK = 0x00000001, 163 WIRELESS_OFDM = 0x00000002, 164 WIRELESS_HT = 0x00000004, 165 WIRELESS_VHT = 0x00000008, 166 }; 167 168 #define HT_STBC_EN BIT(0) 169 #define VHT_STBC_EN BIT(1) 170 #define HT_LDPC_EN BIT(0) 171 #define VHT_LDPC_EN BIT(1) 172 173 enum rtw_chip_type { 174 RTW_CHIP_TYPE_8822B, 175 RTW_CHIP_TYPE_8822C, 176 }; 177 178 enum rtw_tx_queue_type { 179 /* the order of AC queues matters */ 180 RTW_TX_QUEUE_BK = 0x0, 181 RTW_TX_QUEUE_BE = 0x1, 182 RTW_TX_QUEUE_VI = 0x2, 183 RTW_TX_QUEUE_VO = 0x3, 184 185 RTW_TX_QUEUE_BCN = 0x4, 186 RTW_TX_QUEUE_MGMT = 0x5, 187 RTW_TX_QUEUE_HI0 = 0x6, 188 RTW_TX_QUEUE_H2C = 0x7, 189 /* keep it last */ 190 RTK_MAX_TX_QUEUE_NUM 191 }; 192 193 enum rtw_rx_queue_type { 194 RTW_RX_QUEUE_MPDU = 0x0, 195 RTW_RX_QUEUE_C2H = 0x1, 196 /* keep it last */ 197 RTK_MAX_RX_QUEUE_NUM 198 }; 199 200 enum rtw_fw_type { 201 RTW_NORMAL_FW = 0x0, 202 RTW_WOWLAN_FW = 0x1, 203 }; 204 205 enum rtw_rate_index { 206 RTW_RATEID_BGN_40M_2SS = 0, 207 RTW_RATEID_BGN_40M_1SS = 1, 208 RTW_RATEID_BGN_20M_2SS = 2, 209 RTW_RATEID_BGN_20M_1SS = 3, 210 RTW_RATEID_GN_N2SS = 4, 211 RTW_RATEID_GN_N1SS = 5, 212 RTW_RATEID_BG = 6, 213 RTW_RATEID_G = 7, 214 RTW_RATEID_B_20M = 8, 215 RTW_RATEID_ARFR0_AC_2SS = 9, 216 RTW_RATEID_ARFR1_AC_1SS = 10, 217 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 218 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 219 RTW_RATEID_ARFR4_AC_3SS = 13, 220 RTW_RATEID_ARFR5_N_3SS = 14, 221 RTW_RATEID_ARFR7_N_4SS = 15, 222 RTW_RATEID_ARFR6_AC_4SS = 16 223 }; 224 225 enum rtw_trx_desc_rate { 226 DESC_RATE1M = 0x00, 227 DESC_RATE2M = 0x01, 228 DESC_RATE5_5M = 0x02, 229 DESC_RATE11M = 0x03, 230 231 DESC_RATE6M = 0x04, 232 DESC_RATE9M = 0x05, 233 DESC_RATE12M = 0x06, 234 DESC_RATE18M = 0x07, 235 DESC_RATE24M = 0x08, 236 DESC_RATE36M = 0x09, 237 DESC_RATE48M = 0x0a, 238 DESC_RATE54M = 0x0b, 239 240 DESC_RATEMCS0 = 0x0c, 241 DESC_RATEMCS1 = 0x0d, 242 DESC_RATEMCS2 = 0x0e, 243 DESC_RATEMCS3 = 0x0f, 244 DESC_RATEMCS4 = 0x10, 245 DESC_RATEMCS5 = 0x11, 246 DESC_RATEMCS6 = 0x12, 247 DESC_RATEMCS7 = 0x13, 248 DESC_RATEMCS8 = 0x14, 249 DESC_RATEMCS9 = 0x15, 250 DESC_RATEMCS10 = 0x16, 251 DESC_RATEMCS11 = 0x17, 252 DESC_RATEMCS12 = 0x18, 253 DESC_RATEMCS13 = 0x19, 254 DESC_RATEMCS14 = 0x1a, 255 DESC_RATEMCS15 = 0x1b, 256 DESC_RATEMCS16 = 0x1c, 257 DESC_RATEMCS17 = 0x1d, 258 DESC_RATEMCS18 = 0x1e, 259 DESC_RATEMCS19 = 0x1f, 260 DESC_RATEMCS20 = 0x20, 261 DESC_RATEMCS21 = 0x21, 262 DESC_RATEMCS22 = 0x22, 263 DESC_RATEMCS23 = 0x23, 264 DESC_RATEMCS24 = 0x24, 265 DESC_RATEMCS25 = 0x25, 266 DESC_RATEMCS26 = 0x26, 267 DESC_RATEMCS27 = 0x27, 268 DESC_RATEMCS28 = 0x28, 269 DESC_RATEMCS29 = 0x29, 270 DESC_RATEMCS30 = 0x2a, 271 DESC_RATEMCS31 = 0x2b, 272 273 DESC_RATEVHT1SS_MCS0 = 0x2c, 274 DESC_RATEVHT1SS_MCS1 = 0x2d, 275 DESC_RATEVHT1SS_MCS2 = 0x2e, 276 DESC_RATEVHT1SS_MCS3 = 0x2f, 277 DESC_RATEVHT1SS_MCS4 = 0x30, 278 DESC_RATEVHT1SS_MCS5 = 0x31, 279 DESC_RATEVHT1SS_MCS6 = 0x32, 280 DESC_RATEVHT1SS_MCS7 = 0x33, 281 DESC_RATEVHT1SS_MCS8 = 0x34, 282 DESC_RATEVHT1SS_MCS9 = 0x35, 283 284 DESC_RATEVHT2SS_MCS0 = 0x36, 285 DESC_RATEVHT2SS_MCS1 = 0x37, 286 DESC_RATEVHT2SS_MCS2 = 0x38, 287 DESC_RATEVHT2SS_MCS3 = 0x39, 288 DESC_RATEVHT2SS_MCS4 = 0x3a, 289 DESC_RATEVHT2SS_MCS5 = 0x3b, 290 DESC_RATEVHT2SS_MCS6 = 0x3c, 291 DESC_RATEVHT2SS_MCS7 = 0x3d, 292 DESC_RATEVHT2SS_MCS8 = 0x3e, 293 DESC_RATEVHT2SS_MCS9 = 0x3f, 294 295 DESC_RATEVHT3SS_MCS0 = 0x40, 296 DESC_RATEVHT3SS_MCS1 = 0x41, 297 DESC_RATEVHT3SS_MCS2 = 0x42, 298 DESC_RATEVHT3SS_MCS3 = 0x43, 299 DESC_RATEVHT3SS_MCS4 = 0x44, 300 DESC_RATEVHT3SS_MCS5 = 0x45, 301 DESC_RATEVHT3SS_MCS6 = 0x46, 302 DESC_RATEVHT3SS_MCS7 = 0x47, 303 DESC_RATEVHT3SS_MCS8 = 0x48, 304 DESC_RATEVHT3SS_MCS9 = 0x49, 305 306 DESC_RATEVHT4SS_MCS0 = 0x4a, 307 DESC_RATEVHT4SS_MCS1 = 0x4b, 308 DESC_RATEVHT4SS_MCS2 = 0x4c, 309 DESC_RATEVHT4SS_MCS3 = 0x4d, 310 DESC_RATEVHT4SS_MCS4 = 0x4e, 311 DESC_RATEVHT4SS_MCS5 = 0x4f, 312 DESC_RATEVHT4SS_MCS6 = 0x50, 313 DESC_RATEVHT4SS_MCS7 = 0x51, 314 DESC_RATEVHT4SS_MCS8 = 0x52, 315 DESC_RATEVHT4SS_MCS9 = 0x53, 316 317 DESC_RATE_MAX, 318 }; 319 320 enum rtw_regulatory_domains { 321 RTW_REGD_FCC = 0, 322 RTW_REGD_MKK = 1, 323 RTW_REGD_ETSI = 2, 324 RTW_REGD_IC = 3, 325 RTW_REGD_KCC = 4, 326 RTW_REGD_ACMA = 5, 327 RTW_REGD_CHILE = 6, 328 RTW_REGD_UKRAINE = 7, 329 RTW_REGD_MEXICO = 8, 330 RTW_REGD_WW, 331 332 RTW_REGD_MAX 333 }; 334 335 enum rtw_txq_flags { 336 RTW_TXQ_AMPDU, 337 RTW_TXQ_BLOCK_BA, 338 }; 339 340 enum rtw_flags { 341 RTW_FLAG_RUNNING, 342 RTW_FLAG_FW_RUNNING, 343 RTW_FLAG_SCANNING, 344 RTW_FLAG_INACTIVE_PS, 345 RTW_FLAG_LEISURE_PS, 346 RTW_FLAG_LEISURE_PS_DEEP, 347 RTW_FLAG_DIG_DISABLE, 348 RTW_FLAG_BUSY_TRAFFIC, 349 RTW_FLAG_WOWLAN, 350 351 NUM_OF_RTW_FLAGS, 352 }; 353 354 enum rtw_evm { 355 RTW_EVM_OFDM = 0, 356 RTW_EVM_1SS, 357 RTW_EVM_2SS_A, 358 RTW_EVM_2SS_B, 359 /* keep it last */ 360 RTW_EVM_NUM 361 }; 362 363 enum rtw_snr { 364 RTW_SNR_OFDM_A = 0, 365 RTW_SNR_OFDM_B, 366 RTW_SNR_OFDM_C, 367 RTW_SNR_OFDM_D, 368 RTW_SNR_1SS_A, 369 RTW_SNR_1SS_B, 370 RTW_SNR_1SS_C, 371 RTW_SNR_1SS_D, 372 RTW_SNR_2SS_A, 373 RTW_SNR_2SS_B, 374 RTW_SNR_2SS_C, 375 RTW_SNR_2SS_D, 376 /* keep it last */ 377 RTW_SNR_NUM 378 }; 379 380 enum rtw_wow_flags { 381 RTW_WOW_FLAG_EN_MAGIC_PKT, 382 RTW_WOW_FLAG_EN_REKEY_PKT, 383 RTW_WOW_FLAG_EN_DISCONNECT, 384 385 /* keep it last */ 386 RTW_WOW_FLAG_MAX, 387 }; 388 389 /* the power index is represented by differences, which cck-1s & ht40-1s are 390 * the base values, so for 1s's differences, there are only ht20 & ofdm 391 */ 392 struct rtw_2g_1s_pwr_idx_diff { 393 #ifdef __LITTLE_ENDIAN 394 s8 ofdm:4; 395 s8 bw20:4; 396 #else 397 s8 bw20:4; 398 s8 ofdm:4; 399 #endif 400 } __packed; 401 402 struct rtw_2g_ns_pwr_idx_diff { 403 #ifdef __LITTLE_ENDIAN 404 s8 bw20:4; 405 s8 bw40:4; 406 s8 cck:4; 407 s8 ofdm:4; 408 #else 409 s8 ofdm:4; 410 s8 cck:4; 411 s8 bw40:4; 412 s8 bw20:4; 413 #endif 414 } __packed; 415 416 struct rtw_2g_txpwr_idx { 417 u8 cck_base[6]; 418 u8 bw40_base[5]; 419 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 420 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 421 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 422 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 423 }; 424 425 struct rtw_5g_ht_1s_pwr_idx_diff { 426 #ifdef __LITTLE_ENDIAN 427 s8 ofdm:4; 428 s8 bw20:4; 429 #else 430 s8 bw20:4; 431 s8 ofdm:4; 432 #endif 433 } __packed; 434 435 struct rtw_5g_ht_ns_pwr_idx_diff { 436 #ifdef __LITTLE_ENDIAN 437 s8 bw20:4; 438 s8 bw40:4; 439 #else 440 s8 bw40:4; 441 s8 bw20:4; 442 #endif 443 } __packed; 444 445 struct rtw_5g_ofdm_ns_pwr_idx_diff { 446 #ifdef __LITTLE_ENDIAN 447 s8 ofdm_3s:4; 448 s8 ofdm_2s:4; 449 s8 ofdm_4s:4; 450 s8 res:4; 451 #else 452 s8 res:4; 453 s8 ofdm_4s:4; 454 s8 ofdm_2s:4; 455 s8 ofdm_3s:4; 456 #endif 457 } __packed; 458 459 struct rtw_5g_vht_ns_pwr_idx_diff { 460 #ifdef __LITTLE_ENDIAN 461 s8 bw160:4; 462 s8 bw80:4; 463 #else 464 s8 bw80:4; 465 s8 bw160:4; 466 #endif 467 } __packed; 468 469 struct rtw_5g_txpwr_idx { 470 u8 bw40_base[14]; 471 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 472 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 473 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 474 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 475 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 476 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 477 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 478 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 479 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 480 }; 481 482 struct rtw_txpwr_idx { 483 struct rtw_2g_txpwr_idx pwr_idx_2g; 484 struct rtw_5g_txpwr_idx pwr_idx_5g; 485 }; 486 487 struct rtw_timer_list { 488 struct timer_list timer; 489 void (*function)(void *data); 490 void *args; 491 }; 492 493 struct rtw_channel_params { 494 u8 center_chan; 495 u8 bandwidth; 496 u8 primary_chan_idx; 497 /* center channel by different available bandwidth, 498 * val of (bw > current bandwidth) is invalid 499 */ 500 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 501 }; 502 503 struct rtw_hw_reg { 504 u32 addr; 505 u32 mask; 506 }; 507 508 struct rtw_backup_info { 509 u8 len; 510 u32 reg; 511 u32 val; 512 }; 513 514 enum rtw_vif_port_set { 515 PORT_SET_MAC_ADDR = BIT(0), 516 PORT_SET_BSSID = BIT(1), 517 PORT_SET_NET_TYPE = BIT(2), 518 PORT_SET_AID = BIT(3), 519 PORT_SET_BCN_CTRL = BIT(4), 520 }; 521 522 struct rtw_vif_port { 523 struct rtw_hw_reg mac_addr; 524 struct rtw_hw_reg bssid; 525 struct rtw_hw_reg net_type; 526 struct rtw_hw_reg aid; 527 struct rtw_hw_reg bcn_ctrl; 528 }; 529 530 struct rtw_tx_pkt_info { 531 u32 tx_pkt_size; 532 u8 offset; 533 u8 pkt_offset; 534 u8 mac_id; 535 u8 rate_id; 536 u8 rate; 537 u8 qsel; 538 u8 bw; 539 u8 sec_type; 540 u8 sn; 541 bool ampdu_en; 542 u8 ampdu_factor; 543 u8 ampdu_density; 544 u16 seq; 545 bool stbc; 546 bool ldpc; 547 bool dis_rate_fallback; 548 bool bmc; 549 bool use_rate; 550 bool ls; 551 bool fs; 552 bool short_gi; 553 bool report; 554 bool rts; 555 }; 556 557 struct rtw_rx_pkt_stat { 558 bool phy_status; 559 bool icv_err; 560 bool crc_err; 561 bool decrypted; 562 bool is_c2h; 563 564 s32 signal_power; 565 u16 pkt_len; 566 u8 bw; 567 u8 drv_info_sz; 568 u8 shift; 569 u8 rate; 570 u8 mac_id; 571 u8 cam_id; 572 u8 ppdu_cnt; 573 u32 tsf_low; 574 s8 rx_power[RTW_RF_PATH_MAX]; 575 u8 rssi; 576 u8 rxsc; 577 s8 rx_snr[RTW_RF_PATH_MAX]; 578 u8 rx_evm[RTW_RF_PATH_MAX]; 579 s8 cfo_tail[RTW_RF_PATH_MAX]; 580 581 struct rtw_sta_info *si; 582 struct ieee80211_vif *vif; 583 }; 584 585 DECLARE_EWMA(tp, 10, 2); 586 587 struct rtw_traffic_stats { 588 /* units in bytes */ 589 u64 tx_unicast; 590 u64 rx_unicast; 591 592 /* count for packets */ 593 u64 tx_cnt; 594 u64 rx_cnt; 595 596 /* units in Mbps */ 597 u32 tx_throughput; 598 u32 rx_throughput; 599 struct ewma_tp tx_ewma_tp; 600 struct ewma_tp rx_ewma_tp; 601 }; 602 603 enum rtw_lps_mode { 604 RTW_MODE_ACTIVE = 0, 605 RTW_MODE_LPS = 1, 606 RTW_MODE_WMM_PS = 2, 607 }; 608 609 enum rtw_lps_deep_mode { 610 LPS_DEEP_MODE_NONE = 0, 611 LPS_DEEP_MODE_LCLK = 1, 612 LPS_DEEP_MODE_PG = 2, 613 }; 614 615 enum rtw_pwr_state { 616 RTW_RF_OFF = 0x0, 617 RTW_RF_ON = 0x4, 618 RTW_ALL_ON = 0xc, 619 }; 620 621 struct rtw_lps_conf { 622 enum rtw_lps_mode mode; 623 enum rtw_lps_deep_mode deep_mode; 624 enum rtw_pwr_state state; 625 u8 awake_interval; 626 u8 rlbm; 627 u8 smart_ps; 628 u8 port_id; 629 bool sec_cam_backup; 630 bool pattern_cam_backup; 631 }; 632 633 enum rtw_hw_key_type { 634 RTW_CAM_NONE = 0, 635 RTW_CAM_WEP40 = 1, 636 RTW_CAM_TKIP = 2, 637 RTW_CAM_AES = 4, 638 RTW_CAM_WEP104 = 5, 639 }; 640 641 struct rtw_cam_entry { 642 bool valid; 643 bool group; 644 u8 addr[ETH_ALEN]; 645 u8 hw_key_type; 646 struct ieee80211_key_conf *key; 647 }; 648 649 struct rtw_sec_desc { 650 /* search strategy */ 651 bool default_key_search; 652 653 u32 total_cam_num; 654 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 655 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 656 }; 657 658 struct rtw_tx_report { 659 /* protect the tx report queue */ 660 spinlock_t q_lock; 661 struct sk_buff_head queue; 662 atomic_t sn; 663 struct timer_list purge_timer; 664 }; 665 666 struct rtw_ra_report { 667 struct rate_info txrate; 668 u32 bit_rate; 669 u8 desc_rate; 670 }; 671 672 struct rtw_txq { 673 struct list_head list; 674 675 unsigned long flags; 676 unsigned long last_push; 677 }; 678 679 #define RTW_BC_MC_MACID 1 680 DECLARE_EWMA(rssi, 10, 16); 681 682 struct rtw_sta_info { 683 struct ieee80211_sta *sta; 684 struct ieee80211_vif *vif; 685 686 struct ewma_rssi avg_rssi; 687 u8 rssi_level; 688 689 u8 mac_id; 690 u8 rate_id; 691 enum rtw_bandwidth bw_mode; 692 enum rtw_rf_type rf_type; 693 enum rtw_wireless_set wireless_set; 694 u8 stbc_en:2; 695 u8 ldpc_en:2; 696 bool sgi_enable; 697 bool vht_enable; 698 bool updated; 699 u8 init_ra_lv; 700 u64 ra_mask; 701 702 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 703 704 struct rtw_ra_report ra_report; 705 706 bool use_cfg_mask; 707 struct cfg80211_bitrate_mask *mask; 708 }; 709 710 enum rtw_bfee_role { 711 RTW_BFEE_NONE, 712 RTW_BFEE_SU, 713 RTW_BFEE_MU 714 }; 715 716 struct rtw_bfee { 717 enum rtw_bfee_role role; 718 719 u16 p_aid; 720 u8 g_id; 721 u8 mac_addr[ETH_ALEN]; 722 u8 sound_dim; 723 724 /* SU-MIMO */ 725 u8 su_reg_index; 726 727 /* MU-MIMO */ 728 u16 aid; 729 }; 730 731 struct rtw_bf_info { 732 u8 bfer_mu_cnt; 733 u8 bfer_su_cnt; 734 DECLARE_BITMAP(bfer_su_reg_maping, 2); 735 u8 cur_csi_rpt_rate; 736 }; 737 738 struct rtw_vif { 739 enum rtw_net_type net_type; 740 u16 aid; 741 u8 mac_addr[ETH_ALEN]; 742 u8 bssid[ETH_ALEN]; 743 u8 port; 744 u8 bcn_ctrl; 745 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 746 const struct rtw_vif_port *conf; 747 748 struct rtw_traffic_stats stats; 749 750 struct rtw_bfee bfee; 751 }; 752 753 struct rtw_regulatory { 754 char alpha2[2]; 755 u8 chplan; 756 u8 txpwr_regd; 757 }; 758 759 struct rtw_chip_ops { 760 int (*mac_init)(struct rtw_dev *rtwdev); 761 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 762 void (*phy_set_param)(struct rtw_dev *rtwdev); 763 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 764 u8 bandwidth, u8 primary_chan_idx); 765 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 766 struct rtw_rx_pkt_stat *pkt_stat, 767 struct ieee80211_rx_status *rx_status); 768 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 769 u32 addr, u32 mask); 770 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 771 u32 addr, u32 mask, u32 data); 772 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 773 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 774 u32 size); 775 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx, 776 u8 antenna_rx); 777 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 778 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 779 void (*phy_calibration)(struct rtw_dev *rtwdev); 780 void (*dpk_track)(struct rtw_dev *rtwdev); 781 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 782 void (*pwr_track)(struct rtw_dev *rtwdev); 783 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 784 struct rtw_bfee *bfee, bool enable); 785 void (*set_gid_table)(struct rtw_dev *rtwdev, 786 struct ieee80211_vif *vif, 787 struct ieee80211_bss_conf *conf); 788 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 789 u8 fixrate_en, u8 *new_rate); 790 791 /* for coex */ 792 void (*coex_set_init)(struct rtw_dev *rtwdev); 793 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 794 u8 ctrl_type, u8 pos_type); 795 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 796 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 797 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 798 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 799 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 800 }; 801 802 #define RTW_PWR_POLLING_CNT 20000 803 804 #define RTW_PWR_CMD_READ 0x00 805 #define RTW_PWR_CMD_WRITE 0x01 806 #define RTW_PWR_CMD_POLLING 0x02 807 #define RTW_PWR_CMD_DELAY 0x03 808 #define RTW_PWR_CMD_END 0x04 809 810 /* define the base address of each block */ 811 #define RTW_PWR_ADDR_MAC 0x00 812 #define RTW_PWR_ADDR_USB 0x01 813 #define RTW_PWR_ADDR_PCIE 0x02 814 #define RTW_PWR_ADDR_SDIO 0x03 815 816 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 817 #define RTW_PWR_INTF_USB_MSK BIT(1) 818 #define RTW_PWR_INTF_PCI_MSK BIT(2) 819 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 820 821 #define RTW_PWR_CUT_A_MSK BIT(1) 822 #define RTW_PWR_CUT_B_MSK BIT(2) 823 #define RTW_PWR_CUT_C_MSK BIT(3) 824 #define RTW_PWR_CUT_D_MSK BIT(4) 825 #define RTW_PWR_CUT_E_MSK BIT(5) 826 #define RTW_PWR_CUT_F_MSK BIT(6) 827 #define RTW_PWR_CUT_G_MSK BIT(7) 828 #define RTW_PWR_CUT_ALL_MSK 0xFF 829 830 enum rtw_pwr_seq_cmd_delay_unit { 831 RTW_PWR_DELAY_US, 832 RTW_PWR_DELAY_MS, 833 }; 834 835 struct rtw_pwr_seq_cmd { 836 u16 offset; 837 u8 cut_mask; 838 u8 intf_mask; 839 u8 base:4; 840 u8 cmd:4; 841 u8 mask; 842 u8 value; 843 }; 844 845 enum rtw_chip_ver { 846 RTW_CHIP_VER_CUT_A = 0x00, 847 RTW_CHIP_VER_CUT_B = 0x01, 848 RTW_CHIP_VER_CUT_C = 0x02, 849 RTW_CHIP_VER_CUT_D = 0x03, 850 RTW_CHIP_VER_CUT_E = 0x04, 851 RTW_CHIP_VER_CUT_F = 0x05, 852 RTW_CHIP_VER_CUT_G = 0x06, 853 }; 854 855 #define RTW_INTF_PHY_PLATFORM_ALL 0 856 857 enum rtw_intf_phy_cut { 858 RTW_INTF_PHY_CUT_A = BIT(0), 859 RTW_INTF_PHY_CUT_B = BIT(1), 860 RTW_INTF_PHY_CUT_C = BIT(2), 861 RTW_INTF_PHY_CUT_D = BIT(3), 862 RTW_INTF_PHY_CUT_E = BIT(4), 863 RTW_INTF_PHY_CUT_F = BIT(5), 864 RTW_INTF_PHY_CUT_G = BIT(6), 865 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 866 }; 867 868 enum rtw_ip_sel { 869 RTW_IP_SEL_PHY = 0, 870 RTW_IP_SEL_MAC = 1, 871 RTW_IP_SEL_DBI = 2, 872 873 RTW_IP_SEL_UNDEF = 0xFFFF 874 }; 875 876 enum rtw_pq_map_id { 877 RTW_PQ_MAP_VO = 0x0, 878 RTW_PQ_MAP_VI = 0x1, 879 RTW_PQ_MAP_BE = 0x2, 880 RTW_PQ_MAP_BK = 0x3, 881 RTW_PQ_MAP_MG = 0x4, 882 RTW_PQ_MAP_HI = 0x5, 883 RTW_PQ_MAP_NUM = 0x6, 884 885 RTW_PQ_MAP_UNDEF, 886 }; 887 888 enum rtw_dma_mapping { 889 RTW_DMA_MAPPING_EXTRA = 0, 890 RTW_DMA_MAPPING_LOW = 1, 891 RTW_DMA_MAPPING_NORMAL = 2, 892 RTW_DMA_MAPPING_HIGH = 3, 893 894 RTW_DMA_MAPPING_MAX, 895 RTW_DMA_MAPPING_UNDEF, 896 }; 897 898 struct rtw_rqpn { 899 enum rtw_dma_mapping dma_map_vo; 900 enum rtw_dma_mapping dma_map_vi; 901 enum rtw_dma_mapping dma_map_be; 902 enum rtw_dma_mapping dma_map_bk; 903 enum rtw_dma_mapping dma_map_mg; 904 enum rtw_dma_mapping dma_map_hi; 905 }; 906 907 struct rtw_page_table { 908 u16 hq_num; 909 u16 nq_num; 910 u16 lq_num; 911 u16 exq_num; 912 u16 gapq_num; 913 }; 914 915 struct rtw_intf_phy_para { 916 u16 offset; 917 u16 value; 918 u16 ip_sel; 919 u16 cut_mask; 920 u16 platform; 921 }; 922 923 struct rtw_wow_pattern { 924 u16 crc; 925 u8 type; 926 u8 valid; 927 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 928 }; 929 930 struct rtw_pno_request { 931 bool inited; 932 u32 match_set_cnt; 933 struct cfg80211_match_set *match_sets; 934 u8 channel_cnt; 935 struct ieee80211_channel *channels; 936 struct cfg80211_sched_scan_plan scan_plan; 937 }; 938 939 struct rtw_wow_param { 940 struct ieee80211_vif *wow_vif; 941 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 942 u8 txpause; 943 u8 pattern_cnt; 944 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 945 946 bool ips_enabled; 947 struct rtw_pno_request pno_req; 948 }; 949 950 struct rtw_intf_phy_para_table { 951 struct rtw_intf_phy_para *usb2_para; 952 struct rtw_intf_phy_para *usb3_para; 953 struct rtw_intf_phy_para *gen1_para; 954 struct rtw_intf_phy_para *gen2_para; 955 u8 n_usb2_para; 956 u8 n_usb3_para; 957 u8 n_gen1_para; 958 u8 n_gen2_para; 959 }; 960 961 struct rtw_table { 962 const void *data; 963 const u32 size; 964 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 965 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 966 u32 addr, u32 data); 967 enum rtw_rf_path rf_path; 968 }; 969 970 static inline void rtw_load_table(struct rtw_dev *rtwdev, 971 const struct rtw_table *tbl) 972 { 973 (*tbl->parse)(rtwdev, tbl); 974 } 975 976 enum rtw_rfe_fem { 977 RTW_RFE_IFEM, 978 RTW_RFE_EFEM, 979 RTW_RFE_IFEM2G_EFEM5G, 980 RTW_RFE_NUM, 981 }; 982 983 struct rtw_rfe_def { 984 const struct rtw_table *phy_pg_tbl; 985 const struct rtw_table *txpwr_lmt_tbl; 986 }; 987 988 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 989 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 990 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 991 } 992 993 #define RTW_PWR_TRK_5G_1 0 994 #define RTW_PWR_TRK_5G_2 1 995 #define RTW_PWR_TRK_5G_3 2 996 #define RTW_PWR_TRK_5G_NUM 3 997 998 #define RTW_PWR_TRK_TBL_SZ 30 999 1000 /* This table stores the values of TX power that will be adjusted by power 1001 * tracking. 1002 * 1003 * For 5G bands, there are 3 different settings. 1004 * For 2G there are cck rate and ofdm rate with different settings. 1005 */ 1006 struct rtw_pwr_track_tbl { 1007 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1008 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1009 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1010 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1011 const u8 *pwrtrk_2gb_n; 1012 const u8 *pwrtrk_2gb_p; 1013 const u8 *pwrtrk_2ga_n; 1014 const u8 *pwrtrk_2ga_p; 1015 const u8 *pwrtrk_2g_cckb_n; 1016 const u8 *pwrtrk_2g_cckb_p; 1017 const u8 *pwrtrk_2g_ccka_n; 1018 const u8 *pwrtrk_2g_ccka_p; 1019 }; 1020 1021 /* hardware configuration for each IC */ 1022 struct rtw_chip_info { 1023 struct rtw_chip_ops *ops; 1024 u8 id; 1025 1026 const char *fw_name; 1027 u8 tx_pkt_desc_sz; 1028 u8 tx_buf_desc_sz; 1029 u8 rx_pkt_desc_sz; 1030 u8 rx_buf_desc_sz; 1031 u32 phy_efuse_size; 1032 u32 log_efuse_size; 1033 u32 ptct_efuse_size; 1034 u32 txff_size; 1035 u32 rxff_size; 1036 u8 band; 1037 u8 page_size; 1038 u8 csi_buf_pg_num; 1039 u8 dig_max; 1040 u8 dig_min; 1041 u8 txgi_factor; 1042 bool is_pwr_by_rate_dec; 1043 u8 max_power_index; 1044 1045 bool ht_supported; 1046 bool vht_supported; 1047 u8 lps_deep_mode_supported; 1048 1049 /* init values */ 1050 u8 sys_func_en; 1051 struct rtw_pwr_seq_cmd **pwr_on_seq; 1052 struct rtw_pwr_seq_cmd **pwr_off_seq; 1053 struct rtw_rqpn *rqpn_table; 1054 struct rtw_page_table *page_table; 1055 struct rtw_intf_phy_para_table *intf_table; 1056 1057 struct rtw_hw_reg *dig; 1058 u32 rf_base_addr[2]; 1059 u32 rf_sipi_addr[2]; 1060 1061 const struct rtw_table *mac_tbl; 1062 const struct rtw_table *agc_tbl; 1063 const struct rtw_table *bb_tbl; 1064 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1065 const struct rtw_table *rfk_init_tbl; 1066 1067 const struct rtw_rfe_def *rfe_defs; 1068 u32 rfe_defs_size; 1069 1070 bool en_dis_dpd; 1071 u16 dpd_ratemask; 1072 u8 iqk_threshold; 1073 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1074 1075 u8 bfer_su_max_num; 1076 u8 bfer_mu_max_num; 1077 1078 const char *wow_fw_name; 1079 const struct wiphy_wowlan_support *wowlan_stub; 1080 const u8 max_sched_scan_ssids; 1081 1082 /* coex paras */ 1083 u32 coex_para_ver; 1084 u8 bt_desired_ver; 1085 bool scbd_support; 1086 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1087 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1088 u8 bt_rssi_type; 1089 u8 ant_isolation; 1090 u8 rssi_tolerance; 1091 u8 table_sant_num; 1092 u8 table_nsant_num; 1093 u8 tdma_sant_num; 1094 u8 tdma_nsant_num; 1095 u8 bt_afh_span_bw20; 1096 u8 bt_afh_span_bw40; 1097 u8 afh_5g_num; 1098 u8 wl_rf_para_num; 1099 const u8 *bt_rssi_step; 1100 const u8 *wl_rssi_step; 1101 const struct coex_table_para *table_nsant; 1102 const struct coex_table_para *table_sant; 1103 const struct coex_tdma_para *tdma_sant; 1104 const struct coex_tdma_para *tdma_nsant; 1105 const struct coex_rf_para *wl_rf_para_tx; 1106 const struct coex_rf_para *wl_rf_para_rx; 1107 const struct coex_5g_afh_map *afh_5g; 1108 }; 1109 1110 enum rtw_coex_bt_state_cnt { 1111 COEX_CNT_BT_RETRY, 1112 COEX_CNT_BT_REINIT, 1113 COEX_CNT_BT_REENABLE, 1114 COEX_CNT_BT_POPEVENT, 1115 COEX_CNT_BT_SETUPLINK, 1116 COEX_CNT_BT_IGNWLANACT, 1117 COEX_CNT_BT_INQ, 1118 COEX_CNT_BT_PAGE, 1119 COEX_CNT_BT_ROLESWITCH, 1120 COEX_CNT_BT_AFHUPDATE, 1121 COEX_CNT_BT_INFOUPDATE, 1122 COEX_CNT_BT_IQK, 1123 COEX_CNT_BT_IQKFAIL, 1124 1125 COEX_CNT_BT_MAX 1126 }; 1127 1128 enum rtw_coex_wl_state_cnt { 1129 COEX_CNT_WL_CONNPKT, 1130 COEX_CNT_WL_COEXRUN, 1131 COEX_CNT_WL_NOISY0, 1132 COEX_CNT_WL_NOISY1, 1133 COEX_CNT_WL_NOISY2, 1134 COEX_CNT_WL_5MS_NOEXTEND, 1135 COEX_CNT_WL_FW_NOTIFY, 1136 1137 COEX_CNT_WL_MAX 1138 }; 1139 1140 struct rtw_coex_rfe { 1141 bool ant_switch_exist; 1142 bool ant_switch_diversity; 1143 bool ant_switch_with_bt; 1144 u8 rfe_module_type; 1145 u8 ant_switch_polarity; 1146 1147 /* true if WLG at BTG, else at WLAG */ 1148 bool wlg_at_btg; 1149 }; 1150 1151 struct rtw_coex_dm { 1152 bool cur_ps_tdma_on; 1153 bool cur_wl_rx_low_gain_en; 1154 1155 u8 reason; 1156 u8 bt_rssi_state[4]; 1157 u8 wl_rssi_state[4]; 1158 u8 wl_ch_info[3]; 1159 u8 cur_ps_tdma; 1160 u8 cur_table; 1161 u8 ps_tdma_para[5]; 1162 u8 cur_bt_pwr_lvl; 1163 u8 cur_bt_lna_lvl; 1164 u8 cur_wl_pwr_lvl; 1165 u8 bt_status; 1166 u32 cur_ant_pos_type; 1167 u32 cur_switch_status; 1168 u32 setting_tdma; 1169 }; 1170 1171 #define COEX_BTINFO_SRC_WL_FW 0x0 1172 #define COEX_BTINFO_SRC_BT_RSP 0x1 1173 #define COEX_BTINFO_SRC_BT_ACT 0x2 1174 #define COEX_BTINFO_SRC_BT_IQK 0x3 1175 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1176 #define COEX_BTINFO_SRC_MAX 0x5 1177 1178 #define COEX_INFO_FTP BIT(7) 1179 #define COEX_INFO_A2DP BIT(6) 1180 #define COEX_INFO_HID BIT(5) 1181 #define COEX_INFO_SCO_BUSY BIT(4) 1182 #define COEX_INFO_ACL_BUSY BIT(3) 1183 #define COEX_INFO_INQ_PAGE BIT(2) 1184 #define COEX_INFO_SCO_ESCO BIT(1) 1185 #define COEX_INFO_CONNECTION BIT(0) 1186 #define COEX_BTINFO_LENGTH_MAX 10 1187 1188 struct rtw_coex_stat { 1189 bool bt_disabled; 1190 bool bt_disabled_pre; 1191 bool bt_link_exist; 1192 bool bt_whck_test; 1193 bool bt_inq_page; 1194 bool bt_inq; 1195 bool bt_page; 1196 bool bt_ble_voice; 1197 bool bt_ble_exist; 1198 bool bt_hfp_exist; 1199 bool bt_a2dp_exist; 1200 bool bt_hid_exist; 1201 bool bt_pan_exist; /* PAN or OPP */ 1202 bool bt_opp_exist; /* OPP only */ 1203 bool bt_acl_busy; 1204 bool bt_fix_2M; 1205 bool bt_setup_link; 1206 bool bt_multi_link; 1207 bool bt_a2dp_sink; 1208 bool bt_a2dp_active; 1209 bool bt_reenable; 1210 bool bt_ble_scan_en; 1211 bool bt_init_scan; 1212 bool bt_slave; 1213 bool bt_418_hid_exist; 1214 bool bt_mailbox_reply; 1215 1216 bool wl_under_lps; 1217 bool wl_under_ips; 1218 bool wl_hi_pri_task1; 1219 bool wl_hi_pri_task2; 1220 bool wl_force_lps_ctrl; 1221 bool wl_gl_busy; 1222 bool wl_linkscan_proc; 1223 bool wl_ps_state_fail; 1224 bool wl_tx_limit_en; 1225 bool wl_ampdu_limit_en; 1226 bool wl_connected; 1227 bool wl_slot_extend; 1228 bool wl_cck_lock; 1229 bool wl_cck_lock_pre; 1230 bool wl_cck_lock_ever; 1231 1232 u32 bt_supported_version; 1233 u32 bt_supported_feature; 1234 s8 bt_rssi; 1235 u8 kt_ver; 1236 u8 gnt_workaround_state; 1237 u8 tdma_timer_base; 1238 u8 bt_profile_num; 1239 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1240 u8 bt_info_lb2; 1241 u8 bt_info_lb3; 1242 u8 bt_info_hb0; 1243 u8 bt_info_hb1; 1244 u8 bt_info_hb2; 1245 u8 bt_info_hb3; 1246 u8 bt_ble_scan_type; 1247 u8 bt_hid_pair_num; 1248 u8 bt_hid_slot; 1249 u8 bt_a2dp_bitpool; 1250 u8 bt_iqk_state; 1251 1252 u8 wl_noisy_level; 1253 u8 wl_fw_dbg_info[10]; 1254 u8 wl_fw_dbg_info_pre[10]; 1255 u8 wl_coex_mode; 1256 u8 ampdu_max_time; 1257 u8 wl_tput_dir; 1258 1259 u16 score_board; 1260 u16 retry_limit; 1261 1262 /* counters to record bt states */ 1263 u32 cnt_bt[COEX_CNT_BT_MAX]; 1264 1265 /* counters to record wifi states */ 1266 u32 cnt_wl[COEX_CNT_WL_MAX]; 1267 1268 u32 darfrc; 1269 u32 darfrch; 1270 }; 1271 1272 struct rtw_coex { 1273 /* protects coex info request section */ 1274 struct mutex mutex; 1275 struct sk_buff_head queue; 1276 wait_queue_head_t wait; 1277 1278 bool under_5g; 1279 bool stop_dm; 1280 bool freeze; 1281 bool freerun; 1282 bool wl_rf_off; 1283 1284 struct rtw_coex_stat stat; 1285 struct rtw_coex_dm dm; 1286 struct rtw_coex_rfe rfe; 1287 1288 struct delayed_work bt_relink_work; 1289 struct delayed_work bt_reenable_work; 1290 struct delayed_work defreeze_work; 1291 }; 1292 1293 #define DPK_RF_REG_NUM 7 1294 #define DPK_RF_PATH_NUM 2 1295 #define DPK_BB_REG_NUM 18 1296 #define DPK_CHANNEL_WIDTH_80 1 1297 1298 DECLARE_EWMA(thermal, 10, 4); 1299 1300 struct rtw_dpk_info { 1301 bool is_dpk_pwr_on; 1302 bool is_reload; 1303 1304 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1305 1306 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1307 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1308 1309 u32 gnt_control; 1310 u32 gnt_value; 1311 1312 u8 result[RTW_RF_PATH_MAX]; 1313 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1314 u32 coef[RTW_RF_PATH_MAX][20]; 1315 u16 dpk_gs[RTW_RF_PATH_MAX]; 1316 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1317 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1318 1319 u8 dpk_band; 1320 u8 dpk_ch; 1321 u8 dpk_bw; 1322 }; 1323 1324 struct rtw_phy_cck_pd_reg { 1325 u32 reg_pd; 1326 u32 mask_pd; 1327 u32 reg_cs; 1328 u32 mask_cs; 1329 }; 1330 1331 #define DACK_MSBK_BACKUP_NUM 0xf 1332 #define DACK_DCK_BACKUP_NUM 0x2 1333 1334 struct rtw_swing_table { 1335 const u8 *p[RTW_RF_PATH_MAX]; 1336 const u8 *n[RTW_RF_PATH_MAX]; 1337 }; 1338 1339 struct rtw_pkt_count { 1340 u16 num_bcn_pkt; 1341 u16 num_qry_pkt[DESC_RATE_MAX]; 1342 }; 1343 1344 DECLARE_EWMA(evm, 10, 4); 1345 DECLARE_EWMA(snr, 10, 4); 1346 1347 struct rtw_dm_info { 1348 u32 cck_fa_cnt; 1349 u32 ofdm_fa_cnt; 1350 u32 total_fa_cnt; 1351 u32 cck_cca_cnt; 1352 u32 ofdm_cca_cnt; 1353 u32 total_cca_cnt; 1354 1355 u32 cck_ok_cnt; 1356 u32 cck_err_cnt; 1357 u32 ofdm_ok_cnt; 1358 u32 ofdm_err_cnt; 1359 u32 ht_ok_cnt; 1360 u32 ht_err_cnt; 1361 u32 vht_ok_cnt; 1362 u32 vht_err_cnt; 1363 1364 u8 min_rssi; 1365 u8 pre_min_rssi; 1366 u16 fa_history[4]; 1367 u8 igi_history[4]; 1368 u8 igi_bitmap; 1369 bool damping; 1370 u8 damping_cnt; 1371 u8 damping_rssi; 1372 1373 u8 cck_gi_u_bnd; 1374 u8 cck_gi_l_bnd; 1375 1376 u8 tx_rate; 1377 u8 thermal_avg[RTW_RF_PATH_MAX]; 1378 u8 thermal_meter_k; 1379 s8 delta_power_index[RTW_RF_PATH_MAX]; 1380 u8 default_ofdm_index; 1381 bool pwr_trk_triggered; 1382 bool pwr_trk_init_trigger; 1383 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1384 1385 /* backup dack results for each path and I/Q */ 1386 u32 dack_adck[RTW_RF_PATH_MAX]; 1387 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1388 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1389 1390 struct rtw_dpk_info dpk_info; 1391 1392 /* [bandwidth 0:20M/1:40M][number of path] */ 1393 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1394 u32 cck_fa_avg; 1395 1396 /* save the last rx phy status for debug */ 1397 s8 rx_snr[RTW_RF_PATH_MAX]; 1398 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1399 s16 cfo_tail[RTW_RF_PATH_MAX]; 1400 u8 rssi[RTW_RF_PATH_MAX]; 1401 u8 curr_rx_rate; 1402 struct rtw_pkt_count cur_pkt_count; 1403 struct rtw_pkt_count last_pkt_count; 1404 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1405 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1406 }; 1407 1408 struct rtw_efuse { 1409 u32 size; 1410 u32 physical_size; 1411 u32 logical_size; 1412 u32 protect_size; 1413 1414 u8 addr[ETH_ALEN]; 1415 u8 channel_plan; 1416 u8 country_code[2]; 1417 u8 rf_board_option; 1418 u8 rfe_option; 1419 u8 power_track_type; 1420 u8 thermal_meter[RTW_RF_PATH_MAX]; 1421 u8 thermal_meter_k; 1422 u8 crystal_cap; 1423 u8 ant_div_cfg; 1424 u8 ant_div_type; 1425 u8 regd; 1426 1427 u8 lna_type_2g; 1428 u8 lna_type_5g; 1429 u8 glna_type; 1430 u8 alna_type; 1431 bool ext_lna_2g; 1432 bool ext_lna_5g; 1433 u8 pa_type_2g; 1434 u8 pa_type_5g; 1435 u8 gpa_type; 1436 u8 apa_type; 1437 bool ext_pa_2g; 1438 bool ext_pa_5g; 1439 1440 bool btcoex; 1441 /* bt share antenna with wifi */ 1442 bool share_ant; 1443 u8 bt_setting; 1444 1445 struct { 1446 u8 hci; 1447 u8 bw; 1448 u8 ptcl; 1449 u8 nss; 1450 u8 ant_num; 1451 } hw_cap; 1452 1453 struct rtw_txpwr_idx txpwr_idx_table[4]; 1454 }; 1455 1456 struct rtw_phy_cond { 1457 #ifdef __LITTLE_ENDIAN 1458 u32 rfe:8; 1459 u32 intf:4; 1460 u32 pkg:4; 1461 u32 plat:4; 1462 u32 intf_rsvd:4; 1463 u32 cut:4; 1464 u32 branch:2; 1465 u32 neg:1; 1466 u32 pos:1; 1467 #else 1468 u32 pos:1; 1469 u32 neg:1; 1470 u32 branch:2; 1471 u32 cut:4; 1472 u32 intf_rsvd:4; 1473 u32 plat:4; 1474 u32 pkg:4; 1475 u32 intf:4; 1476 u32 rfe:8; 1477 #endif 1478 /* for intf:4 */ 1479 #define INTF_PCIE BIT(0) 1480 #define INTF_USB BIT(1) 1481 #define INTF_SDIO BIT(2) 1482 /* for branch:2 */ 1483 #define BRANCH_IF 0 1484 #define BRANCH_ELIF 1 1485 #define BRANCH_ELSE 2 1486 #define BRANCH_ENDIF 3 1487 }; 1488 1489 struct rtw_fifo_conf { 1490 /* tx fifo information */ 1491 u16 rsvd_boundary; 1492 u16 rsvd_pg_num; 1493 u16 rsvd_drv_pg_num; 1494 u16 txff_pg_num; 1495 u16 acq_pg_num; 1496 u16 rsvd_drv_addr; 1497 u16 rsvd_h2c_info_addr; 1498 u16 rsvd_h2c_sta_info_addr; 1499 u16 rsvd_h2cq_addr; 1500 u16 rsvd_cpu_instr_addr; 1501 u16 rsvd_fw_txbuf_addr; 1502 u16 rsvd_csibuf_addr; 1503 struct rtw_rqpn *rqpn; 1504 }; 1505 1506 struct rtw_fw_state { 1507 const struct firmware *firmware; 1508 struct rtw_dev *rtwdev; 1509 struct completion completion; 1510 u16 version; 1511 u8 sub_version; 1512 u8 sub_index; 1513 u16 h2c_version; 1514 }; 1515 1516 struct rtw_hal { 1517 u32 rcr; 1518 1519 u32 chip_version; 1520 u8 fab_version; 1521 u8 cut_version; 1522 u8 mp_chip; 1523 u8 oem_id; 1524 struct rtw_phy_cond phy_cond; 1525 1526 u8 ps_mode; 1527 u8 current_channel; 1528 u8 current_band_width; 1529 u8 current_band_type; 1530 1531 /* center channel for different available bandwidth, 1532 * val of (bw > current_band_width) is invalid 1533 */ 1534 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1535 1536 u8 sec_ch_offset; 1537 u8 rf_type; 1538 u8 rf_path_num; 1539 u8 antenna_tx; 1540 u8 antenna_rx; 1541 u8 bfee_sts_cap; 1542 1543 /* protect tx power section */ 1544 struct mutex tx_power_mutex; 1545 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1546 [DESC_RATE_MAX]; 1547 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1548 [DESC_RATE_MAX]; 1549 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1550 [RTW_RATE_SECTION_MAX]; 1551 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1552 [RTW_RATE_SECTION_MAX]; 1553 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1554 [RTW_CHANNEL_WIDTH_MAX] 1555 [RTW_RATE_SECTION_MAX] 1556 [RTW_MAX_CHANNEL_NUM_2G]; 1557 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1558 [RTW_CHANNEL_WIDTH_MAX] 1559 [RTW_RATE_SECTION_MAX] 1560 [RTW_MAX_CHANNEL_NUM_5G]; 1561 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1562 [DESC_RATE_MAX]; 1563 }; 1564 1565 struct rtw_dev { 1566 struct ieee80211_hw *hw; 1567 struct device *dev; 1568 1569 struct rtw_hci hci; 1570 1571 struct rtw_chip_info *chip; 1572 struct rtw_hal hal; 1573 struct rtw_fifo_conf fifo; 1574 struct rtw_fw_state fw; 1575 struct rtw_efuse efuse; 1576 struct rtw_sec_desc sec; 1577 struct rtw_traffic_stats stats; 1578 struct rtw_regulatory regd; 1579 struct rtw_bf_info bf_info; 1580 1581 struct rtw_dm_info dm_info; 1582 struct rtw_coex coex; 1583 1584 /* ensures exclusive access from mac80211 callbacks */ 1585 struct mutex mutex; 1586 1587 /* read/write rf register */ 1588 spinlock_t rf_lock; 1589 1590 /* watch dog every 2 sec */ 1591 struct delayed_work watch_dog_work; 1592 u32 watch_dog_cnt; 1593 1594 struct list_head rsvd_page_list; 1595 1596 /* c2h cmd queue & handler work */ 1597 struct sk_buff_head c2h_queue; 1598 struct work_struct c2h_work; 1599 1600 /* used to protect txqs list */ 1601 spinlock_t txq_lock; 1602 struct list_head txqs; 1603 struct tasklet_struct tx_tasklet; 1604 struct work_struct ba_work; 1605 1606 struct rtw_tx_report tx_report; 1607 1608 struct { 1609 /* incicate the mail box to use with fw */ 1610 u8 last_box_num; 1611 /* protect to send h2c to fw */ 1612 spinlock_t lock; 1613 u32 seq; 1614 } h2c; 1615 1616 /* lps power state & handler work */ 1617 struct rtw_lps_conf lps_conf; 1618 bool ps_enabled; 1619 1620 struct dentry *debugfs; 1621 1622 u8 sta_cnt; 1623 u32 rts_threshold; 1624 1625 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1626 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1627 1628 u8 mp_mode; 1629 1630 struct rtw_fw_state wow_fw; 1631 struct rtw_wow_param wow; 1632 1633 /* hci related data, must be last */ 1634 u8 priv[0] __aligned(sizeof(void *)); 1635 }; 1636 1637 #include "hci.h" 1638 1639 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1640 { 1641 return !!rtwdev->sta_cnt; 1642 } 1643 1644 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1645 { 1646 void *p = rtwtxq; 1647 1648 return container_of(p, struct ieee80211_txq, drv_priv); 1649 } 1650 1651 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1652 { 1653 void *p = rtwvif; 1654 1655 return container_of(p, struct ieee80211_vif, drv_priv); 1656 } 1657 1658 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1659 struct cfg80211_ssid *b) 1660 { 1661 if (!a || !b || a->ssid_len != b->ssid_len) 1662 return false; 1663 1664 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1665 return false; 1666 1667 return true; 1668 } 1669 1670 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1671 struct rtw_channel_params *ch_param); 1672 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1673 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1674 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1675 void rtw_restore_reg(struct rtw_dev *rtwdev, 1676 struct rtw_backup_info *bckp, u32 num); 1677 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1678 void rtw_set_channel(struct rtw_dev *rtwdev); 1679 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1680 u32 config); 1681 void rtw_tx_report_purge_timer(struct timer_list *t); 1682 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1683 int rtw_core_start(struct rtw_dev *rtwdev); 1684 void rtw_core_stop(struct rtw_dev *rtwdev); 1685 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1686 int rtw_core_init(struct rtw_dev *rtwdev); 1687 void rtw_core_deinit(struct rtw_dev *rtwdev); 1688 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1689 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1690 u16 rtw_desc_to_bitrate(u8 desc_rate); 1691 1692 #endif 1693