1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_NAPI_WEIGHT_NUM 64 21 #define RTW_MAX_MAC_ID_NUM 32 22 #define RTW_MAX_SEC_CAM_NUM 32 23 #define MAX_PG_CAM_BACKUP_NUM 8 24 25 #define RTW_SCAN_MAX_SSIDS 4 26 #define RTW_SCAN_MAX_IE_LEN 128 27 28 #define RTW_MAX_PATTERN_NUM 12 29 #define RTW_MAX_PATTERN_MASK_SIZE 16 30 #define RTW_MAX_PATTERN_SIZE 128 31 32 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 33 34 #define RFREG_MASK 0xfffff 35 #define INV_RF_DATA 0xffffffff 36 #define TX_PAGE_SIZE_SHIFT 7 37 38 #define RTW_CHANNEL_WIDTH_MAX 3 39 #define RTW_RF_PATH_MAX 4 40 #define HW_FEATURE_LEN 13 41 42 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 43 44 extern bool rtw_bf_support; 45 extern bool rtw_disable_lps_deep_mode; 46 extern unsigned int rtw_debug_mask; 47 extern bool rtw_edcca_enabled; 48 extern const struct ieee80211_ops rtw_ops; 49 50 #define RTW_MAX_CHANNEL_NUM_2G 14 51 #define RTW_MAX_CHANNEL_NUM_5G 49 52 53 struct rtw_dev; 54 55 enum rtw_hci_type { 56 RTW_HCI_TYPE_PCIE, 57 RTW_HCI_TYPE_USB, 58 RTW_HCI_TYPE_SDIO, 59 60 RTW_HCI_TYPE_UNDEFINE, 61 }; 62 63 struct rtw_hci { 64 struct rtw_hci_ops *ops; 65 enum rtw_hci_type type; 66 67 u32 rpwm_addr; 68 u32 cpwm_addr; 69 70 u8 bulkout_num; 71 }; 72 73 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 74 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 75 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 76 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 77 78 #define IS_CH_5G_BAND_MID(channel) \ 79 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 80 81 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 82 #define IS_CH_5G_BAND(channel) \ 83 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 84 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 85 86 enum rtw_supported_band { 87 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 88 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 89 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 90 }; 91 92 /* now, support upto 80M bw */ 93 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 94 95 enum rtw_bandwidth { 96 RTW_CHANNEL_WIDTH_20 = 0, 97 RTW_CHANNEL_WIDTH_40 = 1, 98 RTW_CHANNEL_WIDTH_80 = 2, 99 RTW_CHANNEL_WIDTH_160 = 3, 100 RTW_CHANNEL_WIDTH_80_80 = 4, 101 RTW_CHANNEL_WIDTH_5 = 5, 102 RTW_CHANNEL_WIDTH_10 = 6, 103 }; 104 105 enum rtw_sc_offset { 106 RTW_SC_DONT_CARE = 0, 107 RTW_SC_20_UPPER = 1, 108 RTW_SC_20_LOWER = 2, 109 RTW_SC_20_UPMOST = 3, 110 RTW_SC_20_LOWEST = 4, 111 RTW_SC_40_UPPER = 9, 112 RTW_SC_40_LOWER = 10, 113 }; 114 115 enum rtw_net_type { 116 RTW_NET_NO_LINK = 0, 117 RTW_NET_AD_HOC = 1, 118 RTW_NET_MGD_LINKED = 2, 119 RTW_NET_AP_MODE = 3, 120 }; 121 122 enum rtw_rf_type { 123 RF_1T1R = 0, 124 RF_1T2R = 1, 125 RF_2T2R = 2, 126 RF_2T3R = 3, 127 RF_2T4R = 4, 128 RF_3T3R = 5, 129 RF_3T4R = 6, 130 RF_4T4R = 7, 131 RF_TYPE_MAX, 132 }; 133 134 enum rtw_rf_path { 135 RF_PATH_A = 0, 136 RF_PATH_B = 1, 137 RF_PATH_C = 2, 138 RF_PATH_D = 3, 139 }; 140 141 enum rtw_bb_path { 142 BB_PATH_A = BIT(0), 143 BB_PATH_B = BIT(1), 144 BB_PATH_C = BIT(2), 145 BB_PATH_D = BIT(3), 146 147 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 148 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 149 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 150 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 151 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 152 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 153 154 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 155 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 156 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 157 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 159 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 160 }; 161 162 enum rtw_rate_section { 163 RTW_RATE_SECTION_CCK = 0, 164 RTW_RATE_SECTION_OFDM, 165 RTW_RATE_SECTION_HT_1S, 166 RTW_RATE_SECTION_HT_2S, 167 RTW_RATE_SECTION_VHT_1S, 168 RTW_RATE_SECTION_VHT_2S, 169 170 /* keep last */ 171 RTW_RATE_SECTION_MAX, 172 }; 173 174 enum rtw_wireless_set { 175 WIRELESS_CCK = 0x00000001, 176 WIRELESS_OFDM = 0x00000002, 177 WIRELESS_HT = 0x00000004, 178 WIRELESS_VHT = 0x00000008, 179 }; 180 181 #define HT_STBC_EN BIT(0) 182 #define VHT_STBC_EN BIT(1) 183 #define HT_LDPC_EN BIT(0) 184 #define VHT_LDPC_EN BIT(1) 185 186 enum rtw_chip_type { 187 RTW_CHIP_TYPE_8822B, 188 RTW_CHIP_TYPE_8822C, 189 RTW_CHIP_TYPE_8723D, 190 RTW_CHIP_TYPE_8821C, 191 }; 192 193 enum rtw_tx_queue_type { 194 /* the order of AC queues matters */ 195 RTW_TX_QUEUE_BK = 0x0, 196 RTW_TX_QUEUE_BE = 0x1, 197 RTW_TX_QUEUE_VI = 0x2, 198 RTW_TX_QUEUE_VO = 0x3, 199 200 RTW_TX_QUEUE_BCN = 0x4, 201 RTW_TX_QUEUE_MGMT = 0x5, 202 RTW_TX_QUEUE_HI0 = 0x6, 203 RTW_TX_QUEUE_H2C = 0x7, 204 /* keep it last */ 205 RTK_MAX_TX_QUEUE_NUM 206 }; 207 208 enum rtw_rx_queue_type { 209 RTW_RX_QUEUE_MPDU = 0x0, 210 RTW_RX_QUEUE_C2H = 0x1, 211 /* keep it last */ 212 RTK_MAX_RX_QUEUE_NUM 213 }; 214 215 enum rtw_fw_type { 216 RTW_NORMAL_FW = 0x0, 217 RTW_WOWLAN_FW = 0x1, 218 }; 219 220 enum rtw_rate_index { 221 RTW_RATEID_BGN_40M_2SS = 0, 222 RTW_RATEID_BGN_40M_1SS = 1, 223 RTW_RATEID_BGN_20M_2SS = 2, 224 RTW_RATEID_BGN_20M_1SS = 3, 225 RTW_RATEID_GN_N2SS = 4, 226 RTW_RATEID_GN_N1SS = 5, 227 RTW_RATEID_BG = 6, 228 RTW_RATEID_G = 7, 229 RTW_RATEID_B_20M = 8, 230 RTW_RATEID_ARFR0_AC_2SS = 9, 231 RTW_RATEID_ARFR1_AC_1SS = 10, 232 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 233 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 234 RTW_RATEID_ARFR4_AC_3SS = 13, 235 RTW_RATEID_ARFR5_N_3SS = 14, 236 RTW_RATEID_ARFR7_N_4SS = 15, 237 RTW_RATEID_ARFR6_AC_4SS = 16 238 }; 239 240 enum rtw_trx_desc_rate { 241 DESC_RATE1M = 0x00, 242 DESC_RATE2M = 0x01, 243 DESC_RATE5_5M = 0x02, 244 DESC_RATE11M = 0x03, 245 246 DESC_RATE6M = 0x04, 247 DESC_RATE9M = 0x05, 248 DESC_RATE12M = 0x06, 249 DESC_RATE18M = 0x07, 250 DESC_RATE24M = 0x08, 251 DESC_RATE36M = 0x09, 252 DESC_RATE48M = 0x0a, 253 DESC_RATE54M = 0x0b, 254 255 DESC_RATEMCS0 = 0x0c, 256 DESC_RATEMCS1 = 0x0d, 257 DESC_RATEMCS2 = 0x0e, 258 DESC_RATEMCS3 = 0x0f, 259 DESC_RATEMCS4 = 0x10, 260 DESC_RATEMCS5 = 0x11, 261 DESC_RATEMCS6 = 0x12, 262 DESC_RATEMCS7 = 0x13, 263 DESC_RATEMCS8 = 0x14, 264 DESC_RATEMCS9 = 0x15, 265 DESC_RATEMCS10 = 0x16, 266 DESC_RATEMCS11 = 0x17, 267 DESC_RATEMCS12 = 0x18, 268 DESC_RATEMCS13 = 0x19, 269 DESC_RATEMCS14 = 0x1a, 270 DESC_RATEMCS15 = 0x1b, 271 DESC_RATEMCS16 = 0x1c, 272 DESC_RATEMCS17 = 0x1d, 273 DESC_RATEMCS18 = 0x1e, 274 DESC_RATEMCS19 = 0x1f, 275 DESC_RATEMCS20 = 0x20, 276 DESC_RATEMCS21 = 0x21, 277 DESC_RATEMCS22 = 0x22, 278 DESC_RATEMCS23 = 0x23, 279 DESC_RATEMCS24 = 0x24, 280 DESC_RATEMCS25 = 0x25, 281 DESC_RATEMCS26 = 0x26, 282 DESC_RATEMCS27 = 0x27, 283 DESC_RATEMCS28 = 0x28, 284 DESC_RATEMCS29 = 0x29, 285 DESC_RATEMCS30 = 0x2a, 286 DESC_RATEMCS31 = 0x2b, 287 288 DESC_RATEVHT1SS_MCS0 = 0x2c, 289 DESC_RATEVHT1SS_MCS1 = 0x2d, 290 DESC_RATEVHT1SS_MCS2 = 0x2e, 291 DESC_RATEVHT1SS_MCS3 = 0x2f, 292 DESC_RATEVHT1SS_MCS4 = 0x30, 293 DESC_RATEVHT1SS_MCS5 = 0x31, 294 DESC_RATEVHT1SS_MCS6 = 0x32, 295 DESC_RATEVHT1SS_MCS7 = 0x33, 296 DESC_RATEVHT1SS_MCS8 = 0x34, 297 DESC_RATEVHT1SS_MCS9 = 0x35, 298 299 DESC_RATEVHT2SS_MCS0 = 0x36, 300 DESC_RATEVHT2SS_MCS1 = 0x37, 301 DESC_RATEVHT2SS_MCS2 = 0x38, 302 DESC_RATEVHT2SS_MCS3 = 0x39, 303 DESC_RATEVHT2SS_MCS4 = 0x3a, 304 DESC_RATEVHT2SS_MCS5 = 0x3b, 305 DESC_RATEVHT2SS_MCS6 = 0x3c, 306 DESC_RATEVHT2SS_MCS7 = 0x3d, 307 DESC_RATEVHT2SS_MCS8 = 0x3e, 308 DESC_RATEVHT2SS_MCS9 = 0x3f, 309 310 DESC_RATEVHT3SS_MCS0 = 0x40, 311 DESC_RATEVHT3SS_MCS1 = 0x41, 312 DESC_RATEVHT3SS_MCS2 = 0x42, 313 DESC_RATEVHT3SS_MCS3 = 0x43, 314 DESC_RATEVHT3SS_MCS4 = 0x44, 315 DESC_RATEVHT3SS_MCS5 = 0x45, 316 DESC_RATEVHT3SS_MCS6 = 0x46, 317 DESC_RATEVHT3SS_MCS7 = 0x47, 318 DESC_RATEVHT3SS_MCS8 = 0x48, 319 DESC_RATEVHT3SS_MCS9 = 0x49, 320 321 DESC_RATEVHT4SS_MCS0 = 0x4a, 322 DESC_RATEVHT4SS_MCS1 = 0x4b, 323 DESC_RATEVHT4SS_MCS2 = 0x4c, 324 DESC_RATEVHT4SS_MCS3 = 0x4d, 325 DESC_RATEVHT4SS_MCS4 = 0x4e, 326 DESC_RATEVHT4SS_MCS5 = 0x4f, 327 DESC_RATEVHT4SS_MCS6 = 0x50, 328 DESC_RATEVHT4SS_MCS7 = 0x51, 329 DESC_RATEVHT4SS_MCS8 = 0x52, 330 DESC_RATEVHT4SS_MCS9 = 0x53, 331 332 DESC_RATE_MAX, 333 }; 334 335 enum rtw_regulatory_domains { 336 RTW_REGD_FCC = 0, 337 RTW_REGD_MKK = 1, 338 RTW_REGD_ETSI = 2, 339 RTW_REGD_IC = 3, 340 RTW_REGD_KCC = 4, 341 RTW_REGD_ACMA = 5, 342 RTW_REGD_CHILE = 6, 343 RTW_REGD_UKRAINE = 7, 344 RTW_REGD_MEXICO = 8, 345 RTW_REGD_CN = 9, 346 RTW_REGD_WW, 347 348 RTW_REGD_MAX 349 }; 350 351 enum rtw_txq_flags { 352 RTW_TXQ_AMPDU, 353 RTW_TXQ_BLOCK_BA, 354 }; 355 356 enum rtw_flags { 357 RTW_FLAG_RUNNING, 358 RTW_FLAG_FW_RUNNING, 359 RTW_FLAG_SCANNING, 360 RTW_FLAG_INACTIVE_PS, 361 RTW_FLAG_LEISURE_PS, 362 RTW_FLAG_LEISURE_PS_DEEP, 363 RTW_FLAG_DIG_DISABLE, 364 RTW_FLAG_BUSY_TRAFFIC, 365 RTW_FLAG_WOWLAN, 366 RTW_FLAG_RESTARTING, 367 RTW_FLAG_RESTART_TRIGGERING, 368 RTW_FLAG_FORCE_LOWEST_RATE, 369 370 NUM_OF_RTW_FLAGS, 371 }; 372 373 enum rtw_evm { 374 RTW_EVM_OFDM = 0, 375 RTW_EVM_1SS, 376 RTW_EVM_2SS_A, 377 RTW_EVM_2SS_B, 378 /* keep it last */ 379 RTW_EVM_NUM 380 }; 381 382 enum rtw_snr { 383 RTW_SNR_OFDM_A = 0, 384 RTW_SNR_OFDM_B, 385 RTW_SNR_OFDM_C, 386 RTW_SNR_OFDM_D, 387 RTW_SNR_1SS_A, 388 RTW_SNR_1SS_B, 389 RTW_SNR_1SS_C, 390 RTW_SNR_1SS_D, 391 RTW_SNR_2SS_A, 392 RTW_SNR_2SS_B, 393 RTW_SNR_2SS_C, 394 RTW_SNR_2SS_D, 395 /* keep it last */ 396 RTW_SNR_NUM 397 }; 398 399 enum rtw_wow_flags { 400 RTW_WOW_FLAG_EN_MAGIC_PKT, 401 RTW_WOW_FLAG_EN_REKEY_PKT, 402 RTW_WOW_FLAG_EN_DISCONNECT, 403 404 /* keep it last */ 405 RTW_WOW_FLAG_MAX, 406 }; 407 408 /* the power index is represented by differences, which cck-1s & ht40-1s are 409 * the base values, so for 1s's differences, there are only ht20 & ofdm 410 */ 411 struct rtw_2g_1s_pwr_idx_diff { 412 #ifdef __LITTLE_ENDIAN 413 s8 ofdm:4; 414 s8 bw20:4; 415 #else 416 s8 bw20:4; 417 s8 ofdm:4; 418 #endif 419 } __packed; 420 421 struct rtw_2g_ns_pwr_idx_diff { 422 #ifdef __LITTLE_ENDIAN 423 s8 bw20:4; 424 s8 bw40:4; 425 s8 cck:4; 426 s8 ofdm:4; 427 #else 428 s8 ofdm:4; 429 s8 cck:4; 430 s8 bw40:4; 431 s8 bw20:4; 432 #endif 433 } __packed; 434 435 struct rtw_2g_txpwr_idx { 436 u8 cck_base[6]; 437 u8 bw40_base[5]; 438 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 439 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 440 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 441 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 442 }; 443 444 struct rtw_5g_ht_1s_pwr_idx_diff { 445 #ifdef __LITTLE_ENDIAN 446 s8 ofdm:4; 447 s8 bw20:4; 448 #else 449 s8 bw20:4; 450 s8 ofdm:4; 451 #endif 452 } __packed; 453 454 struct rtw_5g_ht_ns_pwr_idx_diff { 455 #ifdef __LITTLE_ENDIAN 456 s8 bw20:4; 457 s8 bw40:4; 458 #else 459 s8 bw40:4; 460 s8 bw20:4; 461 #endif 462 } __packed; 463 464 struct rtw_5g_ofdm_ns_pwr_idx_diff { 465 #ifdef __LITTLE_ENDIAN 466 s8 ofdm_3s:4; 467 s8 ofdm_2s:4; 468 s8 ofdm_4s:4; 469 s8 res:4; 470 #else 471 s8 res:4; 472 s8 ofdm_4s:4; 473 s8 ofdm_2s:4; 474 s8 ofdm_3s:4; 475 #endif 476 } __packed; 477 478 struct rtw_5g_vht_ns_pwr_idx_diff { 479 #ifdef __LITTLE_ENDIAN 480 s8 bw160:4; 481 s8 bw80:4; 482 #else 483 s8 bw80:4; 484 s8 bw160:4; 485 #endif 486 } __packed; 487 488 struct rtw_5g_txpwr_idx { 489 u8 bw40_base[14]; 490 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 491 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 492 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 493 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 494 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 495 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 496 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 497 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 498 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 499 }; 500 501 struct rtw_txpwr_idx { 502 struct rtw_2g_txpwr_idx pwr_idx_2g; 503 struct rtw_5g_txpwr_idx pwr_idx_5g; 504 }; 505 506 struct rtw_timer_list { 507 struct timer_list timer; 508 void (*function)(void *data); 509 void *args; 510 }; 511 512 struct rtw_channel_params { 513 u8 center_chan; 514 u8 bandwidth; 515 u8 primary_chan_idx; 516 /* center channel by different available bandwidth, 517 * val of (bw > current bandwidth) is invalid 518 */ 519 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 520 }; 521 522 struct rtw_hw_reg { 523 u32 addr; 524 u32 mask; 525 }; 526 527 struct rtw_ltecoex_addr { 528 u32 ctrl; 529 u32 wdata; 530 u32 rdata; 531 }; 532 533 struct rtw_reg_domain { 534 u32 addr; 535 u32 mask; 536 #define RTW_REG_DOMAIN_MAC32 0 537 #define RTW_REG_DOMAIN_MAC16 1 538 #define RTW_REG_DOMAIN_MAC8 2 539 #define RTW_REG_DOMAIN_RF_A 3 540 #define RTW_REG_DOMAIN_RF_B 4 541 #define RTW_REG_DOMAIN_NL 0xFF 542 u8 domain; 543 }; 544 545 struct rtw_rf_sipi_addr { 546 u32 hssi_1; 547 u32 hssi_2; 548 u32 lssi_read; 549 u32 lssi_read_pi; 550 }; 551 552 struct rtw_hw_reg_offset { 553 struct rtw_hw_reg hw_reg; 554 u8 offset; 555 }; 556 557 struct rtw_backup_info { 558 u8 len; 559 u32 reg; 560 u32 val; 561 }; 562 563 enum rtw_vif_port_set { 564 PORT_SET_MAC_ADDR = BIT(0), 565 PORT_SET_BSSID = BIT(1), 566 PORT_SET_NET_TYPE = BIT(2), 567 PORT_SET_AID = BIT(3), 568 PORT_SET_BCN_CTRL = BIT(4), 569 }; 570 571 struct rtw_vif_port { 572 struct rtw_hw_reg mac_addr; 573 struct rtw_hw_reg bssid; 574 struct rtw_hw_reg net_type; 575 struct rtw_hw_reg aid; 576 struct rtw_hw_reg bcn_ctrl; 577 }; 578 579 struct rtw_tx_pkt_info { 580 u32 tx_pkt_size; 581 u8 offset; 582 u8 pkt_offset; 583 u8 mac_id; 584 u8 rate_id; 585 u8 rate; 586 u8 qsel; 587 u8 bw; 588 u8 sec_type; 589 u8 sn; 590 bool ampdu_en; 591 u8 ampdu_factor; 592 u8 ampdu_density; 593 u16 seq; 594 bool stbc; 595 bool ldpc; 596 bool dis_rate_fallback; 597 bool bmc; 598 bool use_rate; 599 bool ls; 600 bool fs; 601 bool short_gi; 602 bool report; 603 bool rts; 604 bool dis_qselseq; 605 bool en_hwseq; 606 u8 hw_ssn_sel; 607 bool nav_use_hdr; 608 bool bt_null; 609 }; 610 611 struct rtw_rx_pkt_stat { 612 bool phy_status; 613 bool icv_err; 614 bool crc_err; 615 bool decrypted; 616 bool is_c2h; 617 618 s32 signal_power; 619 u16 pkt_len; 620 u8 bw; 621 u8 drv_info_sz; 622 u8 shift; 623 u8 rate; 624 u8 mac_id; 625 u8 cam_id; 626 u8 ppdu_cnt; 627 u32 tsf_low; 628 s8 rx_power[RTW_RF_PATH_MAX]; 629 u8 rssi; 630 u8 rxsc; 631 s8 rx_snr[RTW_RF_PATH_MAX]; 632 u8 rx_evm[RTW_RF_PATH_MAX]; 633 s8 cfo_tail[RTW_RF_PATH_MAX]; 634 u16 freq; 635 u8 band; 636 637 struct rtw_sta_info *si; 638 struct ieee80211_vif *vif; 639 struct ieee80211_hdr *hdr; 640 }; 641 642 DECLARE_EWMA(tp, 10, 2); 643 644 struct rtw_traffic_stats { 645 /* units in bytes */ 646 u64 tx_unicast; 647 u64 rx_unicast; 648 649 /* count for packets */ 650 u64 tx_cnt; 651 u64 rx_cnt; 652 653 /* units in Mbps */ 654 u32 tx_throughput; 655 u32 rx_throughput; 656 struct ewma_tp tx_ewma_tp; 657 struct ewma_tp rx_ewma_tp; 658 }; 659 660 enum rtw_lps_mode { 661 RTW_MODE_ACTIVE = 0, 662 RTW_MODE_LPS = 1, 663 RTW_MODE_WMM_PS = 2, 664 }; 665 666 enum rtw_lps_deep_mode { 667 LPS_DEEP_MODE_NONE = 0, 668 LPS_DEEP_MODE_LCLK = 1, 669 LPS_DEEP_MODE_PG = 2, 670 }; 671 672 enum rtw_pwr_state { 673 RTW_RF_OFF = 0x0, 674 RTW_RF_ON = 0x4, 675 RTW_ALL_ON = 0xc, 676 }; 677 678 struct rtw_lps_conf { 679 enum rtw_lps_mode mode; 680 enum rtw_lps_deep_mode deep_mode; 681 enum rtw_lps_deep_mode wow_deep_mode; 682 enum rtw_pwr_state state; 683 u8 awake_interval; 684 u8 rlbm; 685 u8 smart_ps; 686 u8 port_id; 687 bool sec_cam_backup; 688 bool pattern_cam_backup; 689 }; 690 691 enum rtw_hw_key_type { 692 RTW_CAM_NONE = 0, 693 RTW_CAM_WEP40 = 1, 694 RTW_CAM_TKIP = 2, 695 RTW_CAM_AES = 4, 696 RTW_CAM_WEP104 = 5, 697 }; 698 699 struct rtw_cam_entry { 700 bool valid; 701 bool group; 702 u8 addr[ETH_ALEN]; 703 u8 hw_key_type; 704 struct ieee80211_key_conf *key; 705 }; 706 707 struct rtw_sec_desc { 708 /* search strategy */ 709 bool default_key_search; 710 711 u32 total_cam_num; 712 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 713 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 714 }; 715 716 struct rtw_tx_report { 717 /* protect the tx report queue */ 718 spinlock_t q_lock; 719 struct sk_buff_head queue; 720 atomic_t sn; 721 struct timer_list purge_timer; 722 }; 723 724 struct rtw_ra_report { 725 struct rate_info txrate; 726 u32 bit_rate; 727 u8 desc_rate; 728 }; 729 730 struct rtw_txq { 731 struct list_head list; 732 733 unsigned long flags; 734 unsigned long last_push; 735 }; 736 737 #define RTW_BC_MC_MACID 1 738 DECLARE_EWMA(rssi, 10, 16); 739 740 struct rtw_sta_info { 741 struct ieee80211_sta *sta; 742 struct ieee80211_vif *vif; 743 744 struct ewma_rssi avg_rssi; 745 u8 rssi_level; 746 747 u8 mac_id; 748 u8 rate_id; 749 enum rtw_bandwidth bw_mode; 750 enum rtw_rf_type rf_type; 751 enum rtw_wireless_set wireless_set; 752 u8 stbc_en:2; 753 u8 ldpc_en:2; 754 bool sgi_enable; 755 bool vht_enable; 756 bool updated; 757 u8 init_ra_lv; 758 u64 ra_mask; 759 760 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 761 762 struct rtw_ra_report ra_report; 763 764 bool use_cfg_mask; 765 struct cfg80211_bitrate_mask *mask; 766 }; 767 768 enum rtw_bfee_role { 769 RTW_BFEE_NONE, 770 RTW_BFEE_SU, 771 RTW_BFEE_MU 772 }; 773 774 struct rtw_bfee { 775 enum rtw_bfee_role role; 776 777 u16 p_aid; 778 u8 g_id; 779 u8 mac_addr[ETH_ALEN]; 780 u8 sound_dim; 781 782 /* SU-MIMO */ 783 u8 su_reg_index; 784 785 /* MU-MIMO */ 786 u16 aid; 787 }; 788 789 struct rtw_bf_info { 790 u8 bfer_mu_cnt; 791 u8 bfer_su_cnt; 792 DECLARE_BITMAP(bfer_su_reg_maping, 2); 793 u8 cur_csi_rpt_rate; 794 }; 795 796 struct rtw_vif { 797 enum rtw_net_type net_type; 798 u16 aid; 799 u8 mac_addr[ETH_ALEN]; 800 u8 bssid[ETH_ALEN]; 801 u8 port; 802 u8 bcn_ctrl; 803 struct list_head rsvd_page_list; 804 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 805 const struct rtw_vif_port *conf; 806 struct cfg80211_scan_request *scan_req; 807 struct ieee80211_scan_ies *scan_ies; 808 809 struct rtw_traffic_stats stats; 810 811 struct rtw_bfee bfee; 812 }; 813 814 struct rtw_regulatory { 815 char alpha2[2]; 816 u8 txpwr_regd_2g; 817 u8 txpwr_regd_5g; 818 }; 819 820 enum rtw_regd_state { 821 RTW_REGD_STATE_WORLDWIDE, 822 RTW_REGD_STATE_PROGRAMMED, 823 RTW_REGD_STATE_SETTING, 824 825 RTW_REGD_STATE_NR, 826 }; 827 828 struct rtw_regd { 829 enum rtw_regd_state state; 830 const struct rtw_regulatory *regulatory; 831 enum nl80211_dfs_regions dfs_region; 832 }; 833 834 struct rtw_chip_ops { 835 int (*mac_init)(struct rtw_dev *rtwdev); 836 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 837 void (*shutdown)(struct rtw_dev *rtwdev); 838 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 839 void (*phy_set_param)(struct rtw_dev *rtwdev); 840 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 841 u8 bandwidth, u8 primary_chan_idx); 842 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 843 struct rtw_rx_pkt_stat *pkt_stat, 844 struct ieee80211_rx_status *rx_status); 845 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 846 u32 addr, u32 mask); 847 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 848 u32 addr, u32 mask, u32 data); 849 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 850 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 851 u32 size); 852 int (*set_antenna)(struct rtw_dev *rtwdev, 853 u32 antenna_tx, 854 u32 antenna_rx); 855 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 856 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 857 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 858 void (*phy_calibration)(struct rtw_dev *rtwdev); 859 void (*dpk_track)(struct rtw_dev *rtwdev); 860 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 861 void (*pwr_track)(struct rtw_dev *rtwdev); 862 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 863 struct rtw_bfee *bfee, bool enable); 864 void (*set_gid_table)(struct rtw_dev *rtwdev, 865 struct ieee80211_vif *vif, 866 struct ieee80211_bss_conf *conf); 867 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 868 u8 fixrate_en, u8 *new_rate); 869 void (*adaptivity_init)(struct rtw_dev *rtwdev); 870 void (*adaptivity)(struct rtw_dev *rtwdev); 871 void (*cfo_init)(struct rtw_dev *rtwdev); 872 void (*cfo_track)(struct rtw_dev *rtwdev); 873 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 874 enum rtw_bb_path tx_path_1ss, 875 enum rtw_bb_path tx_path_cck, 876 bool is_tx2_path); 877 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 878 u8 rx_path, bool is_tx2_path); 879 880 /* for coex */ 881 void (*coex_set_init)(struct rtw_dev *rtwdev); 882 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 883 u8 ctrl_type, u8 pos_type); 884 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 885 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 886 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 887 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 888 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 889 }; 890 891 #define RTW_PWR_POLLING_CNT 20000 892 893 #define RTW_PWR_CMD_READ 0x00 894 #define RTW_PWR_CMD_WRITE 0x01 895 #define RTW_PWR_CMD_POLLING 0x02 896 #define RTW_PWR_CMD_DELAY 0x03 897 #define RTW_PWR_CMD_END 0x04 898 899 /* define the base address of each block */ 900 #define RTW_PWR_ADDR_MAC 0x00 901 #define RTW_PWR_ADDR_USB 0x01 902 #define RTW_PWR_ADDR_PCIE 0x02 903 #define RTW_PWR_ADDR_SDIO 0x03 904 905 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 906 #define RTW_PWR_INTF_USB_MSK BIT(1) 907 #define RTW_PWR_INTF_PCI_MSK BIT(2) 908 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 909 910 #define RTW_PWR_CUT_TEST_MSK BIT(0) 911 #define RTW_PWR_CUT_A_MSK BIT(1) 912 #define RTW_PWR_CUT_B_MSK BIT(2) 913 #define RTW_PWR_CUT_C_MSK BIT(3) 914 #define RTW_PWR_CUT_D_MSK BIT(4) 915 #define RTW_PWR_CUT_E_MSK BIT(5) 916 #define RTW_PWR_CUT_F_MSK BIT(6) 917 #define RTW_PWR_CUT_G_MSK BIT(7) 918 #define RTW_PWR_CUT_ALL_MSK 0xFF 919 920 enum rtw_pwr_seq_cmd_delay_unit { 921 RTW_PWR_DELAY_US, 922 RTW_PWR_DELAY_MS, 923 }; 924 925 struct rtw_pwr_seq_cmd { 926 u16 offset; 927 u8 cut_mask; 928 u8 intf_mask; 929 u8 base:4; 930 u8 cmd:4; 931 u8 mask; 932 u8 value; 933 }; 934 935 enum rtw_chip_ver { 936 RTW_CHIP_VER_CUT_A = 0x00, 937 RTW_CHIP_VER_CUT_B = 0x01, 938 RTW_CHIP_VER_CUT_C = 0x02, 939 RTW_CHIP_VER_CUT_D = 0x03, 940 RTW_CHIP_VER_CUT_E = 0x04, 941 RTW_CHIP_VER_CUT_F = 0x05, 942 RTW_CHIP_VER_CUT_G = 0x06, 943 }; 944 945 #define RTW_INTF_PHY_PLATFORM_ALL 0 946 947 enum rtw_intf_phy_cut { 948 RTW_INTF_PHY_CUT_A = BIT(0), 949 RTW_INTF_PHY_CUT_B = BIT(1), 950 RTW_INTF_PHY_CUT_C = BIT(2), 951 RTW_INTF_PHY_CUT_D = BIT(3), 952 RTW_INTF_PHY_CUT_E = BIT(4), 953 RTW_INTF_PHY_CUT_F = BIT(5), 954 RTW_INTF_PHY_CUT_G = BIT(6), 955 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 956 }; 957 958 enum rtw_ip_sel { 959 RTW_IP_SEL_PHY = 0, 960 RTW_IP_SEL_MAC = 1, 961 RTW_IP_SEL_DBI = 2, 962 963 RTW_IP_SEL_UNDEF = 0xFFFF 964 }; 965 966 enum rtw_pq_map_id { 967 RTW_PQ_MAP_VO = 0x0, 968 RTW_PQ_MAP_VI = 0x1, 969 RTW_PQ_MAP_BE = 0x2, 970 RTW_PQ_MAP_BK = 0x3, 971 RTW_PQ_MAP_MG = 0x4, 972 RTW_PQ_MAP_HI = 0x5, 973 RTW_PQ_MAP_NUM = 0x6, 974 975 RTW_PQ_MAP_UNDEF, 976 }; 977 978 enum rtw_dma_mapping { 979 RTW_DMA_MAPPING_EXTRA = 0, 980 RTW_DMA_MAPPING_LOW = 1, 981 RTW_DMA_MAPPING_NORMAL = 2, 982 RTW_DMA_MAPPING_HIGH = 3, 983 984 RTW_DMA_MAPPING_MAX, 985 RTW_DMA_MAPPING_UNDEF, 986 }; 987 988 struct rtw_rqpn { 989 enum rtw_dma_mapping dma_map_vo; 990 enum rtw_dma_mapping dma_map_vi; 991 enum rtw_dma_mapping dma_map_be; 992 enum rtw_dma_mapping dma_map_bk; 993 enum rtw_dma_mapping dma_map_mg; 994 enum rtw_dma_mapping dma_map_hi; 995 }; 996 997 struct rtw_prioq_addr { 998 u32 rsvd; 999 u32 avail; 1000 }; 1001 1002 struct rtw_prioq_addrs { 1003 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1004 bool wsize; 1005 }; 1006 1007 struct rtw_page_table { 1008 u16 hq_num; 1009 u16 nq_num; 1010 u16 lq_num; 1011 u16 exq_num; 1012 u16 gapq_num; 1013 }; 1014 1015 struct rtw_intf_phy_para { 1016 u16 offset; 1017 u16 value; 1018 u16 ip_sel; 1019 u16 cut_mask; 1020 u16 platform; 1021 }; 1022 1023 struct rtw_wow_pattern { 1024 u16 crc; 1025 u8 type; 1026 u8 valid; 1027 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1028 }; 1029 1030 struct rtw_pno_request { 1031 bool inited; 1032 u32 match_set_cnt; 1033 struct cfg80211_match_set *match_sets; 1034 u8 channel_cnt; 1035 struct ieee80211_channel *channels; 1036 struct cfg80211_sched_scan_plan scan_plan; 1037 }; 1038 1039 struct rtw_wow_param { 1040 struct ieee80211_vif *wow_vif; 1041 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1042 u8 txpause; 1043 u8 pattern_cnt; 1044 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1045 1046 bool ips_enabled; 1047 struct rtw_pno_request pno_req; 1048 }; 1049 1050 struct rtw_intf_phy_para_table { 1051 const struct rtw_intf_phy_para *usb2_para; 1052 const struct rtw_intf_phy_para *usb3_para; 1053 const struct rtw_intf_phy_para *gen1_para; 1054 const struct rtw_intf_phy_para *gen2_para; 1055 u8 n_usb2_para; 1056 u8 n_usb3_para; 1057 u8 n_gen1_para; 1058 u8 n_gen2_para; 1059 }; 1060 1061 struct rtw_table { 1062 const void *data; 1063 const u32 size; 1064 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1065 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1066 u32 addr, u32 data); 1067 enum rtw_rf_path rf_path; 1068 }; 1069 1070 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1071 const struct rtw_table *tbl) 1072 { 1073 (*tbl->parse)(rtwdev, tbl); 1074 } 1075 1076 enum rtw_rfe_fem { 1077 RTW_RFE_IFEM, 1078 RTW_RFE_EFEM, 1079 RTW_RFE_IFEM2G_EFEM5G, 1080 RTW_RFE_NUM, 1081 }; 1082 1083 struct rtw_rfe_def { 1084 const struct rtw_table *phy_pg_tbl; 1085 const struct rtw_table *txpwr_lmt_tbl; 1086 const struct rtw_table *agc_btg_tbl; 1087 }; 1088 1089 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1090 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1091 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1092 } 1093 1094 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1095 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1096 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1097 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1098 } 1099 1100 #define RTW_PWR_TRK_5G_1 0 1101 #define RTW_PWR_TRK_5G_2 1 1102 #define RTW_PWR_TRK_5G_3 2 1103 #define RTW_PWR_TRK_5G_NUM 3 1104 1105 #define RTW_PWR_TRK_TBL_SZ 30 1106 1107 /* This table stores the values of TX power that will be adjusted by power 1108 * tracking. 1109 * 1110 * For 5G bands, there are 3 different settings. 1111 * For 2G there are cck rate and ofdm rate with different settings. 1112 */ 1113 struct rtw_pwr_track_tbl { 1114 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1115 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1116 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1117 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1118 const u8 *pwrtrk_2gb_n; 1119 const u8 *pwrtrk_2gb_p; 1120 const u8 *pwrtrk_2ga_n; 1121 const u8 *pwrtrk_2ga_p; 1122 const u8 *pwrtrk_2g_cckb_n; 1123 const u8 *pwrtrk_2g_cckb_p; 1124 const u8 *pwrtrk_2g_ccka_n; 1125 const u8 *pwrtrk_2g_ccka_p; 1126 const s8 *pwrtrk_xtal_n; 1127 const s8 *pwrtrk_xtal_p; 1128 }; 1129 1130 enum rtw_wlan_cpu { 1131 RTW_WCPU_11AC, 1132 RTW_WCPU_11N, 1133 }; 1134 1135 enum rtw_fw_fifo_sel { 1136 RTW_FW_FIFO_SEL_TX, 1137 RTW_FW_FIFO_SEL_RX, 1138 RTW_FW_FIFO_SEL_RSVD_PAGE, 1139 RTW_FW_FIFO_SEL_REPORT, 1140 RTW_FW_FIFO_SEL_LLT, 1141 RTW_FW_FIFO_SEL_RXBUF_FW, 1142 1143 RTW_FW_FIFO_MAX, 1144 }; 1145 1146 enum rtw_fwcd_item { 1147 RTW_FWCD_TLV, 1148 RTW_FWCD_REG, 1149 RTW_FWCD_ROM, 1150 RTW_FWCD_IMEM, 1151 RTW_FWCD_DMEM, 1152 RTW_FWCD_EMEM, 1153 }; 1154 1155 /* hardware configuration for each IC */ 1156 struct rtw_chip_info { 1157 struct rtw_chip_ops *ops; 1158 u8 id; 1159 1160 const char *fw_name; 1161 enum rtw_wlan_cpu wlan_cpu; 1162 u8 tx_pkt_desc_sz; 1163 u8 tx_buf_desc_sz; 1164 u8 rx_pkt_desc_sz; 1165 u8 rx_buf_desc_sz; 1166 u32 phy_efuse_size; 1167 u32 log_efuse_size; 1168 u32 ptct_efuse_size; 1169 u32 txff_size; 1170 u32 rxff_size; 1171 u32 fw_rxff_size; 1172 u8 band; 1173 u8 page_size; 1174 u8 csi_buf_pg_num; 1175 u8 dig_max; 1176 u8 dig_min; 1177 u8 txgi_factor; 1178 bool is_pwr_by_rate_dec; 1179 bool rx_ldpc; 1180 bool tx_stbc; 1181 u8 max_power_index; 1182 1183 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1184 const struct rtw_fwcd_segs *fwcd_segs; 1185 1186 u8 default_1ss_tx_path; 1187 1188 bool path_div_supported; 1189 bool ht_supported; 1190 bool vht_supported; 1191 u8 lps_deep_mode_supported; 1192 1193 /* init values */ 1194 u8 sys_func_en; 1195 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1196 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1197 const struct rtw_rqpn *rqpn_table; 1198 const struct rtw_prioq_addrs *prioq_addrs; 1199 const struct rtw_page_table *page_table; 1200 const struct rtw_intf_phy_para_table *intf_table; 1201 1202 const struct rtw_hw_reg *dig; 1203 const struct rtw_hw_reg *dig_cck; 1204 u32 rf_base_addr[2]; 1205 u32 rf_sipi_addr[2]; 1206 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1207 u8 fix_rf_phy_num; 1208 const struct rtw_ltecoex_addr *ltecoex_addr; 1209 1210 const struct rtw_table *mac_tbl; 1211 const struct rtw_table *agc_tbl; 1212 const struct rtw_table *bb_tbl; 1213 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1214 const struct rtw_table *rfk_init_tbl; 1215 1216 const struct rtw_rfe_def *rfe_defs; 1217 u32 rfe_defs_size; 1218 1219 bool en_dis_dpd; 1220 u16 dpd_ratemask; 1221 u8 iqk_threshold; 1222 u8 lck_threshold; 1223 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1224 1225 u8 bfer_su_max_num; 1226 u8 bfer_mu_max_num; 1227 1228 struct rtw_hw_reg_offset *edcca_th; 1229 s8 l2h_th_ini_cs; 1230 s8 l2h_th_ini_ad; 1231 1232 const char *wow_fw_name; 1233 const struct wiphy_wowlan_support *wowlan_stub; 1234 const u8 max_sched_scan_ssids; 1235 1236 /* for 8821c set channel */ 1237 u32 ch_param[3]; 1238 1239 /* coex paras */ 1240 u32 coex_para_ver; 1241 u8 bt_desired_ver; 1242 bool scbd_support; 1243 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1244 bool ble_hid_profile_support; 1245 bool wl_mimo_ps_support; 1246 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1247 u8 bt_rssi_type; 1248 u8 ant_isolation; 1249 u8 rssi_tolerance; 1250 u8 table_sant_num; 1251 u8 table_nsant_num; 1252 u8 tdma_sant_num; 1253 u8 tdma_nsant_num; 1254 u8 bt_afh_span_bw20; 1255 u8 bt_afh_span_bw40; 1256 u8 afh_5g_num; 1257 u8 wl_rf_para_num; 1258 u8 coex_info_hw_regs_num; 1259 const u8 *bt_rssi_step; 1260 const u8 *wl_rssi_step; 1261 const struct coex_table_para *table_nsant; 1262 const struct coex_table_para *table_sant; 1263 const struct coex_tdma_para *tdma_sant; 1264 const struct coex_tdma_para *tdma_nsant; 1265 const struct coex_rf_para *wl_rf_para_tx; 1266 const struct coex_rf_para *wl_rf_para_rx; 1267 const struct coex_5g_afh_map *afh_5g; 1268 const struct rtw_hw_reg *btg_reg; 1269 const struct rtw_reg_domain *coex_info_hw_regs; 1270 u32 wl_fw_desired_ver; 1271 }; 1272 1273 enum rtw_coex_bt_state_cnt { 1274 COEX_CNT_BT_RETRY, 1275 COEX_CNT_BT_REINIT, 1276 COEX_CNT_BT_REENABLE, 1277 COEX_CNT_BT_POPEVENT, 1278 COEX_CNT_BT_SETUPLINK, 1279 COEX_CNT_BT_IGNWLANACT, 1280 COEX_CNT_BT_INQ, 1281 COEX_CNT_BT_PAGE, 1282 COEX_CNT_BT_ROLESWITCH, 1283 COEX_CNT_BT_AFHUPDATE, 1284 COEX_CNT_BT_INFOUPDATE, 1285 COEX_CNT_BT_IQK, 1286 COEX_CNT_BT_IQKFAIL, 1287 1288 COEX_CNT_BT_MAX 1289 }; 1290 1291 enum rtw_coex_wl_state_cnt { 1292 COEX_CNT_WL_SCANAP, 1293 COEX_CNT_WL_CONNPKT, 1294 COEX_CNT_WL_COEXRUN, 1295 COEX_CNT_WL_NOISY0, 1296 COEX_CNT_WL_NOISY1, 1297 COEX_CNT_WL_NOISY2, 1298 COEX_CNT_WL_5MS_NOEXTEND, 1299 COEX_CNT_WL_FW_NOTIFY, 1300 1301 COEX_CNT_WL_MAX 1302 }; 1303 1304 struct rtw_coex_rfe { 1305 bool ant_switch_exist; 1306 bool ant_switch_diversity; 1307 bool ant_switch_with_bt; 1308 u8 rfe_module_type; 1309 u8 ant_switch_polarity; 1310 1311 /* true if WLG at BTG, else at WLAG */ 1312 bool wlg_at_btg; 1313 }; 1314 1315 #define COEX_WL_TDMA_PARA_LENGTH 5 1316 1317 struct rtw_coex_dm { 1318 bool cur_ps_tdma_on; 1319 bool cur_wl_rx_low_gain_en; 1320 bool ignore_wl_act; 1321 1322 u8 reason; 1323 u8 bt_rssi_state[4]; 1324 u8 wl_rssi_state[4]; 1325 u8 wl_ch_info[3]; 1326 u8 cur_ps_tdma; 1327 u8 cur_table; 1328 u8 ps_tdma_para[5]; 1329 u8 cur_bt_pwr_lvl; 1330 u8 cur_bt_lna_lvl; 1331 u8 cur_wl_pwr_lvl; 1332 u8 bt_status; 1333 u32 cur_ant_pos_type; 1334 u32 cur_switch_status; 1335 u32 setting_tdma; 1336 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1337 }; 1338 1339 #define COEX_BTINFO_SRC_WL_FW 0x0 1340 #define COEX_BTINFO_SRC_BT_RSP 0x1 1341 #define COEX_BTINFO_SRC_BT_ACT 0x2 1342 #define COEX_BTINFO_SRC_BT_IQK 0x3 1343 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1344 #define COEX_BTINFO_SRC_H2C60 0x5 1345 #define COEX_BTINFO_SRC_MAX 0x6 1346 1347 #define COEX_INFO_FTP BIT(7) 1348 #define COEX_INFO_A2DP BIT(6) 1349 #define COEX_INFO_HID BIT(5) 1350 #define COEX_INFO_SCO_BUSY BIT(4) 1351 #define COEX_INFO_ACL_BUSY BIT(3) 1352 #define COEX_INFO_INQ_PAGE BIT(2) 1353 #define COEX_INFO_SCO_ESCO BIT(1) 1354 #define COEX_INFO_CONNECTION BIT(0) 1355 #define COEX_BTINFO_LENGTH_MAX 10 1356 #define COEX_BTINFO_LENGTH 7 1357 1358 #define COEX_BT_HIDINFO_LIST 0x0 1359 #define COEX_BT_HIDINFO_A 0x1 1360 #define COEX_BT_HIDINFO_NAME 3 1361 1362 #define COEX_BT_HIDINFO_LENGTH 6 1363 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1364 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1365 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1366 #define COEX_BT_BLE_HANDLE_THRS 0x10 1367 #define COEX_BT_HIDINFO_NOTCON 0xff 1368 1369 struct rtw_coex_hid { 1370 u8 hid_handle; 1371 u8 hid_vendor; 1372 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1373 bool hid_info_completed; 1374 bool is_game_hid; 1375 }; 1376 1377 struct rtw_coex_hid_handle_list { 1378 u8 cmd_id; 1379 u8 len; 1380 u8 subid; 1381 u8 handle_cnt; 1382 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1383 } __packed; 1384 1385 struct rtw_coex_hid_info_a { 1386 u8 cmd_id; 1387 u8 len; 1388 u8 subid; 1389 u8 handle; 1390 u8 vendor; 1391 u8 name[COEX_BT_HIDINFO_NAME]; 1392 } __packed; 1393 1394 struct rtw_coex_stat { 1395 bool bt_disabled; 1396 bool bt_disabled_pre; 1397 bool bt_link_exist; 1398 bool bt_whck_test; 1399 bool bt_inq_page; 1400 bool bt_inq_remain; 1401 bool bt_inq; 1402 bool bt_page; 1403 bool bt_ble_voice; 1404 bool bt_ble_exist; 1405 bool bt_hfp_exist; 1406 bool bt_a2dp_exist; 1407 bool bt_hid_exist; 1408 bool bt_pan_exist; /* PAN or OPP */ 1409 bool bt_opp_exist; /* OPP only */ 1410 bool bt_acl_busy; 1411 bool bt_fix_2M; 1412 bool bt_setup_link; 1413 bool bt_multi_link; 1414 bool bt_multi_link_pre; 1415 bool bt_multi_link_remain; 1416 bool bt_a2dp_sink; 1417 bool bt_a2dp_active; 1418 bool bt_reenable; 1419 bool bt_ble_scan_en; 1420 bool bt_init_scan; 1421 bool bt_slave; 1422 bool bt_418_hid_exist; 1423 bool bt_ble_hid_exist; 1424 bool bt_game_hid_exist; 1425 bool bt_hid_handle_cnt; 1426 bool bt_mailbox_reply; 1427 1428 bool wl_under_lps; 1429 bool wl_under_ips; 1430 bool wl_hi_pri_task1; 1431 bool wl_hi_pri_task2; 1432 bool wl_force_lps_ctrl; 1433 bool wl_gl_busy; 1434 bool wl_linkscan_proc; 1435 bool wl_ps_state_fail; 1436 bool wl_tx_limit_en; 1437 bool wl_ampdu_limit_en; 1438 bool wl_connected; 1439 bool wl_slot_extend; 1440 bool wl_cck_lock; 1441 bool wl_cck_lock_pre; 1442 bool wl_cck_lock_ever; 1443 bool wl_connecting; 1444 bool wl_slot_toggle; 1445 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1446 bool wl_mimo_ps; 1447 1448 u32 bt_supported_version; 1449 u32 bt_supported_feature; 1450 u32 hi_pri_tx; 1451 u32 hi_pri_rx; 1452 u32 lo_pri_tx; 1453 u32 lo_pri_rx; 1454 u32 patch_ver; 1455 u16 bt_reg_vendor_ae; 1456 u16 bt_reg_vendor_ac; 1457 s8 bt_rssi; 1458 u8 kt_ver; 1459 u8 gnt_workaround_state; 1460 u8 tdma_timer_base; 1461 u8 bt_profile_num; 1462 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1463 u8 bt_info_lb2; 1464 u8 bt_info_lb3; 1465 u8 bt_info_hb0; 1466 u8 bt_info_hb1; 1467 u8 bt_info_hb2; 1468 u8 bt_info_hb3; 1469 u8 bt_ble_scan_type; 1470 u8 bt_hid_pair_num; 1471 u8 bt_hid_slot; 1472 u8 bt_a2dp_bitpool; 1473 u8 bt_iqk_state; 1474 1475 u16 wl_beacon_interval; 1476 u8 wl_noisy_level; 1477 u8 wl_fw_dbg_info[10]; 1478 u8 wl_fw_dbg_info_pre[10]; 1479 u8 wl_rx_rate; 1480 u8 wl_tx_rate; 1481 u8 wl_rts_rx_rate; 1482 u8 wl_coex_mode; 1483 u8 wl_iot_peer; 1484 u8 ampdu_max_time; 1485 u8 wl_tput_dir; 1486 1487 u8 wl_toggle_para[6]; 1488 u8 wl_toggle_interval; 1489 1490 u16 score_board; 1491 u16 retry_limit; 1492 1493 /* counters to record bt states */ 1494 u32 cnt_bt[COEX_CNT_BT_MAX]; 1495 1496 /* counters to record wifi states */ 1497 u32 cnt_wl[COEX_CNT_WL_MAX]; 1498 1499 /* counters to record bt c2h data */ 1500 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1501 1502 u32 darfrc; 1503 u32 darfrch; 1504 1505 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1506 struct rtw_coex_hid_handle_list hid_handle_list; 1507 }; 1508 1509 struct rtw_coex { 1510 /* protects coex info request section */ 1511 struct mutex mutex; 1512 struct sk_buff_head queue; 1513 wait_queue_head_t wait; 1514 1515 bool under_5g; 1516 bool stop_dm; 1517 bool freeze; 1518 bool freerun; 1519 bool wl_rf_off; 1520 bool manual_control; 1521 1522 struct rtw_coex_stat stat; 1523 struct rtw_coex_dm dm; 1524 struct rtw_coex_rfe rfe; 1525 1526 struct delayed_work bt_relink_work; 1527 struct delayed_work bt_reenable_work; 1528 struct delayed_work defreeze_work; 1529 struct delayed_work wl_remain_work; 1530 struct delayed_work bt_remain_work; 1531 struct delayed_work wl_connecting_work; 1532 struct delayed_work bt_multi_link_remain_work; 1533 struct delayed_work wl_ccklock_work; 1534 1535 }; 1536 1537 #define DPK_RF_REG_NUM 7 1538 #define DPK_RF_PATH_NUM 2 1539 #define DPK_BB_REG_NUM 18 1540 #define DPK_CHANNEL_WIDTH_80 1 1541 1542 DECLARE_EWMA(thermal, 10, 4); 1543 1544 struct rtw_dpk_info { 1545 bool is_dpk_pwr_on; 1546 bool is_reload; 1547 1548 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1549 1550 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1551 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1552 1553 u32 gnt_control; 1554 u32 gnt_value; 1555 1556 u8 result[RTW_RF_PATH_MAX]; 1557 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1558 u32 coef[RTW_RF_PATH_MAX][20]; 1559 u16 dpk_gs[RTW_RF_PATH_MAX]; 1560 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1561 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1562 1563 u8 dpk_band; 1564 u8 dpk_ch; 1565 u8 dpk_bw; 1566 }; 1567 1568 struct rtw_phy_cck_pd_reg { 1569 u32 reg_pd; 1570 u32 mask_pd; 1571 u32 reg_cs; 1572 u32 mask_cs; 1573 }; 1574 1575 #define DACK_MSBK_BACKUP_NUM 0xf 1576 #define DACK_DCK_BACKUP_NUM 0x2 1577 1578 struct rtw_swing_table { 1579 const u8 *p[RTW_RF_PATH_MAX]; 1580 const u8 *n[RTW_RF_PATH_MAX]; 1581 }; 1582 1583 struct rtw_pkt_count { 1584 u16 num_bcn_pkt; 1585 u16 num_qry_pkt[DESC_RATE_MAX]; 1586 }; 1587 1588 DECLARE_EWMA(evm, 10, 4); 1589 DECLARE_EWMA(snr, 10, 4); 1590 1591 struct rtw_iqk_info { 1592 bool done; 1593 struct { 1594 u32 s1_x; 1595 u32 s1_y; 1596 u32 s0_x; 1597 u32 s0_y; 1598 } result; 1599 }; 1600 1601 enum rtw_rf_band { 1602 RF_BAND_2G_CCK, 1603 RF_BAND_2G_OFDM, 1604 RF_BAND_5G_L, 1605 RF_BAND_5G_M, 1606 RF_BAND_5G_H, 1607 RF_BAND_MAX 1608 }; 1609 1610 #define RF_GAIN_NUM 11 1611 #define RF_HW_OFFSET_NUM 10 1612 1613 struct rtw_gapk_info { 1614 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1615 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1616 bool txgapk_bp_done; 1617 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1618 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1619 u8 read_txgain; 1620 u8 channel; 1621 }; 1622 1623 #define EDCCA_TH_L2H_IDX 0 1624 #define EDCCA_TH_H2L_IDX 1 1625 #define EDCCA_TH_L2H_LB 48 1626 #define EDCCA_ADC_BACKOFF 12 1627 #define EDCCA_IGI_BASE 50 1628 #define EDCCA_IGI_L2H_DIFF 8 1629 #define EDCCA_L2H_H2L_DIFF 7 1630 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1631 1632 enum rtw_edcca_mode { 1633 RTW_EDCCA_NORMAL = 0, 1634 RTW_EDCCA_ADAPTIVITY = 1, 1635 }; 1636 1637 struct rtw_cfo_track { 1638 bool is_adjust; 1639 u8 crystal_cap; 1640 s32 cfo_tail[RTW_RF_PATH_MAX]; 1641 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1642 u32 packet_count; 1643 u32 packet_count_pre; 1644 }; 1645 1646 #define RRSR_INIT_2G 0x15f 1647 #define RRSR_INIT_5G 0x150 1648 1649 enum rtw_dm_cap { 1650 RTW_DM_CAP_NA, 1651 RTW_DM_CAP_TXGAPK, 1652 RTW_DM_CAP_NUM 1653 }; 1654 1655 struct rtw_dm_info { 1656 u32 cck_fa_cnt; 1657 u32 ofdm_fa_cnt; 1658 u32 total_fa_cnt; 1659 u32 cck_cca_cnt; 1660 u32 ofdm_cca_cnt; 1661 u32 total_cca_cnt; 1662 1663 u32 cck_ok_cnt; 1664 u32 cck_err_cnt; 1665 u32 ofdm_ok_cnt; 1666 u32 ofdm_err_cnt; 1667 u32 ht_ok_cnt; 1668 u32 ht_err_cnt; 1669 u32 vht_ok_cnt; 1670 u32 vht_err_cnt; 1671 1672 u8 min_rssi; 1673 u8 pre_min_rssi; 1674 u16 fa_history[4]; 1675 u8 igi_history[4]; 1676 u8 igi_bitmap; 1677 bool damping; 1678 u8 damping_cnt; 1679 u8 damping_rssi; 1680 1681 u8 cck_gi_u_bnd; 1682 u8 cck_gi_l_bnd; 1683 1684 u8 fix_rate; 1685 u8 tx_rate; 1686 u32 rrsr_val_init; 1687 u32 rrsr_mask_min; 1688 u8 thermal_avg[RTW_RF_PATH_MAX]; 1689 u8 thermal_meter_k; 1690 u8 thermal_meter_lck; 1691 s8 delta_power_index[RTW_RF_PATH_MAX]; 1692 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1693 u8 default_ofdm_index; 1694 bool pwr_trk_triggered; 1695 bool pwr_trk_init_trigger; 1696 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1697 s8 txagc_remnant_cck; 1698 s8 txagc_remnant_ofdm; 1699 1700 /* backup dack results for each path and I/Q */ 1701 u32 dack_adck[RTW_RF_PATH_MAX]; 1702 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1703 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1704 1705 struct rtw_dpk_info dpk_info; 1706 struct rtw_cfo_track cfo_track; 1707 1708 /* [bandwidth 0:20M/1:40M][number of path] */ 1709 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1710 u32 cck_fa_avg; 1711 u8 cck_pd_default; 1712 1713 /* save the last rx phy status for debug */ 1714 s8 rx_snr[RTW_RF_PATH_MAX]; 1715 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1716 s16 cfo_tail[RTW_RF_PATH_MAX]; 1717 u8 rssi[RTW_RF_PATH_MAX]; 1718 u8 curr_rx_rate; 1719 struct rtw_pkt_count cur_pkt_count; 1720 struct rtw_pkt_count last_pkt_count; 1721 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1722 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1723 1724 u32 dm_flags; /* enum rtw_dm_cap */ 1725 struct rtw_iqk_info iqk; 1726 struct rtw_gapk_info gapk; 1727 bool is_bt_iqk_timeout; 1728 1729 s8 l2h_th_ini; 1730 enum rtw_edcca_mode edcca_mode; 1731 u8 scan_density; 1732 }; 1733 1734 struct rtw_efuse { 1735 u32 size; 1736 u32 physical_size; 1737 u32 logical_size; 1738 u32 protect_size; 1739 1740 u8 addr[ETH_ALEN]; 1741 u8 channel_plan; 1742 u8 country_code[2]; 1743 u8 rf_board_option; 1744 u8 rfe_option; 1745 u8 power_track_type; 1746 u8 thermal_meter[RTW_RF_PATH_MAX]; 1747 u8 thermal_meter_k; 1748 u8 crystal_cap; 1749 u8 ant_div_cfg; 1750 u8 ant_div_type; 1751 u8 regd; 1752 u8 afe; 1753 1754 u8 lna_type_2g; 1755 u8 lna_type_5g; 1756 u8 glna_type; 1757 u8 alna_type; 1758 bool ext_lna_2g; 1759 bool ext_lna_5g; 1760 u8 pa_type_2g; 1761 u8 pa_type_5g; 1762 u8 gpa_type; 1763 u8 apa_type; 1764 bool ext_pa_2g; 1765 bool ext_pa_5g; 1766 u8 tx_bb_swing_setting_2g; 1767 u8 tx_bb_swing_setting_5g; 1768 1769 bool btcoex; 1770 /* bt share antenna with wifi */ 1771 bool share_ant; 1772 u8 bt_setting; 1773 1774 struct { 1775 u8 hci; 1776 u8 bw; 1777 u8 ptcl; 1778 u8 nss; 1779 u8 ant_num; 1780 } hw_cap; 1781 1782 struct rtw_txpwr_idx txpwr_idx_table[4]; 1783 }; 1784 1785 struct rtw_phy_cond { 1786 #ifdef __LITTLE_ENDIAN 1787 u32 rfe:8; 1788 u32 intf:4; 1789 u32 pkg:4; 1790 u32 plat:4; 1791 u32 intf_rsvd:4; 1792 u32 cut:4; 1793 u32 branch:2; 1794 u32 neg:1; 1795 u32 pos:1; 1796 #else 1797 u32 pos:1; 1798 u32 neg:1; 1799 u32 branch:2; 1800 u32 cut:4; 1801 u32 intf_rsvd:4; 1802 u32 plat:4; 1803 u32 pkg:4; 1804 u32 intf:4; 1805 u32 rfe:8; 1806 #endif 1807 /* for intf:4 */ 1808 #define INTF_PCIE BIT(0) 1809 #define INTF_USB BIT(1) 1810 #define INTF_SDIO BIT(2) 1811 /* for branch:2 */ 1812 #define BRANCH_IF 0 1813 #define BRANCH_ELIF 1 1814 #define BRANCH_ELSE 2 1815 #define BRANCH_ENDIF 3 1816 }; 1817 1818 struct rtw_fifo_conf { 1819 /* tx fifo information */ 1820 u16 rsvd_boundary; 1821 u16 rsvd_pg_num; 1822 u16 rsvd_drv_pg_num; 1823 u16 txff_pg_num; 1824 u16 acq_pg_num; 1825 u16 rsvd_drv_addr; 1826 u16 rsvd_h2c_info_addr; 1827 u16 rsvd_h2c_sta_info_addr; 1828 u16 rsvd_h2cq_addr; 1829 u16 rsvd_cpu_instr_addr; 1830 u16 rsvd_fw_txbuf_addr; 1831 u16 rsvd_csibuf_addr; 1832 const struct rtw_rqpn *rqpn; 1833 }; 1834 1835 struct rtw_fwcd_desc { 1836 u32 size; 1837 u8 *next; 1838 u8 *data; 1839 }; 1840 1841 struct rtw_fwcd_segs { 1842 const u32 *segs; 1843 u8 num; 1844 }; 1845 1846 #define FW_CD_TYPE 0xffff 1847 #define FW_CD_LEN 4 1848 #define FW_CD_VAL 0xaabbccdd 1849 struct rtw_fw_state { 1850 const struct firmware *firmware; 1851 struct rtw_dev *rtwdev; 1852 struct completion completion; 1853 struct rtw_fwcd_desc fwcd_desc; 1854 u16 version; 1855 u8 sub_version; 1856 u8 sub_index; 1857 u16 h2c_version; 1858 u32 feature; 1859 }; 1860 1861 enum rtw_sar_sources { 1862 RTW_SAR_SOURCE_NONE, 1863 RTW_SAR_SOURCE_COMMON, 1864 }; 1865 1866 enum rtw_sar_bands { 1867 RTW_SAR_BAND_0, 1868 RTW_SAR_BAND_1, 1869 /* RTW_SAR_BAND_2, not used now */ 1870 RTW_SAR_BAND_3, 1871 RTW_SAR_BAND_4, 1872 1873 RTW_SAR_BAND_NR, 1874 }; 1875 1876 /* the union is reserved for other knids of SAR sources 1877 * which might not re-use same format with array common. 1878 */ 1879 union rtw_sar_cfg { 1880 s8 common[RTW_SAR_BAND_NR]; 1881 }; 1882 1883 struct rtw_sar { 1884 enum rtw_sar_sources src; 1885 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1886 }; 1887 1888 struct rtw_hal { 1889 u32 rcr; 1890 1891 u32 chip_version; 1892 u8 cut_version; 1893 u8 mp_chip; 1894 u8 oem_id; 1895 struct rtw_phy_cond phy_cond; 1896 1897 u8 ps_mode; 1898 u8 current_channel; 1899 u8 current_primary_channel_index; 1900 u8 current_band_width; 1901 u8 current_band_type; 1902 1903 /* center channel for different available bandwidth, 1904 * val of (bw > current_band_width) is invalid 1905 */ 1906 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1907 1908 u8 sec_ch_offset; 1909 u8 rf_type; 1910 u8 rf_path_num; 1911 u8 rf_phy_num; 1912 u32 antenna_tx; 1913 u32 antenna_rx; 1914 u8 bfee_sts_cap; 1915 bool txrx_1ss; 1916 1917 /* protect tx power section */ 1918 struct mutex tx_power_mutex; 1919 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1920 [DESC_RATE_MAX]; 1921 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1922 [DESC_RATE_MAX]; 1923 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1924 [RTW_RATE_SECTION_MAX]; 1925 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1926 [RTW_RATE_SECTION_MAX]; 1927 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1928 [RTW_CHANNEL_WIDTH_MAX] 1929 [RTW_RATE_SECTION_MAX] 1930 [RTW_MAX_CHANNEL_NUM_2G]; 1931 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1932 [RTW_CHANNEL_WIDTH_MAX] 1933 [RTW_RATE_SECTION_MAX] 1934 [RTW_MAX_CHANNEL_NUM_5G]; 1935 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1936 [DESC_RATE_MAX]; 1937 1938 enum rtw_sar_bands sar_band; 1939 struct rtw_sar sar; 1940 }; 1941 1942 struct rtw_path_div { 1943 enum rtw_bb_path current_tx_path; 1944 u32 path_a_sum; 1945 u32 path_b_sum; 1946 u16 path_a_cnt; 1947 u16 path_b_cnt; 1948 }; 1949 1950 struct rtw_chan_info { 1951 int pri_ch_idx; 1952 int action_id; 1953 int bw; 1954 u8 extra_info; 1955 u8 channel; 1956 u16 timeout; 1957 }; 1958 1959 struct rtw_chan_list { 1960 u32 buf_size; 1961 u32 ch_num; 1962 u32 size; 1963 u16 addr; 1964 }; 1965 1966 struct rtw_hw_scan_info { 1967 struct ieee80211_vif *scanning_vif; 1968 u8 probe_pg_size; 1969 u8 op_pri_ch_idx; 1970 u8 op_chan; 1971 u8 op_bw; 1972 }; 1973 1974 struct rtw_dev { 1975 struct ieee80211_hw *hw; 1976 struct device *dev; 1977 1978 struct rtw_hci hci; 1979 1980 struct rtw_hw_scan_info scan_info; 1981 struct rtw_chip_info *chip; 1982 struct rtw_hal hal; 1983 struct rtw_fifo_conf fifo; 1984 struct rtw_fw_state fw; 1985 struct rtw_efuse efuse; 1986 struct rtw_sec_desc sec; 1987 struct rtw_traffic_stats stats; 1988 struct rtw_regd regd; 1989 struct rtw_bf_info bf_info; 1990 1991 struct rtw_dm_info dm_info; 1992 struct rtw_coex coex; 1993 1994 /* ensures exclusive access from mac80211 callbacks */ 1995 struct mutex mutex; 1996 1997 /* read/write rf register */ 1998 spinlock_t rf_lock; 1999 2000 /* watch dog every 2 sec */ 2001 struct delayed_work watch_dog_work; 2002 u32 watch_dog_cnt; 2003 2004 struct list_head rsvd_page_list; 2005 2006 /* c2h cmd queue & handler work */ 2007 struct sk_buff_head c2h_queue; 2008 struct work_struct c2h_work; 2009 struct work_struct ips_work; 2010 struct work_struct fw_recovery_work; 2011 2012 /* used to protect txqs list */ 2013 spinlock_t txq_lock; 2014 struct list_head txqs; 2015 struct workqueue_struct *tx_wq; 2016 struct work_struct tx_work; 2017 struct work_struct ba_work; 2018 2019 struct rtw_tx_report tx_report; 2020 2021 struct { 2022 /* incicate the mail box to use with fw */ 2023 u8 last_box_num; 2024 /* protect to send h2c to fw */ 2025 spinlock_t lock; 2026 u32 seq; 2027 } h2c; 2028 2029 /* lps power state & handler work */ 2030 struct rtw_lps_conf lps_conf; 2031 bool ps_enabled; 2032 bool beacon_loss; 2033 struct completion lps_leave_check; 2034 2035 struct dentry *debugfs; 2036 2037 u8 sta_cnt; 2038 u32 rts_threshold; 2039 2040 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2041 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2042 2043 u8 mp_mode; 2044 struct rtw_path_div dm_path_div; 2045 2046 struct rtw_fw_state wow_fw; 2047 struct rtw_wow_param wow; 2048 2049 bool need_rfk; 2050 struct completion fw_scan_density; 2051 2052 /* hci related data, must be last */ 2053 u8 priv[] __aligned(sizeof(void *)); 2054 }; 2055 2056 #include "hci.h" 2057 2058 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2059 { 2060 return !!rtwdev->sta_cnt; 2061 } 2062 2063 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2064 { 2065 void *p = rtwtxq; 2066 2067 return container_of(p, struct ieee80211_txq, drv_priv); 2068 } 2069 2070 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2071 { 2072 void *p = rtwvif; 2073 2074 return container_of(p, struct ieee80211_vif, drv_priv); 2075 } 2076 2077 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 2078 struct cfg80211_ssid *b) 2079 { 2080 if (!a || !b || a->ssid_len != b->ssid_len) 2081 return false; 2082 2083 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 2084 return false; 2085 2086 return true; 2087 } 2088 2089 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2090 { 2091 if (rtwdev->chip->ops->efuse_grant) 2092 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2093 } 2094 2095 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2096 { 2097 if (rtwdev->chip->ops->efuse_grant) 2098 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2099 } 2100 2101 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2102 { 2103 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2104 } 2105 2106 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2107 { 2108 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2109 } 2110 2111 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2112 { 2113 return rtwdev->chip->rx_ldpc; 2114 } 2115 2116 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2117 { 2118 return rtwdev->chip->tx_stbc; 2119 } 2120 2121 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2122 { 2123 clear_bit(mac_id, rtwdev->mac_id_map); 2124 } 2125 2126 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2127 { 2128 if (rtwdev->chip->ops->dump_fw_crash) 2129 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2130 2131 return 0; 2132 } 2133 2134 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2135 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2136 struct rtw_channel_params *ch_param); 2137 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2138 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2139 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2140 void rtw_restore_reg(struct rtw_dev *rtwdev, 2141 struct rtw_backup_info *bckp, u32 num); 2142 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2143 void rtw_set_channel(struct rtw_dev *rtwdev); 2144 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2145 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2146 u32 config); 2147 void rtw_tx_report_purge_timer(struct timer_list *t); 2148 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 2149 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2150 const u8 *mac_addr, bool hw_scan); 2151 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2152 bool hw_scan); 2153 int rtw_core_start(struct rtw_dev *rtwdev); 2154 void rtw_core_stop(struct rtw_dev *rtwdev); 2155 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2156 int rtw_core_init(struct rtw_dev *rtwdev); 2157 void rtw_core_deinit(struct rtw_dev *rtwdev); 2158 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2159 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2160 u16 rtw_desc_to_bitrate(u8 desc_rate); 2161 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2162 struct ieee80211_bss_conf *conf); 2163 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2164 struct ieee80211_vif *vif); 2165 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2166 bool fw_exist); 2167 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2168 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2169 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2170 u32 fwcd_item); 2171 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2172 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2173 #endif 2174