1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 15 #include "util.h" 16 17 #define RTW_MAX_MAC_ID_NUM 32 18 #define RTW_MAX_SEC_CAM_NUM 32 19 20 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 21 22 #define RFREG_MASK 0xfffff 23 #define INV_RF_DATA 0xffffffff 24 #define TX_PAGE_SIZE_SHIFT 7 25 26 #define RTW_CHANNEL_WIDTH_MAX 3 27 #define RTW_RF_PATH_MAX 4 28 #define HW_FEATURE_LEN 13 29 30 extern unsigned int rtw_debug_mask; 31 extern const struct ieee80211_ops rtw_ops; 32 extern struct rtw_chip_info rtw8822b_hw_spec; 33 extern struct rtw_chip_info rtw8822c_hw_spec; 34 35 #define RTW_MAX_CHANNEL_NUM_2G 14 36 #define RTW_MAX_CHANNEL_NUM_5G 49 37 38 struct rtw_dev; 39 40 enum rtw_hci_type { 41 RTW_HCI_TYPE_PCIE, 42 RTW_HCI_TYPE_USB, 43 RTW_HCI_TYPE_SDIO, 44 45 RTW_HCI_TYPE_UNDEFINE, 46 }; 47 48 struct rtw_hci { 49 struct rtw_hci_ops *ops; 50 enum rtw_hci_type type; 51 52 u32 rpwm_addr; 53 54 u8 bulkout_num; 55 }; 56 57 enum rtw_supported_band { 58 RTW_BAND_2G = 1 << 0, 59 RTW_BAND_5G = 1 << 1, 60 RTW_BAND_60G = 1 << 2, 61 62 RTW_BAND_MAX, 63 }; 64 65 /* now, support upto 80M bw */ 66 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 67 68 enum rtw_bandwidth { 69 RTW_CHANNEL_WIDTH_20 = 0, 70 RTW_CHANNEL_WIDTH_40 = 1, 71 RTW_CHANNEL_WIDTH_80 = 2, 72 RTW_CHANNEL_WIDTH_160 = 3, 73 RTW_CHANNEL_WIDTH_80_80 = 4, 74 RTW_CHANNEL_WIDTH_5 = 5, 75 RTW_CHANNEL_WIDTH_10 = 6, 76 }; 77 78 enum rtw_net_type { 79 RTW_NET_NO_LINK = 0, 80 RTW_NET_AD_HOC = 1, 81 RTW_NET_MGD_LINKED = 2, 82 RTW_NET_AP_MODE = 3, 83 }; 84 85 enum rtw_rf_type { 86 RF_1T1R = 0, 87 RF_1T2R = 1, 88 RF_2T2R = 2, 89 RF_2T3R = 3, 90 RF_2T4R = 4, 91 RF_3T3R = 5, 92 RF_3T4R = 6, 93 RF_4T4R = 7, 94 RF_TYPE_MAX, 95 }; 96 97 enum rtw_rf_path { 98 RF_PATH_A = 0, 99 RF_PATH_B = 1, 100 RF_PATH_C = 2, 101 RF_PATH_D = 3, 102 }; 103 104 enum rtw_bb_path { 105 BB_PATH_A = BIT(0), 106 BB_PATH_B = BIT(1), 107 BB_PATH_C = BIT(2), 108 BB_PATH_D = BIT(3), 109 110 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 111 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 112 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 113 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 114 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 115 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 116 117 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 118 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 119 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 120 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 121 122 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 123 }; 124 125 enum rtw_rate_section { 126 RTW_RATE_SECTION_CCK = 0, 127 RTW_RATE_SECTION_OFDM, 128 RTW_RATE_SECTION_HT_1S, 129 RTW_RATE_SECTION_HT_2S, 130 RTW_RATE_SECTION_VHT_1S, 131 RTW_RATE_SECTION_VHT_2S, 132 133 /* keep last */ 134 RTW_RATE_SECTION_MAX, 135 }; 136 137 enum rtw_wireless_set { 138 WIRELESS_CCK = 0x00000001, 139 WIRELESS_OFDM = 0x00000002, 140 WIRELESS_HT = 0x00000004, 141 WIRELESS_VHT = 0x00000008, 142 }; 143 144 #define HT_STBC_EN BIT(0) 145 #define VHT_STBC_EN BIT(1) 146 #define HT_LDPC_EN BIT(0) 147 #define VHT_LDPC_EN BIT(1) 148 149 enum rtw_chip_type { 150 RTW_CHIP_TYPE_8822B, 151 RTW_CHIP_TYPE_8822C, 152 }; 153 154 enum rtw_tx_queue_type { 155 /* the order of AC queues matters */ 156 RTW_TX_QUEUE_BK = 0x0, 157 RTW_TX_QUEUE_BE = 0x1, 158 RTW_TX_QUEUE_VI = 0x2, 159 RTW_TX_QUEUE_VO = 0x3, 160 161 RTW_TX_QUEUE_BCN = 0x4, 162 RTW_TX_QUEUE_MGMT = 0x5, 163 RTW_TX_QUEUE_HI0 = 0x6, 164 RTW_TX_QUEUE_H2C = 0x7, 165 /* keep it last */ 166 RTK_MAX_TX_QUEUE_NUM 167 }; 168 169 enum rtw_rx_queue_type { 170 RTW_RX_QUEUE_MPDU = 0x0, 171 RTW_RX_QUEUE_C2H = 0x1, 172 /* keep it last */ 173 RTK_MAX_RX_QUEUE_NUM 174 }; 175 176 enum rtw_rate_index { 177 RTW_RATEID_BGN_40M_2SS = 0, 178 RTW_RATEID_BGN_40M_1SS = 1, 179 RTW_RATEID_BGN_20M_2SS = 2, 180 RTW_RATEID_BGN_20M_1SS = 3, 181 RTW_RATEID_GN_N2SS = 4, 182 RTW_RATEID_GN_N1SS = 5, 183 RTW_RATEID_BG = 6, 184 RTW_RATEID_G = 7, 185 RTW_RATEID_B_20M = 8, 186 RTW_RATEID_ARFR0_AC_2SS = 9, 187 RTW_RATEID_ARFR1_AC_1SS = 10, 188 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 189 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 190 RTW_RATEID_ARFR4_AC_3SS = 13, 191 RTW_RATEID_ARFR5_N_3SS = 14, 192 RTW_RATEID_ARFR7_N_4SS = 15, 193 RTW_RATEID_ARFR6_AC_4SS = 16 194 }; 195 196 enum rtw_trx_desc_rate { 197 DESC_RATE1M = 0x00, 198 DESC_RATE2M = 0x01, 199 DESC_RATE5_5M = 0x02, 200 DESC_RATE11M = 0x03, 201 202 DESC_RATE6M = 0x04, 203 DESC_RATE9M = 0x05, 204 DESC_RATE12M = 0x06, 205 DESC_RATE18M = 0x07, 206 DESC_RATE24M = 0x08, 207 DESC_RATE36M = 0x09, 208 DESC_RATE48M = 0x0a, 209 DESC_RATE54M = 0x0b, 210 211 DESC_RATEMCS0 = 0x0c, 212 DESC_RATEMCS1 = 0x0d, 213 DESC_RATEMCS2 = 0x0e, 214 DESC_RATEMCS3 = 0x0f, 215 DESC_RATEMCS4 = 0x10, 216 DESC_RATEMCS5 = 0x11, 217 DESC_RATEMCS6 = 0x12, 218 DESC_RATEMCS7 = 0x13, 219 DESC_RATEMCS8 = 0x14, 220 DESC_RATEMCS9 = 0x15, 221 DESC_RATEMCS10 = 0x16, 222 DESC_RATEMCS11 = 0x17, 223 DESC_RATEMCS12 = 0x18, 224 DESC_RATEMCS13 = 0x19, 225 DESC_RATEMCS14 = 0x1a, 226 DESC_RATEMCS15 = 0x1b, 227 DESC_RATEMCS16 = 0x1c, 228 DESC_RATEMCS17 = 0x1d, 229 DESC_RATEMCS18 = 0x1e, 230 DESC_RATEMCS19 = 0x1f, 231 DESC_RATEMCS20 = 0x20, 232 DESC_RATEMCS21 = 0x21, 233 DESC_RATEMCS22 = 0x22, 234 DESC_RATEMCS23 = 0x23, 235 DESC_RATEMCS24 = 0x24, 236 DESC_RATEMCS25 = 0x25, 237 DESC_RATEMCS26 = 0x26, 238 DESC_RATEMCS27 = 0x27, 239 DESC_RATEMCS28 = 0x28, 240 DESC_RATEMCS29 = 0x29, 241 DESC_RATEMCS30 = 0x2a, 242 DESC_RATEMCS31 = 0x2b, 243 244 DESC_RATEVHT1SS_MCS0 = 0x2c, 245 DESC_RATEVHT1SS_MCS1 = 0x2d, 246 DESC_RATEVHT1SS_MCS2 = 0x2e, 247 DESC_RATEVHT1SS_MCS3 = 0x2f, 248 DESC_RATEVHT1SS_MCS4 = 0x30, 249 DESC_RATEVHT1SS_MCS5 = 0x31, 250 DESC_RATEVHT1SS_MCS6 = 0x32, 251 DESC_RATEVHT1SS_MCS7 = 0x33, 252 DESC_RATEVHT1SS_MCS8 = 0x34, 253 DESC_RATEVHT1SS_MCS9 = 0x35, 254 255 DESC_RATEVHT2SS_MCS0 = 0x36, 256 DESC_RATEVHT2SS_MCS1 = 0x37, 257 DESC_RATEVHT2SS_MCS2 = 0x38, 258 DESC_RATEVHT2SS_MCS3 = 0x39, 259 DESC_RATEVHT2SS_MCS4 = 0x3a, 260 DESC_RATEVHT2SS_MCS5 = 0x3b, 261 DESC_RATEVHT2SS_MCS6 = 0x3c, 262 DESC_RATEVHT2SS_MCS7 = 0x3d, 263 DESC_RATEVHT2SS_MCS8 = 0x3e, 264 DESC_RATEVHT2SS_MCS9 = 0x3f, 265 266 DESC_RATEVHT3SS_MCS0 = 0x40, 267 DESC_RATEVHT3SS_MCS1 = 0x41, 268 DESC_RATEVHT3SS_MCS2 = 0x42, 269 DESC_RATEVHT3SS_MCS3 = 0x43, 270 DESC_RATEVHT3SS_MCS4 = 0x44, 271 DESC_RATEVHT3SS_MCS5 = 0x45, 272 DESC_RATEVHT3SS_MCS6 = 0x46, 273 DESC_RATEVHT3SS_MCS7 = 0x47, 274 DESC_RATEVHT3SS_MCS8 = 0x48, 275 DESC_RATEVHT3SS_MCS9 = 0x49, 276 277 DESC_RATEVHT4SS_MCS0 = 0x4a, 278 DESC_RATEVHT4SS_MCS1 = 0x4b, 279 DESC_RATEVHT4SS_MCS2 = 0x4c, 280 DESC_RATEVHT4SS_MCS3 = 0x4d, 281 DESC_RATEVHT4SS_MCS4 = 0x4e, 282 DESC_RATEVHT4SS_MCS5 = 0x4f, 283 DESC_RATEVHT4SS_MCS6 = 0x50, 284 DESC_RATEVHT4SS_MCS7 = 0x51, 285 DESC_RATEVHT4SS_MCS8 = 0x52, 286 DESC_RATEVHT4SS_MCS9 = 0x53, 287 288 DESC_RATE_MAX, 289 }; 290 291 enum rtw_regulatory_domains { 292 RTW_REGD_FCC = 0, 293 RTW_REGD_MKK = 1, 294 RTW_REGD_ETSI = 2, 295 RTW_REGD_IC = 3, 296 RTW_REGD_KCC = 4, 297 RTW_REGD_ACMA = 5, 298 RTW_REGD_CHILE = 6, 299 RTW_REGD_UKRAINE = 7, 300 RTW_REGD_MEXICO = 8, 301 RTW_REGD_WW, 302 303 RTW_REGD_MAX 304 }; 305 306 enum rtw_flags { 307 RTW_FLAG_RUNNING, 308 RTW_FLAG_FW_RUNNING, 309 RTW_FLAG_SCANNING, 310 RTW_FLAG_INACTIVE_PS, 311 RTW_FLAG_LEISURE_PS, 312 RTW_FLAG_DIG_DISABLE, 313 RTW_FLAG_BUSY_TRAFFIC, 314 315 NUM_OF_RTW_FLAGS, 316 }; 317 318 /* the power index is represented by differences, which cck-1s & ht40-1s are 319 * the base values, so for 1s's differences, there are only ht20 & ofdm 320 */ 321 struct rtw_2g_1s_pwr_idx_diff { 322 #ifdef __LITTLE_ENDIAN 323 s8 ofdm:4; 324 s8 bw20:4; 325 #else 326 s8 bw20:4; 327 s8 ofdm:4; 328 #endif 329 } __packed; 330 331 struct rtw_2g_ns_pwr_idx_diff { 332 #ifdef __LITTLE_ENDIAN 333 s8 bw20:4; 334 s8 bw40:4; 335 s8 cck:4; 336 s8 ofdm:4; 337 #else 338 s8 ofdm:4; 339 s8 cck:4; 340 s8 bw40:4; 341 s8 bw20:4; 342 #endif 343 } __packed; 344 345 struct rtw_2g_txpwr_idx { 346 u8 cck_base[6]; 347 u8 bw40_base[5]; 348 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 349 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 350 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 351 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 352 }; 353 354 struct rtw_5g_ht_1s_pwr_idx_diff { 355 #ifdef __LITTLE_ENDIAN 356 s8 ofdm:4; 357 s8 bw20:4; 358 #else 359 s8 bw20:4; 360 s8 ofdm:4; 361 #endif 362 } __packed; 363 364 struct rtw_5g_ht_ns_pwr_idx_diff { 365 #ifdef __LITTLE_ENDIAN 366 s8 bw20:4; 367 s8 bw40:4; 368 #else 369 s8 bw40:4; 370 s8 bw20:4; 371 #endif 372 } __packed; 373 374 struct rtw_5g_ofdm_ns_pwr_idx_diff { 375 #ifdef __LITTLE_ENDIAN 376 s8 ofdm_3s:4; 377 s8 ofdm_2s:4; 378 s8 ofdm_4s:4; 379 s8 res:4; 380 #else 381 s8 res:4; 382 s8 ofdm_4s:4; 383 s8 ofdm_2s:4; 384 s8 ofdm_3s:4; 385 #endif 386 } __packed; 387 388 struct rtw_5g_vht_ns_pwr_idx_diff { 389 #ifdef __LITTLE_ENDIAN 390 s8 bw160:4; 391 s8 bw80:4; 392 #else 393 s8 bw80:4; 394 s8 bw160:4; 395 #endif 396 } __packed; 397 398 struct rtw_5g_txpwr_idx { 399 u8 bw40_base[14]; 400 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 401 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 402 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 403 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 404 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 405 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 406 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 407 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 408 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 409 }; 410 411 struct rtw_txpwr_idx { 412 struct rtw_2g_txpwr_idx pwr_idx_2g; 413 struct rtw_5g_txpwr_idx pwr_idx_5g; 414 }; 415 416 struct rtw_timer_list { 417 struct timer_list timer; 418 void (*function)(void *data); 419 void *args; 420 }; 421 422 struct rtw_channel_params { 423 u8 center_chan; 424 u8 bandwidth; 425 u8 primary_chan_idx; 426 /* center channel by different available bandwidth, 427 * val of (bw > current bandwidth) is invalid 428 */ 429 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 430 }; 431 432 struct rtw_hw_reg { 433 u32 addr; 434 u32 mask; 435 }; 436 437 struct rtw_backup_info { 438 u8 len; 439 u32 reg; 440 u32 val; 441 }; 442 443 enum rtw_vif_port_set { 444 PORT_SET_MAC_ADDR = BIT(0), 445 PORT_SET_BSSID = BIT(1), 446 PORT_SET_NET_TYPE = BIT(2), 447 PORT_SET_AID = BIT(3), 448 PORT_SET_BCN_CTRL = BIT(4), 449 }; 450 451 struct rtw_vif_port { 452 struct rtw_hw_reg mac_addr; 453 struct rtw_hw_reg bssid; 454 struct rtw_hw_reg net_type; 455 struct rtw_hw_reg aid; 456 struct rtw_hw_reg bcn_ctrl; 457 }; 458 459 struct rtw_tx_pkt_info { 460 u32 tx_pkt_size; 461 u8 offset; 462 u8 pkt_offset; 463 u8 mac_id; 464 u8 rate_id; 465 u8 rate; 466 u8 qsel; 467 u8 bw; 468 u8 sec_type; 469 u8 sn; 470 bool ampdu_en; 471 u8 ampdu_factor; 472 u8 ampdu_density; 473 u16 seq; 474 bool stbc; 475 bool ldpc; 476 bool dis_rate_fallback; 477 bool bmc; 478 bool use_rate; 479 bool ls; 480 bool fs; 481 bool short_gi; 482 bool report; 483 }; 484 485 struct rtw_rx_pkt_stat { 486 bool phy_status; 487 bool icv_err; 488 bool crc_err; 489 bool decrypted; 490 bool is_c2h; 491 492 s32 signal_power; 493 u16 pkt_len; 494 u8 bw; 495 u8 drv_info_sz; 496 u8 shift; 497 u8 rate; 498 u8 mac_id; 499 u8 cam_id; 500 u8 ppdu_cnt; 501 u32 tsf_low; 502 s8 rx_power[RTW_RF_PATH_MAX]; 503 u8 rssi; 504 u8 rxsc; 505 struct rtw_sta_info *si; 506 struct ieee80211_vif *vif; 507 }; 508 509 struct rtw_traffic_stats { 510 /* units in bytes */ 511 u64 tx_unicast; 512 u64 rx_unicast; 513 514 /* count for packets */ 515 u64 tx_cnt; 516 u64 rx_cnt; 517 518 /* units in Mbps */ 519 u32 tx_throughput; 520 u32 rx_throughput; 521 }; 522 523 enum rtw_lps_mode { 524 RTW_MODE_ACTIVE = 0, 525 RTW_MODE_LPS = 1, 526 RTW_MODE_WMM_PS = 2, 527 }; 528 529 enum rtw_pwr_state { 530 RTW_RF_OFF = 0x0, 531 RTW_RF_ON = 0x4, 532 RTW_ALL_ON = 0xc, 533 }; 534 535 struct rtw_lps_conf { 536 /* the interface to enter lps */ 537 struct rtw_vif *rtwvif; 538 enum rtw_lps_mode mode; 539 enum rtw_pwr_state state; 540 u8 awake_interval; 541 u8 rlbm; 542 u8 smart_ps; 543 u8 port_id; 544 }; 545 546 enum rtw_hw_key_type { 547 RTW_CAM_NONE = 0, 548 RTW_CAM_WEP40 = 1, 549 RTW_CAM_TKIP = 2, 550 RTW_CAM_AES = 4, 551 RTW_CAM_WEP104 = 5, 552 }; 553 554 struct rtw_cam_entry { 555 bool valid; 556 bool group; 557 u8 addr[ETH_ALEN]; 558 u8 hw_key_type; 559 struct ieee80211_key_conf *key; 560 }; 561 562 struct rtw_sec_desc { 563 /* search strategy */ 564 bool default_key_search; 565 566 u32 total_cam_num; 567 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 568 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 569 }; 570 571 struct rtw_tx_report { 572 /* protect the tx report queue */ 573 spinlock_t q_lock; 574 struct sk_buff_head queue; 575 atomic_t sn; 576 struct timer_list purge_timer; 577 }; 578 579 #define RTW_BC_MC_MACID 1 580 DECLARE_EWMA(rssi, 10, 16); 581 582 struct rtw_sta_info { 583 struct ieee80211_sta *sta; 584 struct ieee80211_vif *vif; 585 586 struct ewma_rssi avg_rssi; 587 u8 rssi_level; 588 589 u8 mac_id; 590 u8 rate_id; 591 enum rtw_bandwidth bw_mode; 592 enum rtw_rf_type rf_type; 593 enum rtw_wireless_set wireless_set; 594 u8 stbc_en:2; 595 u8 ldpc_en:2; 596 bool sgi_enable; 597 bool vht_enable; 598 bool updated; 599 u8 init_ra_lv; 600 u64 ra_mask; 601 }; 602 603 struct rtw_vif { 604 struct ieee80211_vif *vif; 605 enum rtw_net_type net_type; 606 u16 aid; 607 u8 mac_addr[ETH_ALEN]; 608 u8 bssid[ETH_ALEN]; 609 u8 port; 610 u8 bcn_ctrl; 611 const struct rtw_vif_port *conf; 612 613 struct rtw_traffic_stats stats; 614 bool in_lps; 615 }; 616 617 struct rtw_regulatory { 618 char alpha2[2]; 619 u8 chplan; 620 u8 txpwr_regd; 621 }; 622 623 struct rtw_chip_ops { 624 int (*mac_init)(struct rtw_dev *rtwdev); 625 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 626 void (*phy_set_param)(struct rtw_dev *rtwdev); 627 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 628 u8 bandwidth, u8 primary_chan_idx); 629 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 630 struct rtw_rx_pkt_stat *pkt_stat, 631 struct ieee80211_rx_status *rx_status); 632 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 633 u32 addr, u32 mask); 634 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 635 u32 addr, u32 mask, u32 data); 636 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 637 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 638 u32 size); 639 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx, 640 u8 antenna_rx); 641 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 642 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 643 void (*do_iqk)(struct rtw_dev *rtwdev); 644 645 /* for coex */ 646 void (*coex_set_init)(struct rtw_dev *rtwdev); 647 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 648 u8 ctrl_type, u8 pos_type); 649 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 650 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 651 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 652 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 653 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 654 }; 655 656 #define RTW_PWR_POLLING_CNT 20000 657 658 #define RTW_PWR_CMD_READ 0x00 659 #define RTW_PWR_CMD_WRITE 0x01 660 #define RTW_PWR_CMD_POLLING 0x02 661 #define RTW_PWR_CMD_DELAY 0x03 662 #define RTW_PWR_CMD_END 0x04 663 664 /* define the base address of each block */ 665 #define RTW_PWR_ADDR_MAC 0x00 666 #define RTW_PWR_ADDR_USB 0x01 667 #define RTW_PWR_ADDR_PCIE 0x02 668 #define RTW_PWR_ADDR_SDIO 0x03 669 670 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 671 #define RTW_PWR_INTF_USB_MSK BIT(1) 672 #define RTW_PWR_INTF_PCI_MSK BIT(2) 673 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 674 675 #define RTW_PWR_CUT_A_MSK BIT(1) 676 #define RTW_PWR_CUT_B_MSK BIT(2) 677 #define RTW_PWR_CUT_C_MSK BIT(3) 678 #define RTW_PWR_CUT_D_MSK BIT(4) 679 #define RTW_PWR_CUT_E_MSK BIT(5) 680 #define RTW_PWR_CUT_F_MSK BIT(6) 681 #define RTW_PWR_CUT_G_MSK BIT(7) 682 #define RTW_PWR_CUT_ALL_MSK 0xFF 683 684 enum rtw_pwr_seq_cmd_delay_unit { 685 RTW_PWR_DELAY_US, 686 RTW_PWR_DELAY_MS, 687 }; 688 689 struct rtw_pwr_seq_cmd { 690 u16 offset; 691 u8 cut_mask; 692 u8 intf_mask; 693 u8 base:4; 694 u8 cmd:4; 695 u8 mask; 696 u8 value; 697 }; 698 699 enum rtw_chip_ver { 700 RTW_CHIP_VER_CUT_A = 0x00, 701 RTW_CHIP_VER_CUT_B = 0x01, 702 RTW_CHIP_VER_CUT_C = 0x02, 703 RTW_CHIP_VER_CUT_D = 0x03, 704 RTW_CHIP_VER_CUT_E = 0x04, 705 RTW_CHIP_VER_CUT_F = 0x05, 706 RTW_CHIP_VER_CUT_G = 0x06, 707 }; 708 709 #define RTW_INTF_PHY_PLATFORM_ALL 0 710 711 enum rtw_intf_phy_cut { 712 RTW_INTF_PHY_CUT_A = BIT(0), 713 RTW_INTF_PHY_CUT_B = BIT(1), 714 RTW_INTF_PHY_CUT_C = BIT(2), 715 RTW_INTF_PHY_CUT_D = BIT(3), 716 RTW_INTF_PHY_CUT_E = BIT(4), 717 RTW_INTF_PHY_CUT_F = BIT(5), 718 RTW_INTF_PHY_CUT_G = BIT(6), 719 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 720 }; 721 722 enum rtw_ip_sel { 723 RTW_IP_SEL_PHY = 0, 724 RTW_IP_SEL_MAC = 1, 725 RTW_IP_SEL_DBI = 2, 726 727 RTW_IP_SEL_UNDEF = 0xFFFF 728 }; 729 730 enum rtw_pq_map_id { 731 RTW_PQ_MAP_VO = 0x0, 732 RTW_PQ_MAP_VI = 0x1, 733 RTW_PQ_MAP_BE = 0x2, 734 RTW_PQ_MAP_BK = 0x3, 735 RTW_PQ_MAP_MG = 0x4, 736 RTW_PQ_MAP_HI = 0x5, 737 RTW_PQ_MAP_NUM = 0x6, 738 739 RTW_PQ_MAP_UNDEF, 740 }; 741 742 enum rtw_dma_mapping { 743 RTW_DMA_MAPPING_EXTRA = 0, 744 RTW_DMA_MAPPING_LOW = 1, 745 RTW_DMA_MAPPING_NORMAL = 2, 746 RTW_DMA_MAPPING_HIGH = 3, 747 748 RTW_DMA_MAPPING_UNDEF, 749 }; 750 751 struct rtw_rqpn { 752 enum rtw_dma_mapping dma_map_vo; 753 enum rtw_dma_mapping dma_map_vi; 754 enum rtw_dma_mapping dma_map_be; 755 enum rtw_dma_mapping dma_map_bk; 756 enum rtw_dma_mapping dma_map_mg; 757 enum rtw_dma_mapping dma_map_hi; 758 }; 759 760 struct rtw_page_table { 761 u16 hq_num; 762 u16 nq_num; 763 u16 lq_num; 764 u16 exq_num; 765 u16 gapq_num; 766 }; 767 768 struct rtw_intf_phy_para { 769 u16 offset; 770 u16 value; 771 u16 ip_sel; 772 u16 cut_mask; 773 u16 platform; 774 }; 775 776 struct rtw_intf_phy_para_table { 777 struct rtw_intf_phy_para *usb2_para; 778 struct rtw_intf_phy_para *usb3_para; 779 struct rtw_intf_phy_para *gen1_para; 780 struct rtw_intf_phy_para *gen2_para; 781 u8 n_usb2_para; 782 u8 n_usb3_para; 783 u8 n_gen1_para; 784 u8 n_gen2_para; 785 }; 786 787 struct rtw_table { 788 const void *data; 789 const u32 size; 790 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 791 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 792 u32 addr, u32 data); 793 enum rtw_rf_path rf_path; 794 }; 795 796 static inline void rtw_load_table(struct rtw_dev *rtwdev, 797 const struct rtw_table *tbl) 798 { 799 (*tbl->parse)(rtwdev, tbl); 800 } 801 802 enum rtw_rfe_fem { 803 RTW_RFE_IFEM, 804 RTW_RFE_EFEM, 805 RTW_RFE_IFEM2G_EFEM5G, 806 RTW_RFE_NUM, 807 }; 808 809 struct rtw_rfe_def { 810 const struct rtw_table *phy_pg_tbl; 811 const struct rtw_table *txpwr_lmt_tbl; 812 }; 813 814 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 815 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 816 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 817 } 818 819 /* hardware configuration for each IC */ 820 struct rtw_chip_info { 821 struct rtw_chip_ops *ops; 822 u8 id; 823 824 const char *fw_name; 825 u8 tx_pkt_desc_sz; 826 u8 tx_buf_desc_sz; 827 u8 rx_pkt_desc_sz; 828 u8 rx_buf_desc_sz; 829 u32 phy_efuse_size; 830 u32 log_efuse_size; 831 u32 ptct_efuse_size; 832 u32 txff_size; 833 u32 rxff_size; 834 u8 band; 835 u8 page_size; 836 u8 csi_buf_pg_num; 837 u8 dig_max; 838 u8 dig_min; 839 u8 txgi_factor; 840 bool is_pwr_by_rate_dec; 841 u8 max_power_index; 842 843 bool ht_supported; 844 bool vht_supported; 845 846 /* init values */ 847 u8 sys_func_en; 848 struct rtw_pwr_seq_cmd **pwr_on_seq; 849 struct rtw_pwr_seq_cmd **pwr_off_seq; 850 struct rtw_rqpn *rqpn_table; 851 struct rtw_page_table *page_table; 852 struct rtw_intf_phy_para_table *intf_table; 853 854 struct rtw_hw_reg *dig; 855 u32 rf_base_addr[2]; 856 u32 rf_sipi_addr[2]; 857 858 const struct rtw_table *mac_tbl; 859 const struct rtw_table *agc_tbl; 860 const struct rtw_table *bb_tbl; 861 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 862 const struct rtw_table *rfk_init_tbl; 863 864 const struct rtw_rfe_def *rfe_defs; 865 u32 rfe_defs_size; 866 867 /* coex paras */ 868 u32 coex_para_ver; 869 u8 bt_desired_ver; 870 bool scbd_support; 871 bool new_scbd10_def; /* true: fix 2M(8822c) */ 872 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 873 u8 bt_rssi_type; 874 u8 ant_isolation; 875 u8 rssi_tolerance; 876 u8 table_sant_num; 877 u8 table_nsant_num; 878 u8 tdma_sant_num; 879 u8 tdma_nsant_num; 880 u8 bt_afh_span_bw20; 881 u8 bt_afh_span_bw40; 882 u8 afh_5g_num; 883 u8 wl_rf_para_num; 884 const u8 *bt_rssi_step; 885 const u8 *wl_rssi_step; 886 const struct coex_table_para *table_nsant; 887 const struct coex_table_para *table_sant; 888 const struct coex_tdma_para *tdma_sant; 889 const struct coex_tdma_para *tdma_nsant; 890 const struct coex_rf_para *wl_rf_para_tx; 891 const struct coex_rf_para *wl_rf_para_rx; 892 const struct coex_5g_afh_map *afh_5g; 893 }; 894 895 enum rtw_coex_bt_state_cnt { 896 COEX_CNT_BT_RETRY, 897 COEX_CNT_BT_REINIT, 898 COEX_CNT_BT_REENABLE, 899 COEX_CNT_BT_POPEVENT, 900 COEX_CNT_BT_SETUPLINK, 901 COEX_CNT_BT_IGNWLANACT, 902 COEX_CNT_BT_INQ, 903 COEX_CNT_BT_PAGE, 904 COEX_CNT_BT_ROLESWITCH, 905 COEX_CNT_BT_AFHUPDATE, 906 COEX_CNT_BT_INFOUPDATE, 907 COEX_CNT_BT_IQK, 908 COEX_CNT_BT_IQKFAIL, 909 910 COEX_CNT_BT_MAX 911 }; 912 913 enum rtw_coex_wl_state_cnt { 914 COEX_CNT_WL_CONNPKT, 915 COEX_CNT_WL_COEXRUN, 916 COEX_CNT_WL_NOISY0, 917 COEX_CNT_WL_NOISY1, 918 COEX_CNT_WL_NOISY2, 919 COEX_CNT_WL_5MS_NOEXTEND, 920 COEX_CNT_WL_FW_NOTIFY, 921 922 COEX_CNT_WL_MAX 923 }; 924 925 struct rtw_coex_rfe { 926 bool ant_switch_exist; 927 bool ant_switch_diversity; 928 bool ant_switch_with_bt; 929 u8 rfe_module_type; 930 u8 ant_switch_polarity; 931 932 /* true if WLG at BTG, else at WLAG */ 933 bool wlg_at_btg; 934 }; 935 936 struct rtw_coex_dm { 937 bool cur_ps_tdma_on; 938 bool cur_wl_rx_low_gain_en; 939 940 u8 reason; 941 u8 bt_rssi_state[4]; 942 u8 wl_rssi_state[4]; 943 u8 wl_ch_info[3]; 944 u8 cur_ps_tdma; 945 u8 cur_table; 946 u8 ps_tdma_para[5]; 947 u8 cur_bt_pwr_lvl; 948 u8 cur_bt_lna_lvl; 949 u8 cur_wl_pwr_lvl; 950 u8 bt_status; 951 u32 cur_ant_pos_type; 952 u32 cur_switch_status; 953 u32 setting_tdma; 954 }; 955 956 #define COEX_BTINFO_SRC_WL_FW 0x0 957 #define COEX_BTINFO_SRC_BT_RSP 0x1 958 #define COEX_BTINFO_SRC_BT_ACT 0x2 959 #define COEX_BTINFO_SRC_BT_IQK 0x3 960 #define COEX_BTINFO_SRC_BT_SCBD 0x4 961 #define COEX_BTINFO_SRC_MAX 0x5 962 963 #define COEX_INFO_FTP BIT(7) 964 #define COEX_INFO_A2DP BIT(6) 965 #define COEX_INFO_HID BIT(5) 966 #define COEX_INFO_SCO_BUSY BIT(4) 967 #define COEX_INFO_ACL_BUSY BIT(3) 968 #define COEX_INFO_INQ_PAGE BIT(2) 969 #define COEX_INFO_SCO_ESCO BIT(1) 970 #define COEX_INFO_CONNECTION BIT(0) 971 #define COEX_BTINFO_LENGTH_MAX 10 972 973 struct rtw_coex_stat { 974 bool bt_disabled; 975 bool bt_disabled_pre; 976 bool bt_link_exist; 977 bool bt_whck_test; 978 bool bt_inq_page; 979 bool bt_inq; 980 bool bt_page; 981 bool bt_ble_voice; 982 bool bt_ble_exist; 983 bool bt_hfp_exist; 984 bool bt_a2dp_exist; 985 bool bt_hid_exist; 986 bool bt_pan_exist; /* PAN or OPP */ 987 bool bt_opp_exist; /* OPP only */ 988 bool bt_acl_busy; 989 bool bt_fix_2M; 990 bool bt_setup_link; 991 bool bt_multi_link; 992 bool bt_a2dp_sink; 993 bool bt_a2dp_active; 994 bool bt_reenable; 995 bool bt_ble_scan_en; 996 bool bt_init_scan; 997 bool bt_slave; 998 bool bt_418_hid_exist; 999 bool bt_mailbox_reply; 1000 1001 bool wl_under_lps; 1002 bool wl_under_ips; 1003 bool wl_hi_pri_task1; 1004 bool wl_hi_pri_task2; 1005 bool wl_force_lps_ctrl; 1006 bool wl_gl_busy; 1007 bool wl_linkscan_proc; 1008 bool wl_ps_state_fail; 1009 bool wl_tx_limit_en; 1010 bool wl_ampdu_limit_en; 1011 bool wl_connected; 1012 bool wl_slot_extend; 1013 bool wl_cck_lock; 1014 bool wl_cck_lock_pre; 1015 bool wl_cck_lock_ever; 1016 1017 u32 bt_supported_version; 1018 u32 bt_supported_feature; 1019 s8 bt_rssi; 1020 u8 kt_ver; 1021 u8 gnt_workaround_state; 1022 u8 tdma_timer_base; 1023 u8 bt_profile_num; 1024 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1025 u8 bt_info_lb2; 1026 u8 bt_info_lb3; 1027 u8 bt_info_hb0; 1028 u8 bt_info_hb1; 1029 u8 bt_info_hb2; 1030 u8 bt_info_hb3; 1031 u8 bt_ble_scan_type; 1032 u8 bt_hid_pair_num; 1033 u8 bt_hid_slot; 1034 u8 bt_a2dp_bitpool; 1035 u8 bt_iqk_state; 1036 1037 u8 wl_noisy_level; 1038 u8 wl_fw_dbg_info[10]; 1039 u8 wl_fw_dbg_info_pre[10]; 1040 u8 wl_coex_mode; 1041 u8 ampdu_max_time; 1042 u8 wl_tput_dir; 1043 1044 u16 score_board; 1045 u16 retry_limit; 1046 1047 /* counters to record bt states */ 1048 u32 cnt_bt[COEX_CNT_BT_MAX]; 1049 1050 /* counters to record wifi states */ 1051 u32 cnt_wl[COEX_CNT_WL_MAX]; 1052 1053 u32 darfrc; 1054 u32 darfrch; 1055 }; 1056 1057 struct rtw_coex { 1058 /* protects coex info request section */ 1059 struct mutex mutex; 1060 struct sk_buff_head queue; 1061 wait_queue_head_t wait; 1062 1063 bool under_5g; 1064 bool stop_dm; 1065 bool freeze; 1066 bool freerun; 1067 bool wl_rf_off; 1068 1069 struct rtw_coex_stat stat; 1070 struct rtw_coex_dm dm; 1071 struct rtw_coex_rfe rfe; 1072 1073 struct delayed_work bt_relink_work; 1074 struct delayed_work bt_reenable_work; 1075 struct delayed_work defreeze_work; 1076 }; 1077 1078 #define DACK_MSBK_BACKUP_NUM 0xf 1079 #define DACK_DCK_BACKUP_NUM 0x2 1080 1081 struct rtw_dm_info { 1082 u32 cck_fa_cnt; 1083 u32 ofdm_fa_cnt; 1084 u32 total_fa_cnt; 1085 1086 u32 cck_ok_cnt; 1087 u32 cck_err_cnt; 1088 u32 ofdm_ok_cnt; 1089 u32 ofdm_err_cnt; 1090 u32 ht_ok_cnt; 1091 u32 ht_err_cnt; 1092 u32 vht_ok_cnt; 1093 u32 vht_err_cnt; 1094 1095 u8 min_rssi; 1096 u8 pre_min_rssi; 1097 u16 fa_history[4]; 1098 u8 igi_history[4]; 1099 u8 igi_bitmap; 1100 bool damping; 1101 u8 damping_cnt; 1102 u8 damping_rssi; 1103 1104 u8 cck_gi_u_bnd; 1105 u8 cck_gi_l_bnd; 1106 1107 /* backup dack results for each path and I/Q */ 1108 u32 dack_adck[RTW_RF_PATH_MAX]; 1109 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1110 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1111 }; 1112 1113 struct rtw_efuse { 1114 u32 size; 1115 u32 physical_size; 1116 u32 logical_size; 1117 u32 protect_size; 1118 1119 u8 addr[ETH_ALEN]; 1120 u8 channel_plan; 1121 u8 country_code[2]; 1122 u8 rf_board_option; 1123 u8 rfe_option; 1124 u8 thermal_meter; 1125 u8 crystal_cap; 1126 u8 ant_div_cfg; 1127 u8 ant_div_type; 1128 u8 regd; 1129 1130 u8 lna_type_2g; 1131 u8 lna_type_5g; 1132 u8 glna_type; 1133 u8 alna_type; 1134 bool ext_lna_2g; 1135 bool ext_lna_5g; 1136 u8 pa_type_2g; 1137 u8 pa_type_5g; 1138 u8 gpa_type; 1139 u8 apa_type; 1140 bool ext_pa_2g; 1141 bool ext_pa_5g; 1142 1143 bool btcoex; 1144 /* bt share antenna with wifi */ 1145 bool share_ant; 1146 u8 bt_setting; 1147 1148 struct { 1149 u8 hci; 1150 u8 bw; 1151 u8 ptcl; 1152 u8 nss; 1153 u8 ant_num; 1154 } hw_cap; 1155 1156 struct rtw_txpwr_idx txpwr_idx_table[4]; 1157 }; 1158 1159 struct rtw_phy_cond { 1160 #ifdef __LITTLE_ENDIAN 1161 u32 rfe:8; 1162 u32 intf:4; 1163 u32 pkg:4; 1164 u32 plat:4; 1165 u32 intf_rsvd:4; 1166 u32 cut:4; 1167 u32 branch:2; 1168 u32 neg:1; 1169 u32 pos:1; 1170 #else 1171 u32 pos:1; 1172 u32 neg:1; 1173 u32 branch:2; 1174 u32 cut:4; 1175 u32 intf_rsvd:4; 1176 u32 plat:4; 1177 u32 pkg:4; 1178 u32 intf:4; 1179 u32 rfe:8; 1180 #endif 1181 /* for intf:4 */ 1182 #define INTF_PCIE BIT(0) 1183 #define INTF_USB BIT(1) 1184 #define INTF_SDIO BIT(2) 1185 /* for branch:2 */ 1186 #define BRANCH_IF 0 1187 #define BRANCH_ELIF 1 1188 #define BRANCH_ELSE 2 1189 #define BRANCH_ENDIF 3 1190 }; 1191 1192 struct rtw_fifo_conf { 1193 /* tx fifo information */ 1194 u16 rsvd_boundary; 1195 u16 rsvd_pg_num; 1196 u16 rsvd_drv_pg_num; 1197 u16 txff_pg_num; 1198 u16 acq_pg_num; 1199 u16 rsvd_drv_addr; 1200 u16 rsvd_h2c_info_addr; 1201 u16 rsvd_h2c_sta_info_addr; 1202 u16 rsvd_h2cq_addr; 1203 u16 rsvd_cpu_instr_addr; 1204 u16 rsvd_fw_txbuf_addr; 1205 u16 rsvd_csibuf_addr; 1206 enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM]; 1207 }; 1208 1209 struct rtw_fw_state { 1210 const struct firmware *firmware; 1211 struct completion completion; 1212 u16 version; 1213 u8 sub_version; 1214 u8 sub_index; 1215 u16 h2c_version; 1216 }; 1217 1218 struct rtw_hal { 1219 u32 rcr; 1220 1221 u32 chip_version; 1222 u8 fab_version; 1223 u8 cut_version; 1224 u8 mp_chip; 1225 u8 oem_id; 1226 struct rtw_phy_cond phy_cond; 1227 1228 u8 ps_mode; 1229 u8 current_channel; 1230 u8 current_band_width; 1231 u8 current_band_type; 1232 1233 /* center channel for different available bandwidth, 1234 * val of (bw > current_band_width) is invalid 1235 */ 1236 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1237 1238 u8 sec_ch_offset; 1239 u8 rf_type; 1240 u8 rf_path_num; 1241 u8 antenna_tx; 1242 u8 antenna_rx; 1243 1244 /* protect tx power section */ 1245 struct mutex tx_power_mutex; 1246 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1247 [DESC_RATE_MAX]; 1248 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1249 [DESC_RATE_MAX]; 1250 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1251 [RTW_RATE_SECTION_MAX]; 1252 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1253 [RTW_RATE_SECTION_MAX]; 1254 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1255 [RTW_CHANNEL_WIDTH_MAX] 1256 [RTW_RATE_SECTION_MAX] 1257 [RTW_MAX_CHANNEL_NUM_2G]; 1258 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1259 [RTW_CHANNEL_WIDTH_MAX] 1260 [RTW_RATE_SECTION_MAX] 1261 [RTW_MAX_CHANNEL_NUM_5G]; 1262 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1263 [DESC_RATE_MAX]; 1264 }; 1265 1266 struct rtw_dev { 1267 struct ieee80211_hw *hw; 1268 struct device *dev; 1269 1270 struct rtw_hci hci; 1271 1272 struct rtw_chip_info *chip; 1273 struct rtw_hal hal; 1274 struct rtw_fifo_conf fifo; 1275 struct rtw_fw_state fw; 1276 struct rtw_efuse efuse; 1277 struct rtw_sec_desc sec; 1278 struct rtw_traffic_stats stats; 1279 struct rtw_regulatory regd; 1280 1281 struct rtw_dm_info dm_info; 1282 struct rtw_coex coex; 1283 1284 /* ensures exclusive access from mac80211 callbacks */ 1285 struct mutex mutex; 1286 1287 /* lock for dm to use */ 1288 spinlock_t dm_lock; 1289 1290 /* read/write rf register */ 1291 spinlock_t rf_lock; 1292 1293 /* watch dog every 2 sec */ 1294 struct delayed_work watch_dog_work; 1295 u32 watch_dog_cnt; 1296 1297 struct list_head rsvd_page_list; 1298 1299 /* c2h cmd queue & handler work */ 1300 struct sk_buff_head c2h_queue; 1301 struct work_struct c2h_work; 1302 1303 struct rtw_tx_report tx_report; 1304 1305 struct { 1306 /* incicate the mail box to use with fw */ 1307 u8 last_box_num; 1308 /* protect to send h2c to fw */ 1309 spinlock_t lock; 1310 u32 seq; 1311 } h2c; 1312 1313 /* lps power state & handler work */ 1314 struct rtw_lps_conf lps_conf; 1315 struct delayed_work lps_work; 1316 1317 struct dentry *debugfs; 1318 1319 u8 sta_cnt; 1320 1321 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1322 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1323 1324 u8 mp_mode; 1325 1326 /* hci related data, must be last */ 1327 u8 priv[0] __aligned(sizeof(void *)); 1328 }; 1329 1330 #include "hci.h" 1331 1332 static inline bool rtw_flag_check(struct rtw_dev *rtwdev, enum rtw_flags flag) 1333 { 1334 return test_bit(flag, rtwdev->flags); 1335 } 1336 1337 static inline void rtw_flag_clear(struct rtw_dev *rtwdev, enum rtw_flags flag) 1338 { 1339 clear_bit(flag, rtwdev->flags); 1340 } 1341 1342 static inline void rtw_flag_set(struct rtw_dev *rtwdev, enum rtw_flags flag) 1343 { 1344 set_bit(flag, rtwdev->flags); 1345 } 1346 1347 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1348 struct rtw_channel_params *ch_param); 1349 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1350 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1351 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1352 void rtw_restore_reg(struct rtw_dev *rtwdev, 1353 struct rtw_backup_info *bckp, u32 num); 1354 void rtw_set_channel(struct rtw_dev *rtwdev); 1355 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1356 u32 config); 1357 void rtw_tx_report_purge_timer(struct timer_list *t); 1358 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1359 int rtw_core_start(struct rtw_dev *rtwdev); 1360 void rtw_core_stop(struct rtw_dev *rtwdev); 1361 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1362 int rtw_core_init(struct rtw_dev *rtwdev); 1363 void rtw_core_deinit(struct rtw_dev *rtwdev); 1364 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1365 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1366 1367 #endif 1368