1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_NAPI_WEIGHT_NUM 64 21 #define RTW_MAX_MAC_ID_NUM 32 22 #define RTW_MAX_SEC_CAM_NUM 32 23 #define MAX_PG_CAM_BACKUP_NUM 8 24 25 #define RTW_MAX_PATTERN_NUM 12 26 #define RTW_MAX_PATTERN_MASK_SIZE 16 27 #define RTW_MAX_PATTERN_SIZE 128 28 29 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 30 31 #define RFREG_MASK 0xfffff 32 #define INV_RF_DATA 0xffffffff 33 #define TX_PAGE_SIZE_SHIFT 7 34 35 #define RTW_CHANNEL_WIDTH_MAX 3 36 #define RTW_RF_PATH_MAX 4 37 #define HW_FEATURE_LEN 13 38 39 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 40 41 extern bool rtw_bf_support; 42 extern bool rtw_disable_lps_deep_mode; 43 extern unsigned int rtw_debug_mask; 44 extern const struct ieee80211_ops rtw_ops; 45 46 #define RTW_MAX_CHANNEL_NUM_2G 14 47 #define RTW_MAX_CHANNEL_NUM_5G 49 48 49 struct rtw_dev; 50 51 enum rtw_hci_type { 52 RTW_HCI_TYPE_PCIE, 53 RTW_HCI_TYPE_USB, 54 RTW_HCI_TYPE_SDIO, 55 56 RTW_HCI_TYPE_UNDEFINE, 57 }; 58 59 struct rtw_hci { 60 struct rtw_hci_ops *ops; 61 enum rtw_hci_type type; 62 63 u32 rpwm_addr; 64 u32 cpwm_addr; 65 66 u8 bulkout_num; 67 }; 68 69 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 70 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 71 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 72 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 73 74 #define IS_CH_5G_BAND_MID(channel) \ 75 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 76 77 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 78 #define IS_CH_5G_BAND(channel) \ 79 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 80 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 81 82 enum rtw_supported_band { 83 RTW_BAND_2G = 1 << 0, 84 RTW_BAND_5G = 1 << 1, 85 RTW_BAND_60G = 1 << 2, 86 87 RTW_BAND_MAX, 88 }; 89 90 /* now, support upto 80M bw */ 91 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 92 93 enum rtw_bandwidth { 94 RTW_CHANNEL_WIDTH_20 = 0, 95 RTW_CHANNEL_WIDTH_40 = 1, 96 RTW_CHANNEL_WIDTH_80 = 2, 97 RTW_CHANNEL_WIDTH_160 = 3, 98 RTW_CHANNEL_WIDTH_80_80 = 4, 99 RTW_CHANNEL_WIDTH_5 = 5, 100 RTW_CHANNEL_WIDTH_10 = 6, 101 }; 102 103 enum rtw_sc_offset { 104 RTW_SC_DONT_CARE = 0, 105 RTW_SC_20_UPPER = 1, 106 RTW_SC_20_LOWER = 2, 107 RTW_SC_20_UPMOST = 3, 108 RTW_SC_20_LOWEST = 4, 109 RTW_SC_40_UPPER = 9, 110 RTW_SC_40_LOWER = 10, 111 }; 112 113 enum rtw_net_type { 114 RTW_NET_NO_LINK = 0, 115 RTW_NET_AD_HOC = 1, 116 RTW_NET_MGD_LINKED = 2, 117 RTW_NET_AP_MODE = 3, 118 }; 119 120 enum rtw_rf_type { 121 RF_1T1R = 0, 122 RF_1T2R = 1, 123 RF_2T2R = 2, 124 RF_2T3R = 3, 125 RF_2T4R = 4, 126 RF_3T3R = 5, 127 RF_3T4R = 6, 128 RF_4T4R = 7, 129 RF_TYPE_MAX, 130 }; 131 132 enum rtw_rf_path { 133 RF_PATH_A = 0, 134 RF_PATH_B = 1, 135 RF_PATH_C = 2, 136 RF_PATH_D = 3, 137 }; 138 139 enum rtw_bb_path { 140 BB_PATH_A = BIT(0), 141 BB_PATH_B = BIT(1), 142 BB_PATH_C = BIT(2), 143 BB_PATH_D = BIT(3), 144 145 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 146 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 147 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 148 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 149 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 150 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 151 152 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 153 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 154 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 155 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 156 157 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 158 }; 159 160 enum rtw_rate_section { 161 RTW_RATE_SECTION_CCK = 0, 162 RTW_RATE_SECTION_OFDM, 163 RTW_RATE_SECTION_HT_1S, 164 RTW_RATE_SECTION_HT_2S, 165 RTW_RATE_SECTION_VHT_1S, 166 RTW_RATE_SECTION_VHT_2S, 167 168 /* keep last */ 169 RTW_RATE_SECTION_MAX, 170 }; 171 172 enum rtw_wireless_set { 173 WIRELESS_CCK = 0x00000001, 174 WIRELESS_OFDM = 0x00000002, 175 WIRELESS_HT = 0x00000004, 176 WIRELESS_VHT = 0x00000008, 177 }; 178 179 #define HT_STBC_EN BIT(0) 180 #define VHT_STBC_EN BIT(1) 181 #define HT_LDPC_EN BIT(0) 182 #define VHT_LDPC_EN BIT(1) 183 184 enum rtw_chip_type { 185 RTW_CHIP_TYPE_8822B, 186 RTW_CHIP_TYPE_8822C, 187 RTW_CHIP_TYPE_8723D, 188 RTW_CHIP_TYPE_8821C, 189 }; 190 191 enum rtw_tx_queue_type { 192 /* the order of AC queues matters */ 193 RTW_TX_QUEUE_BK = 0x0, 194 RTW_TX_QUEUE_BE = 0x1, 195 RTW_TX_QUEUE_VI = 0x2, 196 RTW_TX_QUEUE_VO = 0x3, 197 198 RTW_TX_QUEUE_BCN = 0x4, 199 RTW_TX_QUEUE_MGMT = 0x5, 200 RTW_TX_QUEUE_HI0 = 0x6, 201 RTW_TX_QUEUE_H2C = 0x7, 202 /* keep it last */ 203 RTK_MAX_TX_QUEUE_NUM 204 }; 205 206 enum rtw_rx_queue_type { 207 RTW_RX_QUEUE_MPDU = 0x0, 208 RTW_RX_QUEUE_C2H = 0x1, 209 /* keep it last */ 210 RTK_MAX_RX_QUEUE_NUM 211 }; 212 213 enum rtw_fw_type { 214 RTW_NORMAL_FW = 0x0, 215 RTW_WOWLAN_FW = 0x1, 216 }; 217 218 enum rtw_rate_index { 219 RTW_RATEID_BGN_40M_2SS = 0, 220 RTW_RATEID_BGN_40M_1SS = 1, 221 RTW_RATEID_BGN_20M_2SS = 2, 222 RTW_RATEID_BGN_20M_1SS = 3, 223 RTW_RATEID_GN_N2SS = 4, 224 RTW_RATEID_GN_N1SS = 5, 225 RTW_RATEID_BG = 6, 226 RTW_RATEID_G = 7, 227 RTW_RATEID_B_20M = 8, 228 RTW_RATEID_ARFR0_AC_2SS = 9, 229 RTW_RATEID_ARFR1_AC_1SS = 10, 230 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 231 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 232 RTW_RATEID_ARFR4_AC_3SS = 13, 233 RTW_RATEID_ARFR5_N_3SS = 14, 234 RTW_RATEID_ARFR7_N_4SS = 15, 235 RTW_RATEID_ARFR6_AC_4SS = 16 236 }; 237 238 enum rtw_trx_desc_rate { 239 DESC_RATE1M = 0x00, 240 DESC_RATE2M = 0x01, 241 DESC_RATE5_5M = 0x02, 242 DESC_RATE11M = 0x03, 243 244 DESC_RATE6M = 0x04, 245 DESC_RATE9M = 0x05, 246 DESC_RATE12M = 0x06, 247 DESC_RATE18M = 0x07, 248 DESC_RATE24M = 0x08, 249 DESC_RATE36M = 0x09, 250 DESC_RATE48M = 0x0a, 251 DESC_RATE54M = 0x0b, 252 253 DESC_RATEMCS0 = 0x0c, 254 DESC_RATEMCS1 = 0x0d, 255 DESC_RATEMCS2 = 0x0e, 256 DESC_RATEMCS3 = 0x0f, 257 DESC_RATEMCS4 = 0x10, 258 DESC_RATEMCS5 = 0x11, 259 DESC_RATEMCS6 = 0x12, 260 DESC_RATEMCS7 = 0x13, 261 DESC_RATEMCS8 = 0x14, 262 DESC_RATEMCS9 = 0x15, 263 DESC_RATEMCS10 = 0x16, 264 DESC_RATEMCS11 = 0x17, 265 DESC_RATEMCS12 = 0x18, 266 DESC_RATEMCS13 = 0x19, 267 DESC_RATEMCS14 = 0x1a, 268 DESC_RATEMCS15 = 0x1b, 269 DESC_RATEMCS16 = 0x1c, 270 DESC_RATEMCS17 = 0x1d, 271 DESC_RATEMCS18 = 0x1e, 272 DESC_RATEMCS19 = 0x1f, 273 DESC_RATEMCS20 = 0x20, 274 DESC_RATEMCS21 = 0x21, 275 DESC_RATEMCS22 = 0x22, 276 DESC_RATEMCS23 = 0x23, 277 DESC_RATEMCS24 = 0x24, 278 DESC_RATEMCS25 = 0x25, 279 DESC_RATEMCS26 = 0x26, 280 DESC_RATEMCS27 = 0x27, 281 DESC_RATEMCS28 = 0x28, 282 DESC_RATEMCS29 = 0x29, 283 DESC_RATEMCS30 = 0x2a, 284 DESC_RATEMCS31 = 0x2b, 285 286 DESC_RATEVHT1SS_MCS0 = 0x2c, 287 DESC_RATEVHT1SS_MCS1 = 0x2d, 288 DESC_RATEVHT1SS_MCS2 = 0x2e, 289 DESC_RATEVHT1SS_MCS3 = 0x2f, 290 DESC_RATEVHT1SS_MCS4 = 0x30, 291 DESC_RATEVHT1SS_MCS5 = 0x31, 292 DESC_RATEVHT1SS_MCS6 = 0x32, 293 DESC_RATEVHT1SS_MCS7 = 0x33, 294 DESC_RATEVHT1SS_MCS8 = 0x34, 295 DESC_RATEVHT1SS_MCS9 = 0x35, 296 297 DESC_RATEVHT2SS_MCS0 = 0x36, 298 DESC_RATEVHT2SS_MCS1 = 0x37, 299 DESC_RATEVHT2SS_MCS2 = 0x38, 300 DESC_RATEVHT2SS_MCS3 = 0x39, 301 DESC_RATEVHT2SS_MCS4 = 0x3a, 302 DESC_RATEVHT2SS_MCS5 = 0x3b, 303 DESC_RATEVHT2SS_MCS6 = 0x3c, 304 DESC_RATEVHT2SS_MCS7 = 0x3d, 305 DESC_RATEVHT2SS_MCS8 = 0x3e, 306 DESC_RATEVHT2SS_MCS9 = 0x3f, 307 308 DESC_RATEVHT3SS_MCS0 = 0x40, 309 DESC_RATEVHT3SS_MCS1 = 0x41, 310 DESC_RATEVHT3SS_MCS2 = 0x42, 311 DESC_RATEVHT3SS_MCS3 = 0x43, 312 DESC_RATEVHT3SS_MCS4 = 0x44, 313 DESC_RATEVHT3SS_MCS5 = 0x45, 314 DESC_RATEVHT3SS_MCS6 = 0x46, 315 DESC_RATEVHT3SS_MCS7 = 0x47, 316 DESC_RATEVHT3SS_MCS8 = 0x48, 317 DESC_RATEVHT3SS_MCS9 = 0x49, 318 319 DESC_RATEVHT4SS_MCS0 = 0x4a, 320 DESC_RATEVHT4SS_MCS1 = 0x4b, 321 DESC_RATEVHT4SS_MCS2 = 0x4c, 322 DESC_RATEVHT4SS_MCS3 = 0x4d, 323 DESC_RATEVHT4SS_MCS4 = 0x4e, 324 DESC_RATEVHT4SS_MCS5 = 0x4f, 325 DESC_RATEVHT4SS_MCS6 = 0x50, 326 DESC_RATEVHT4SS_MCS7 = 0x51, 327 DESC_RATEVHT4SS_MCS8 = 0x52, 328 DESC_RATEVHT4SS_MCS9 = 0x53, 329 330 DESC_RATE_MAX, 331 }; 332 333 enum rtw_regulatory_domains { 334 RTW_REGD_FCC = 0, 335 RTW_REGD_MKK = 1, 336 RTW_REGD_ETSI = 2, 337 RTW_REGD_IC = 3, 338 RTW_REGD_KCC = 4, 339 RTW_REGD_ACMA = 5, 340 RTW_REGD_CHILE = 6, 341 RTW_REGD_UKRAINE = 7, 342 RTW_REGD_MEXICO = 8, 343 RTW_REGD_CN = 9, 344 RTW_REGD_WW, 345 346 RTW_REGD_MAX 347 }; 348 349 enum rtw_txq_flags { 350 RTW_TXQ_AMPDU, 351 RTW_TXQ_BLOCK_BA, 352 }; 353 354 enum rtw_flags { 355 RTW_FLAG_RUNNING, 356 RTW_FLAG_FW_RUNNING, 357 RTW_FLAG_SCANNING, 358 RTW_FLAG_INACTIVE_PS, 359 RTW_FLAG_LEISURE_PS, 360 RTW_FLAG_LEISURE_PS_DEEP, 361 RTW_FLAG_DIG_DISABLE, 362 RTW_FLAG_BUSY_TRAFFIC, 363 RTW_FLAG_WOWLAN, 364 RTW_FLAG_RESTARTING, 365 366 NUM_OF_RTW_FLAGS, 367 }; 368 369 enum rtw_evm { 370 RTW_EVM_OFDM = 0, 371 RTW_EVM_1SS, 372 RTW_EVM_2SS_A, 373 RTW_EVM_2SS_B, 374 /* keep it last */ 375 RTW_EVM_NUM 376 }; 377 378 enum rtw_snr { 379 RTW_SNR_OFDM_A = 0, 380 RTW_SNR_OFDM_B, 381 RTW_SNR_OFDM_C, 382 RTW_SNR_OFDM_D, 383 RTW_SNR_1SS_A, 384 RTW_SNR_1SS_B, 385 RTW_SNR_1SS_C, 386 RTW_SNR_1SS_D, 387 RTW_SNR_2SS_A, 388 RTW_SNR_2SS_B, 389 RTW_SNR_2SS_C, 390 RTW_SNR_2SS_D, 391 /* keep it last */ 392 RTW_SNR_NUM 393 }; 394 395 enum rtw_wow_flags { 396 RTW_WOW_FLAG_EN_MAGIC_PKT, 397 RTW_WOW_FLAG_EN_REKEY_PKT, 398 RTW_WOW_FLAG_EN_DISCONNECT, 399 400 /* keep it last */ 401 RTW_WOW_FLAG_MAX, 402 }; 403 404 /* the power index is represented by differences, which cck-1s & ht40-1s are 405 * the base values, so for 1s's differences, there are only ht20 & ofdm 406 */ 407 struct rtw_2g_1s_pwr_idx_diff { 408 #ifdef __LITTLE_ENDIAN 409 s8 ofdm:4; 410 s8 bw20:4; 411 #else 412 s8 bw20:4; 413 s8 ofdm:4; 414 #endif 415 } __packed; 416 417 struct rtw_2g_ns_pwr_idx_diff { 418 #ifdef __LITTLE_ENDIAN 419 s8 bw20:4; 420 s8 bw40:4; 421 s8 cck:4; 422 s8 ofdm:4; 423 #else 424 s8 ofdm:4; 425 s8 cck:4; 426 s8 bw40:4; 427 s8 bw20:4; 428 #endif 429 } __packed; 430 431 struct rtw_2g_txpwr_idx { 432 u8 cck_base[6]; 433 u8 bw40_base[5]; 434 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 435 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 436 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 437 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 438 }; 439 440 struct rtw_5g_ht_1s_pwr_idx_diff { 441 #ifdef __LITTLE_ENDIAN 442 s8 ofdm:4; 443 s8 bw20:4; 444 #else 445 s8 bw20:4; 446 s8 ofdm:4; 447 #endif 448 } __packed; 449 450 struct rtw_5g_ht_ns_pwr_idx_diff { 451 #ifdef __LITTLE_ENDIAN 452 s8 bw20:4; 453 s8 bw40:4; 454 #else 455 s8 bw40:4; 456 s8 bw20:4; 457 #endif 458 } __packed; 459 460 struct rtw_5g_ofdm_ns_pwr_idx_diff { 461 #ifdef __LITTLE_ENDIAN 462 s8 ofdm_3s:4; 463 s8 ofdm_2s:4; 464 s8 ofdm_4s:4; 465 s8 res:4; 466 #else 467 s8 res:4; 468 s8 ofdm_4s:4; 469 s8 ofdm_2s:4; 470 s8 ofdm_3s:4; 471 #endif 472 } __packed; 473 474 struct rtw_5g_vht_ns_pwr_idx_diff { 475 #ifdef __LITTLE_ENDIAN 476 s8 bw160:4; 477 s8 bw80:4; 478 #else 479 s8 bw80:4; 480 s8 bw160:4; 481 #endif 482 } __packed; 483 484 struct rtw_5g_txpwr_idx { 485 u8 bw40_base[14]; 486 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 487 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 488 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 489 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 490 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 491 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 492 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 493 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 494 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 495 }; 496 497 struct rtw_txpwr_idx { 498 struct rtw_2g_txpwr_idx pwr_idx_2g; 499 struct rtw_5g_txpwr_idx pwr_idx_5g; 500 }; 501 502 struct rtw_timer_list { 503 struct timer_list timer; 504 void (*function)(void *data); 505 void *args; 506 }; 507 508 struct rtw_channel_params { 509 u8 center_chan; 510 u8 bandwidth; 511 u8 primary_chan_idx; 512 /* center channel by different available bandwidth, 513 * val of (bw > current bandwidth) is invalid 514 */ 515 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 516 }; 517 518 struct rtw_hw_reg { 519 u32 addr; 520 u32 mask; 521 }; 522 523 struct rtw_ltecoex_addr { 524 u32 ctrl; 525 u32 wdata; 526 u32 rdata; 527 }; 528 529 struct rtw_reg_domain { 530 u32 addr; 531 u32 mask; 532 #define RTW_REG_DOMAIN_MAC32 0 533 #define RTW_REG_DOMAIN_MAC16 1 534 #define RTW_REG_DOMAIN_MAC8 2 535 #define RTW_REG_DOMAIN_RF_A 3 536 #define RTW_REG_DOMAIN_RF_B 4 537 #define RTW_REG_DOMAIN_NL 0xFF 538 u8 domain; 539 }; 540 541 struct rtw_rf_sipi_addr { 542 u32 hssi_1; 543 u32 hssi_2; 544 u32 lssi_read; 545 u32 lssi_read_pi; 546 }; 547 548 struct rtw_backup_info { 549 u8 len; 550 u32 reg; 551 u32 val; 552 }; 553 554 enum rtw_vif_port_set { 555 PORT_SET_MAC_ADDR = BIT(0), 556 PORT_SET_BSSID = BIT(1), 557 PORT_SET_NET_TYPE = BIT(2), 558 PORT_SET_AID = BIT(3), 559 PORT_SET_BCN_CTRL = BIT(4), 560 }; 561 562 struct rtw_vif_port { 563 struct rtw_hw_reg mac_addr; 564 struct rtw_hw_reg bssid; 565 struct rtw_hw_reg net_type; 566 struct rtw_hw_reg aid; 567 struct rtw_hw_reg bcn_ctrl; 568 }; 569 570 struct rtw_tx_pkt_info { 571 u32 tx_pkt_size; 572 u8 offset; 573 u8 pkt_offset; 574 u8 mac_id; 575 u8 rate_id; 576 u8 rate; 577 u8 qsel; 578 u8 bw; 579 u8 sec_type; 580 u8 sn; 581 bool ampdu_en; 582 u8 ampdu_factor; 583 u8 ampdu_density; 584 u16 seq; 585 bool stbc; 586 bool ldpc; 587 bool dis_rate_fallback; 588 bool bmc; 589 bool use_rate; 590 bool ls; 591 bool fs; 592 bool short_gi; 593 bool report; 594 bool rts; 595 bool dis_qselseq; 596 bool en_hwseq; 597 u8 hw_ssn_sel; 598 bool nav_use_hdr; 599 bool bt_null; 600 }; 601 602 struct rtw_rx_pkt_stat { 603 bool phy_status; 604 bool icv_err; 605 bool crc_err; 606 bool decrypted; 607 bool is_c2h; 608 609 s32 signal_power; 610 u16 pkt_len; 611 u8 bw; 612 u8 drv_info_sz; 613 u8 shift; 614 u8 rate; 615 u8 mac_id; 616 u8 cam_id; 617 u8 ppdu_cnt; 618 u32 tsf_low; 619 s8 rx_power[RTW_RF_PATH_MAX]; 620 u8 rssi; 621 u8 rxsc; 622 s8 rx_snr[RTW_RF_PATH_MAX]; 623 u8 rx_evm[RTW_RF_PATH_MAX]; 624 s8 cfo_tail[RTW_RF_PATH_MAX]; 625 626 struct rtw_sta_info *si; 627 struct ieee80211_vif *vif; 628 }; 629 630 DECLARE_EWMA(tp, 10, 2); 631 632 struct rtw_traffic_stats { 633 /* units in bytes */ 634 u64 tx_unicast; 635 u64 rx_unicast; 636 637 /* count for packets */ 638 u64 tx_cnt; 639 u64 rx_cnt; 640 641 /* units in Mbps */ 642 u32 tx_throughput; 643 u32 rx_throughput; 644 struct ewma_tp tx_ewma_tp; 645 struct ewma_tp rx_ewma_tp; 646 }; 647 648 enum rtw_lps_mode { 649 RTW_MODE_ACTIVE = 0, 650 RTW_MODE_LPS = 1, 651 RTW_MODE_WMM_PS = 2, 652 }; 653 654 enum rtw_lps_deep_mode { 655 LPS_DEEP_MODE_NONE = 0, 656 LPS_DEEP_MODE_LCLK = 1, 657 LPS_DEEP_MODE_PG = 2, 658 }; 659 660 enum rtw_pwr_state { 661 RTW_RF_OFF = 0x0, 662 RTW_RF_ON = 0x4, 663 RTW_ALL_ON = 0xc, 664 }; 665 666 struct rtw_lps_conf { 667 enum rtw_lps_mode mode; 668 enum rtw_lps_deep_mode deep_mode; 669 enum rtw_lps_deep_mode wow_deep_mode; 670 enum rtw_pwr_state state; 671 u8 awake_interval; 672 u8 rlbm; 673 u8 smart_ps; 674 u8 port_id; 675 bool sec_cam_backup; 676 bool pattern_cam_backup; 677 }; 678 679 enum rtw_hw_key_type { 680 RTW_CAM_NONE = 0, 681 RTW_CAM_WEP40 = 1, 682 RTW_CAM_TKIP = 2, 683 RTW_CAM_AES = 4, 684 RTW_CAM_WEP104 = 5, 685 }; 686 687 struct rtw_cam_entry { 688 bool valid; 689 bool group; 690 u8 addr[ETH_ALEN]; 691 u8 hw_key_type; 692 struct ieee80211_key_conf *key; 693 }; 694 695 struct rtw_sec_desc { 696 /* search strategy */ 697 bool default_key_search; 698 699 u32 total_cam_num; 700 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 701 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 702 }; 703 704 struct rtw_tx_report { 705 /* protect the tx report queue */ 706 spinlock_t q_lock; 707 struct sk_buff_head queue; 708 atomic_t sn; 709 struct timer_list purge_timer; 710 }; 711 712 struct rtw_ra_report { 713 struct rate_info txrate; 714 u32 bit_rate; 715 u8 desc_rate; 716 }; 717 718 struct rtw_txq { 719 struct list_head list; 720 721 unsigned long flags; 722 unsigned long last_push; 723 }; 724 725 #define RTW_BC_MC_MACID 1 726 DECLARE_EWMA(rssi, 10, 16); 727 728 struct rtw_sta_info { 729 struct ieee80211_sta *sta; 730 struct ieee80211_vif *vif; 731 732 struct ewma_rssi avg_rssi; 733 u8 rssi_level; 734 735 u8 mac_id; 736 u8 rate_id; 737 enum rtw_bandwidth bw_mode; 738 enum rtw_rf_type rf_type; 739 enum rtw_wireless_set wireless_set; 740 u8 stbc_en:2; 741 u8 ldpc_en:2; 742 bool sgi_enable; 743 bool vht_enable; 744 bool updated; 745 u8 init_ra_lv; 746 u64 ra_mask; 747 748 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 749 750 struct rtw_ra_report ra_report; 751 752 bool use_cfg_mask; 753 struct cfg80211_bitrate_mask *mask; 754 }; 755 756 enum rtw_bfee_role { 757 RTW_BFEE_NONE, 758 RTW_BFEE_SU, 759 RTW_BFEE_MU 760 }; 761 762 struct rtw_bfee { 763 enum rtw_bfee_role role; 764 765 u16 p_aid; 766 u8 g_id; 767 u8 mac_addr[ETH_ALEN]; 768 u8 sound_dim; 769 770 /* SU-MIMO */ 771 u8 su_reg_index; 772 773 /* MU-MIMO */ 774 u16 aid; 775 }; 776 777 struct rtw_bf_info { 778 u8 bfer_mu_cnt; 779 u8 bfer_su_cnt; 780 DECLARE_BITMAP(bfer_su_reg_maping, 2); 781 u8 cur_csi_rpt_rate; 782 }; 783 784 struct rtw_vif { 785 enum rtw_net_type net_type; 786 u16 aid; 787 u8 mac_addr[ETH_ALEN]; 788 u8 bssid[ETH_ALEN]; 789 u8 port; 790 u8 bcn_ctrl; 791 struct list_head rsvd_page_list; 792 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 793 const struct rtw_vif_port *conf; 794 795 struct rtw_traffic_stats stats; 796 797 struct rtw_bfee bfee; 798 }; 799 800 struct rtw_regulatory { 801 char alpha2[2]; 802 u8 chplan; 803 u8 txpwr_regd; 804 }; 805 806 struct rtw_chip_ops { 807 int (*mac_init)(struct rtw_dev *rtwdev); 808 void (*shutdown)(struct rtw_dev *rtwdev); 809 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 810 void (*phy_set_param)(struct rtw_dev *rtwdev); 811 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 812 u8 bandwidth, u8 primary_chan_idx); 813 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 814 struct rtw_rx_pkt_stat *pkt_stat, 815 struct ieee80211_rx_status *rx_status); 816 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 817 u32 addr, u32 mask); 818 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 819 u32 addr, u32 mask, u32 data); 820 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 821 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 822 u32 size); 823 int (*set_antenna)(struct rtw_dev *rtwdev, 824 u32 antenna_tx, 825 u32 antenna_rx); 826 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 827 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 828 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 829 void (*phy_calibration)(struct rtw_dev *rtwdev); 830 void (*dpk_track)(struct rtw_dev *rtwdev); 831 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 832 void (*pwr_track)(struct rtw_dev *rtwdev); 833 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 834 struct rtw_bfee *bfee, bool enable); 835 void (*set_gid_table)(struct rtw_dev *rtwdev, 836 struct ieee80211_vif *vif, 837 struct ieee80211_bss_conf *conf); 838 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 839 u8 fixrate_en, u8 *new_rate); 840 841 /* for coex */ 842 void (*coex_set_init)(struct rtw_dev *rtwdev); 843 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 844 u8 ctrl_type, u8 pos_type); 845 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 846 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 847 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 848 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 849 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 850 }; 851 852 #define RTW_PWR_POLLING_CNT 20000 853 854 #define RTW_PWR_CMD_READ 0x00 855 #define RTW_PWR_CMD_WRITE 0x01 856 #define RTW_PWR_CMD_POLLING 0x02 857 #define RTW_PWR_CMD_DELAY 0x03 858 #define RTW_PWR_CMD_END 0x04 859 860 /* define the base address of each block */ 861 #define RTW_PWR_ADDR_MAC 0x00 862 #define RTW_PWR_ADDR_USB 0x01 863 #define RTW_PWR_ADDR_PCIE 0x02 864 #define RTW_PWR_ADDR_SDIO 0x03 865 866 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 867 #define RTW_PWR_INTF_USB_MSK BIT(1) 868 #define RTW_PWR_INTF_PCI_MSK BIT(2) 869 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 870 871 #define RTW_PWR_CUT_TEST_MSK BIT(0) 872 #define RTW_PWR_CUT_A_MSK BIT(1) 873 #define RTW_PWR_CUT_B_MSK BIT(2) 874 #define RTW_PWR_CUT_C_MSK BIT(3) 875 #define RTW_PWR_CUT_D_MSK BIT(4) 876 #define RTW_PWR_CUT_E_MSK BIT(5) 877 #define RTW_PWR_CUT_F_MSK BIT(6) 878 #define RTW_PWR_CUT_G_MSK BIT(7) 879 #define RTW_PWR_CUT_ALL_MSK 0xFF 880 881 enum rtw_pwr_seq_cmd_delay_unit { 882 RTW_PWR_DELAY_US, 883 RTW_PWR_DELAY_MS, 884 }; 885 886 struct rtw_pwr_seq_cmd { 887 u16 offset; 888 u8 cut_mask; 889 u8 intf_mask; 890 u8 base:4; 891 u8 cmd:4; 892 u8 mask; 893 u8 value; 894 }; 895 896 enum rtw_chip_ver { 897 RTW_CHIP_VER_CUT_A = 0x00, 898 RTW_CHIP_VER_CUT_B = 0x01, 899 RTW_CHIP_VER_CUT_C = 0x02, 900 RTW_CHIP_VER_CUT_D = 0x03, 901 RTW_CHIP_VER_CUT_E = 0x04, 902 RTW_CHIP_VER_CUT_F = 0x05, 903 RTW_CHIP_VER_CUT_G = 0x06, 904 }; 905 906 #define RTW_INTF_PHY_PLATFORM_ALL 0 907 908 enum rtw_intf_phy_cut { 909 RTW_INTF_PHY_CUT_A = BIT(0), 910 RTW_INTF_PHY_CUT_B = BIT(1), 911 RTW_INTF_PHY_CUT_C = BIT(2), 912 RTW_INTF_PHY_CUT_D = BIT(3), 913 RTW_INTF_PHY_CUT_E = BIT(4), 914 RTW_INTF_PHY_CUT_F = BIT(5), 915 RTW_INTF_PHY_CUT_G = BIT(6), 916 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 917 }; 918 919 enum rtw_ip_sel { 920 RTW_IP_SEL_PHY = 0, 921 RTW_IP_SEL_MAC = 1, 922 RTW_IP_SEL_DBI = 2, 923 924 RTW_IP_SEL_UNDEF = 0xFFFF 925 }; 926 927 enum rtw_pq_map_id { 928 RTW_PQ_MAP_VO = 0x0, 929 RTW_PQ_MAP_VI = 0x1, 930 RTW_PQ_MAP_BE = 0x2, 931 RTW_PQ_MAP_BK = 0x3, 932 RTW_PQ_MAP_MG = 0x4, 933 RTW_PQ_MAP_HI = 0x5, 934 RTW_PQ_MAP_NUM = 0x6, 935 936 RTW_PQ_MAP_UNDEF, 937 }; 938 939 enum rtw_dma_mapping { 940 RTW_DMA_MAPPING_EXTRA = 0, 941 RTW_DMA_MAPPING_LOW = 1, 942 RTW_DMA_MAPPING_NORMAL = 2, 943 RTW_DMA_MAPPING_HIGH = 3, 944 945 RTW_DMA_MAPPING_MAX, 946 RTW_DMA_MAPPING_UNDEF, 947 }; 948 949 struct rtw_rqpn { 950 enum rtw_dma_mapping dma_map_vo; 951 enum rtw_dma_mapping dma_map_vi; 952 enum rtw_dma_mapping dma_map_be; 953 enum rtw_dma_mapping dma_map_bk; 954 enum rtw_dma_mapping dma_map_mg; 955 enum rtw_dma_mapping dma_map_hi; 956 }; 957 958 struct rtw_prioq_addr { 959 u32 rsvd; 960 u32 avail; 961 }; 962 963 struct rtw_prioq_addrs { 964 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 965 bool wsize; 966 }; 967 968 struct rtw_page_table { 969 u16 hq_num; 970 u16 nq_num; 971 u16 lq_num; 972 u16 exq_num; 973 u16 gapq_num; 974 }; 975 976 struct rtw_intf_phy_para { 977 u16 offset; 978 u16 value; 979 u16 ip_sel; 980 u16 cut_mask; 981 u16 platform; 982 }; 983 984 struct rtw_wow_pattern { 985 u16 crc; 986 u8 type; 987 u8 valid; 988 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 989 }; 990 991 struct rtw_pno_request { 992 bool inited; 993 u32 match_set_cnt; 994 struct cfg80211_match_set *match_sets; 995 u8 channel_cnt; 996 struct ieee80211_channel *channels; 997 struct cfg80211_sched_scan_plan scan_plan; 998 }; 999 1000 struct rtw_wow_param { 1001 struct ieee80211_vif *wow_vif; 1002 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1003 u8 txpause; 1004 u8 pattern_cnt; 1005 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1006 1007 bool ips_enabled; 1008 struct rtw_pno_request pno_req; 1009 }; 1010 1011 struct rtw_intf_phy_para_table { 1012 const struct rtw_intf_phy_para *usb2_para; 1013 const struct rtw_intf_phy_para *usb3_para; 1014 const struct rtw_intf_phy_para *gen1_para; 1015 const struct rtw_intf_phy_para *gen2_para; 1016 u8 n_usb2_para; 1017 u8 n_usb3_para; 1018 u8 n_gen1_para; 1019 u8 n_gen2_para; 1020 }; 1021 1022 struct rtw_table { 1023 const void *data; 1024 const u32 size; 1025 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1026 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1027 u32 addr, u32 data); 1028 enum rtw_rf_path rf_path; 1029 }; 1030 1031 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1032 const struct rtw_table *tbl) 1033 { 1034 (*tbl->parse)(rtwdev, tbl); 1035 } 1036 1037 enum rtw_rfe_fem { 1038 RTW_RFE_IFEM, 1039 RTW_RFE_EFEM, 1040 RTW_RFE_IFEM2G_EFEM5G, 1041 RTW_RFE_NUM, 1042 }; 1043 1044 struct rtw_rfe_def { 1045 const struct rtw_table *phy_pg_tbl; 1046 const struct rtw_table *txpwr_lmt_tbl; 1047 const struct rtw_table *agc_btg_tbl; 1048 }; 1049 1050 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1051 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1052 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1053 } 1054 1055 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1056 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1057 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1058 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1059 } 1060 1061 #define RTW_PWR_TRK_5G_1 0 1062 #define RTW_PWR_TRK_5G_2 1 1063 #define RTW_PWR_TRK_5G_3 2 1064 #define RTW_PWR_TRK_5G_NUM 3 1065 1066 #define RTW_PWR_TRK_TBL_SZ 30 1067 1068 /* This table stores the values of TX power that will be adjusted by power 1069 * tracking. 1070 * 1071 * For 5G bands, there are 3 different settings. 1072 * For 2G there are cck rate and ofdm rate with different settings. 1073 */ 1074 struct rtw_pwr_track_tbl { 1075 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1076 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1077 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1078 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1079 const u8 *pwrtrk_2gb_n; 1080 const u8 *pwrtrk_2gb_p; 1081 const u8 *pwrtrk_2ga_n; 1082 const u8 *pwrtrk_2ga_p; 1083 const u8 *pwrtrk_2g_cckb_n; 1084 const u8 *pwrtrk_2g_cckb_p; 1085 const u8 *pwrtrk_2g_ccka_n; 1086 const u8 *pwrtrk_2g_ccka_p; 1087 const s8 *pwrtrk_xtal_n; 1088 const s8 *pwrtrk_xtal_p; 1089 }; 1090 1091 enum rtw_wlan_cpu { 1092 RTW_WCPU_11AC, 1093 RTW_WCPU_11N, 1094 }; 1095 1096 enum rtw_fw_fifo_sel { 1097 RTW_FW_FIFO_SEL_TX, 1098 RTW_FW_FIFO_SEL_RX, 1099 RTW_FW_FIFO_SEL_RSVD_PAGE, 1100 RTW_FW_FIFO_SEL_REPORT, 1101 RTW_FW_FIFO_SEL_LLT, 1102 RTW_FW_FIFO_SEL_RXBUF_FW, 1103 1104 RTW_FW_FIFO_MAX, 1105 }; 1106 1107 /* hardware configuration for each IC */ 1108 struct rtw_chip_info { 1109 struct rtw_chip_ops *ops; 1110 u8 id; 1111 1112 const char *fw_name; 1113 enum rtw_wlan_cpu wlan_cpu; 1114 u8 tx_pkt_desc_sz; 1115 u8 tx_buf_desc_sz; 1116 u8 rx_pkt_desc_sz; 1117 u8 rx_buf_desc_sz; 1118 u32 phy_efuse_size; 1119 u32 log_efuse_size; 1120 u32 ptct_efuse_size; 1121 u32 txff_size; 1122 u32 rxff_size; 1123 u32 fw_rxff_size; 1124 u8 band; 1125 u8 page_size; 1126 u8 csi_buf_pg_num; 1127 u8 dig_max; 1128 u8 dig_min; 1129 u8 txgi_factor; 1130 bool is_pwr_by_rate_dec; 1131 bool rx_ldpc; 1132 u8 max_power_index; 1133 1134 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1135 1136 bool ht_supported; 1137 bool vht_supported; 1138 u8 lps_deep_mode_supported; 1139 1140 /* init values */ 1141 u8 sys_func_en; 1142 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1143 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1144 const struct rtw_rqpn *rqpn_table; 1145 const struct rtw_prioq_addrs *prioq_addrs; 1146 const struct rtw_page_table *page_table; 1147 const struct rtw_intf_phy_para_table *intf_table; 1148 1149 const struct rtw_hw_reg *dig; 1150 const struct rtw_hw_reg *dig_cck; 1151 u32 rf_base_addr[2]; 1152 u32 rf_sipi_addr[2]; 1153 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1154 u8 fix_rf_phy_num; 1155 const struct rtw_ltecoex_addr *ltecoex_addr; 1156 1157 const struct rtw_table *mac_tbl; 1158 const struct rtw_table *agc_tbl; 1159 const struct rtw_table *bb_tbl; 1160 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1161 const struct rtw_table *rfk_init_tbl; 1162 1163 const struct rtw_rfe_def *rfe_defs; 1164 u32 rfe_defs_size; 1165 1166 bool en_dis_dpd; 1167 u16 dpd_ratemask; 1168 u8 iqk_threshold; 1169 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1170 1171 u8 bfer_su_max_num; 1172 u8 bfer_mu_max_num; 1173 1174 const char *wow_fw_name; 1175 const struct wiphy_wowlan_support *wowlan_stub; 1176 const u8 max_sched_scan_ssids; 1177 1178 /* for 8821c set channel */ 1179 u32 ch_param[3]; 1180 1181 /* coex paras */ 1182 u32 coex_para_ver; 1183 u8 bt_desired_ver; 1184 bool scbd_support; 1185 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1186 bool ble_hid_profile_support; 1187 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1188 u8 bt_rssi_type; 1189 u8 ant_isolation; 1190 u8 rssi_tolerance; 1191 u8 table_sant_num; 1192 u8 table_nsant_num; 1193 u8 tdma_sant_num; 1194 u8 tdma_nsant_num; 1195 u8 bt_afh_span_bw20; 1196 u8 bt_afh_span_bw40; 1197 u8 afh_5g_num; 1198 u8 wl_rf_para_num; 1199 u8 coex_info_hw_regs_num; 1200 const u8 *bt_rssi_step; 1201 const u8 *wl_rssi_step; 1202 const struct coex_table_para *table_nsant; 1203 const struct coex_table_para *table_sant; 1204 const struct coex_tdma_para *tdma_sant; 1205 const struct coex_tdma_para *tdma_nsant; 1206 const struct coex_rf_para *wl_rf_para_tx; 1207 const struct coex_rf_para *wl_rf_para_rx; 1208 const struct coex_5g_afh_map *afh_5g; 1209 const struct rtw_hw_reg *btg_reg; 1210 const struct rtw_reg_domain *coex_info_hw_regs; 1211 u32 wl_fw_desired_ver; 1212 }; 1213 1214 enum rtw_coex_bt_state_cnt { 1215 COEX_CNT_BT_RETRY, 1216 COEX_CNT_BT_REINIT, 1217 COEX_CNT_BT_REENABLE, 1218 COEX_CNT_BT_POPEVENT, 1219 COEX_CNT_BT_SETUPLINK, 1220 COEX_CNT_BT_IGNWLANACT, 1221 COEX_CNT_BT_INQ, 1222 COEX_CNT_BT_PAGE, 1223 COEX_CNT_BT_ROLESWITCH, 1224 COEX_CNT_BT_AFHUPDATE, 1225 COEX_CNT_BT_INFOUPDATE, 1226 COEX_CNT_BT_IQK, 1227 COEX_CNT_BT_IQKFAIL, 1228 1229 COEX_CNT_BT_MAX 1230 }; 1231 1232 enum rtw_coex_wl_state_cnt { 1233 COEX_CNT_WL_SCANAP, 1234 COEX_CNT_WL_CONNPKT, 1235 COEX_CNT_WL_COEXRUN, 1236 COEX_CNT_WL_NOISY0, 1237 COEX_CNT_WL_NOISY1, 1238 COEX_CNT_WL_NOISY2, 1239 COEX_CNT_WL_5MS_NOEXTEND, 1240 COEX_CNT_WL_FW_NOTIFY, 1241 1242 COEX_CNT_WL_MAX 1243 }; 1244 1245 struct rtw_coex_rfe { 1246 bool ant_switch_exist; 1247 bool ant_switch_diversity; 1248 bool ant_switch_with_bt; 1249 u8 rfe_module_type; 1250 u8 ant_switch_polarity; 1251 1252 /* true if WLG at BTG, else at WLAG */ 1253 bool wlg_at_btg; 1254 }; 1255 1256 #define COEX_WL_TDMA_PARA_LENGTH 5 1257 1258 struct rtw_coex_dm { 1259 bool cur_ps_tdma_on; 1260 bool cur_wl_rx_low_gain_en; 1261 bool ignore_wl_act; 1262 1263 u8 reason; 1264 u8 bt_rssi_state[4]; 1265 u8 wl_rssi_state[4]; 1266 u8 wl_ch_info[3]; 1267 u8 cur_ps_tdma; 1268 u8 cur_table; 1269 u8 ps_tdma_para[5]; 1270 u8 cur_bt_pwr_lvl; 1271 u8 cur_bt_lna_lvl; 1272 u8 cur_wl_pwr_lvl; 1273 u8 bt_status; 1274 u32 cur_ant_pos_type; 1275 u32 cur_switch_status; 1276 u32 setting_tdma; 1277 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1278 }; 1279 1280 #define COEX_BTINFO_SRC_WL_FW 0x0 1281 #define COEX_BTINFO_SRC_BT_RSP 0x1 1282 #define COEX_BTINFO_SRC_BT_ACT 0x2 1283 #define COEX_BTINFO_SRC_BT_IQK 0x3 1284 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1285 #define COEX_BTINFO_SRC_H2C60 0x5 1286 #define COEX_BTINFO_SRC_MAX 0x6 1287 1288 #define COEX_INFO_FTP BIT(7) 1289 #define COEX_INFO_A2DP BIT(6) 1290 #define COEX_INFO_HID BIT(5) 1291 #define COEX_INFO_SCO_BUSY BIT(4) 1292 #define COEX_INFO_ACL_BUSY BIT(3) 1293 #define COEX_INFO_INQ_PAGE BIT(2) 1294 #define COEX_INFO_SCO_ESCO BIT(1) 1295 #define COEX_INFO_CONNECTION BIT(0) 1296 #define COEX_BTINFO_LENGTH_MAX 10 1297 #define COEX_BTINFO_LENGTH 7 1298 1299 struct rtw_coex_stat { 1300 bool bt_disabled; 1301 bool bt_disabled_pre; 1302 bool bt_link_exist; 1303 bool bt_whck_test; 1304 bool bt_inq_page; 1305 bool bt_inq_remain; 1306 bool bt_inq; 1307 bool bt_page; 1308 bool bt_ble_voice; 1309 bool bt_ble_exist; 1310 bool bt_hfp_exist; 1311 bool bt_a2dp_exist; 1312 bool bt_hid_exist; 1313 bool bt_pan_exist; /* PAN or OPP */ 1314 bool bt_opp_exist; /* OPP only */ 1315 bool bt_acl_busy; 1316 bool bt_fix_2M; 1317 bool bt_setup_link; 1318 bool bt_multi_link; 1319 bool bt_multi_link_pre; 1320 bool bt_multi_link_remain; 1321 bool bt_a2dp_sink; 1322 bool bt_a2dp_active; 1323 bool bt_reenable; 1324 bool bt_ble_scan_en; 1325 bool bt_init_scan; 1326 bool bt_slave; 1327 bool bt_418_hid_exist; 1328 bool bt_ble_hid_exist; 1329 bool bt_mailbox_reply; 1330 1331 bool wl_under_lps; 1332 bool wl_under_ips; 1333 bool wl_hi_pri_task1; 1334 bool wl_hi_pri_task2; 1335 bool wl_force_lps_ctrl; 1336 bool wl_gl_busy; 1337 bool wl_linkscan_proc; 1338 bool wl_ps_state_fail; 1339 bool wl_tx_limit_en; 1340 bool wl_ampdu_limit_en; 1341 bool wl_connected; 1342 bool wl_slot_extend; 1343 bool wl_cck_lock; 1344 bool wl_cck_lock_pre; 1345 bool wl_cck_lock_ever; 1346 bool wl_connecting; 1347 bool wl_slot_toggle; 1348 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1349 1350 u32 bt_supported_version; 1351 u32 bt_supported_feature; 1352 u32 hi_pri_tx; 1353 u32 hi_pri_rx; 1354 u32 lo_pri_tx; 1355 u32 lo_pri_rx; 1356 u32 patch_ver; 1357 u16 bt_reg_vendor_ae; 1358 u16 bt_reg_vendor_ac; 1359 s8 bt_rssi; 1360 u8 kt_ver; 1361 u8 gnt_workaround_state; 1362 u8 tdma_timer_base; 1363 u8 bt_profile_num; 1364 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1365 u8 bt_info_lb2; 1366 u8 bt_info_lb3; 1367 u8 bt_info_hb0; 1368 u8 bt_info_hb1; 1369 u8 bt_info_hb2; 1370 u8 bt_info_hb3; 1371 u8 bt_ble_scan_type; 1372 u8 bt_hid_pair_num; 1373 u8 bt_hid_slot; 1374 u8 bt_a2dp_bitpool; 1375 u8 bt_iqk_state; 1376 1377 u16 wl_beacon_interval; 1378 u8 wl_noisy_level; 1379 u8 wl_fw_dbg_info[10]; 1380 u8 wl_fw_dbg_info_pre[10]; 1381 u8 wl_rx_rate; 1382 u8 wl_tx_rate; 1383 u8 wl_rts_rx_rate; 1384 u8 wl_coex_mode; 1385 u8 wl_iot_peer; 1386 u8 ampdu_max_time; 1387 u8 wl_tput_dir; 1388 1389 u8 wl_toggle_para[6]; 1390 u8 wl_toggle_interval; 1391 1392 u16 score_board; 1393 u16 retry_limit; 1394 1395 /* counters to record bt states */ 1396 u32 cnt_bt[COEX_CNT_BT_MAX]; 1397 1398 /* counters to record wifi states */ 1399 u32 cnt_wl[COEX_CNT_WL_MAX]; 1400 1401 /* counters to record bt c2h data */ 1402 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1403 1404 u32 darfrc; 1405 u32 darfrch; 1406 }; 1407 1408 struct rtw_coex { 1409 /* protects coex info request section */ 1410 struct mutex mutex; 1411 struct sk_buff_head queue; 1412 wait_queue_head_t wait; 1413 1414 bool under_5g; 1415 bool stop_dm; 1416 bool freeze; 1417 bool freerun; 1418 bool wl_rf_off; 1419 bool manual_control; 1420 1421 struct rtw_coex_stat stat; 1422 struct rtw_coex_dm dm; 1423 struct rtw_coex_rfe rfe; 1424 1425 struct delayed_work bt_relink_work; 1426 struct delayed_work bt_reenable_work; 1427 struct delayed_work defreeze_work; 1428 struct delayed_work wl_remain_work; 1429 struct delayed_work bt_remain_work; 1430 struct delayed_work wl_connecting_work; 1431 struct delayed_work bt_multi_link_remain_work; 1432 struct delayed_work wl_ccklock_work; 1433 1434 }; 1435 1436 #define DPK_RF_REG_NUM 7 1437 #define DPK_RF_PATH_NUM 2 1438 #define DPK_BB_REG_NUM 18 1439 #define DPK_CHANNEL_WIDTH_80 1 1440 1441 DECLARE_EWMA(thermal, 10, 4); 1442 1443 struct rtw_dpk_info { 1444 bool is_dpk_pwr_on; 1445 bool is_reload; 1446 1447 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1448 1449 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1450 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1451 1452 u32 gnt_control; 1453 u32 gnt_value; 1454 1455 u8 result[RTW_RF_PATH_MAX]; 1456 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1457 u32 coef[RTW_RF_PATH_MAX][20]; 1458 u16 dpk_gs[RTW_RF_PATH_MAX]; 1459 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1460 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1461 1462 u8 dpk_band; 1463 u8 dpk_ch; 1464 u8 dpk_bw; 1465 }; 1466 1467 struct rtw_phy_cck_pd_reg { 1468 u32 reg_pd; 1469 u32 mask_pd; 1470 u32 reg_cs; 1471 u32 mask_cs; 1472 }; 1473 1474 #define DACK_MSBK_BACKUP_NUM 0xf 1475 #define DACK_DCK_BACKUP_NUM 0x2 1476 1477 struct rtw_swing_table { 1478 const u8 *p[RTW_RF_PATH_MAX]; 1479 const u8 *n[RTW_RF_PATH_MAX]; 1480 }; 1481 1482 struct rtw_pkt_count { 1483 u16 num_bcn_pkt; 1484 u16 num_qry_pkt[DESC_RATE_MAX]; 1485 }; 1486 1487 DECLARE_EWMA(evm, 10, 4); 1488 DECLARE_EWMA(snr, 10, 4); 1489 1490 struct rtw_iqk_info { 1491 bool done; 1492 struct { 1493 u32 s1_x; 1494 u32 s1_y; 1495 u32 s0_x; 1496 u32 s0_y; 1497 } result; 1498 }; 1499 1500 #define RRSR_INIT_2G 0x15f 1501 #define RRSR_INIT_5G 0x150 1502 1503 struct rtw_dm_info { 1504 u32 cck_fa_cnt; 1505 u32 ofdm_fa_cnt; 1506 u32 total_fa_cnt; 1507 u32 cck_cca_cnt; 1508 u32 ofdm_cca_cnt; 1509 u32 total_cca_cnt; 1510 1511 u32 cck_ok_cnt; 1512 u32 cck_err_cnt; 1513 u32 ofdm_ok_cnt; 1514 u32 ofdm_err_cnt; 1515 u32 ht_ok_cnt; 1516 u32 ht_err_cnt; 1517 u32 vht_ok_cnt; 1518 u32 vht_err_cnt; 1519 1520 u8 min_rssi; 1521 u8 pre_min_rssi; 1522 u16 fa_history[4]; 1523 u8 igi_history[4]; 1524 u8 igi_bitmap; 1525 bool damping; 1526 u8 damping_cnt; 1527 u8 damping_rssi; 1528 1529 u8 cck_gi_u_bnd; 1530 u8 cck_gi_l_bnd; 1531 1532 u8 tx_rate; 1533 u32 rrsr_val_init; 1534 u32 rrsr_mask_min; 1535 u8 thermal_avg[RTW_RF_PATH_MAX]; 1536 u8 thermal_meter_k; 1537 s8 delta_power_index[RTW_RF_PATH_MAX]; 1538 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1539 u8 default_ofdm_index; 1540 bool pwr_trk_triggered; 1541 bool pwr_trk_init_trigger; 1542 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1543 s8 txagc_remnant_cck; 1544 s8 txagc_remnant_ofdm; 1545 1546 /* backup dack results for each path and I/Q */ 1547 u32 dack_adck[RTW_RF_PATH_MAX]; 1548 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1549 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1550 1551 struct rtw_dpk_info dpk_info; 1552 1553 /* [bandwidth 0:20M/1:40M][number of path] */ 1554 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1555 u32 cck_fa_avg; 1556 u8 cck_pd_default; 1557 1558 /* save the last rx phy status for debug */ 1559 s8 rx_snr[RTW_RF_PATH_MAX]; 1560 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1561 s16 cfo_tail[RTW_RF_PATH_MAX]; 1562 u8 rssi[RTW_RF_PATH_MAX]; 1563 u8 curr_rx_rate; 1564 struct rtw_pkt_count cur_pkt_count; 1565 struct rtw_pkt_count last_pkt_count; 1566 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1567 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1568 1569 struct rtw_iqk_info iqk; 1570 }; 1571 1572 struct rtw_efuse { 1573 u32 size; 1574 u32 physical_size; 1575 u32 logical_size; 1576 u32 protect_size; 1577 1578 u8 addr[ETH_ALEN]; 1579 u8 channel_plan; 1580 u8 country_code[2]; 1581 u8 rf_board_option; 1582 u8 rfe_option; 1583 u8 power_track_type; 1584 u8 thermal_meter[RTW_RF_PATH_MAX]; 1585 u8 thermal_meter_k; 1586 u8 crystal_cap; 1587 u8 ant_div_cfg; 1588 u8 ant_div_type; 1589 u8 regd; 1590 u8 afe; 1591 1592 u8 lna_type_2g; 1593 u8 lna_type_5g; 1594 u8 glna_type; 1595 u8 alna_type; 1596 bool ext_lna_2g; 1597 bool ext_lna_5g; 1598 u8 pa_type_2g; 1599 u8 pa_type_5g; 1600 u8 gpa_type; 1601 u8 apa_type; 1602 bool ext_pa_2g; 1603 bool ext_pa_5g; 1604 u8 tx_bb_swing_setting_2g; 1605 u8 tx_bb_swing_setting_5g; 1606 1607 bool btcoex; 1608 /* bt share antenna with wifi */ 1609 bool share_ant; 1610 u8 bt_setting; 1611 1612 struct { 1613 u8 hci; 1614 u8 bw; 1615 u8 ptcl; 1616 u8 nss; 1617 u8 ant_num; 1618 } hw_cap; 1619 1620 struct rtw_txpwr_idx txpwr_idx_table[4]; 1621 }; 1622 1623 struct rtw_phy_cond { 1624 #ifdef __LITTLE_ENDIAN 1625 u32 rfe:8; 1626 u32 intf:4; 1627 u32 pkg:4; 1628 u32 plat:4; 1629 u32 intf_rsvd:4; 1630 u32 cut:4; 1631 u32 branch:2; 1632 u32 neg:1; 1633 u32 pos:1; 1634 #else 1635 u32 pos:1; 1636 u32 neg:1; 1637 u32 branch:2; 1638 u32 cut:4; 1639 u32 intf_rsvd:4; 1640 u32 plat:4; 1641 u32 pkg:4; 1642 u32 intf:4; 1643 u32 rfe:8; 1644 #endif 1645 /* for intf:4 */ 1646 #define INTF_PCIE BIT(0) 1647 #define INTF_USB BIT(1) 1648 #define INTF_SDIO BIT(2) 1649 /* for branch:2 */ 1650 #define BRANCH_IF 0 1651 #define BRANCH_ELIF 1 1652 #define BRANCH_ELSE 2 1653 #define BRANCH_ENDIF 3 1654 }; 1655 1656 struct rtw_fifo_conf { 1657 /* tx fifo information */ 1658 u16 rsvd_boundary; 1659 u16 rsvd_pg_num; 1660 u16 rsvd_drv_pg_num; 1661 u16 txff_pg_num; 1662 u16 acq_pg_num; 1663 u16 rsvd_drv_addr; 1664 u16 rsvd_h2c_info_addr; 1665 u16 rsvd_h2c_sta_info_addr; 1666 u16 rsvd_h2cq_addr; 1667 u16 rsvd_cpu_instr_addr; 1668 u16 rsvd_fw_txbuf_addr; 1669 u16 rsvd_csibuf_addr; 1670 const struct rtw_rqpn *rqpn; 1671 }; 1672 1673 #define FW_CD_TYPE 0xffff 1674 #define FW_CD_LEN 4 1675 #define FW_CD_VAL 0xaabbccdd 1676 struct rtw_fw_state { 1677 const struct firmware *firmware; 1678 struct rtw_dev *rtwdev; 1679 struct completion completion; 1680 u16 version; 1681 u8 sub_version; 1682 u8 sub_index; 1683 u16 h2c_version; 1684 u8 prev_dump_seq; 1685 u32 feature; 1686 }; 1687 1688 struct rtw_hal { 1689 u32 rcr; 1690 1691 u32 chip_version; 1692 u8 cut_version; 1693 u8 mp_chip; 1694 u8 oem_id; 1695 struct rtw_phy_cond phy_cond; 1696 1697 u8 ps_mode; 1698 u8 current_channel; 1699 u8 current_band_width; 1700 u8 current_band_type; 1701 1702 /* center channel for different available bandwidth, 1703 * val of (bw > current_band_width) is invalid 1704 */ 1705 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1706 1707 u8 sec_ch_offset; 1708 u8 rf_type; 1709 u8 rf_path_num; 1710 u8 rf_phy_num; 1711 u32 antenna_tx; 1712 u32 antenna_rx; 1713 u8 bfee_sts_cap; 1714 1715 /* protect tx power section */ 1716 struct mutex tx_power_mutex; 1717 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1718 [DESC_RATE_MAX]; 1719 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1720 [DESC_RATE_MAX]; 1721 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1722 [RTW_RATE_SECTION_MAX]; 1723 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1724 [RTW_RATE_SECTION_MAX]; 1725 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1726 [RTW_CHANNEL_WIDTH_MAX] 1727 [RTW_RATE_SECTION_MAX] 1728 [RTW_MAX_CHANNEL_NUM_2G]; 1729 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1730 [RTW_CHANNEL_WIDTH_MAX] 1731 [RTW_RATE_SECTION_MAX] 1732 [RTW_MAX_CHANNEL_NUM_5G]; 1733 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1734 [DESC_RATE_MAX]; 1735 }; 1736 1737 struct rtw_dev { 1738 struct ieee80211_hw *hw; 1739 struct device *dev; 1740 1741 struct rtw_hci hci; 1742 1743 struct rtw_chip_info *chip; 1744 struct rtw_hal hal; 1745 struct rtw_fifo_conf fifo; 1746 struct rtw_fw_state fw; 1747 struct rtw_efuse efuse; 1748 struct rtw_sec_desc sec; 1749 struct rtw_traffic_stats stats; 1750 struct rtw_regulatory regd; 1751 struct rtw_bf_info bf_info; 1752 1753 struct rtw_dm_info dm_info; 1754 struct rtw_coex coex; 1755 1756 /* ensures exclusive access from mac80211 callbacks */ 1757 struct mutex mutex; 1758 1759 /* read/write rf register */ 1760 spinlock_t rf_lock; 1761 1762 /* watch dog every 2 sec */ 1763 struct delayed_work watch_dog_work; 1764 u32 watch_dog_cnt; 1765 1766 struct list_head rsvd_page_list; 1767 1768 /* c2h cmd queue & handler work */ 1769 struct sk_buff_head c2h_queue; 1770 struct work_struct c2h_work; 1771 struct work_struct fw_recovery_work; 1772 1773 /* used to protect txqs list */ 1774 spinlock_t txq_lock; 1775 struct list_head txqs; 1776 struct workqueue_struct *tx_wq; 1777 struct work_struct tx_work; 1778 struct work_struct ba_work; 1779 1780 struct rtw_tx_report tx_report; 1781 1782 struct { 1783 /* incicate the mail box to use with fw */ 1784 u8 last_box_num; 1785 /* protect to send h2c to fw */ 1786 spinlock_t lock; 1787 u32 seq; 1788 } h2c; 1789 1790 /* lps power state & handler work */ 1791 struct rtw_lps_conf lps_conf; 1792 bool ps_enabled; 1793 struct completion lps_leave_check; 1794 1795 struct dentry *debugfs; 1796 1797 u8 sta_cnt; 1798 u32 rts_threshold; 1799 1800 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1801 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1802 1803 u8 mp_mode; 1804 1805 struct rtw_fw_state wow_fw; 1806 struct rtw_wow_param wow; 1807 1808 bool need_rfk; 1809 1810 /* hci related data, must be last */ 1811 u8 priv[] __aligned(sizeof(void *)); 1812 }; 1813 1814 #include "hci.h" 1815 1816 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1817 { 1818 return !!rtwdev->sta_cnt; 1819 } 1820 1821 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1822 { 1823 void *p = rtwtxq; 1824 1825 return container_of(p, struct ieee80211_txq, drv_priv); 1826 } 1827 1828 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1829 { 1830 void *p = rtwvif; 1831 1832 return container_of(p, struct ieee80211_vif, drv_priv); 1833 } 1834 1835 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 1836 struct cfg80211_ssid *b) 1837 { 1838 if (!a || !b || a->ssid_len != b->ssid_len) 1839 return false; 1840 1841 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 1842 return false; 1843 1844 return true; 1845 } 1846 1847 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 1848 { 1849 if (rtwdev->chip->ops->efuse_grant) 1850 rtwdev->chip->ops->efuse_grant(rtwdev, true); 1851 } 1852 1853 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 1854 { 1855 if (rtwdev->chip->ops->efuse_grant) 1856 rtwdev->chip->ops->efuse_grant(rtwdev, false); 1857 } 1858 1859 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 1860 { 1861 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 1862 } 1863 1864 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 1865 { 1866 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 1867 } 1868 1869 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 1870 { 1871 return rtwdev->chip->rx_ldpc; 1872 } 1873 1874 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 1875 { 1876 clear_bit(mac_id, rtwdev->mac_id_map); 1877 } 1878 1879 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1880 struct rtw_channel_params *ch_param); 1881 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1882 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1883 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1884 void rtw_restore_reg(struct rtw_dev *rtwdev, 1885 struct rtw_backup_info *bckp, u32 num); 1886 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1887 void rtw_set_channel(struct rtw_dev *rtwdev); 1888 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 1889 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1890 u32 config); 1891 void rtw_tx_report_purge_timer(struct timer_list *t); 1892 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1893 int rtw_core_start(struct rtw_dev *rtwdev); 1894 void rtw_core_stop(struct rtw_dev *rtwdev); 1895 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1896 int rtw_core_init(struct rtw_dev *rtwdev); 1897 void rtw_core_deinit(struct rtw_dev *rtwdev); 1898 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1899 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1900 u16 rtw_desc_to_bitrate(u8 desc_rate); 1901 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 1902 struct ieee80211_bss_conf *conf); 1903 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 1904 struct ieee80211_vif *vif); 1905 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 1906 bool fw_exist); 1907 void rtw_fw_recovery(struct rtw_dev *rtwdev); 1908 1909 #endif 1910