1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7 
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17 
18 #include "util.h"
19 
20 #define RTW_MAX_MAC_ID_NUM		32
21 #define RTW_MAX_SEC_CAM_NUM		32
22 #define MAX_PG_CAM_BACKUP_NUM		8
23 
24 #define RTW_SCAN_MAX_SSIDS		4
25 
26 #define RTW_MAX_PATTERN_NUM		12
27 #define RTW_MAX_PATTERN_MASK_SIZE	16
28 #define RTW_MAX_PATTERN_SIZE		128
29 
30 #define RTW_WATCH_DOG_DELAY_TIME	round_jiffies_relative(HZ * 2)
31 
32 #define RFREG_MASK			0xfffff
33 #define INV_RF_DATA			0xffffffff
34 #define TX_PAGE_SIZE_SHIFT		7
35 #define TX_PAGE_SIZE			(1 << TX_PAGE_SIZE_SHIFT)
36 
37 #define RTW_CHANNEL_WIDTH_MAX		3
38 #define RTW_RF_PATH_MAX			4
39 #define HW_FEATURE_LEN			13
40 
41 #define RTW_TP_SHIFT			18 /* bytes/2s --> Mbps */
42 
43 extern bool rtw_bf_support;
44 extern bool rtw_disable_lps_deep_mode;
45 extern unsigned int rtw_debug_mask;
46 extern bool rtw_edcca_enabled;
47 extern const struct ieee80211_ops rtw_ops;
48 
49 #define RTW_MAX_CHANNEL_NUM_2G 14
50 #define RTW_MAX_CHANNEL_NUM_5G 49
51 
52 struct rtw_dev;
53 
54 enum rtw_hci_type {
55 	RTW_HCI_TYPE_PCIE,
56 	RTW_HCI_TYPE_USB,
57 	RTW_HCI_TYPE_SDIO,
58 
59 	RTW_HCI_TYPE_UNDEFINE,
60 };
61 
62 struct rtw_hci {
63 	struct rtw_hci_ops *ops;
64 	enum rtw_hci_type type;
65 
66 	u32 rpwm_addr;
67 	u32 cpwm_addr;
68 
69 	u8 bulkout_num;
70 };
71 
72 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
73 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
74 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
75 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
76 
77 #define IS_CH_5G_BAND_MID(channel) \
78 	(IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
79 
80 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
81 #define IS_CH_5G_BAND(channel) \
82 	(IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
83 	 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
84 
85 enum rtw_supported_band {
86 	RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
87 	RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
88 	RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
89 };
90 
91 /* now, support up to 80M bw */
92 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
93 
94 enum rtw_bandwidth {
95 	RTW_CHANNEL_WIDTH_20	= 0,
96 	RTW_CHANNEL_WIDTH_40	= 1,
97 	RTW_CHANNEL_WIDTH_80	= 2,
98 	RTW_CHANNEL_WIDTH_160	= 3,
99 	RTW_CHANNEL_WIDTH_80_80	= 4,
100 	RTW_CHANNEL_WIDTH_5	= 5,
101 	RTW_CHANNEL_WIDTH_10	= 6,
102 };
103 
104 enum rtw_sc_offset {
105 	RTW_SC_DONT_CARE	= 0,
106 	RTW_SC_20_UPPER		= 1,
107 	RTW_SC_20_LOWER		= 2,
108 	RTW_SC_20_UPMOST	= 3,
109 	RTW_SC_20_LOWEST	= 4,
110 	RTW_SC_40_UPPER		= 9,
111 	RTW_SC_40_LOWER		= 10,
112 };
113 
114 enum rtw_net_type {
115 	RTW_NET_NO_LINK		= 0,
116 	RTW_NET_AD_HOC		= 1,
117 	RTW_NET_MGD_LINKED	= 2,
118 	RTW_NET_AP_MODE		= 3,
119 };
120 
121 enum rtw_rf_type {
122 	RF_1T1R			= 0,
123 	RF_1T2R			= 1,
124 	RF_2T2R			= 2,
125 	RF_2T3R			= 3,
126 	RF_2T4R			= 4,
127 	RF_3T3R			= 5,
128 	RF_3T4R			= 6,
129 	RF_4T4R			= 7,
130 	RF_TYPE_MAX,
131 };
132 
133 enum rtw_rf_path {
134 	RF_PATH_A = 0,
135 	RF_PATH_B = 1,
136 	RF_PATH_C = 2,
137 	RF_PATH_D = 3,
138 };
139 
140 enum rtw_bb_path {
141 	BB_PATH_A = BIT(0),
142 	BB_PATH_B = BIT(1),
143 	BB_PATH_C = BIT(2),
144 	BB_PATH_D = BIT(3),
145 
146 	BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
147 	BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
148 	BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
149 	BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
150 	BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
151 	BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
152 
153 	BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
154 	BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
155 	BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
156 	BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
157 
158 	BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
159 };
160 
161 enum rtw_rate_section {
162 	RTW_RATE_SECTION_CCK = 0,
163 	RTW_RATE_SECTION_OFDM,
164 	RTW_RATE_SECTION_HT_1S,
165 	RTW_RATE_SECTION_HT_2S,
166 	RTW_RATE_SECTION_VHT_1S,
167 	RTW_RATE_SECTION_VHT_2S,
168 
169 	/* keep last */
170 	RTW_RATE_SECTION_MAX,
171 };
172 
173 enum rtw_wireless_set {
174 	WIRELESS_CCK	= 0x00000001,
175 	WIRELESS_OFDM	= 0x00000002,
176 	WIRELESS_HT	= 0x00000004,
177 	WIRELESS_VHT	= 0x00000008,
178 };
179 
180 #define HT_STBC_EN	BIT(0)
181 #define VHT_STBC_EN	BIT(1)
182 #define HT_LDPC_EN	BIT(0)
183 #define VHT_LDPC_EN	BIT(1)
184 
185 enum rtw_chip_type {
186 	RTW_CHIP_TYPE_8822B,
187 	RTW_CHIP_TYPE_8822C,
188 	RTW_CHIP_TYPE_8723D,
189 	RTW_CHIP_TYPE_8821C,
190 };
191 
192 enum rtw_tx_queue_type {
193 	/* the order of AC queues matters */
194 	RTW_TX_QUEUE_BK = 0x0,
195 	RTW_TX_QUEUE_BE = 0x1,
196 	RTW_TX_QUEUE_VI = 0x2,
197 	RTW_TX_QUEUE_VO = 0x3,
198 
199 	RTW_TX_QUEUE_BCN = 0x4,
200 	RTW_TX_QUEUE_MGMT = 0x5,
201 	RTW_TX_QUEUE_HI0 = 0x6,
202 	RTW_TX_QUEUE_H2C = 0x7,
203 	/* keep it last */
204 	RTK_MAX_TX_QUEUE_NUM
205 };
206 
207 enum rtw_rx_queue_type {
208 	RTW_RX_QUEUE_MPDU = 0x0,
209 	RTW_RX_QUEUE_C2H = 0x1,
210 	/* keep it last */
211 	RTK_MAX_RX_QUEUE_NUM
212 };
213 
214 enum rtw_fw_type {
215 	RTW_NORMAL_FW = 0x0,
216 	RTW_WOWLAN_FW = 0x1,
217 };
218 
219 enum rtw_rate_index {
220 	RTW_RATEID_BGN_40M_2SS	= 0,
221 	RTW_RATEID_BGN_40M_1SS	= 1,
222 	RTW_RATEID_BGN_20M_2SS	= 2,
223 	RTW_RATEID_BGN_20M_1SS	= 3,
224 	RTW_RATEID_GN_N2SS	= 4,
225 	RTW_RATEID_GN_N1SS	= 5,
226 	RTW_RATEID_BG		= 6,
227 	RTW_RATEID_G		= 7,
228 	RTW_RATEID_B_20M	= 8,
229 	RTW_RATEID_ARFR0_AC_2SS	= 9,
230 	RTW_RATEID_ARFR1_AC_1SS	= 10,
231 	RTW_RATEID_ARFR2_AC_2G_1SS = 11,
232 	RTW_RATEID_ARFR3_AC_2G_2SS = 12,
233 	RTW_RATEID_ARFR4_AC_3SS	= 13,
234 	RTW_RATEID_ARFR5_N_3SS	= 14,
235 	RTW_RATEID_ARFR7_N_4SS	= 15,
236 	RTW_RATEID_ARFR6_AC_4SS	= 16
237 };
238 
239 enum rtw_trx_desc_rate {
240 	DESC_RATE1M	= 0x00,
241 	DESC_RATE2M	= 0x01,
242 	DESC_RATE5_5M	= 0x02,
243 	DESC_RATE11M	= 0x03,
244 
245 	DESC_RATE6M	= 0x04,
246 	DESC_RATE9M	= 0x05,
247 	DESC_RATE12M	= 0x06,
248 	DESC_RATE18M	= 0x07,
249 	DESC_RATE24M	= 0x08,
250 	DESC_RATE36M	= 0x09,
251 	DESC_RATE48M	= 0x0a,
252 	DESC_RATE54M	= 0x0b,
253 
254 	DESC_RATEMCS0	= 0x0c,
255 	DESC_RATEMCS1	= 0x0d,
256 	DESC_RATEMCS2	= 0x0e,
257 	DESC_RATEMCS3	= 0x0f,
258 	DESC_RATEMCS4	= 0x10,
259 	DESC_RATEMCS5	= 0x11,
260 	DESC_RATEMCS6	= 0x12,
261 	DESC_RATEMCS7	= 0x13,
262 	DESC_RATEMCS8	= 0x14,
263 	DESC_RATEMCS9	= 0x15,
264 	DESC_RATEMCS10	= 0x16,
265 	DESC_RATEMCS11	= 0x17,
266 	DESC_RATEMCS12	= 0x18,
267 	DESC_RATEMCS13	= 0x19,
268 	DESC_RATEMCS14	= 0x1a,
269 	DESC_RATEMCS15	= 0x1b,
270 	DESC_RATEMCS16	= 0x1c,
271 	DESC_RATEMCS17	= 0x1d,
272 	DESC_RATEMCS18	= 0x1e,
273 	DESC_RATEMCS19	= 0x1f,
274 	DESC_RATEMCS20	= 0x20,
275 	DESC_RATEMCS21	= 0x21,
276 	DESC_RATEMCS22	= 0x22,
277 	DESC_RATEMCS23	= 0x23,
278 	DESC_RATEMCS24	= 0x24,
279 	DESC_RATEMCS25	= 0x25,
280 	DESC_RATEMCS26	= 0x26,
281 	DESC_RATEMCS27	= 0x27,
282 	DESC_RATEMCS28	= 0x28,
283 	DESC_RATEMCS29	= 0x29,
284 	DESC_RATEMCS30	= 0x2a,
285 	DESC_RATEMCS31	= 0x2b,
286 
287 	DESC_RATEVHT1SS_MCS0	= 0x2c,
288 	DESC_RATEVHT1SS_MCS1	= 0x2d,
289 	DESC_RATEVHT1SS_MCS2	= 0x2e,
290 	DESC_RATEVHT1SS_MCS3	= 0x2f,
291 	DESC_RATEVHT1SS_MCS4	= 0x30,
292 	DESC_RATEVHT1SS_MCS5	= 0x31,
293 	DESC_RATEVHT1SS_MCS6	= 0x32,
294 	DESC_RATEVHT1SS_MCS7	= 0x33,
295 	DESC_RATEVHT1SS_MCS8	= 0x34,
296 	DESC_RATEVHT1SS_MCS9	= 0x35,
297 
298 	DESC_RATEVHT2SS_MCS0	= 0x36,
299 	DESC_RATEVHT2SS_MCS1	= 0x37,
300 	DESC_RATEVHT2SS_MCS2	= 0x38,
301 	DESC_RATEVHT2SS_MCS3	= 0x39,
302 	DESC_RATEVHT2SS_MCS4	= 0x3a,
303 	DESC_RATEVHT2SS_MCS5	= 0x3b,
304 	DESC_RATEVHT2SS_MCS6	= 0x3c,
305 	DESC_RATEVHT2SS_MCS7	= 0x3d,
306 	DESC_RATEVHT2SS_MCS8	= 0x3e,
307 	DESC_RATEVHT2SS_MCS9	= 0x3f,
308 
309 	DESC_RATEVHT3SS_MCS0	= 0x40,
310 	DESC_RATEVHT3SS_MCS1	= 0x41,
311 	DESC_RATEVHT3SS_MCS2	= 0x42,
312 	DESC_RATEVHT3SS_MCS3	= 0x43,
313 	DESC_RATEVHT3SS_MCS4	= 0x44,
314 	DESC_RATEVHT3SS_MCS5	= 0x45,
315 	DESC_RATEVHT3SS_MCS6	= 0x46,
316 	DESC_RATEVHT3SS_MCS7	= 0x47,
317 	DESC_RATEVHT3SS_MCS8	= 0x48,
318 	DESC_RATEVHT3SS_MCS9	= 0x49,
319 
320 	DESC_RATEVHT4SS_MCS0	= 0x4a,
321 	DESC_RATEVHT4SS_MCS1	= 0x4b,
322 	DESC_RATEVHT4SS_MCS2	= 0x4c,
323 	DESC_RATEVHT4SS_MCS3	= 0x4d,
324 	DESC_RATEVHT4SS_MCS4	= 0x4e,
325 	DESC_RATEVHT4SS_MCS5	= 0x4f,
326 	DESC_RATEVHT4SS_MCS6	= 0x50,
327 	DESC_RATEVHT4SS_MCS7	= 0x51,
328 	DESC_RATEVHT4SS_MCS8	= 0x52,
329 	DESC_RATEVHT4SS_MCS9	= 0x53,
330 
331 	DESC_RATE_MAX,
332 };
333 
334 enum rtw_regulatory_domains {
335 	RTW_REGD_FCC		= 0,
336 	RTW_REGD_MKK		= 1,
337 	RTW_REGD_ETSI		= 2,
338 	RTW_REGD_IC		= 3,
339 	RTW_REGD_KCC		= 4,
340 	RTW_REGD_ACMA		= 5,
341 	RTW_REGD_CHILE		= 6,
342 	RTW_REGD_UKRAINE	= 7,
343 	RTW_REGD_MEXICO		= 8,
344 	RTW_REGD_CN		= 9,
345 	RTW_REGD_WW,
346 
347 	RTW_REGD_MAX
348 };
349 
350 enum rtw_txq_flags {
351 	RTW_TXQ_AMPDU,
352 	RTW_TXQ_BLOCK_BA,
353 };
354 
355 enum rtw_flags {
356 	RTW_FLAG_RUNNING,
357 	RTW_FLAG_FW_RUNNING,
358 	RTW_FLAG_SCANNING,
359 	RTW_FLAG_POWERON,
360 	RTW_FLAG_LEISURE_PS,
361 	RTW_FLAG_LEISURE_PS_DEEP,
362 	RTW_FLAG_DIG_DISABLE,
363 	RTW_FLAG_BUSY_TRAFFIC,
364 	RTW_FLAG_WOWLAN,
365 	RTW_FLAG_RESTARTING,
366 	RTW_FLAG_RESTART_TRIGGERING,
367 	RTW_FLAG_FORCE_LOWEST_RATE,
368 
369 	NUM_OF_RTW_FLAGS,
370 };
371 
372 enum rtw_evm {
373 	RTW_EVM_OFDM = 0,
374 	RTW_EVM_1SS,
375 	RTW_EVM_2SS_A,
376 	RTW_EVM_2SS_B,
377 	/* keep it last */
378 	RTW_EVM_NUM
379 };
380 
381 enum rtw_snr {
382 	RTW_SNR_OFDM_A = 0,
383 	RTW_SNR_OFDM_B,
384 	RTW_SNR_OFDM_C,
385 	RTW_SNR_OFDM_D,
386 	RTW_SNR_1SS_A,
387 	RTW_SNR_1SS_B,
388 	RTW_SNR_1SS_C,
389 	RTW_SNR_1SS_D,
390 	RTW_SNR_2SS_A,
391 	RTW_SNR_2SS_B,
392 	RTW_SNR_2SS_C,
393 	RTW_SNR_2SS_D,
394 	/* keep it last */
395 	RTW_SNR_NUM
396 };
397 
398 enum rtw_port {
399 	RTW_PORT_0 = 0,
400 	RTW_PORT_1 = 1,
401 	RTW_PORT_2 = 2,
402 	RTW_PORT_3 = 3,
403 	RTW_PORT_4 = 4,
404 	RTW_PORT_NUM
405 };
406 
407 enum rtw_wow_flags {
408 	RTW_WOW_FLAG_EN_MAGIC_PKT,
409 	RTW_WOW_FLAG_EN_REKEY_PKT,
410 	RTW_WOW_FLAG_EN_DISCONNECT,
411 
412 	/* keep it last */
413 	RTW_WOW_FLAG_MAX,
414 };
415 
416 /* the power index is represented by differences, which cck-1s & ht40-1s are
417  * the base values, so for 1s's differences, there are only ht20 & ofdm
418  */
419 struct rtw_2g_1s_pwr_idx_diff {
420 #ifdef __LITTLE_ENDIAN
421 	s8 ofdm:4;
422 	s8 bw20:4;
423 #else
424 	s8 bw20:4;
425 	s8 ofdm:4;
426 #endif
427 } __packed;
428 
429 struct rtw_2g_ns_pwr_idx_diff {
430 #ifdef __LITTLE_ENDIAN
431 	s8 bw20:4;
432 	s8 bw40:4;
433 	s8 cck:4;
434 	s8 ofdm:4;
435 #else
436 	s8 ofdm:4;
437 	s8 cck:4;
438 	s8 bw40:4;
439 	s8 bw20:4;
440 #endif
441 } __packed;
442 
443 struct rtw_2g_txpwr_idx {
444 	u8 cck_base[6];
445 	u8 bw40_base[5];
446 	struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
447 	struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
448 	struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
449 	struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
450 };
451 
452 struct rtw_5g_ht_1s_pwr_idx_diff {
453 #ifdef __LITTLE_ENDIAN
454 	s8 ofdm:4;
455 	s8 bw20:4;
456 #else
457 	s8 bw20:4;
458 	s8 ofdm:4;
459 #endif
460 } __packed;
461 
462 struct rtw_5g_ht_ns_pwr_idx_diff {
463 #ifdef __LITTLE_ENDIAN
464 	s8 bw20:4;
465 	s8 bw40:4;
466 #else
467 	s8 bw40:4;
468 	s8 bw20:4;
469 #endif
470 } __packed;
471 
472 struct rtw_5g_ofdm_ns_pwr_idx_diff {
473 #ifdef __LITTLE_ENDIAN
474 	s8 ofdm_3s:4;
475 	s8 ofdm_2s:4;
476 	s8 ofdm_4s:4;
477 	s8 res:4;
478 #else
479 	s8 res:4;
480 	s8 ofdm_4s:4;
481 	s8 ofdm_2s:4;
482 	s8 ofdm_3s:4;
483 #endif
484 } __packed;
485 
486 struct rtw_5g_vht_ns_pwr_idx_diff {
487 #ifdef __LITTLE_ENDIAN
488 	s8 bw160:4;
489 	s8 bw80:4;
490 #else
491 	s8 bw80:4;
492 	s8 bw160:4;
493 #endif
494 } __packed;
495 
496 struct rtw_5g_txpwr_idx {
497 	u8 bw40_base[14];
498 	struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
499 	struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
500 	struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
501 	struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
502 	struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
503 	struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
504 	struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
505 	struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
506 	struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
507 };
508 
509 struct rtw_txpwr_idx {
510 	struct rtw_2g_txpwr_idx pwr_idx_2g;
511 	struct rtw_5g_txpwr_idx pwr_idx_5g;
512 };
513 
514 struct rtw_channel_params {
515 	u8 center_chan;
516 	u8 primary_chan;
517 	u8 bandwidth;
518 };
519 
520 struct rtw_hw_reg {
521 	u32 addr;
522 	u32 mask;
523 };
524 
525 struct rtw_ltecoex_addr {
526 	u32 ctrl;
527 	u32 wdata;
528 	u32 rdata;
529 };
530 
531 struct rtw_reg_domain {
532 	u32 addr;
533 	u32 mask;
534 #define RTW_REG_DOMAIN_MAC32	0
535 #define RTW_REG_DOMAIN_MAC16	1
536 #define RTW_REG_DOMAIN_MAC8	2
537 #define RTW_REG_DOMAIN_RF_A	3
538 #define RTW_REG_DOMAIN_RF_B	4
539 #define RTW_REG_DOMAIN_NL	0xFF
540 	u8 domain;
541 };
542 
543 struct rtw_rf_sipi_addr {
544 	u32 hssi_1;
545 	u32 hssi_2;
546 	u32 lssi_read;
547 	u32 lssi_read_pi;
548 };
549 
550 struct rtw_hw_reg_offset {
551 	struct rtw_hw_reg hw_reg;
552 	u8 offset;
553 };
554 
555 struct rtw_backup_info {
556 	u8 len;
557 	u32 reg;
558 	u32 val;
559 };
560 
561 enum rtw_vif_port_set {
562 	PORT_SET_MAC_ADDR	= BIT(0),
563 	PORT_SET_BSSID		= BIT(1),
564 	PORT_SET_NET_TYPE	= BIT(2),
565 	PORT_SET_AID		= BIT(3),
566 	PORT_SET_BCN_CTRL	= BIT(4),
567 };
568 
569 struct rtw_vif_port {
570 	struct rtw_hw_reg mac_addr;
571 	struct rtw_hw_reg bssid;
572 	struct rtw_hw_reg net_type;
573 	struct rtw_hw_reg aid;
574 	struct rtw_hw_reg bcn_ctrl;
575 };
576 
577 struct rtw_tx_pkt_info {
578 	u32 tx_pkt_size;
579 	u8 offset;
580 	u8 pkt_offset;
581 	u8 tim_offset;
582 	u8 mac_id;
583 	u8 rate_id;
584 	u8 rate;
585 	u8 qsel;
586 	u8 bw;
587 	u8 sec_type;
588 	u8 sn;
589 	bool ampdu_en;
590 	u8 ampdu_factor;
591 	u8 ampdu_density;
592 	u16 seq;
593 	bool stbc;
594 	bool ldpc;
595 	bool dis_rate_fallback;
596 	bool bmc;
597 	bool use_rate;
598 	bool ls;
599 	bool fs;
600 	bool short_gi;
601 	bool report;
602 	bool rts;
603 	bool dis_qselseq;
604 	bool en_hwseq;
605 	u8 hw_ssn_sel;
606 	bool nav_use_hdr;
607 	bool bt_null;
608 };
609 
610 struct rtw_rx_pkt_stat {
611 	bool phy_status;
612 	bool icv_err;
613 	bool crc_err;
614 	bool decrypted;
615 	bool is_c2h;
616 
617 	s32 signal_power;
618 	u16 pkt_len;
619 	u8 bw;
620 	u8 drv_info_sz;
621 	u8 shift;
622 	u8 rate;
623 	u8 mac_id;
624 	u8 cam_id;
625 	u8 ppdu_cnt;
626 	u32 tsf_low;
627 	s8 rx_power[RTW_RF_PATH_MAX];
628 	u8 rssi;
629 	u8 rxsc;
630 	s8 rx_snr[RTW_RF_PATH_MAX];
631 	u8 rx_evm[RTW_RF_PATH_MAX];
632 	s8 cfo_tail[RTW_RF_PATH_MAX];
633 	u16 freq;
634 	u8 band;
635 
636 	struct rtw_sta_info *si;
637 	struct ieee80211_vif *vif;
638 	struct ieee80211_hdr *hdr;
639 };
640 
641 DECLARE_EWMA(tp, 10, 2);
642 
643 struct rtw_traffic_stats {
644 	/* units in bytes */
645 	u64 tx_unicast;
646 	u64 rx_unicast;
647 
648 	/* count for packets */
649 	u64 tx_cnt;
650 	u64 rx_cnt;
651 
652 	/* units in Mbps */
653 	u32 tx_throughput;
654 	u32 rx_throughput;
655 	struct ewma_tp tx_ewma_tp;
656 	struct ewma_tp rx_ewma_tp;
657 };
658 
659 enum rtw_lps_mode {
660 	RTW_MODE_ACTIVE	= 0,
661 	RTW_MODE_LPS	= 1,
662 	RTW_MODE_WMM_PS	= 2,
663 };
664 
665 enum rtw_lps_deep_mode {
666 	LPS_DEEP_MODE_NONE	= 0,
667 	LPS_DEEP_MODE_LCLK	= 1,
668 	LPS_DEEP_MODE_PG	= 2,
669 };
670 
671 enum rtw_pwr_state {
672 	RTW_RF_OFF	= 0x0,
673 	RTW_RF_ON	= 0x4,
674 	RTW_ALL_ON	= 0xc,
675 };
676 
677 struct rtw_lps_conf {
678 	enum rtw_lps_mode mode;
679 	enum rtw_lps_deep_mode deep_mode;
680 	enum rtw_lps_deep_mode wow_deep_mode;
681 	enum rtw_pwr_state state;
682 	u8 awake_interval;
683 	u8 rlbm;
684 	u8 smart_ps;
685 	u8 port_id;
686 	bool sec_cam_backup;
687 	bool pattern_cam_backup;
688 };
689 
690 enum rtw_hw_key_type {
691 	RTW_CAM_NONE	= 0,
692 	RTW_CAM_WEP40	= 1,
693 	RTW_CAM_TKIP	= 2,
694 	RTW_CAM_AES	= 4,
695 	RTW_CAM_WEP104	= 5,
696 };
697 
698 struct rtw_cam_entry {
699 	bool valid;
700 	bool group;
701 	u8 addr[ETH_ALEN];
702 	u8 hw_key_type;
703 	struct ieee80211_key_conf *key;
704 };
705 
706 struct rtw_sec_desc {
707 	/* search strategy */
708 	bool default_key_search;
709 
710 	u32 total_cam_num;
711 	struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
712 	DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
713 };
714 
715 struct rtw_tx_report {
716 	/* protect the tx report queue */
717 	spinlock_t q_lock;
718 	struct sk_buff_head queue;
719 	atomic_t sn;
720 	struct timer_list purge_timer;
721 };
722 
723 struct rtw_ra_report {
724 	struct rate_info txrate;
725 	u32 bit_rate;
726 	u8 desc_rate;
727 };
728 
729 struct rtw_txq {
730 	struct list_head list;
731 	unsigned long flags;
732 };
733 
734 #define RTW_BC_MC_MACID 1
735 DECLARE_EWMA(rssi, 10, 16);
736 
737 struct rtw_sta_info {
738 	struct rtw_dev *rtwdev;
739 	struct ieee80211_sta *sta;
740 	struct ieee80211_vif *vif;
741 
742 	struct ewma_rssi avg_rssi;
743 	u8 rssi_level;
744 
745 	u8 mac_id;
746 	u8 rate_id;
747 	enum rtw_bandwidth bw_mode;
748 	enum rtw_rf_type rf_type;
749 	u8 stbc_en:2;
750 	u8 ldpc_en:2;
751 	bool sgi_enable;
752 	bool vht_enable;
753 	u8 init_ra_lv;
754 	u64 ra_mask;
755 
756 	DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
757 
758 	struct rtw_ra_report ra_report;
759 
760 	bool use_cfg_mask;
761 	struct cfg80211_bitrate_mask *mask;
762 
763 	struct work_struct rc_work;
764 };
765 
766 enum rtw_bfee_role {
767 	RTW_BFEE_NONE,
768 	RTW_BFEE_SU,
769 	RTW_BFEE_MU
770 };
771 
772 struct rtw_bfee {
773 	enum rtw_bfee_role role;
774 
775 	u16 p_aid;
776 	u8 g_id;
777 	u8 mac_addr[ETH_ALEN];
778 	u8 sound_dim;
779 
780 	/* SU-MIMO */
781 	u8 su_reg_index;
782 
783 	/* MU-MIMO */
784 	u16 aid;
785 };
786 
787 struct rtw_bf_info {
788 	u8 bfer_mu_cnt;
789 	u8 bfer_su_cnt;
790 	DECLARE_BITMAP(bfer_su_reg_maping, 2);
791 	u8 cur_csi_rpt_rate;
792 };
793 
794 struct rtw_vif {
795 	enum rtw_net_type net_type;
796 	u16 aid;
797 	u8 mac_id; /* for STA mode only */
798 	u8 mac_addr[ETH_ALEN];
799 	u8 bssid[ETH_ALEN];
800 	u8 port;
801 	u8 bcn_ctrl;
802 	struct list_head rsvd_page_list;
803 	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
804 	const struct rtw_vif_port *conf;
805 	struct cfg80211_scan_request *scan_req;
806 	struct ieee80211_scan_ies *scan_ies;
807 
808 	struct rtw_traffic_stats stats;
809 
810 	struct rtw_bfee bfee;
811 };
812 
813 struct rtw_regulatory {
814 	char alpha2[2];
815 	u8 txpwr_regd_2g;
816 	u8 txpwr_regd_5g;
817 };
818 
819 enum rtw_regd_state {
820 	RTW_REGD_STATE_WORLDWIDE,
821 	RTW_REGD_STATE_PROGRAMMED,
822 	RTW_REGD_STATE_SETTING,
823 
824 	RTW_REGD_STATE_NR,
825 };
826 
827 struct rtw_regd {
828 	enum rtw_regd_state state;
829 	const struct rtw_regulatory *regulatory;
830 	enum nl80211_dfs_regions dfs_region;
831 };
832 
833 struct rtw_chip_ops {
834 	int (*mac_init)(struct rtw_dev *rtwdev);
835 	int (*dump_fw_crash)(struct rtw_dev *rtwdev);
836 	void (*shutdown)(struct rtw_dev *rtwdev);
837 	int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
838 	void (*phy_set_param)(struct rtw_dev *rtwdev);
839 	void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
840 			    u8 bandwidth, u8 primary_chan_idx);
841 	void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
842 			      struct rtw_rx_pkt_stat *pkt_stat,
843 			      struct ieee80211_rx_status *rx_status);
844 	u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
845 		       u32 addr, u32 mask);
846 	bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
847 			 u32 addr, u32 mask, u32 data);
848 	void (*set_tx_power_index)(struct rtw_dev *rtwdev);
849 	int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
850 			      u32 size);
851 	int (*set_antenna)(struct rtw_dev *rtwdev,
852 			   u32 antenna_tx,
853 			   u32 antenna_rx);
854 	void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
855 	void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
856 	void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
857 	void (*phy_calibration)(struct rtw_dev *rtwdev);
858 	void (*dpk_track)(struct rtw_dev *rtwdev);
859 	void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
860 	void (*pwr_track)(struct rtw_dev *rtwdev);
861 	void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
862 			    struct rtw_bfee *bfee, bool enable);
863 	void (*set_gid_table)(struct rtw_dev *rtwdev,
864 			      struct ieee80211_vif *vif,
865 			      struct ieee80211_bss_conf *conf);
866 	void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
867 			     u8 fixrate_en, u8 *new_rate);
868 	void (*adaptivity_init)(struct rtw_dev *rtwdev);
869 	void (*adaptivity)(struct rtw_dev *rtwdev);
870 	void (*cfo_init)(struct rtw_dev *rtwdev);
871 	void (*cfo_track)(struct rtw_dev *rtwdev);
872 	void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
873 			       enum rtw_bb_path tx_path_1ss,
874 			       enum rtw_bb_path tx_path_cck,
875 			       bool is_tx2_path);
876 	void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
877 				 u8 rx_path, bool is_tx2_path);
878 	/* for USB/SDIO only */
879 	void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
880 				     struct rtw_tx_pkt_info *pkt_info,
881 				     u8 *txdesc);
882 
883 	/* for coex */
884 	void (*coex_set_init)(struct rtw_dev *rtwdev);
885 	void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
886 				    u8 ctrl_type, u8 pos_type);
887 	void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
888 	void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
889 	void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
890 	void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
891 	void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
892 };
893 
894 #define RTW_PWR_POLLING_CNT	20000
895 
896 #define RTW_PWR_CMD_READ	0x00
897 #define RTW_PWR_CMD_WRITE	0x01
898 #define RTW_PWR_CMD_POLLING	0x02
899 #define RTW_PWR_CMD_DELAY	0x03
900 #define RTW_PWR_CMD_END		0x04
901 
902 /* define the base address of each block */
903 #define RTW_PWR_ADDR_MAC	0x00
904 #define RTW_PWR_ADDR_USB	0x01
905 #define RTW_PWR_ADDR_PCIE	0x02
906 #define RTW_PWR_ADDR_SDIO	0x03
907 
908 #define RTW_PWR_INTF_SDIO_MSK	BIT(0)
909 #define RTW_PWR_INTF_USB_MSK	BIT(1)
910 #define RTW_PWR_INTF_PCI_MSK	BIT(2)
911 #define RTW_PWR_INTF_ALL_MSK	(BIT(0) | BIT(1) | BIT(2) | BIT(3))
912 
913 #define RTW_PWR_CUT_TEST_MSK	BIT(0)
914 #define RTW_PWR_CUT_A_MSK	BIT(1)
915 #define RTW_PWR_CUT_B_MSK	BIT(2)
916 #define RTW_PWR_CUT_C_MSK	BIT(3)
917 #define RTW_PWR_CUT_D_MSK	BIT(4)
918 #define RTW_PWR_CUT_E_MSK	BIT(5)
919 #define RTW_PWR_CUT_F_MSK	BIT(6)
920 #define RTW_PWR_CUT_G_MSK	BIT(7)
921 #define RTW_PWR_CUT_ALL_MSK	0xFF
922 
923 enum rtw_pwr_seq_cmd_delay_unit {
924 	RTW_PWR_DELAY_US,
925 	RTW_PWR_DELAY_MS,
926 };
927 
928 struct rtw_pwr_seq_cmd {
929 	u16 offset;
930 	u8 cut_mask;
931 	u8 intf_mask;
932 	u8 base:4;
933 	u8 cmd:4;
934 	u8 mask;
935 	u8 value;
936 };
937 
938 enum rtw_chip_ver {
939 	RTW_CHIP_VER_CUT_A = 0x00,
940 	RTW_CHIP_VER_CUT_B = 0x01,
941 	RTW_CHIP_VER_CUT_C = 0x02,
942 	RTW_CHIP_VER_CUT_D = 0x03,
943 	RTW_CHIP_VER_CUT_E = 0x04,
944 	RTW_CHIP_VER_CUT_F = 0x05,
945 	RTW_CHIP_VER_CUT_G = 0x06,
946 };
947 
948 #define RTW_INTF_PHY_PLATFORM_ALL 0
949 
950 enum rtw_intf_phy_cut {
951 	RTW_INTF_PHY_CUT_A = BIT(0),
952 	RTW_INTF_PHY_CUT_B = BIT(1),
953 	RTW_INTF_PHY_CUT_C = BIT(2),
954 	RTW_INTF_PHY_CUT_D = BIT(3),
955 	RTW_INTF_PHY_CUT_E = BIT(4),
956 	RTW_INTF_PHY_CUT_F = BIT(5),
957 	RTW_INTF_PHY_CUT_G = BIT(6),
958 	RTW_INTF_PHY_CUT_ALL = 0xFFFF,
959 };
960 
961 enum rtw_ip_sel {
962 	RTW_IP_SEL_PHY = 0,
963 	RTW_IP_SEL_MAC = 1,
964 	RTW_IP_SEL_DBI = 2,
965 
966 	RTW_IP_SEL_UNDEF = 0xFFFF
967 };
968 
969 enum rtw_pq_map_id {
970 	RTW_PQ_MAP_VO = 0x0,
971 	RTW_PQ_MAP_VI = 0x1,
972 	RTW_PQ_MAP_BE = 0x2,
973 	RTW_PQ_MAP_BK = 0x3,
974 	RTW_PQ_MAP_MG = 0x4,
975 	RTW_PQ_MAP_HI = 0x5,
976 	RTW_PQ_MAP_NUM = 0x6,
977 
978 	RTW_PQ_MAP_UNDEF,
979 };
980 
981 enum rtw_dma_mapping {
982 	RTW_DMA_MAPPING_EXTRA	= 0,
983 	RTW_DMA_MAPPING_LOW	= 1,
984 	RTW_DMA_MAPPING_NORMAL	= 2,
985 	RTW_DMA_MAPPING_HIGH	= 3,
986 
987 	RTW_DMA_MAPPING_MAX,
988 	RTW_DMA_MAPPING_UNDEF,
989 };
990 
991 struct rtw_rqpn {
992 	enum rtw_dma_mapping dma_map_vo;
993 	enum rtw_dma_mapping dma_map_vi;
994 	enum rtw_dma_mapping dma_map_be;
995 	enum rtw_dma_mapping dma_map_bk;
996 	enum rtw_dma_mapping dma_map_mg;
997 	enum rtw_dma_mapping dma_map_hi;
998 };
999 
1000 struct rtw_prioq_addr {
1001 	u32 rsvd;
1002 	u32 avail;
1003 };
1004 
1005 struct rtw_prioq_addrs {
1006 	struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
1007 	bool wsize;
1008 };
1009 
1010 struct rtw_page_table {
1011 	u16 hq_num;
1012 	u16 nq_num;
1013 	u16 lq_num;
1014 	u16 exq_num;
1015 	u16 gapq_num;
1016 };
1017 
1018 struct rtw_intf_phy_para {
1019 	u16 offset;
1020 	u16 value;
1021 	u16 ip_sel;
1022 	u16 cut_mask;
1023 	u16 platform;
1024 };
1025 
1026 struct rtw_wow_pattern {
1027 	u16 crc;
1028 	u8 type;
1029 	u8 valid;
1030 	u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1031 };
1032 
1033 struct rtw_pno_request {
1034 	bool inited;
1035 	u32 match_set_cnt;
1036 	struct cfg80211_match_set *match_sets;
1037 	u8 channel_cnt;
1038 	struct ieee80211_channel *channels;
1039 	struct cfg80211_sched_scan_plan scan_plan;
1040 };
1041 
1042 struct rtw_wow_param {
1043 	struct ieee80211_vif *wow_vif;
1044 	DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1045 	u8 txpause;
1046 	u8 pattern_cnt;
1047 	struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1048 
1049 	bool ips_enabled;
1050 	struct rtw_pno_request pno_req;
1051 };
1052 
1053 struct rtw_intf_phy_para_table {
1054 	const struct rtw_intf_phy_para *usb2_para;
1055 	const struct rtw_intf_phy_para *usb3_para;
1056 	const struct rtw_intf_phy_para *gen1_para;
1057 	const struct rtw_intf_phy_para *gen2_para;
1058 	u8 n_usb2_para;
1059 	u8 n_usb3_para;
1060 	u8 n_gen1_para;
1061 	u8 n_gen2_para;
1062 };
1063 
1064 struct rtw_table {
1065 	const void *data;
1066 	const u32 size;
1067 	void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1068 	void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1069 		       u32 addr, u32 data);
1070 	enum rtw_rf_path rf_path;
1071 };
1072 
1073 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1074 				  const struct rtw_table *tbl)
1075 {
1076 	(*tbl->parse)(rtwdev, tbl);
1077 }
1078 
1079 enum rtw_rfe_fem {
1080 	RTW_RFE_IFEM,
1081 	RTW_RFE_EFEM,
1082 	RTW_RFE_IFEM2G_EFEM5G,
1083 	RTW_RFE_NUM,
1084 };
1085 
1086 struct rtw_rfe_def {
1087 	const struct rtw_table *phy_pg_tbl;
1088 	const struct rtw_table *txpwr_lmt_tbl;
1089 	const struct rtw_table *agc_btg_tbl;
1090 };
1091 
1092 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) {				  \
1093 	.phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,	  \
1094 	.txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1095 	}
1096 
1097 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) {			  \
1098 	.phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl,	  \
1099 	.txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1100 	.agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1101 	}
1102 
1103 #define RTW_PWR_TRK_5G_1		0
1104 #define RTW_PWR_TRK_5G_2		1
1105 #define RTW_PWR_TRK_5G_3		2
1106 #define RTW_PWR_TRK_5G_NUM		3
1107 
1108 #define RTW_PWR_TRK_TBL_SZ		30
1109 
1110 /* This table stores the values of TX power that will be adjusted by power
1111  * tracking.
1112  *
1113  * For 5G bands, there are 3 different settings.
1114  * For 2G there are cck rate and ofdm rate with different settings.
1115  */
1116 struct rtw_pwr_track_tbl {
1117 	const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1118 	const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1119 	const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1120 	const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1121 	const u8 *pwrtrk_2gb_n;
1122 	const u8 *pwrtrk_2gb_p;
1123 	const u8 *pwrtrk_2ga_n;
1124 	const u8 *pwrtrk_2ga_p;
1125 	const u8 *pwrtrk_2g_cckb_n;
1126 	const u8 *pwrtrk_2g_cckb_p;
1127 	const u8 *pwrtrk_2g_ccka_n;
1128 	const u8 *pwrtrk_2g_ccka_p;
1129 	const s8 *pwrtrk_xtal_n;
1130 	const s8 *pwrtrk_xtal_p;
1131 };
1132 
1133 enum rtw_wlan_cpu {
1134 	RTW_WCPU_11AC,
1135 	RTW_WCPU_11N,
1136 };
1137 
1138 enum rtw_fw_fifo_sel {
1139 	RTW_FW_FIFO_SEL_TX,
1140 	RTW_FW_FIFO_SEL_RX,
1141 	RTW_FW_FIFO_SEL_RSVD_PAGE,
1142 	RTW_FW_FIFO_SEL_REPORT,
1143 	RTW_FW_FIFO_SEL_LLT,
1144 	RTW_FW_FIFO_SEL_RXBUF_FW,
1145 
1146 	RTW_FW_FIFO_MAX,
1147 };
1148 
1149 enum rtw_fwcd_item {
1150 	RTW_FWCD_TLV,
1151 	RTW_FWCD_REG,
1152 	RTW_FWCD_ROM,
1153 	RTW_FWCD_IMEM,
1154 	RTW_FWCD_DMEM,
1155 	RTW_FWCD_EMEM,
1156 };
1157 
1158 /* hardware configuration for each IC */
1159 struct rtw_chip_info {
1160 	struct rtw_chip_ops *ops;
1161 	u8 id;
1162 
1163 	const char *fw_name;
1164 	enum rtw_wlan_cpu wlan_cpu;
1165 	u8 tx_pkt_desc_sz;
1166 	u8 tx_buf_desc_sz;
1167 	u8 rx_pkt_desc_sz;
1168 	u8 rx_buf_desc_sz;
1169 	u32 phy_efuse_size;
1170 	u32 log_efuse_size;
1171 	u32 ptct_efuse_size;
1172 	u32 txff_size;
1173 	u32 rxff_size;
1174 	u32 fw_rxff_size;
1175 	u16 rsvd_drv_pg_num;
1176 	u8 band;
1177 	u8 page_size;
1178 	u8 csi_buf_pg_num;
1179 	u8 dig_max;
1180 	u8 dig_min;
1181 	u8 txgi_factor;
1182 	bool is_pwr_by_rate_dec;
1183 	bool rx_ldpc;
1184 	bool tx_stbc;
1185 	u8 max_power_index;
1186 	u8 ampdu_density;
1187 
1188 	u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1189 	const struct rtw_fwcd_segs *fwcd_segs;
1190 
1191 	u8 default_1ss_tx_path;
1192 
1193 	bool path_div_supported;
1194 	bool ht_supported;
1195 	bool vht_supported;
1196 	u8 lps_deep_mode_supported;
1197 
1198 	/* init values */
1199 	u8 sys_func_en;
1200 	const struct rtw_pwr_seq_cmd **pwr_on_seq;
1201 	const struct rtw_pwr_seq_cmd **pwr_off_seq;
1202 	const struct rtw_rqpn *rqpn_table;
1203 	const struct rtw_prioq_addrs *prioq_addrs;
1204 	const struct rtw_page_table *page_table;
1205 	const struct rtw_intf_phy_para_table *intf_table;
1206 
1207 	const struct rtw_hw_reg *dig;
1208 	const struct rtw_hw_reg *dig_cck;
1209 	u32 rf_base_addr[2];
1210 	u32 rf_sipi_addr[2];
1211 	const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1212 	u8 fix_rf_phy_num;
1213 	const struct rtw_ltecoex_addr *ltecoex_addr;
1214 
1215 	const struct rtw_table *mac_tbl;
1216 	const struct rtw_table *agc_tbl;
1217 	const struct rtw_table *bb_tbl;
1218 	const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1219 	const struct rtw_table *rfk_init_tbl;
1220 
1221 	const struct rtw_rfe_def *rfe_defs;
1222 	u32 rfe_defs_size;
1223 
1224 	bool en_dis_dpd;
1225 	u16 dpd_ratemask;
1226 	u8 iqk_threshold;
1227 	u8 lck_threshold;
1228 	const struct rtw_pwr_track_tbl *pwr_track_tbl;
1229 
1230 	u8 bfer_su_max_num;
1231 	u8 bfer_mu_max_num;
1232 
1233 	struct rtw_hw_reg_offset *edcca_th;
1234 	s8 l2h_th_ini_cs;
1235 	s8 l2h_th_ini_ad;
1236 
1237 	const char *wow_fw_name;
1238 	const struct wiphy_wowlan_support *wowlan_stub;
1239 	const u8 max_sched_scan_ssids;
1240 	const u16 max_scan_ie_len;
1241 
1242 	/* coex paras */
1243 	u32 coex_para_ver;
1244 	u8 bt_desired_ver;
1245 	bool scbd_support;
1246 	bool new_scbd10_def; /* true: fix 2M(8822c) */
1247 	bool ble_hid_profile_support;
1248 	bool wl_mimo_ps_support;
1249 	u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1250 	u8 bt_rssi_type;
1251 	u8 ant_isolation;
1252 	u8 rssi_tolerance;
1253 	u8 table_sant_num;
1254 	u8 table_nsant_num;
1255 	u8 tdma_sant_num;
1256 	u8 tdma_nsant_num;
1257 	u8 bt_afh_span_bw20;
1258 	u8 bt_afh_span_bw40;
1259 	u8 afh_5g_num;
1260 	u8 wl_rf_para_num;
1261 	u8 coex_info_hw_regs_num;
1262 	const u8 *bt_rssi_step;
1263 	const u8 *wl_rssi_step;
1264 	const struct coex_table_para *table_nsant;
1265 	const struct coex_table_para *table_sant;
1266 	const struct coex_tdma_para *tdma_sant;
1267 	const struct coex_tdma_para *tdma_nsant;
1268 	const struct coex_rf_para *wl_rf_para_tx;
1269 	const struct coex_rf_para *wl_rf_para_rx;
1270 	const struct coex_5g_afh_map *afh_5g;
1271 	const struct rtw_hw_reg *btg_reg;
1272 	const struct rtw_reg_domain *coex_info_hw_regs;
1273 	u32 wl_fw_desired_ver;
1274 };
1275 
1276 enum rtw_coex_bt_state_cnt {
1277 	COEX_CNT_BT_RETRY,
1278 	COEX_CNT_BT_REINIT,
1279 	COEX_CNT_BT_REENABLE,
1280 	COEX_CNT_BT_POPEVENT,
1281 	COEX_CNT_BT_SETUPLINK,
1282 	COEX_CNT_BT_IGNWLANACT,
1283 	COEX_CNT_BT_INQ,
1284 	COEX_CNT_BT_PAGE,
1285 	COEX_CNT_BT_ROLESWITCH,
1286 	COEX_CNT_BT_AFHUPDATE,
1287 	COEX_CNT_BT_INFOUPDATE,
1288 	COEX_CNT_BT_IQK,
1289 	COEX_CNT_BT_IQKFAIL,
1290 
1291 	COEX_CNT_BT_MAX
1292 };
1293 
1294 enum rtw_coex_wl_state_cnt {
1295 	COEX_CNT_WL_SCANAP,
1296 	COEX_CNT_WL_CONNPKT,
1297 	COEX_CNT_WL_COEXRUN,
1298 	COEX_CNT_WL_NOISY0,
1299 	COEX_CNT_WL_NOISY1,
1300 	COEX_CNT_WL_NOISY2,
1301 	COEX_CNT_WL_5MS_NOEXTEND,
1302 	COEX_CNT_WL_FW_NOTIFY,
1303 
1304 	COEX_CNT_WL_MAX
1305 };
1306 
1307 struct rtw_coex_rfe {
1308 	bool ant_switch_exist;
1309 	bool ant_switch_diversity;
1310 	bool ant_switch_with_bt;
1311 	u8 rfe_module_type;
1312 	u8 ant_switch_polarity;
1313 
1314 	/* true if WLG at BTG, else at WLAG */
1315 	bool wlg_at_btg;
1316 };
1317 
1318 #define COEX_WL_TDMA_PARA_LENGTH	5
1319 
1320 struct rtw_coex_dm {
1321 	bool cur_ps_tdma_on;
1322 	bool cur_wl_rx_low_gain_en;
1323 	bool ignore_wl_act;
1324 
1325 	u8 reason;
1326 	u8 bt_rssi_state[4];
1327 	u8 wl_rssi_state[4];
1328 	u8 wl_ch_info[3];
1329 	u8 cur_ps_tdma;
1330 	u8 cur_table;
1331 	u8 ps_tdma_para[5];
1332 	u8 cur_bt_pwr_lvl;
1333 	u8 cur_bt_lna_lvl;
1334 	u8 cur_wl_pwr_lvl;
1335 	u8 bt_status;
1336 	u32 cur_ant_pos_type;
1337 	u32 cur_switch_status;
1338 	u32 setting_tdma;
1339 	u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1340 };
1341 
1342 #define COEX_BTINFO_SRC_WL_FW	0x0
1343 #define COEX_BTINFO_SRC_BT_RSP	0x1
1344 #define COEX_BTINFO_SRC_BT_ACT	0x2
1345 #define COEX_BTINFO_SRC_BT_IQK	0x3
1346 #define COEX_BTINFO_SRC_BT_SCBD	0x4
1347 #define COEX_BTINFO_SRC_H2C60	0x5
1348 #define COEX_BTINFO_SRC_MAX	0x6
1349 
1350 #define COEX_INFO_FTP		BIT(7)
1351 #define COEX_INFO_A2DP		BIT(6)
1352 #define COEX_INFO_HID		BIT(5)
1353 #define COEX_INFO_SCO_BUSY	BIT(4)
1354 #define COEX_INFO_ACL_BUSY	BIT(3)
1355 #define COEX_INFO_INQ_PAGE	BIT(2)
1356 #define COEX_INFO_SCO_ESCO	BIT(1)
1357 #define COEX_INFO_CONNECTION	BIT(0)
1358 #define COEX_BTINFO_LENGTH_MAX	10
1359 #define COEX_BTINFO_LENGTH	7
1360 
1361 #define COEX_BT_HIDINFO_LIST	0x0
1362 #define COEX_BT_HIDINFO_A	0x1
1363 #define COEX_BT_HIDINFO_NAME	3
1364 
1365 #define COEX_BT_HIDINFO_LENGTH	6
1366 #define COEX_BT_HIDINFO_HANDLE_NUM	4
1367 #define COEX_BT_HIDINFO_C2H_HANDLE	0
1368 #define COEX_BT_HIDINFO_C2H_VENDOR	1
1369 #define COEX_BT_BLE_HANDLE_THRS	0x10
1370 #define COEX_BT_HIDINFO_NOTCON	0xff
1371 
1372 struct rtw_coex_hid {
1373 	u8 hid_handle;
1374 	u8 hid_vendor;
1375 	u8 hid_name[COEX_BT_HIDINFO_NAME];
1376 	bool hid_info_completed;
1377 	bool is_game_hid;
1378 };
1379 
1380 struct rtw_coex_hid_handle_list {
1381 	u8 cmd_id;
1382 	u8 len;
1383 	u8 subid;
1384 	u8 handle_cnt;
1385 	u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
1386 } __packed;
1387 
1388 struct rtw_coex_hid_info_a {
1389 	u8 cmd_id;
1390 	u8 len;
1391 	u8 subid;
1392 	u8 handle;
1393 	u8 vendor;
1394 	u8 name[COEX_BT_HIDINFO_NAME];
1395 } __packed;
1396 
1397 struct rtw_coex_stat {
1398 	bool bt_disabled;
1399 	bool bt_disabled_pre;
1400 	bool bt_link_exist;
1401 	bool bt_whck_test;
1402 	bool bt_inq_page;
1403 	bool bt_inq_remain;
1404 	bool bt_inq;
1405 	bool bt_page;
1406 	bool bt_ble_voice;
1407 	bool bt_ble_exist;
1408 	bool bt_hfp_exist;
1409 	bool bt_a2dp_exist;
1410 	bool bt_hid_exist;
1411 	bool bt_pan_exist; /* PAN or OPP */
1412 	bool bt_opp_exist; /* OPP only */
1413 	bool bt_acl_busy;
1414 	bool bt_fix_2M;
1415 	bool bt_setup_link;
1416 	bool bt_multi_link;
1417 	bool bt_multi_link_pre;
1418 	bool bt_multi_link_remain;
1419 	bool bt_a2dp_sink;
1420 	bool bt_a2dp_active;
1421 	bool bt_reenable;
1422 	bool bt_ble_scan_en;
1423 	bool bt_init_scan;
1424 	bool bt_slave;
1425 	bool bt_418_hid_exist;
1426 	bool bt_ble_hid_exist;
1427 	bool bt_game_hid_exist;
1428 	bool bt_hid_handle_cnt;
1429 	bool bt_mailbox_reply;
1430 
1431 	bool wl_under_lps;
1432 	bool wl_under_ips;
1433 	bool wl_hi_pri_task1;
1434 	bool wl_hi_pri_task2;
1435 	bool wl_force_lps_ctrl;
1436 	bool wl_gl_busy;
1437 	bool wl_linkscan_proc;
1438 	bool wl_ps_state_fail;
1439 	bool wl_tx_limit_en;
1440 	bool wl_ampdu_limit_en;
1441 	bool wl_connected;
1442 	bool wl_slot_extend;
1443 	bool wl_cck_lock;
1444 	bool wl_cck_lock_pre;
1445 	bool wl_cck_lock_ever;
1446 	bool wl_connecting;
1447 	bool wl_slot_toggle;
1448 	bool wl_slot_toggle_change; /* if toggle to no-toggle */
1449 	bool wl_mimo_ps;
1450 
1451 	u32 bt_supported_version;
1452 	u32 bt_supported_feature;
1453 	u32 hi_pri_tx;
1454 	u32 hi_pri_rx;
1455 	u32 lo_pri_tx;
1456 	u32 lo_pri_rx;
1457 	u32 patch_ver;
1458 	u16 bt_reg_vendor_ae;
1459 	u16 bt_reg_vendor_ac;
1460 	s8 bt_rssi;
1461 	u8 kt_ver;
1462 	u8 gnt_workaround_state;
1463 	u8 tdma_timer_base;
1464 	u8 bt_profile_num;
1465 	u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1466 	u8 bt_info_lb2;
1467 	u8 bt_info_lb3;
1468 	u8 bt_info_hb0;
1469 	u8 bt_info_hb1;
1470 	u8 bt_info_hb2;
1471 	u8 bt_info_hb3;
1472 	u8 bt_ble_scan_type;
1473 	u8 bt_hid_pair_num;
1474 	u8 bt_hid_slot;
1475 	u8 bt_a2dp_bitpool;
1476 	u8 bt_iqk_state;
1477 
1478 	u16 wl_beacon_interval;
1479 	u8 wl_noisy_level;
1480 	u8 wl_fw_dbg_info[10];
1481 	u8 wl_fw_dbg_info_pre[10];
1482 	u8 wl_rx_rate;
1483 	u8 wl_tx_rate;
1484 	u8 wl_rts_rx_rate;
1485 	u8 wl_coex_mode;
1486 	u8 wl_iot_peer;
1487 	u8 ampdu_max_time;
1488 	u8 wl_tput_dir;
1489 
1490 	u8 wl_toggle_para[6];
1491 	u8 wl_toggle_interval;
1492 
1493 	u16 score_board;
1494 	u16 retry_limit;
1495 
1496 	/* counters to record bt states */
1497 	u32 cnt_bt[COEX_CNT_BT_MAX];
1498 
1499 	/* counters to record wifi states */
1500 	u32 cnt_wl[COEX_CNT_WL_MAX];
1501 
1502 	/* counters to record bt c2h data */
1503 	u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1504 
1505 	u32 darfrc;
1506 	u32 darfrch;
1507 
1508 	struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
1509 	struct rtw_coex_hid_handle_list hid_handle_list;
1510 };
1511 
1512 struct rtw_coex {
1513 	struct sk_buff_head queue;
1514 	wait_queue_head_t wait;
1515 
1516 	bool under_5g;
1517 	bool stop_dm;
1518 	bool freeze;
1519 	bool freerun;
1520 	bool wl_rf_off;
1521 	bool manual_control;
1522 
1523 	struct rtw_coex_stat stat;
1524 	struct rtw_coex_dm dm;
1525 	struct rtw_coex_rfe rfe;
1526 
1527 	struct delayed_work bt_relink_work;
1528 	struct delayed_work bt_reenable_work;
1529 	struct delayed_work defreeze_work;
1530 	struct delayed_work wl_remain_work;
1531 	struct delayed_work bt_remain_work;
1532 	struct delayed_work wl_connecting_work;
1533 	struct delayed_work bt_multi_link_remain_work;
1534 	struct delayed_work wl_ccklock_work;
1535 
1536 };
1537 
1538 #define DPK_RF_REG_NUM 7
1539 #define DPK_RF_PATH_NUM 2
1540 #define DPK_BB_REG_NUM 18
1541 #define DPK_CHANNEL_WIDTH_80 1
1542 
1543 DECLARE_EWMA(thermal, 10, 4);
1544 
1545 struct rtw_dpk_info {
1546 	bool is_dpk_pwr_on;
1547 	bool is_reload;
1548 
1549 	DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1550 
1551 	u8 thermal_dpk[DPK_RF_PATH_NUM];
1552 	struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1553 
1554 	u32 gnt_control;
1555 	u32 gnt_value;
1556 
1557 	u8 result[RTW_RF_PATH_MAX];
1558 	u8 dpk_txagc[RTW_RF_PATH_MAX];
1559 	u32 coef[RTW_RF_PATH_MAX][20];
1560 	u16 dpk_gs[RTW_RF_PATH_MAX];
1561 	u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1562 	u8 pre_pwsf[RTW_RF_PATH_MAX];
1563 
1564 	u8 dpk_band;
1565 	u8 dpk_ch;
1566 	u8 dpk_bw;
1567 };
1568 
1569 struct rtw_phy_cck_pd_reg {
1570 	u32 reg_pd;
1571 	u32 mask_pd;
1572 	u32 reg_cs;
1573 	u32 mask_cs;
1574 };
1575 
1576 #define DACK_MSBK_BACKUP_NUM	0xf
1577 #define DACK_DCK_BACKUP_NUM	0x2
1578 
1579 struct rtw_swing_table {
1580 	const u8 *p[RTW_RF_PATH_MAX];
1581 	const u8 *n[RTW_RF_PATH_MAX];
1582 };
1583 
1584 struct rtw_pkt_count {
1585 	u16 num_bcn_pkt;
1586 	u16 num_qry_pkt[DESC_RATE_MAX];
1587 };
1588 
1589 DECLARE_EWMA(evm, 10, 4);
1590 DECLARE_EWMA(snr, 10, 4);
1591 
1592 struct rtw_iqk_info {
1593 	bool done;
1594 	struct {
1595 		u32 s1_x;
1596 		u32 s1_y;
1597 		u32 s0_x;
1598 		u32 s0_y;
1599 	} result;
1600 };
1601 
1602 enum rtw_rf_band {
1603 	RF_BAND_2G_CCK,
1604 	RF_BAND_2G_OFDM,
1605 	RF_BAND_5G_L,
1606 	RF_BAND_5G_M,
1607 	RF_BAND_5G_H,
1608 	RF_BAND_MAX
1609 };
1610 
1611 #define RF_GAIN_NUM 11
1612 #define RF_HW_OFFSET_NUM 10
1613 
1614 struct rtw_gapk_info {
1615 	u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1616 	u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1617 	bool txgapk_bp_done;
1618 	s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1619 	s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1620 	u8 read_txgain;
1621 	u8 channel;
1622 };
1623 
1624 #define EDCCA_TH_L2H_IDX 0
1625 #define EDCCA_TH_H2L_IDX 1
1626 #define EDCCA_TH_L2H_LB 48
1627 #define EDCCA_ADC_BACKOFF 12
1628 #define EDCCA_IGI_BASE 50
1629 #define EDCCA_IGI_L2H_DIFF 8
1630 #define EDCCA_L2H_H2L_DIFF 7
1631 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1632 
1633 enum rtw_edcca_mode {
1634 	RTW_EDCCA_NORMAL	= 0,
1635 	RTW_EDCCA_ADAPTIVITY	= 1,
1636 };
1637 
1638 struct rtw_cfo_track {
1639 	bool is_adjust;
1640 	u8 crystal_cap;
1641 	s32 cfo_tail[RTW_RF_PATH_MAX];
1642 	s32 cfo_cnt[RTW_RF_PATH_MAX];
1643 	u32 packet_count;
1644 	u32 packet_count_pre;
1645 };
1646 
1647 #define RRSR_INIT_2G 0x15f
1648 #define RRSR_INIT_5G 0x150
1649 
1650 enum rtw_dm_cap {
1651 	RTW_DM_CAP_NA,
1652 	RTW_DM_CAP_TXGAPK,
1653 	RTW_DM_CAP_NUM
1654 };
1655 
1656 struct rtw_dm_info {
1657 	u32 cck_fa_cnt;
1658 	u32 ofdm_fa_cnt;
1659 	u32 total_fa_cnt;
1660 	u32 cck_cca_cnt;
1661 	u32 ofdm_cca_cnt;
1662 	u32 total_cca_cnt;
1663 
1664 	u32 cck_ok_cnt;
1665 	u32 cck_err_cnt;
1666 	u32 ofdm_ok_cnt;
1667 	u32 ofdm_err_cnt;
1668 	u32 ht_ok_cnt;
1669 	u32 ht_err_cnt;
1670 	u32 vht_ok_cnt;
1671 	u32 vht_err_cnt;
1672 
1673 	u8 min_rssi;
1674 	u8 pre_min_rssi;
1675 	u16 fa_history[4];
1676 	u8 igi_history[4];
1677 	u8 igi_bitmap;
1678 	bool damping;
1679 	u8 damping_cnt;
1680 	u8 damping_rssi;
1681 
1682 	u8 cck_gi_u_bnd;
1683 	u8 cck_gi_l_bnd;
1684 
1685 	u8 fix_rate;
1686 	u8 tx_rate;
1687 	u32 rrsr_val_init;
1688 	u32 rrsr_mask_min;
1689 	u8 thermal_avg[RTW_RF_PATH_MAX];
1690 	u8 thermal_meter_k;
1691 	u8 thermal_meter_lck;
1692 	s8 delta_power_index[RTW_RF_PATH_MAX];
1693 	s8 delta_power_index_last[RTW_RF_PATH_MAX];
1694 	u8 default_ofdm_index;
1695 	bool pwr_trk_triggered;
1696 	bool pwr_trk_init_trigger;
1697 	struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1698 	s8 txagc_remnant_cck;
1699 	s8 txagc_remnant_ofdm;
1700 
1701 	/* backup dack results for each path and I/Q */
1702 	u32 dack_adck[RTW_RF_PATH_MAX];
1703 	u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1704 	u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1705 
1706 	struct rtw_dpk_info dpk_info;
1707 	struct rtw_cfo_track cfo_track;
1708 
1709 	/* [bandwidth 0:20M/1:40M][number of path] */
1710 	u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1711 	u32 cck_fa_avg;
1712 	u8 cck_pd_default;
1713 
1714 	/* save the last rx phy status for debug */
1715 	s8 rx_snr[RTW_RF_PATH_MAX];
1716 	u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1717 	s16 cfo_tail[RTW_RF_PATH_MAX];
1718 	u8 rssi[RTW_RF_PATH_MAX];
1719 	u8 curr_rx_rate;
1720 	struct rtw_pkt_count cur_pkt_count;
1721 	struct rtw_pkt_count last_pkt_count;
1722 	struct ewma_evm ewma_evm[RTW_EVM_NUM];
1723 	struct ewma_snr ewma_snr[RTW_SNR_NUM];
1724 
1725 	u32 dm_flags; /* enum rtw_dm_cap */
1726 	struct rtw_iqk_info iqk;
1727 	struct rtw_gapk_info gapk;
1728 	bool is_bt_iqk_timeout;
1729 
1730 	s8 l2h_th_ini;
1731 	enum rtw_edcca_mode edcca_mode;
1732 	u8 scan_density;
1733 };
1734 
1735 struct rtw_efuse {
1736 	u32 size;
1737 	u32 physical_size;
1738 	u32 logical_size;
1739 	u32 protect_size;
1740 
1741 	u8 addr[ETH_ALEN];
1742 	u8 channel_plan;
1743 	u8 country_code[2];
1744 	u8 rf_board_option;
1745 	u8 rfe_option;
1746 	u8 power_track_type;
1747 	u8 thermal_meter[RTW_RF_PATH_MAX];
1748 	u8 thermal_meter_k;
1749 	u8 crystal_cap;
1750 	u8 ant_div_cfg;
1751 	u8 ant_div_type;
1752 	u8 regd;
1753 	u8 afe;
1754 
1755 	u8 lna_type_2g;
1756 	u8 lna_type_5g;
1757 	u8 glna_type;
1758 	u8 alna_type;
1759 	bool ext_lna_2g;
1760 	bool ext_lna_5g;
1761 	u8 pa_type_2g;
1762 	u8 pa_type_5g;
1763 	u8 gpa_type;
1764 	u8 apa_type;
1765 	bool ext_pa_2g;
1766 	bool ext_pa_5g;
1767 	u8 tx_bb_swing_setting_2g;
1768 	u8 tx_bb_swing_setting_5g;
1769 
1770 	bool btcoex;
1771 	/* bt share antenna with wifi */
1772 	bool share_ant;
1773 	u8 bt_setting;
1774 
1775 	struct {
1776 		u8 hci;
1777 		u8 bw;
1778 		u8 ptcl;
1779 		u8 nss;
1780 		u8 ant_num;
1781 	} hw_cap;
1782 
1783 	struct rtw_txpwr_idx txpwr_idx_table[4];
1784 };
1785 
1786 struct rtw_phy_cond {
1787 #ifdef __LITTLE_ENDIAN
1788 	u32 rfe:8;
1789 	u32 intf:4;
1790 	u32 pkg:4;
1791 	u32 plat:4;
1792 	u32 intf_rsvd:4;
1793 	u32 cut:4;
1794 	u32 branch:2;
1795 	u32 neg:1;
1796 	u32 pos:1;
1797 #else
1798 	u32 pos:1;
1799 	u32 neg:1;
1800 	u32 branch:2;
1801 	u32 cut:4;
1802 	u32 intf_rsvd:4;
1803 	u32 plat:4;
1804 	u32 pkg:4;
1805 	u32 intf:4;
1806 	u32 rfe:8;
1807 #endif
1808 	/* for intf:4 */
1809 	#define INTF_PCIE	BIT(0)
1810 	#define INTF_USB	BIT(1)
1811 	#define INTF_SDIO	BIT(2)
1812 	/* for branch:2 */
1813 	#define BRANCH_IF	0
1814 	#define BRANCH_ELIF	1
1815 	#define BRANCH_ELSE	2
1816 	#define BRANCH_ENDIF	3
1817 };
1818 
1819 struct rtw_fifo_conf {
1820 	/* tx fifo information */
1821 	u16 rsvd_boundary;
1822 	u16 rsvd_pg_num;
1823 	u16 rsvd_drv_pg_num;
1824 	u16 txff_pg_num;
1825 	u16 acq_pg_num;
1826 	u16 rsvd_drv_addr;
1827 	u16 rsvd_h2c_info_addr;
1828 	u16 rsvd_h2c_sta_info_addr;
1829 	u16 rsvd_h2cq_addr;
1830 	u16 rsvd_cpu_instr_addr;
1831 	u16 rsvd_fw_txbuf_addr;
1832 	u16 rsvd_csibuf_addr;
1833 	const struct rtw_rqpn *rqpn;
1834 };
1835 
1836 struct rtw_fwcd_desc {
1837 	u32 size;
1838 	u8 *next;
1839 	u8 *data;
1840 };
1841 
1842 struct rtw_fwcd_segs {
1843 	const u32 *segs;
1844 	u8 num;
1845 };
1846 
1847 #define FW_CD_TYPE 0xffff
1848 #define FW_CD_LEN 4
1849 #define FW_CD_VAL 0xaabbccdd
1850 struct rtw_fw_state {
1851 	const struct firmware *firmware;
1852 	struct rtw_dev *rtwdev;
1853 	struct completion completion;
1854 	struct rtw_fwcd_desc fwcd_desc;
1855 	u16 version;
1856 	u8 sub_version;
1857 	u8 sub_index;
1858 	u16 h2c_version;
1859 	u32 feature;
1860 	u32 feature_ext;
1861 	enum rtw_fw_type type;
1862 };
1863 
1864 enum rtw_sar_sources {
1865 	RTW_SAR_SOURCE_NONE,
1866 	RTW_SAR_SOURCE_COMMON,
1867 };
1868 
1869 enum rtw_sar_bands {
1870 	RTW_SAR_BAND_0,
1871 	RTW_SAR_BAND_1,
1872 	/* RTW_SAR_BAND_2, not used now */
1873 	RTW_SAR_BAND_3,
1874 	RTW_SAR_BAND_4,
1875 
1876 	RTW_SAR_BAND_NR,
1877 };
1878 
1879 /* the union is reserved for other kinds of SAR sources
1880  * which might not re-use same format with array common.
1881  */
1882 union rtw_sar_cfg {
1883 	s8 common[RTW_SAR_BAND_NR];
1884 };
1885 
1886 struct rtw_sar {
1887 	enum rtw_sar_sources src;
1888 	union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
1889 };
1890 
1891 struct rtw_hal {
1892 	u32 rcr;
1893 
1894 	u32 chip_version;
1895 	u8 cut_version;
1896 	u8 mp_chip;
1897 	u8 oem_id;
1898 	u8 pkg_type;
1899 	struct rtw_phy_cond phy_cond;
1900 	bool rfe_btg;
1901 
1902 	u8 ps_mode;
1903 	u8 current_channel;
1904 	u8 current_primary_channel_index;
1905 	u8 current_band_width;
1906 	u8 current_band_type;
1907 	u8 primary_channel;
1908 
1909 	/* center channel for different available bandwidth,
1910 	 * val of (bw > current_band_width) is invalid
1911 	 */
1912 	u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1913 
1914 	u8 sec_ch_offset;
1915 	u8 rf_type;
1916 	u8 rf_path_num;
1917 	u8 rf_phy_num;
1918 	u32 antenna_tx;
1919 	u32 antenna_rx;
1920 	u8 bfee_sts_cap;
1921 	bool txrx_1ss;
1922 
1923 	/* protect tx power section */
1924 	struct mutex tx_power_mutex;
1925 	s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1926 				   [DESC_RATE_MAX];
1927 	s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1928 				   [DESC_RATE_MAX];
1929 	s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1930 				 [RTW_RATE_SECTION_MAX];
1931 	s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1932 				 [RTW_RATE_SECTION_MAX];
1933 	s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1934 			  [RTW_CHANNEL_WIDTH_MAX]
1935 			  [RTW_RATE_SECTION_MAX]
1936 			  [RTW_MAX_CHANNEL_NUM_2G];
1937 	s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1938 			  [RTW_CHANNEL_WIDTH_MAX]
1939 			  [RTW_RATE_SECTION_MAX]
1940 			  [RTW_MAX_CHANNEL_NUM_5G];
1941 	s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1942 		     [DESC_RATE_MAX];
1943 
1944 	enum rtw_sar_bands sar_band;
1945 	struct rtw_sar sar;
1946 
1947 	/* for 8821c set channel */
1948 	u32 ch_param[3];
1949 };
1950 
1951 struct rtw_path_div {
1952 	enum rtw_bb_path current_tx_path;
1953 	u32 path_a_sum;
1954 	u32 path_b_sum;
1955 	u16 path_a_cnt;
1956 	u16 path_b_cnt;
1957 };
1958 
1959 struct rtw_chan_info {
1960 	int pri_ch_idx;
1961 	int action_id;
1962 	int bw;
1963 	u8 extra_info;
1964 	u8 channel;
1965 	u16 timeout;
1966 };
1967 
1968 struct rtw_chan_list {
1969 	u32 buf_size;
1970 	u32 ch_num;
1971 	u32 size;
1972 	u16 addr;
1973 };
1974 
1975 struct rtw_hw_scan_info {
1976 	struct ieee80211_vif *scanning_vif;
1977 	u8 probe_pg_size;
1978 	u8 op_pri_ch_idx;
1979 	u8 op_pri_ch;
1980 	u8 op_chan;
1981 	u8 op_bw;
1982 };
1983 
1984 struct rtw_dev {
1985 	struct ieee80211_hw *hw;
1986 	struct device *dev;
1987 
1988 	struct rtw_hci hci;
1989 
1990 	struct rtw_hw_scan_info scan_info;
1991 	const struct rtw_chip_info *chip;
1992 	struct rtw_hal hal;
1993 	struct rtw_fifo_conf fifo;
1994 	struct rtw_fw_state fw;
1995 	struct rtw_efuse efuse;
1996 	struct rtw_sec_desc sec;
1997 	struct rtw_traffic_stats stats;
1998 	struct rtw_regd regd;
1999 	struct rtw_bf_info bf_info;
2000 
2001 	struct rtw_dm_info dm_info;
2002 	struct rtw_coex coex;
2003 
2004 	/* ensures exclusive access from mac80211 callbacks */
2005 	struct mutex mutex;
2006 
2007 	/* watch dog every 2 sec */
2008 	struct delayed_work watch_dog_work;
2009 	u32 watch_dog_cnt;
2010 
2011 	struct list_head rsvd_page_list;
2012 
2013 	/* c2h cmd queue & handler work */
2014 	struct sk_buff_head c2h_queue;
2015 	struct work_struct c2h_work;
2016 	struct work_struct ips_work;
2017 	struct work_struct fw_recovery_work;
2018 	struct work_struct update_beacon_work;
2019 
2020 	/* used to protect txqs list */
2021 	spinlock_t txq_lock;
2022 	struct list_head txqs;
2023 	struct workqueue_struct *tx_wq;
2024 	struct work_struct tx_work;
2025 	struct work_struct ba_work;
2026 
2027 	struct rtw_tx_report tx_report;
2028 
2029 	struct {
2030 		/* indicate the mail box to use with fw */
2031 		u8 last_box_num;
2032 		u32 seq;
2033 	} h2c;
2034 
2035 	/* lps power state & handler work */
2036 	struct rtw_lps_conf lps_conf;
2037 	bool ps_enabled;
2038 	bool beacon_loss;
2039 	struct completion lps_leave_check;
2040 
2041 	struct dentry *debugfs;
2042 
2043 	u8 sta_cnt;
2044 	u32 rts_threshold;
2045 
2046 	DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
2047 	DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
2048 	DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
2049 
2050 	u8 mp_mode;
2051 	struct rtw_path_div dm_path_div;
2052 
2053 	struct rtw_fw_state wow_fw;
2054 	struct rtw_wow_param wow;
2055 
2056 	bool need_rfk;
2057 	struct completion fw_scan_density;
2058 	bool ap_active;
2059 
2060 	/* hci related data, must be last */
2061 	u8 priv[] __aligned(sizeof(void *));
2062 };
2063 
2064 #include "hci.h"
2065 
2066 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
2067 {
2068 	return !!rtwdev->sta_cnt;
2069 }
2070 
2071 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
2072 {
2073 	void *p = rtwtxq;
2074 
2075 	return container_of(p, struct ieee80211_txq, drv_priv);
2076 }
2077 
2078 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
2079 {
2080 	void *p = rtwvif;
2081 
2082 	return container_of(p, struct ieee80211_vif, drv_priv);
2083 }
2084 
2085 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
2086 				  struct cfg80211_ssid *b)
2087 {
2088 	if (!a || !b || a->ssid_len != b->ssid_len)
2089 		return false;
2090 
2091 	if (memcmp(a->ssid, b->ssid, a->ssid_len))
2092 		return false;
2093 
2094 	return true;
2095 }
2096 
2097 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
2098 {
2099 	if (rtwdev->chip->ops->efuse_grant)
2100 		rtwdev->chip->ops->efuse_grant(rtwdev, true);
2101 }
2102 
2103 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
2104 {
2105 	if (rtwdev->chip->ops->efuse_grant)
2106 		rtwdev->chip->ops->efuse_grant(rtwdev, false);
2107 }
2108 
2109 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
2110 {
2111 	return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
2112 }
2113 
2114 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
2115 {
2116 	return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
2117 }
2118 
2119 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2120 {
2121 	return rtwdev->chip->rx_ldpc;
2122 }
2123 
2124 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2125 {
2126 	return rtwdev->chip->tx_stbc;
2127 }
2128 
2129 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2130 {
2131 	clear_bit(mac_id, rtwdev->mac_id_map);
2132 }
2133 
2134 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2135 {
2136 	if (rtwdev->chip->ops->dump_fw_crash)
2137 		return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2138 
2139 	return 0;
2140 }
2141 
2142 static inline
2143 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
2144 {
2145 	switch (hw_band) {
2146 	default:
2147 	case RTW_BAND_2G:
2148 		return NL80211_BAND_2GHZ;
2149 	case RTW_BAND_5G:
2150 		return NL80211_BAND_5GHZ;
2151 	case RTW_BAND_60G:
2152 		return NL80211_BAND_60GHZ;
2153 	}
2154 }
2155 
2156 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
2157 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
2158 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2159 			    struct rtw_channel_params *ch_param);
2160 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2161 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2162 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2163 void rtw_restore_reg(struct rtw_dev *rtwdev,
2164 		     struct rtw_backup_info *bckp, u32 num);
2165 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2166 void rtw_set_channel(struct rtw_dev *rtwdev);
2167 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2168 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2169 			 u32 config);
2170 void rtw_tx_report_purge_timer(struct timer_list *t);
2171 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
2172 			 bool reset_ra_mask);
2173 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2174 			 const u8 *mac_addr, bool hw_scan);
2175 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2176 			    bool hw_scan);
2177 int rtw_core_start(struct rtw_dev *rtwdev);
2178 void rtw_core_stop(struct rtw_dev *rtwdev);
2179 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2180 int rtw_core_init(struct rtw_dev *rtwdev);
2181 void rtw_core_deinit(struct rtw_dev *rtwdev);
2182 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2183 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2184 u16 rtw_desc_to_bitrate(u8 desc_rate);
2185 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2186 			   struct ieee80211_bss_conf *conf);
2187 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2188 		struct ieee80211_vif *vif);
2189 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2190 		    bool fw_exist);
2191 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2192 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2193 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2194 		u32 fwcd_item);
2195 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2196 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
2197 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
2198 			u8 primary_channel, enum rtw_supported_band band,
2199 			enum rtw_bandwidth bandwidth);
2200 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
2201 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
2202 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
2203 #endif
2204