1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 15 #include "util.h" 16 17 #define RTW_MAX_MAC_ID_NUM 32 18 #define RTW_MAX_SEC_CAM_NUM 32 19 20 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 21 22 #define RFREG_MASK 0xfffff 23 #define INV_RF_DATA 0xffffffff 24 #define TX_PAGE_SIZE_SHIFT 7 25 26 #define RTW_CHANNEL_WIDTH_MAX 3 27 #define RTW_RF_PATH_MAX 4 28 #define HW_FEATURE_LEN 13 29 30 extern unsigned int rtw_debug_mask; 31 extern const struct ieee80211_ops rtw_ops; 32 extern struct rtw_chip_info rtw8822b_hw_spec; 33 extern struct rtw_chip_info rtw8822c_hw_spec; 34 35 #define RTW_MAX_CHANNEL_NUM_2G 14 36 #define RTW_MAX_CHANNEL_NUM_5G 49 37 38 struct rtw_dev; 39 40 enum rtw_hci_type { 41 RTW_HCI_TYPE_PCIE, 42 RTW_HCI_TYPE_USB, 43 RTW_HCI_TYPE_SDIO, 44 45 RTW_HCI_TYPE_UNDEFINE, 46 }; 47 48 struct rtw_hci { 49 struct rtw_hci_ops *ops; 50 enum rtw_hci_type type; 51 52 u32 rpwm_addr; 53 54 u8 bulkout_num; 55 }; 56 57 enum rtw_supported_band { 58 RTW_BAND_2G = 1 << 0, 59 RTW_BAND_5G = 1 << 1, 60 RTW_BAND_60G = 1 << 2, 61 62 RTW_BAND_MAX, 63 }; 64 65 /* now, support upto 80M bw */ 66 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 67 68 enum rtw_bandwidth { 69 RTW_CHANNEL_WIDTH_20 = 0, 70 RTW_CHANNEL_WIDTH_40 = 1, 71 RTW_CHANNEL_WIDTH_80 = 2, 72 RTW_CHANNEL_WIDTH_160 = 3, 73 RTW_CHANNEL_WIDTH_80_80 = 4, 74 RTW_CHANNEL_WIDTH_5 = 5, 75 RTW_CHANNEL_WIDTH_10 = 6, 76 }; 77 78 enum rtw_net_type { 79 RTW_NET_NO_LINK = 0, 80 RTW_NET_AD_HOC = 1, 81 RTW_NET_MGD_LINKED = 2, 82 RTW_NET_AP_MODE = 3, 83 }; 84 85 enum rtw_rf_type { 86 RF_1T1R = 0, 87 RF_1T2R = 1, 88 RF_2T2R = 2, 89 RF_2T3R = 3, 90 RF_2T4R = 4, 91 RF_3T3R = 5, 92 RF_3T4R = 6, 93 RF_4T4R = 7, 94 RF_TYPE_MAX, 95 }; 96 97 enum rtw_rf_path { 98 RF_PATH_A = 0, 99 RF_PATH_B = 1, 100 RF_PATH_C = 2, 101 RF_PATH_D = 3, 102 }; 103 104 enum rtw_bb_path { 105 BB_PATH_A = BIT(0), 106 BB_PATH_B = BIT(1), 107 BB_PATH_C = BIT(2), 108 BB_PATH_D = BIT(3), 109 110 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 111 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 112 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 113 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 114 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 115 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 116 117 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 118 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 119 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 120 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 121 122 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 123 }; 124 125 enum rtw_rate_section { 126 RTW_RATE_SECTION_CCK = 0, 127 RTW_RATE_SECTION_OFDM, 128 RTW_RATE_SECTION_HT_1S, 129 RTW_RATE_SECTION_HT_2S, 130 RTW_RATE_SECTION_VHT_1S, 131 RTW_RATE_SECTION_VHT_2S, 132 133 /* keep last */ 134 RTW_RATE_SECTION_MAX, 135 }; 136 137 enum rtw_wireless_set { 138 WIRELESS_CCK = 0x00000001, 139 WIRELESS_OFDM = 0x00000002, 140 WIRELESS_HT = 0x00000004, 141 WIRELESS_VHT = 0x00000008, 142 }; 143 144 #define HT_STBC_EN BIT(0) 145 #define VHT_STBC_EN BIT(1) 146 #define HT_LDPC_EN BIT(0) 147 #define VHT_LDPC_EN BIT(1) 148 149 enum rtw_chip_type { 150 RTW_CHIP_TYPE_8822B, 151 RTW_CHIP_TYPE_8822C, 152 }; 153 154 enum rtw_tx_queue_type { 155 /* the order of AC queues matters */ 156 RTW_TX_QUEUE_BK = 0x0, 157 RTW_TX_QUEUE_BE = 0x1, 158 RTW_TX_QUEUE_VI = 0x2, 159 RTW_TX_QUEUE_VO = 0x3, 160 161 RTW_TX_QUEUE_BCN = 0x4, 162 RTW_TX_QUEUE_MGMT = 0x5, 163 RTW_TX_QUEUE_HI0 = 0x6, 164 RTW_TX_QUEUE_H2C = 0x7, 165 /* keep it last */ 166 RTK_MAX_TX_QUEUE_NUM 167 }; 168 169 enum rtw_rx_queue_type { 170 RTW_RX_QUEUE_MPDU = 0x0, 171 RTW_RX_QUEUE_C2H = 0x1, 172 /* keep it last */ 173 RTK_MAX_RX_QUEUE_NUM 174 }; 175 176 enum rtw_rate_index { 177 RTW_RATEID_BGN_40M_2SS = 0, 178 RTW_RATEID_BGN_40M_1SS = 1, 179 RTW_RATEID_BGN_20M_2SS = 2, 180 RTW_RATEID_BGN_20M_1SS = 3, 181 RTW_RATEID_GN_N2SS = 4, 182 RTW_RATEID_GN_N1SS = 5, 183 RTW_RATEID_BG = 6, 184 RTW_RATEID_G = 7, 185 RTW_RATEID_B_20M = 8, 186 RTW_RATEID_ARFR0_AC_2SS = 9, 187 RTW_RATEID_ARFR1_AC_1SS = 10, 188 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 189 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 190 RTW_RATEID_ARFR4_AC_3SS = 13, 191 RTW_RATEID_ARFR5_N_3SS = 14, 192 RTW_RATEID_ARFR7_N_4SS = 15, 193 RTW_RATEID_ARFR6_AC_4SS = 16 194 }; 195 196 enum rtw_trx_desc_rate { 197 DESC_RATE1M = 0x00, 198 DESC_RATE2M = 0x01, 199 DESC_RATE5_5M = 0x02, 200 DESC_RATE11M = 0x03, 201 202 DESC_RATE6M = 0x04, 203 DESC_RATE9M = 0x05, 204 DESC_RATE12M = 0x06, 205 DESC_RATE18M = 0x07, 206 DESC_RATE24M = 0x08, 207 DESC_RATE36M = 0x09, 208 DESC_RATE48M = 0x0a, 209 DESC_RATE54M = 0x0b, 210 211 DESC_RATEMCS0 = 0x0c, 212 DESC_RATEMCS1 = 0x0d, 213 DESC_RATEMCS2 = 0x0e, 214 DESC_RATEMCS3 = 0x0f, 215 DESC_RATEMCS4 = 0x10, 216 DESC_RATEMCS5 = 0x11, 217 DESC_RATEMCS6 = 0x12, 218 DESC_RATEMCS7 = 0x13, 219 DESC_RATEMCS8 = 0x14, 220 DESC_RATEMCS9 = 0x15, 221 DESC_RATEMCS10 = 0x16, 222 DESC_RATEMCS11 = 0x17, 223 DESC_RATEMCS12 = 0x18, 224 DESC_RATEMCS13 = 0x19, 225 DESC_RATEMCS14 = 0x1a, 226 DESC_RATEMCS15 = 0x1b, 227 DESC_RATEMCS16 = 0x1c, 228 DESC_RATEMCS17 = 0x1d, 229 DESC_RATEMCS18 = 0x1e, 230 DESC_RATEMCS19 = 0x1f, 231 DESC_RATEMCS20 = 0x20, 232 DESC_RATEMCS21 = 0x21, 233 DESC_RATEMCS22 = 0x22, 234 DESC_RATEMCS23 = 0x23, 235 DESC_RATEMCS24 = 0x24, 236 DESC_RATEMCS25 = 0x25, 237 DESC_RATEMCS26 = 0x26, 238 DESC_RATEMCS27 = 0x27, 239 DESC_RATEMCS28 = 0x28, 240 DESC_RATEMCS29 = 0x29, 241 DESC_RATEMCS30 = 0x2a, 242 DESC_RATEMCS31 = 0x2b, 243 244 DESC_RATEVHT1SS_MCS0 = 0x2c, 245 DESC_RATEVHT1SS_MCS1 = 0x2d, 246 DESC_RATEVHT1SS_MCS2 = 0x2e, 247 DESC_RATEVHT1SS_MCS3 = 0x2f, 248 DESC_RATEVHT1SS_MCS4 = 0x30, 249 DESC_RATEVHT1SS_MCS5 = 0x31, 250 DESC_RATEVHT1SS_MCS6 = 0x32, 251 DESC_RATEVHT1SS_MCS7 = 0x33, 252 DESC_RATEVHT1SS_MCS8 = 0x34, 253 DESC_RATEVHT1SS_MCS9 = 0x35, 254 255 DESC_RATEVHT2SS_MCS0 = 0x36, 256 DESC_RATEVHT2SS_MCS1 = 0x37, 257 DESC_RATEVHT2SS_MCS2 = 0x38, 258 DESC_RATEVHT2SS_MCS3 = 0x39, 259 DESC_RATEVHT2SS_MCS4 = 0x3a, 260 DESC_RATEVHT2SS_MCS5 = 0x3b, 261 DESC_RATEVHT2SS_MCS6 = 0x3c, 262 DESC_RATEVHT2SS_MCS7 = 0x3d, 263 DESC_RATEVHT2SS_MCS8 = 0x3e, 264 DESC_RATEVHT2SS_MCS9 = 0x3f, 265 266 DESC_RATEVHT3SS_MCS0 = 0x40, 267 DESC_RATEVHT3SS_MCS1 = 0x41, 268 DESC_RATEVHT3SS_MCS2 = 0x42, 269 DESC_RATEVHT3SS_MCS3 = 0x43, 270 DESC_RATEVHT3SS_MCS4 = 0x44, 271 DESC_RATEVHT3SS_MCS5 = 0x45, 272 DESC_RATEVHT3SS_MCS6 = 0x46, 273 DESC_RATEVHT3SS_MCS7 = 0x47, 274 DESC_RATEVHT3SS_MCS8 = 0x48, 275 DESC_RATEVHT3SS_MCS9 = 0x49, 276 277 DESC_RATEVHT4SS_MCS0 = 0x4a, 278 DESC_RATEVHT4SS_MCS1 = 0x4b, 279 DESC_RATEVHT4SS_MCS2 = 0x4c, 280 DESC_RATEVHT4SS_MCS3 = 0x4d, 281 DESC_RATEVHT4SS_MCS4 = 0x4e, 282 DESC_RATEVHT4SS_MCS5 = 0x4f, 283 DESC_RATEVHT4SS_MCS6 = 0x50, 284 DESC_RATEVHT4SS_MCS7 = 0x51, 285 DESC_RATEVHT4SS_MCS8 = 0x52, 286 DESC_RATEVHT4SS_MCS9 = 0x53, 287 288 DESC_RATE_MAX, 289 }; 290 291 enum rtw_regulatory_domains { 292 RTW_REGD_FCC = 0, 293 RTW_REGD_MKK = 1, 294 RTW_REGD_ETSI = 2, 295 RTW_REGD_IC = 3, 296 RTW_REGD_KCC = 4, 297 RTW_REGD_ACMA = 5, 298 RTW_REGD_CHILE = 6, 299 RTW_REGD_UKRAINE = 7, 300 RTW_REGD_MEXICO = 8, 301 RTW_REGD_WW, 302 303 RTW_REGD_MAX 304 }; 305 306 enum rtw_flags { 307 RTW_FLAG_RUNNING, 308 RTW_FLAG_FW_RUNNING, 309 RTW_FLAG_SCANNING, 310 RTW_FLAG_INACTIVE_PS, 311 RTW_FLAG_LEISURE_PS, 312 RTW_FLAG_DIG_DISABLE, 313 314 NUM_OF_RTW_FLAGS, 315 }; 316 317 /* the power index is represented by differences, which cck-1s & ht40-1s are 318 * the base values, so for 1s's differences, there are only ht20 & ofdm 319 */ 320 struct rtw_2g_1s_pwr_idx_diff { 321 #ifdef __LITTLE_ENDIAN 322 s8 ofdm:4; 323 s8 bw20:4; 324 #else 325 s8 bw20:4; 326 s8 ofdm:4; 327 #endif 328 } __packed; 329 330 struct rtw_2g_ns_pwr_idx_diff { 331 #ifdef __LITTLE_ENDIAN 332 s8 bw20:4; 333 s8 bw40:4; 334 s8 cck:4; 335 s8 ofdm:4; 336 #else 337 s8 ofdm:4; 338 s8 cck:4; 339 s8 bw40:4; 340 s8 bw20:4; 341 #endif 342 } __packed; 343 344 struct rtw_2g_txpwr_idx { 345 u8 cck_base[6]; 346 u8 bw40_base[5]; 347 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 348 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 349 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 350 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 351 }; 352 353 struct rtw_5g_ht_1s_pwr_idx_diff { 354 #ifdef __LITTLE_ENDIAN 355 s8 ofdm:4; 356 s8 bw20:4; 357 #else 358 s8 bw20:4; 359 s8 ofdm:4; 360 #endif 361 } __packed; 362 363 struct rtw_5g_ht_ns_pwr_idx_diff { 364 #ifdef __LITTLE_ENDIAN 365 s8 bw20:4; 366 s8 bw40:4; 367 #else 368 s8 bw40:4; 369 s8 bw20:4; 370 #endif 371 } __packed; 372 373 struct rtw_5g_ofdm_ns_pwr_idx_diff { 374 #ifdef __LITTLE_ENDIAN 375 s8 ofdm_3s:4; 376 s8 ofdm_2s:4; 377 s8 ofdm_4s:4; 378 s8 res:4; 379 #else 380 s8 res:4; 381 s8 ofdm_4s:4; 382 s8 ofdm_2s:4; 383 s8 ofdm_3s:4; 384 #endif 385 } __packed; 386 387 struct rtw_5g_vht_ns_pwr_idx_diff { 388 #ifdef __LITTLE_ENDIAN 389 s8 bw160:4; 390 s8 bw80:4; 391 #else 392 s8 bw80:4; 393 s8 bw160:4; 394 #endif 395 } __packed; 396 397 struct rtw_5g_txpwr_idx { 398 u8 bw40_base[14]; 399 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 400 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 401 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 402 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 403 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 404 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 405 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 406 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 407 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 408 }; 409 410 struct rtw_txpwr_idx { 411 struct rtw_2g_txpwr_idx pwr_idx_2g; 412 struct rtw_5g_txpwr_idx pwr_idx_5g; 413 }; 414 415 struct rtw_timer_list { 416 struct timer_list timer; 417 void (*function)(void *data); 418 void *args; 419 }; 420 421 struct rtw_channel_params { 422 u8 center_chan; 423 u8 bandwidth; 424 u8 primary_chan_idx; 425 /* center channel by different available bandwidth, 426 * val of (bw > current bandwidth) is invalid 427 */ 428 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 429 }; 430 431 struct rtw_hw_reg { 432 u32 addr; 433 u32 mask; 434 }; 435 436 struct rtw_backup_info { 437 u8 len; 438 u32 reg; 439 u32 val; 440 }; 441 442 enum rtw_vif_port_set { 443 PORT_SET_MAC_ADDR = BIT(0), 444 PORT_SET_BSSID = BIT(1), 445 PORT_SET_NET_TYPE = BIT(2), 446 PORT_SET_AID = BIT(3), 447 PORT_SET_BCN_CTRL = BIT(4), 448 }; 449 450 struct rtw_vif_port { 451 struct rtw_hw_reg mac_addr; 452 struct rtw_hw_reg bssid; 453 struct rtw_hw_reg net_type; 454 struct rtw_hw_reg aid; 455 struct rtw_hw_reg bcn_ctrl; 456 }; 457 458 struct rtw_tx_pkt_info { 459 u32 tx_pkt_size; 460 u8 offset; 461 u8 pkt_offset; 462 u8 mac_id; 463 u8 rate_id; 464 u8 rate; 465 u8 qsel; 466 u8 bw; 467 u8 sec_type; 468 u8 sn; 469 bool ampdu_en; 470 u8 ampdu_factor; 471 u8 ampdu_density; 472 u16 seq; 473 bool stbc; 474 bool ldpc; 475 bool dis_rate_fallback; 476 bool bmc; 477 bool use_rate; 478 bool ls; 479 bool fs; 480 bool short_gi; 481 bool report; 482 }; 483 484 struct rtw_rx_pkt_stat { 485 bool phy_status; 486 bool icv_err; 487 bool crc_err; 488 bool decrypted; 489 bool is_c2h; 490 491 s32 signal_power; 492 u16 pkt_len; 493 u8 bw; 494 u8 drv_info_sz; 495 u8 shift; 496 u8 rate; 497 u8 mac_id; 498 u8 cam_id; 499 u8 ppdu_cnt; 500 u32 tsf_low; 501 s8 rx_power[RTW_RF_PATH_MAX]; 502 u8 rssi; 503 u8 rxsc; 504 struct rtw_sta_info *si; 505 struct ieee80211_vif *vif; 506 }; 507 508 struct rtw_traffic_stats { 509 /* units in bytes */ 510 u64 tx_unicast; 511 u64 rx_unicast; 512 513 /* count for packets */ 514 u64 tx_cnt; 515 u64 rx_cnt; 516 517 /* units in Mbps */ 518 u32 tx_throughput; 519 u32 rx_throughput; 520 }; 521 522 enum rtw_lps_mode { 523 RTW_MODE_ACTIVE = 0, 524 RTW_MODE_LPS = 1, 525 RTW_MODE_WMM_PS = 2, 526 }; 527 528 enum rtw_pwr_state { 529 RTW_RF_OFF = 0x0, 530 RTW_RF_ON = 0x4, 531 RTW_ALL_ON = 0xc, 532 }; 533 534 struct rtw_lps_conf { 535 /* the interface to enter lps */ 536 struct rtw_vif *rtwvif; 537 enum rtw_lps_mode mode; 538 enum rtw_pwr_state state; 539 u8 awake_interval; 540 u8 rlbm; 541 u8 smart_ps; 542 u8 port_id; 543 }; 544 545 enum rtw_hw_key_type { 546 RTW_CAM_NONE = 0, 547 RTW_CAM_WEP40 = 1, 548 RTW_CAM_TKIP = 2, 549 RTW_CAM_AES = 4, 550 RTW_CAM_WEP104 = 5, 551 }; 552 553 struct rtw_cam_entry { 554 bool valid; 555 bool group; 556 u8 addr[ETH_ALEN]; 557 u8 hw_key_type; 558 struct ieee80211_key_conf *key; 559 }; 560 561 struct rtw_sec_desc { 562 /* search strategy */ 563 bool default_key_search; 564 565 u32 total_cam_num; 566 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 567 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 568 }; 569 570 struct rtw_tx_report { 571 /* protect the tx report queue */ 572 spinlock_t q_lock; 573 struct sk_buff_head queue; 574 atomic_t sn; 575 struct timer_list purge_timer; 576 }; 577 578 #define RTW_BC_MC_MACID 1 579 DECLARE_EWMA(rssi, 10, 16); 580 581 struct rtw_sta_info { 582 struct ieee80211_sta *sta; 583 struct ieee80211_vif *vif; 584 585 struct ewma_rssi avg_rssi; 586 u8 rssi_level; 587 588 u8 mac_id; 589 u8 rate_id; 590 enum rtw_bandwidth bw_mode; 591 enum rtw_rf_type rf_type; 592 enum rtw_wireless_set wireless_set; 593 u8 stbc_en:2; 594 u8 ldpc_en:2; 595 bool sgi_enable; 596 bool vht_enable; 597 bool updated; 598 u8 init_ra_lv; 599 u64 ra_mask; 600 }; 601 602 struct rtw_vif { 603 struct ieee80211_vif *vif; 604 enum rtw_net_type net_type; 605 u16 aid; 606 u8 mac_addr[ETH_ALEN]; 607 u8 bssid[ETH_ALEN]; 608 u8 port; 609 u8 bcn_ctrl; 610 const struct rtw_vif_port *conf; 611 612 struct rtw_traffic_stats stats; 613 bool in_lps; 614 }; 615 616 struct rtw_regulatory { 617 char alpha2[2]; 618 u8 chplan; 619 u8 txpwr_regd; 620 }; 621 622 struct rtw_chip_ops { 623 int (*mac_init)(struct rtw_dev *rtwdev); 624 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 625 void (*phy_set_param)(struct rtw_dev *rtwdev); 626 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 627 u8 bandwidth, u8 primary_chan_idx); 628 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 629 struct rtw_rx_pkt_stat *pkt_stat, 630 struct ieee80211_rx_status *rx_status); 631 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 632 u32 addr, u32 mask); 633 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 634 u32 addr, u32 mask, u32 data); 635 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 636 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 637 u32 size); 638 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx, 639 u8 antenna_rx); 640 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 641 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 642 void (*do_iqk)(struct rtw_dev *rtwdev); 643 }; 644 645 #define RTW_PWR_POLLING_CNT 20000 646 647 #define RTW_PWR_CMD_READ 0x00 648 #define RTW_PWR_CMD_WRITE 0x01 649 #define RTW_PWR_CMD_POLLING 0x02 650 #define RTW_PWR_CMD_DELAY 0x03 651 #define RTW_PWR_CMD_END 0x04 652 653 /* define the base address of each block */ 654 #define RTW_PWR_ADDR_MAC 0x00 655 #define RTW_PWR_ADDR_USB 0x01 656 #define RTW_PWR_ADDR_PCIE 0x02 657 #define RTW_PWR_ADDR_SDIO 0x03 658 659 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 660 #define RTW_PWR_INTF_USB_MSK BIT(1) 661 #define RTW_PWR_INTF_PCI_MSK BIT(2) 662 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 663 664 #define RTW_PWR_CUT_A_MSK BIT(1) 665 #define RTW_PWR_CUT_B_MSK BIT(2) 666 #define RTW_PWR_CUT_C_MSK BIT(3) 667 #define RTW_PWR_CUT_D_MSK BIT(4) 668 #define RTW_PWR_CUT_E_MSK BIT(5) 669 #define RTW_PWR_CUT_F_MSK BIT(6) 670 #define RTW_PWR_CUT_G_MSK BIT(7) 671 #define RTW_PWR_CUT_ALL_MSK 0xFF 672 673 enum rtw_pwr_seq_cmd_delay_unit { 674 RTW_PWR_DELAY_US, 675 RTW_PWR_DELAY_MS, 676 }; 677 678 struct rtw_pwr_seq_cmd { 679 u16 offset; 680 u8 cut_mask; 681 u8 intf_mask; 682 u8 base:4; 683 u8 cmd:4; 684 u8 mask; 685 u8 value; 686 }; 687 688 enum rtw_chip_ver { 689 RTW_CHIP_VER_CUT_A = 0x00, 690 RTW_CHIP_VER_CUT_B = 0x01, 691 RTW_CHIP_VER_CUT_C = 0x02, 692 RTW_CHIP_VER_CUT_D = 0x03, 693 RTW_CHIP_VER_CUT_E = 0x04, 694 RTW_CHIP_VER_CUT_F = 0x05, 695 RTW_CHIP_VER_CUT_G = 0x06, 696 }; 697 698 #define RTW_INTF_PHY_PLATFORM_ALL 0 699 700 enum rtw_intf_phy_cut { 701 RTW_INTF_PHY_CUT_A = BIT(0), 702 RTW_INTF_PHY_CUT_B = BIT(1), 703 RTW_INTF_PHY_CUT_C = BIT(2), 704 RTW_INTF_PHY_CUT_D = BIT(3), 705 RTW_INTF_PHY_CUT_E = BIT(4), 706 RTW_INTF_PHY_CUT_F = BIT(5), 707 RTW_INTF_PHY_CUT_G = BIT(6), 708 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 709 }; 710 711 enum rtw_ip_sel { 712 RTW_IP_SEL_PHY = 0, 713 RTW_IP_SEL_MAC = 1, 714 RTW_IP_SEL_DBI = 2, 715 716 RTW_IP_SEL_UNDEF = 0xFFFF 717 }; 718 719 enum rtw_pq_map_id { 720 RTW_PQ_MAP_VO = 0x0, 721 RTW_PQ_MAP_VI = 0x1, 722 RTW_PQ_MAP_BE = 0x2, 723 RTW_PQ_MAP_BK = 0x3, 724 RTW_PQ_MAP_MG = 0x4, 725 RTW_PQ_MAP_HI = 0x5, 726 RTW_PQ_MAP_NUM = 0x6, 727 728 RTW_PQ_MAP_UNDEF, 729 }; 730 731 enum rtw_dma_mapping { 732 RTW_DMA_MAPPING_EXTRA = 0, 733 RTW_DMA_MAPPING_LOW = 1, 734 RTW_DMA_MAPPING_NORMAL = 2, 735 RTW_DMA_MAPPING_HIGH = 3, 736 737 RTW_DMA_MAPPING_UNDEF, 738 }; 739 740 struct rtw_rqpn { 741 enum rtw_dma_mapping dma_map_vo; 742 enum rtw_dma_mapping dma_map_vi; 743 enum rtw_dma_mapping dma_map_be; 744 enum rtw_dma_mapping dma_map_bk; 745 enum rtw_dma_mapping dma_map_mg; 746 enum rtw_dma_mapping dma_map_hi; 747 }; 748 749 struct rtw_page_table { 750 u16 hq_num; 751 u16 nq_num; 752 u16 lq_num; 753 u16 exq_num; 754 u16 gapq_num; 755 }; 756 757 struct rtw_intf_phy_para { 758 u16 offset; 759 u16 value; 760 u16 ip_sel; 761 u16 cut_mask; 762 u16 platform; 763 }; 764 765 struct rtw_intf_phy_para_table { 766 struct rtw_intf_phy_para *usb2_para; 767 struct rtw_intf_phy_para *usb3_para; 768 struct rtw_intf_phy_para *gen1_para; 769 struct rtw_intf_phy_para *gen2_para; 770 u8 n_usb2_para; 771 u8 n_usb3_para; 772 u8 n_gen1_para; 773 u8 n_gen2_para; 774 }; 775 776 struct rtw_table { 777 const void *data; 778 const u32 size; 779 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 780 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 781 u32 addr, u32 data); 782 enum rtw_rf_path rf_path; 783 }; 784 785 static inline void rtw_load_table(struct rtw_dev *rtwdev, 786 const struct rtw_table *tbl) 787 { 788 (*tbl->parse)(rtwdev, tbl); 789 } 790 791 enum rtw_rfe_fem { 792 RTW_RFE_IFEM, 793 RTW_RFE_EFEM, 794 RTW_RFE_IFEM2G_EFEM5G, 795 RTW_RFE_NUM, 796 }; 797 798 struct rtw_rfe_def { 799 const struct rtw_table *phy_pg_tbl; 800 const struct rtw_table *txpwr_lmt_tbl; 801 }; 802 803 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 804 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 805 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 806 } 807 808 /* hardware configuration for each IC */ 809 struct rtw_chip_info { 810 struct rtw_chip_ops *ops; 811 u8 id; 812 813 const char *fw_name; 814 u8 tx_pkt_desc_sz; 815 u8 tx_buf_desc_sz; 816 u8 rx_pkt_desc_sz; 817 u8 rx_buf_desc_sz; 818 u32 phy_efuse_size; 819 u32 log_efuse_size; 820 u32 ptct_efuse_size; 821 u32 txff_size; 822 u32 rxff_size; 823 u8 band; 824 u8 page_size; 825 u8 csi_buf_pg_num; 826 u8 dig_max; 827 u8 dig_min; 828 u8 txgi_factor; 829 bool is_pwr_by_rate_dec; 830 u8 max_power_index; 831 832 bool ht_supported; 833 bool vht_supported; 834 835 /* init values */ 836 u8 sys_func_en; 837 struct rtw_pwr_seq_cmd **pwr_on_seq; 838 struct rtw_pwr_seq_cmd **pwr_off_seq; 839 struct rtw_rqpn *rqpn_table; 840 struct rtw_page_table *page_table; 841 struct rtw_intf_phy_para_table *intf_table; 842 843 struct rtw_hw_reg *dig; 844 u32 rf_base_addr[2]; 845 u32 rf_sipi_addr[2]; 846 847 const struct rtw_table *mac_tbl; 848 const struct rtw_table *agc_tbl; 849 const struct rtw_table *bb_tbl; 850 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 851 const struct rtw_table *rfk_init_tbl; 852 853 const struct rtw_rfe_def *rfe_defs; 854 u32 rfe_defs_size; 855 }; 856 857 #define DACK_MSBK_BACKUP_NUM 0xf 858 #define DACK_DCK_BACKUP_NUM 0x2 859 860 struct rtw_dm_info { 861 u32 cck_fa_cnt; 862 u32 ofdm_fa_cnt; 863 u32 total_fa_cnt; 864 u8 min_rssi; 865 u8 pre_min_rssi; 866 u16 fa_history[4]; 867 u8 igi_history[4]; 868 u8 igi_bitmap; 869 bool damping; 870 u8 damping_cnt; 871 u8 damping_rssi; 872 873 u8 cck_gi_u_bnd; 874 u8 cck_gi_l_bnd; 875 876 /* backup dack results for each path and I/Q */ 877 u32 dack_adck[RTW_RF_PATH_MAX]; 878 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 879 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 880 }; 881 882 struct rtw_efuse { 883 u32 size; 884 u32 physical_size; 885 u32 logical_size; 886 u32 protect_size; 887 888 u8 addr[ETH_ALEN]; 889 u8 channel_plan; 890 u8 country_code[2]; 891 u8 rfe_option; 892 u8 thermal_meter; 893 u8 crystal_cap; 894 u8 ant_div_cfg; 895 u8 ant_div_type; 896 u8 regd; 897 898 u8 lna_type_2g; 899 u8 lna_type_5g; 900 u8 glna_type; 901 u8 alna_type; 902 bool ext_lna_2g; 903 bool ext_lna_5g; 904 u8 pa_type_2g; 905 u8 pa_type_5g; 906 u8 gpa_type; 907 u8 apa_type; 908 bool ext_pa_2g; 909 bool ext_pa_5g; 910 911 bool btcoex; 912 /* bt share antenna with wifi */ 913 bool share_ant; 914 u8 bt_setting; 915 916 struct { 917 u8 hci; 918 u8 bw; 919 u8 ptcl; 920 u8 nss; 921 u8 ant_num; 922 } hw_cap; 923 924 struct rtw_txpwr_idx txpwr_idx_table[4]; 925 }; 926 927 struct rtw_phy_cond { 928 #ifdef __LITTLE_ENDIAN 929 u32 rfe:8; 930 u32 intf:4; 931 u32 pkg:4; 932 u32 plat:4; 933 u32 intf_rsvd:4; 934 u32 cut:4; 935 u32 branch:2; 936 u32 neg:1; 937 u32 pos:1; 938 #else 939 u32 pos:1; 940 u32 neg:1; 941 u32 branch:2; 942 u32 cut:4; 943 u32 intf_rsvd:4; 944 u32 plat:4; 945 u32 pkg:4; 946 u32 intf:4; 947 u32 rfe:8; 948 #endif 949 /* for intf:4 */ 950 #define INTF_PCIE BIT(0) 951 #define INTF_USB BIT(1) 952 #define INTF_SDIO BIT(2) 953 /* for branch:2 */ 954 #define BRANCH_IF 0 955 #define BRANCH_ELIF 1 956 #define BRANCH_ELSE 2 957 #define BRANCH_ENDIF 3 958 }; 959 960 struct rtw_fifo_conf { 961 /* tx fifo information */ 962 u16 rsvd_boundary; 963 u16 rsvd_pg_num; 964 u16 rsvd_drv_pg_num; 965 u16 txff_pg_num; 966 u16 acq_pg_num; 967 u16 rsvd_drv_addr; 968 u16 rsvd_h2c_info_addr; 969 u16 rsvd_h2c_sta_info_addr; 970 u16 rsvd_h2cq_addr; 971 u16 rsvd_cpu_instr_addr; 972 u16 rsvd_fw_txbuf_addr; 973 u16 rsvd_csibuf_addr; 974 enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM]; 975 }; 976 977 struct rtw_fw_state { 978 const struct firmware *firmware; 979 struct completion completion; 980 u16 version; 981 u8 sub_version; 982 u8 sub_index; 983 u16 h2c_version; 984 }; 985 986 struct rtw_hal { 987 u32 rcr; 988 989 u32 chip_version; 990 u8 fab_version; 991 u8 cut_version; 992 u8 mp_chip; 993 u8 oem_id; 994 struct rtw_phy_cond phy_cond; 995 996 u8 ps_mode; 997 u8 current_channel; 998 u8 current_band_width; 999 u8 current_band_type; 1000 1001 /* center channel for different available bandwidth, 1002 * val of (bw > current_band_width) is invalid 1003 */ 1004 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1005 1006 u8 sec_ch_offset; 1007 u8 rf_type; 1008 u8 rf_path_num; 1009 u8 antenna_tx; 1010 u8 antenna_rx; 1011 1012 /* protect tx power section */ 1013 struct mutex tx_power_mutex; 1014 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1015 [DESC_RATE_MAX]; 1016 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1017 [DESC_RATE_MAX]; 1018 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1019 [RTW_RATE_SECTION_MAX]; 1020 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1021 [RTW_RATE_SECTION_MAX]; 1022 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1023 [RTW_CHANNEL_WIDTH_MAX] 1024 [RTW_RATE_SECTION_MAX] 1025 [RTW_MAX_CHANNEL_NUM_2G]; 1026 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1027 [RTW_CHANNEL_WIDTH_MAX] 1028 [RTW_RATE_SECTION_MAX] 1029 [RTW_MAX_CHANNEL_NUM_5G]; 1030 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1031 [DESC_RATE_MAX]; 1032 }; 1033 1034 struct rtw_dev { 1035 struct ieee80211_hw *hw; 1036 struct device *dev; 1037 1038 struct rtw_hci hci; 1039 1040 struct rtw_chip_info *chip; 1041 struct rtw_hal hal; 1042 struct rtw_fifo_conf fifo; 1043 struct rtw_fw_state fw; 1044 struct rtw_efuse efuse; 1045 struct rtw_sec_desc sec; 1046 struct rtw_traffic_stats stats; 1047 struct rtw_regulatory regd; 1048 1049 struct rtw_dm_info dm_info; 1050 1051 /* ensures exclusive access from mac80211 callbacks */ 1052 struct mutex mutex; 1053 1054 /* lock for dm to use */ 1055 spinlock_t dm_lock; 1056 1057 /* read/write rf register */ 1058 spinlock_t rf_lock; 1059 1060 /* watch dog every 2 sec */ 1061 struct delayed_work watch_dog_work; 1062 u32 watch_dog_cnt; 1063 1064 struct list_head rsvd_page_list; 1065 1066 /* c2h cmd queue & handler work */ 1067 struct sk_buff_head c2h_queue; 1068 struct work_struct c2h_work; 1069 1070 struct rtw_tx_report tx_report; 1071 1072 struct { 1073 /* incicate the mail box to use with fw */ 1074 u8 last_box_num; 1075 /* protect to send h2c to fw */ 1076 spinlock_t lock; 1077 u32 seq; 1078 } h2c; 1079 1080 /* lps power state & handler work */ 1081 struct rtw_lps_conf lps_conf; 1082 struct delayed_work lps_work; 1083 1084 struct dentry *debugfs; 1085 1086 u8 sta_cnt; 1087 1088 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1089 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1090 1091 u8 mp_mode; 1092 1093 /* hci related data, must be last */ 1094 u8 priv[0] __aligned(sizeof(void *)); 1095 }; 1096 1097 #include "hci.h" 1098 1099 static inline bool rtw_flag_check(struct rtw_dev *rtwdev, enum rtw_flags flag) 1100 { 1101 return test_bit(flag, rtwdev->flags); 1102 } 1103 1104 static inline void rtw_flag_clear(struct rtw_dev *rtwdev, enum rtw_flags flag) 1105 { 1106 clear_bit(flag, rtwdev->flags); 1107 } 1108 1109 static inline void rtw_flag_set(struct rtw_dev *rtwdev, enum rtw_flags flag) 1110 { 1111 set_bit(flag, rtwdev->flags); 1112 } 1113 1114 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1115 struct rtw_channel_params *ch_param); 1116 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1117 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1118 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1119 void rtw_restore_reg(struct rtw_dev *rtwdev, 1120 struct rtw_backup_info *bckp, u32 num); 1121 void rtw_set_channel(struct rtw_dev *rtwdev); 1122 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1123 u32 config); 1124 void rtw_tx_report_purge_timer(struct timer_list *t); 1125 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1126 int rtw_core_start(struct rtw_dev *rtwdev); 1127 void rtw_core_stop(struct rtw_dev *rtwdev); 1128 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1129 int rtw_core_init(struct rtw_dev *rtwdev); 1130 void rtw_core_deinit(struct rtw_dev *rtwdev); 1131 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1132 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1133 1134 #endif 1135