1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/interrupt.h> 15 16 #include "util.h" 17 18 #define RTW_MAX_MAC_ID_NUM 32 19 #define RTW_MAX_SEC_CAM_NUM 32 20 #define MAX_PG_CAM_BACKUP_NUM 8 21 22 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 23 24 #define RFREG_MASK 0xfffff 25 #define INV_RF_DATA 0xffffffff 26 #define TX_PAGE_SIZE_SHIFT 7 27 28 #define RTW_CHANNEL_WIDTH_MAX 3 29 #define RTW_RF_PATH_MAX 4 30 #define HW_FEATURE_LEN 13 31 32 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 33 34 extern bool rtw_bf_support; 35 extern unsigned int rtw_fw_lps_deep_mode; 36 extern unsigned int rtw_debug_mask; 37 extern const struct ieee80211_ops rtw_ops; 38 extern struct rtw_chip_info rtw8822b_hw_spec; 39 extern struct rtw_chip_info rtw8822c_hw_spec; 40 41 #define RTW_MAX_CHANNEL_NUM_2G 14 42 #define RTW_MAX_CHANNEL_NUM_5G 49 43 44 struct rtw_dev; 45 46 enum rtw_hci_type { 47 RTW_HCI_TYPE_PCIE, 48 RTW_HCI_TYPE_USB, 49 RTW_HCI_TYPE_SDIO, 50 51 RTW_HCI_TYPE_UNDEFINE, 52 }; 53 54 struct rtw_hci { 55 struct rtw_hci_ops *ops; 56 enum rtw_hci_type type; 57 58 u32 rpwm_addr; 59 u32 cpwm_addr; 60 61 u8 bulkout_num; 62 }; 63 64 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 65 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 66 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 67 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 68 69 #define IS_CH_5G_BAND_MID(channel) \ 70 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 71 72 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 73 #define IS_CH_5G_BAND(channel) \ 74 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 75 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 76 77 enum rtw_supported_band { 78 RTW_BAND_2G = 1 << 0, 79 RTW_BAND_5G = 1 << 1, 80 RTW_BAND_60G = 1 << 2, 81 82 RTW_BAND_MAX, 83 }; 84 85 /* now, support upto 80M bw */ 86 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 87 88 enum rtw_bandwidth { 89 RTW_CHANNEL_WIDTH_20 = 0, 90 RTW_CHANNEL_WIDTH_40 = 1, 91 RTW_CHANNEL_WIDTH_80 = 2, 92 RTW_CHANNEL_WIDTH_160 = 3, 93 RTW_CHANNEL_WIDTH_80_80 = 4, 94 RTW_CHANNEL_WIDTH_5 = 5, 95 RTW_CHANNEL_WIDTH_10 = 6, 96 }; 97 98 enum rtw_net_type { 99 RTW_NET_NO_LINK = 0, 100 RTW_NET_AD_HOC = 1, 101 RTW_NET_MGD_LINKED = 2, 102 RTW_NET_AP_MODE = 3, 103 }; 104 105 enum rtw_rf_type { 106 RF_1T1R = 0, 107 RF_1T2R = 1, 108 RF_2T2R = 2, 109 RF_2T3R = 3, 110 RF_2T4R = 4, 111 RF_3T3R = 5, 112 RF_3T4R = 6, 113 RF_4T4R = 7, 114 RF_TYPE_MAX, 115 }; 116 117 enum rtw_rf_path { 118 RF_PATH_A = 0, 119 RF_PATH_B = 1, 120 RF_PATH_C = 2, 121 RF_PATH_D = 3, 122 }; 123 124 enum rtw_bb_path { 125 BB_PATH_A = BIT(0), 126 BB_PATH_B = BIT(1), 127 BB_PATH_C = BIT(2), 128 BB_PATH_D = BIT(3), 129 130 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 131 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 132 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 133 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 134 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 135 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 136 137 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 138 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 139 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 140 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 141 142 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 143 }; 144 145 enum rtw_rate_section { 146 RTW_RATE_SECTION_CCK = 0, 147 RTW_RATE_SECTION_OFDM, 148 RTW_RATE_SECTION_HT_1S, 149 RTW_RATE_SECTION_HT_2S, 150 RTW_RATE_SECTION_VHT_1S, 151 RTW_RATE_SECTION_VHT_2S, 152 153 /* keep last */ 154 RTW_RATE_SECTION_MAX, 155 }; 156 157 enum rtw_wireless_set { 158 WIRELESS_CCK = 0x00000001, 159 WIRELESS_OFDM = 0x00000002, 160 WIRELESS_HT = 0x00000004, 161 WIRELESS_VHT = 0x00000008, 162 }; 163 164 #define HT_STBC_EN BIT(0) 165 #define VHT_STBC_EN BIT(1) 166 #define HT_LDPC_EN BIT(0) 167 #define VHT_LDPC_EN BIT(1) 168 169 enum rtw_chip_type { 170 RTW_CHIP_TYPE_8822B, 171 RTW_CHIP_TYPE_8822C, 172 }; 173 174 enum rtw_tx_queue_type { 175 /* the order of AC queues matters */ 176 RTW_TX_QUEUE_BK = 0x0, 177 RTW_TX_QUEUE_BE = 0x1, 178 RTW_TX_QUEUE_VI = 0x2, 179 RTW_TX_QUEUE_VO = 0x3, 180 181 RTW_TX_QUEUE_BCN = 0x4, 182 RTW_TX_QUEUE_MGMT = 0x5, 183 RTW_TX_QUEUE_HI0 = 0x6, 184 RTW_TX_QUEUE_H2C = 0x7, 185 /* keep it last */ 186 RTK_MAX_TX_QUEUE_NUM 187 }; 188 189 enum rtw_rx_queue_type { 190 RTW_RX_QUEUE_MPDU = 0x0, 191 RTW_RX_QUEUE_C2H = 0x1, 192 /* keep it last */ 193 RTK_MAX_RX_QUEUE_NUM 194 }; 195 196 enum rtw_rate_index { 197 RTW_RATEID_BGN_40M_2SS = 0, 198 RTW_RATEID_BGN_40M_1SS = 1, 199 RTW_RATEID_BGN_20M_2SS = 2, 200 RTW_RATEID_BGN_20M_1SS = 3, 201 RTW_RATEID_GN_N2SS = 4, 202 RTW_RATEID_GN_N1SS = 5, 203 RTW_RATEID_BG = 6, 204 RTW_RATEID_G = 7, 205 RTW_RATEID_B_20M = 8, 206 RTW_RATEID_ARFR0_AC_2SS = 9, 207 RTW_RATEID_ARFR1_AC_1SS = 10, 208 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 209 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 210 RTW_RATEID_ARFR4_AC_3SS = 13, 211 RTW_RATEID_ARFR5_N_3SS = 14, 212 RTW_RATEID_ARFR7_N_4SS = 15, 213 RTW_RATEID_ARFR6_AC_4SS = 16 214 }; 215 216 enum rtw_trx_desc_rate { 217 DESC_RATE1M = 0x00, 218 DESC_RATE2M = 0x01, 219 DESC_RATE5_5M = 0x02, 220 DESC_RATE11M = 0x03, 221 222 DESC_RATE6M = 0x04, 223 DESC_RATE9M = 0x05, 224 DESC_RATE12M = 0x06, 225 DESC_RATE18M = 0x07, 226 DESC_RATE24M = 0x08, 227 DESC_RATE36M = 0x09, 228 DESC_RATE48M = 0x0a, 229 DESC_RATE54M = 0x0b, 230 231 DESC_RATEMCS0 = 0x0c, 232 DESC_RATEMCS1 = 0x0d, 233 DESC_RATEMCS2 = 0x0e, 234 DESC_RATEMCS3 = 0x0f, 235 DESC_RATEMCS4 = 0x10, 236 DESC_RATEMCS5 = 0x11, 237 DESC_RATEMCS6 = 0x12, 238 DESC_RATEMCS7 = 0x13, 239 DESC_RATEMCS8 = 0x14, 240 DESC_RATEMCS9 = 0x15, 241 DESC_RATEMCS10 = 0x16, 242 DESC_RATEMCS11 = 0x17, 243 DESC_RATEMCS12 = 0x18, 244 DESC_RATEMCS13 = 0x19, 245 DESC_RATEMCS14 = 0x1a, 246 DESC_RATEMCS15 = 0x1b, 247 DESC_RATEMCS16 = 0x1c, 248 DESC_RATEMCS17 = 0x1d, 249 DESC_RATEMCS18 = 0x1e, 250 DESC_RATEMCS19 = 0x1f, 251 DESC_RATEMCS20 = 0x20, 252 DESC_RATEMCS21 = 0x21, 253 DESC_RATEMCS22 = 0x22, 254 DESC_RATEMCS23 = 0x23, 255 DESC_RATEMCS24 = 0x24, 256 DESC_RATEMCS25 = 0x25, 257 DESC_RATEMCS26 = 0x26, 258 DESC_RATEMCS27 = 0x27, 259 DESC_RATEMCS28 = 0x28, 260 DESC_RATEMCS29 = 0x29, 261 DESC_RATEMCS30 = 0x2a, 262 DESC_RATEMCS31 = 0x2b, 263 264 DESC_RATEVHT1SS_MCS0 = 0x2c, 265 DESC_RATEVHT1SS_MCS1 = 0x2d, 266 DESC_RATEVHT1SS_MCS2 = 0x2e, 267 DESC_RATEVHT1SS_MCS3 = 0x2f, 268 DESC_RATEVHT1SS_MCS4 = 0x30, 269 DESC_RATEVHT1SS_MCS5 = 0x31, 270 DESC_RATEVHT1SS_MCS6 = 0x32, 271 DESC_RATEVHT1SS_MCS7 = 0x33, 272 DESC_RATEVHT1SS_MCS8 = 0x34, 273 DESC_RATEVHT1SS_MCS9 = 0x35, 274 275 DESC_RATEVHT2SS_MCS0 = 0x36, 276 DESC_RATEVHT2SS_MCS1 = 0x37, 277 DESC_RATEVHT2SS_MCS2 = 0x38, 278 DESC_RATEVHT2SS_MCS3 = 0x39, 279 DESC_RATEVHT2SS_MCS4 = 0x3a, 280 DESC_RATEVHT2SS_MCS5 = 0x3b, 281 DESC_RATEVHT2SS_MCS6 = 0x3c, 282 DESC_RATEVHT2SS_MCS7 = 0x3d, 283 DESC_RATEVHT2SS_MCS8 = 0x3e, 284 DESC_RATEVHT2SS_MCS9 = 0x3f, 285 286 DESC_RATEVHT3SS_MCS0 = 0x40, 287 DESC_RATEVHT3SS_MCS1 = 0x41, 288 DESC_RATEVHT3SS_MCS2 = 0x42, 289 DESC_RATEVHT3SS_MCS3 = 0x43, 290 DESC_RATEVHT3SS_MCS4 = 0x44, 291 DESC_RATEVHT3SS_MCS5 = 0x45, 292 DESC_RATEVHT3SS_MCS6 = 0x46, 293 DESC_RATEVHT3SS_MCS7 = 0x47, 294 DESC_RATEVHT3SS_MCS8 = 0x48, 295 DESC_RATEVHT3SS_MCS9 = 0x49, 296 297 DESC_RATEVHT4SS_MCS0 = 0x4a, 298 DESC_RATEVHT4SS_MCS1 = 0x4b, 299 DESC_RATEVHT4SS_MCS2 = 0x4c, 300 DESC_RATEVHT4SS_MCS3 = 0x4d, 301 DESC_RATEVHT4SS_MCS4 = 0x4e, 302 DESC_RATEVHT4SS_MCS5 = 0x4f, 303 DESC_RATEVHT4SS_MCS6 = 0x50, 304 DESC_RATEVHT4SS_MCS7 = 0x51, 305 DESC_RATEVHT4SS_MCS8 = 0x52, 306 DESC_RATEVHT4SS_MCS9 = 0x53, 307 308 DESC_RATE_MAX, 309 }; 310 311 enum rtw_regulatory_domains { 312 RTW_REGD_FCC = 0, 313 RTW_REGD_MKK = 1, 314 RTW_REGD_ETSI = 2, 315 RTW_REGD_IC = 3, 316 RTW_REGD_KCC = 4, 317 RTW_REGD_ACMA = 5, 318 RTW_REGD_CHILE = 6, 319 RTW_REGD_UKRAINE = 7, 320 RTW_REGD_MEXICO = 8, 321 RTW_REGD_WW, 322 323 RTW_REGD_MAX 324 }; 325 326 enum rtw_txq_flags { 327 RTW_TXQ_AMPDU, 328 RTW_TXQ_BLOCK_BA, 329 }; 330 331 enum rtw_flags { 332 RTW_FLAG_RUNNING, 333 RTW_FLAG_FW_RUNNING, 334 RTW_FLAG_SCANNING, 335 RTW_FLAG_INACTIVE_PS, 336 RTW_FLAG_LEISURE_PS, 337 RTW_FLAG_LEISURE_PS_DEEP, 338 RTW_FLAG_DIG_DISABLE, 339 RTW_FLAG_BUSY_TRAFFIC, 340 341 NUM_OF_RTW_FLAGS, 342 }; 343 344 enum rtw_evm { 345 RTW_EVM_OFDM = 0, 346 RTW_EVM_1SS, 347 RTW_EVM_2SS_A, 348 RTW_EVM_2SS_B, 349 /* keep it last */ 350 RTW_EVM_NUM 351 }; 352 353 enum rtw_snr { 354 RTW_SNR_OFDM_A = 0, 355 RTW_SNR_OFDM_B, 356 RTW_SNR_OFDM_C, 357 RTW_SNR_OFDM_D, 358 RTW_SNR_1SS_A, 359 RTW_SNR_1SS_B, 360 RTW_SNR_1SS_C, 361 RTW_SNR_1SS_D, 362 RTW_SNR_2SS_A, 363 RTW_SNR_2SS_B, 364 RTW_SNR_2SS_C, 365 RTW_SNR_2SS_D, 366 /* keep it last */ 367 RTW_SNR_NUM 368 }; 369 370 /* the power index is represented by differences, which cck-1s & ht40-1s are 371 * the base values, so for 1s's differences, there are only ht20 & ofdm 372 */ 373 struct rtw_2g_1s_pwr_idx_diff { 374 #ifdef __LITTLE_ENDIAN 375 s8 ofdm:4; 376 s8 bw20:4; 377 #else 378 s8 bw20:4; 379 s8 ofdm:4; 380 #endif 381 } __packed; 382 383 struct rtw_2g_ns_pwr_idx_diff { 384 #ifdef __LITTLE_ENDIAN 385 s8 bw20:4; 386 s8 bw40:4; 387 s8 cck:4; 388 s8 ofdm:4; 389 #else 390 s8 ofdm:4; 391 s8 cck:4; 392 s8 bw40:4; 393 s8 bw20:4; 394 #endif 395 } __packed; 396 397 struct rtw_2g_txpwr_idx { 398 u8 cck_base[6]; 399 u8 bw40_base[5]; 400 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 401 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 402 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 403 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 404 }; 405 406 struct rtw_5g_ht_1s_pwr_idx_diff { 407 #ifdef __LITTLE_ENDIAN 408 s8 ofdm:4; 409 s8 bw20:4; 410 #else 411 s8 bw20:4; 412 s8 ofdm:4; 413 #endif 414 } __packed; 415 416 struct rtw_5g_ht_ns_pwr_idx_diff { 417 #ifdef __LITTLE_ENDIAN 418 s8 bw20:4; 419 s8 bw40:4; 420 #else 421 s8 bw40:4; 422 s8 bw20:4; 423 #endif 424 } __packed; 425 426 struct rtw_5g_ofdm_ns_pwr_idx_diff { 427 #ifdef __LITTLE_ENDIAN 428 s8 ofdm_3s:4; 429 s8 ofdm_2s:4; 430 s8 ofdm_4s:4; 431 s8 res:4; 432 #else 433 s8 res:4; 434 s8 ofdm_4s:4; 435 s8 ofdm_2s:4; 436 s8 ofdm_3s:4; 437 #endif 438 } __packed; 439 440 struct rtw_5g_vht_ns_pwr_idx_diff { 441 #ifdef __LITTLE_ENDIAN 442 s8 bw160:4; 443 s8 bw80:4; 444 #else 445 s8 bw80:4; 446 s8 bw160:4; 447 #endif 448 } __packed; 449 450 struct rtw_5g_txpwr_idx { 451 u8 bw40_base[14]; 452 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 453 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 454 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 455 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 456 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 457 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 458 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 459 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 460 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 461 }; 462 463 struct rtw_txpwr_idx { 464 struct rtw_2g_txpwr_idx pwr_idx_2g; 465 struct rtw_5g_txpwr_idx pwr_idx_5g; 466 }; 467 468 struct rtw_timer_list { 469 struct timer_list timer; 470 void (*function)(void *data); 471 void *args; 472 }; 473 474 struct rtw_channel_params { 475 u8 center_chan; 476 u8 bandwidth; 477 u8 primary_chan_idx; 478 /* center channel by different available bandwidth, 479 * val of (bw > current bandwidth) is invalid 480 */ 481 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 482 }; 483 484 struct rtw_hw_reg { 485 u32 addr; 486 u32 mask; 487 }; 488 489 struct rtw_backup_info { 490 u8 len; 491 u32 reg; 492 u32 val; 493 }; 494 495 enum rtw_vif_port_set { 496 PORT_SET_MAC_ADDR = BIT(0), 497 PORT_SET_BSSID = BIT(1), 498 PORT_SET_NET_TYPE = BIT(2), 499 PORT_SET_AID = BIT(3), 500 PORT_SET_BCN_CTRL = BIT(4), 501 }; 502 503 struct rtw_vif_port { 504 struct rtw_hw_reg mac_addr; 505 struct rtw_hw_reg bssid; 506 struct rtw_hw_reg net_type; 507 struct rtw_hw_reg aid; 508 struct rtw_hw_reg bcn_ctrl; 509 }; 510 511 struct rtw_tx_pkt_info { 512 u32 tx_pkt_size; 513 u8 offset; 514 u8 pkt_offset; 515 u8 mac_id; 516 u8 rate_id; 517 u8 rate; 518 u8 qsel; 519 u8 bw; 520 u8 sec_type; 521 u8 sn; 522 bool ampdu_en; 523 u8 ampdu_factor; 524 u8 ampdu_density; 525 u16 seq; 526 bool stbc; 527 bool ldpc; 528 bool dis_rate_fallback; 529 bool bmc; 530 bool use_rate; 531 bool ls; 532 bool fs; 533 bool short_gi; 534 bool report; 535 bool rts; 536 }; 537 538 struct rtw_rx_pkt_stat { 539 bool phy_status; 540 bool icv_err; 541 bool crc_err; 542 bool decrypted; 543 bool is_c2h; 544 545 s32 signal_power; 546 u16 pkt_len; 547 u8 bw; 548 u8 drv_info_sz; 549 u8 shift; 550 u8 rate; 551 u8 mac_id; 552 u8 cam_id; 553 u8 ppdu_cnt; 554 u32 tsf_low; 555 s8 rx_power[RTW_RF_PATH_MAX]; 556 u8 rssi; 557 u8 rxsc; 558 s8 rx_snr[RTW_RF_PATH_MAX]; 559 u8 rx_evm[RTW_RF_PATH_MAX]; 560 s8 cfo_tail[RTW_RF_PATH_MAX]; 561 562 struct rtw_sta_info *si; 563 struct ieee80211_vif *vif; 564 }; 565 566 DECLARE_EWMA(tp, 10, 2); 567 568 struct rtw_traffic_stats { 569 /* units in bytes */ 570 u64 tx_unicast; 571 u64 rx_unicast; 572 573 /* count for packets */ 574 u64 tx_cnt; 575 u64 rx_cnt; 576 577 /* units in Mbps */ 578 u32 tx_throughput; 579 u32 rx_throughput; 580 struct ewma_tp tx_ewma_tp; 581 struct ewma_tp rx_ewma_tp; 582 }; 583 584 enum rtw_lps_mode { 585 RTW_MODE_ACTIVE = 0, 586 RTW_MODE_LPS = 1, 587 RTW_MODE_WMM_PS = 2, 588 }; 589 590 enum rtw_lps_deep_mode { 591 LPS_DEEP_MODE_NONE = 0, 592 LPS_DEEP_MODE_LCLK = 1, 593 LPS_DEEP_MODE_PG = 2, 594 }; 595 596 enum rtw_pwr_state { 597 RTW_RF_OFF = 0x0, 598 RTW_RF_ON = 0x4, 599 RTW_ALL_ON = 0xc, 600 }; 601 602 struct rtw_lps_conf { 603 enum rtw_lps_mode mode; 604 enum rtw_lps_deep_mode deep_mode; 605 enum rtw_pwr_state state; 606 u8 awake_interval; 607 u8 rlbm; 608 u8 smart_ps; 609 u8 port_id; 610 bool sec_cam_backup; 611 }; 612 613 enum rtw_hw_key_type { 614 RTW_CAM_NONE = 0, 615 RTW_CAM_WEP40 = 1, 616 RTW_CAM_TKIP = 2, 617 RTW_CAM_AES = 4, 618 RTW_CAM_WEP104 = 5, 619 }; 620 621 struct rtw_cam_entry { 622 bool valid; 623 bool group; 624 u8 addr[ETH_ALEN]; 625 u8 hw_key_type; 626 struct ieee80211_key_conf *key; 627 }; 628 629 struct rtw_sec_desc { 630 /* search strategy */ 631 bool default_key_search; 632 633 u32 total_cam_num; 634 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 635 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 636 }; 637 638 struct rtw_tx_report { 639 /* protect the tx report queue */ 640 spinlock_t q_lock; 641 struct sk_buff_head queue; 642 atomic_t sn; 643 struct timer_list purge_timer; 644 }; 645 646 struct rtw_ra_report { 647 struct rate_info txrate; 648 u32 bit_rate; 649 u8 desc_rate; 650 }; 651 652 struct rtw_txq { 653 struct list_head list; 654 655 unsigned long flags; 656 unsigned long last_push; 657 }; 658 659 #define RTW_BC_MC_MACID 1 660 DECLARE_EWMA(rssi, 10, 16); 661 662 struct rtw_sta_info { 663 struct ieee80211_sta *sta; 664 struct ieee80211_vif *vif; 665 666 struct ewma_rssi avg_rssi; 667 u8 rssi_level; 668 669 u8 mac_id; 670 u8 rate_id; 671 enum rtw_bandwidth bw_mode; 672 enum rtw_rf_type rf_type; 673 enum rtw_wireless_set wireless_set; 674 u8 stbc_en:2; 675 u8 ldpc_en:2; 676 bool sgi_enable; 677 bool vht_enable; 678 bool updated; 679 u8 init_ra_lv; 680 u64 ra_mask; 681 682 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 683 684 struct rtw_ra_report ra_report; 685 686 bool use_cfg_mask; 687 struct cfg80211_bitrate_mask *mask; 688 }; 689 690 enum rtw_bfee_role { 691 RTW_BFEE_NONE, 692 RTW_BFEE_SU, 693 RTW_BFEE_MU 694 }; 695 696 struct rtw_bfee { 697 enum rtw_bfee_role role; 698 699 u16 p_aid; 700 u8 g_id; 701 u8 mac_addr[ETH_ALEN]; 702 u8 sound_dim; 703 704 /* SU-MIMO */ 705 u8 su_reg_index; 706 707 /* MU-MIMO */ 708 u16 aid; 709 }; 710 711 struct rtw_bf_info { 712 u8 bfer_mu_cnt; 713 u8 bfer_su_cnt; 714 DECLARE_BITMAP(bfer_su_reg_maping, 2); 715 u8 cur_csi_rpt_rate; 716 }; 717 718 struct rtw_vif { 719 struct ieee80211_vif *vif; 720 enum rtw_net_type net_type; 721 u16 aid; 722 u8 mac_addr[ETH_ALEN]; 723 u8 bssid[ETH_ALEN]; 724 u8 port; 725 u8 bcn_ctrl; 726 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 727 const struct rtw_vif_port *conf; 728 729 struct rtw_traffic_stats stats; 730 bool in_lps; 731 732 struct rtw_bfee bfee; 733 }; 734 735 struct rtw_regulatory { 736 char alpha2[2]; 737 u8 chplan; 738 u8 txpwr_regd; 739 }; 740 741 struct rtw_chip_ops { 742 int (*mac_init)(struct rtw_dev *rtwdev); 743 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 744 void (*phy_set_param)(struct rtw_dev *rtwdev); 745 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 746 u8 bandwidth, u8 primary_chan_idx); 747 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 748 struct rtw_rx_pkt_stat *pkt_stat, 749 struct ieee80211_rx_status *rx_status); 750 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 751 u32 addr, u32 mask); 752 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 753 u32 addr, u32 mask, u32 data); 754 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 755 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 756 u32 size); 757 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx, 758 u8 antenna_rx); 759 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 760 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 761 void (*phy_calibration)(struct rtw_dev *rtwdev); 762 void (*dpk_track)(struct rtw_dev *rtwdev); 763 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 764 void (*pwr_track)(struct rtw_dev *rtwdev); 765 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 766 struct rtw_bfee *bfee, bool enable); 767 void (*set_gid_table)(struct rtw_dev *rtwdev, 768 struct ieee80211_vif *vif, 769 struct ieee80211_bss_conf *conf); 770 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 771 u8 fixrate_en, u8 *new_rate); 772 773 /* for coex */ 774 void (*coex_set_init)(struct rtw_dev *rtwdev); 775 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 776 u8 ctrl_type, u8 pos_type); 777 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 778 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 779 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 780 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 781 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 782 }; 783 784 #define RTW_PWR_POLLING_CNT 20000 785 786 #define RTW_PWR_CMD_READ 0x00 787 #define RTW_PWR_CMD_WRITE 0x01 788 #define RTW_PWR_CMD_POLLING 0x02 789 #define RTW_PWR_CMD_DELAY 0x03 790 #define RTW_PWR_CMD_END 0x04 791 792 /* define the base address of each block */ 793 #define RTW_PWR_ADDR_MAC 0x00 794 #define RTW_PWR_ADDR_USB 0x01 795 #define RTW_PWR_ADDR_PCIE 0x02 796 #define RTW_PWR_ADDR_SDIO 0x03 797 798 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 799 #define RTW_PWR_INTF_USB_MSK BIT(1) 800 #define RTW_PWR_INTF_PCI_MSK BIT(2) 801 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 802 803 #define RTW_PWR_CUT_A_MSK BIT(1) 804 #define RTW_PWR_CUT_B_MSK BIT(2) 805 #define RTW_PWR_CUT_C_MSK BIT(3) 806 #define RTW_PWR_CUT_D_MSK BIT(4) 807 #define RTW_PWR_CUT_E_MSK BIT(5) 808 #define RTW_PWR_CUT_F_MSK BIT(6) 809 #define RTW_PWR_CUT_G_MSK BIT(7) 810 #define RTW_PWR_CUT_ALL_MSK 0xFF 811 812 enum rtw_pwr_seq_cmd_delay_unit { 813 RTW_PWR_DELAY_US, 814 RTW_PWR_DELAY_MS, 815 }; 816 817 struct rtw_pwr_seq_cmd { 818 u16 offset; 819 u8 cut_mask; 820 u8 intf_mask; 821 u8 base:4; 822 u8 cmd:4; 823 u8 mask; 824 u8 value; 825 }; 826 827 enum rtw_chip_ver { 828 RTW_CHIP_VER_CUT_A = 0x00, 829 RTW_CHIP_VER_CUT_B = 0x01, 830 RTW_CHIP_VER_CUT_C = 0x02, 831 RTW_CHIP_VER_CUT_D = 0x03, 832 RTW_CHIP_VER_CUT_E = 0x04, 833 RTW_CHIP_VER_CUT_F = 0x05, 834 RTW_CHIP_VER_CUT_G = 0x06, 835 }; 836 837 #define RTW_INTF_PHY_PLATFORM_ALL 0 838 839 enum rtw_intf_phy_cut { 840 RTW_INTF_PHY_CUT_A = BIT(0), 841 RTW_INTF_PHY_CUT_B = BIT(1), 842 RTW_INTF_PHY_CUT_C = BIT(2), 843 RTW_INTF_PHY_CUT_D = BIT(3), 844 RTW_INTF_PHY_CUT_E = BIT(4), 845 RTW_INTF_PHY_CUT_F = BIT(5), 846 RTW_INTF_PHY_CUT_G = BIT(6), 847 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 848 }; 849 850 enum rtw_ip_sel { 851 RTW_IP_SEL_PHY = 0, 852 RTW_IP_SEL_MAC = 1, 853 RTW_IP_SEL_DBI = 2, 854 855 RTW_IP_SEL_UNDEF = 0xFFFF 856 }; 857 858 enum rtw_pq_map_id { 859 RTW_PQ_MAP_VO = 0x0, 860 RTW_PQ_MAP_VI = 0x1, 861 RTW_PQ_MAP_BE = 0x2, 862 RTW_PQ_MAP_BK = 0x3, 863 RTW_PQ_MAP_MG = 0x4, 864 RTW_PQ_MAP_HI = 0x5, 865 RTW_PQ_MAP_NUM = 0x6, 866 867 RTW_PQ_MAP_UNDEF, 868 }; 869 870 enum rtw_dma_mapping { 871 RTW_DMA_MAPPING_EXTRA = 0, 872 RTW_DMA_MAPPING_LOW = 1, 873 RTW_DMA_MAPPING_NORMAL = 2, 874 RTW_DMA_MAPPING_HIGH = 3, 875 876 RTW_DMA_MAPPING_MAX, 877 RTW_DMA_MAPPING_UNDEF, 878 }; 879 880 struct rtw_rqpn { 881 enum rtw_dma_mapping dma_map_vo; 882 enum rtw_dma_mapping dma_map_vi; 883 enum rtw_dma_mapping dma_map_be; 884 enum rtw_dma_mapping dma_map_bk; 885 enum rtw_dma_mapping dma_map_mg; 886 enum rtw_dma_mapping dma_map_hi; 887 }; 888 889 struct rtw_page_table { 890 u16 hq_num; 891 u16 nq_num; 892 u16 lq_num; 893 u16 exq_num; 894 u16 gapq_num; 895 }; 896 897 struct rtw_intf_phy_para { 898 u16 offset; 899 u16 value; 900 u16 ip_sel; 901 u16 cut_mask; 902 u16 platform; 903 }; 904 905 struct rtw_intf_phy_para_table { 906 struct rtw_intf_phy_para *usb2_para; 907 struct rtw_intf_phy_para *usb3_para; 908 struct rtw_intf_phy_para *gen1_para; 909 struct rtw_intf_phy_para *gen2_para; 910 u8 n_usb2_para; 911 u8 n_usb3_para; 912 u8 n_gen1_para; 913 u8 n_gen2_para; 914 }; 915 916 struct rtw_table { 917 const void *data; 918 const u32 size; 919 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 920 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 921 u32 addr, u32 data); 922 enum rtw_rf_path rf_path; 923 }; 924 925 static inline void rtw_load_table(struct rtw_dev *rtwdev, 926 const struct rtw_table *tbl) 927 { 928 (*tbl->parse)(rtwdev, tbl); 929 } 930 931 enum rtw_rfe_fem { 932 RTW_RFE_IFEM, 933 RTW_RFE_EFEM, 934 RTW_RFE_IFEM2G_EFEM5G, 935 RTW_RFE_NUM, 936 }; 937 938 struct rtw_rfe_def { 939 const struct rtw_table *phy_pg_tbl; 940 const struct rtw_table *txpwr_lmt_tbl; 941 }; 942 943 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 944 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 945 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 946 } 947 948 #define RTW_PWR_TRK_5G_1 0 949 #define RTW_PWR_TRK_5G_2 1 950 #define RTW_PWR_TRK_5G_3 2 951 #define RTW_PWR_TRK_5G_NUM 3 952 953 #define RTW_PWR_TRK_TBL_SZ 30 954 955 /* This table stores the values of TX power that will be adjusted by power 956 * tracking. 957 * 958 * For 5G bands, there are 3 different settings. 959 * For 2G there are cck rate and ofdm rate with different settings. 960 */ 961 struct rtw_pwr_track_tbl { 962 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 963 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 964 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 965 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 966 const u8 *pwrtrk_2gb_n; 967 const u8 *pwrtrk_2gb_p; 968 const u8 *pwrtrk_2ga_n; 969 const u8 *pwrtrk_2ga_p; 970 const u8 *pwrtrk_2g_cckb_n; 971 const u8 *pwrtrk_2g_cckb_p; 972 const u8 *pwrtrk_2g_ccka_n; 973 const u8 *pwrtrk_2g_ccka_p; 974 }; 975 976 /* hardware configuration for each IC */ 977 struct rtw_chip_info { 978 struct rtw_chip_ops *ops; 979 u8 id; 980 981 const char *fw_name; 982 u8 tx_pkt_desc_sz; 983 u8 tx_buf_desc_sz; 984 u8 rx_pkt_desc_sz; 985 u8 rx_buf_desc_sz; 986 u32 phy_efuse_size; 987 u32 log_efuse_size; 988 u32 ptct_efuse_size; 989 u32 txff_size; 990 u32 rxff_size; 991 u8 band; 992 u8 page_size; 993 u8 csi_buf_pg_num; 994 u8 dig_max; 995 u8 dig_min; 996 u8 txgi_factor; 997 bool is_pwr_by_rate_dec; 998 u8 max_power_index; 999 1000 bool ht_supported; 1001 bool vht_supported; 1002 u8 lps_deep_mode_supported; 1003 1004 /* init values */ 1005 u8 sys_func_en; 1006 struct rtw_pwr_seq_cmd **pwr_on_seq; 1007 struct rtw_pwr_seq_cmd **pwr_off_seq; 1008 struct rtw_rqpn *rqpn_table; 1009 struct rtw_page_table *page_table; 1010 struct rtw_intf_phy_para_table *intf_table; 1011 1012 struct rtw_hw_reg *dig; 1013 u32 rf_base_addr[2]; 1014 u32 rf_sipi_addr[2]; 1015 1016 const struct rtw_table *mac_tbl; 1017 const struct rtw_table *agc_tbl; 1018 const struct rtw_table *bb_tbl; 1019 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1020 const struct rtw_table *rfk_init_tbl; 1021 1022 const struct rtw_rfe_def *rfe_defs; 1023 u32 rfe_defs_size; 1024 1025 bool en_dis_dpd; 1026 u16 dpd_ratemask; 1027 u8 iqk_threshold; 1028 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1029 1030 u8 bfer_su_max_num; 1031 u8 bfer_mu_max_num; 1032 1033 /* coex paras */ 1034 u32 coex_para_ver; 1035 u8 bt_desired_ver; 1036 bool scbd_support; 1037 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1038 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1039 u8 bt_rssi_type; 1040 u8 ant_isolation; 1041 u8 rssi_tolerance; 1042 u8 table_sant_num; 1043 u8 table_nsant_num; 1044 u8 tdma_sant_num; 1045 u8 tdma_nsant_num; 1046 u8 bt_afh_span_bw20; 1047 u8 bt_afh_span_bw40; 1048 u8 afh_5g_num; 1049 u8 wl_rf_para_num; 1050 const u8 *bt_rssi_step; 1051 const u8 *wl_rssi_step; 1052 const struct coex_table_para *table_nsant; 1053 const struct coex_table_para *table_sant; 1054 const struct coex_tdma_para *tdma_sant; 1055 const struct coex_tdma_para *tdma_nsant; 1056 const struct coex_rf_para *wl_rf_para_tx; 1057 const struct coex_rf_para *wl_rf_para_rx; 1058 const struct coex_5g_afh_map *afh_5g; 1059 }; 1060 1061 enum rtw_coex_bt_state_cnt { 1062 COEX_CNT_BT_RETRY, 1063 COEX_CNT_BT_REINIT, 1064 COEX_CNT_BT_REENABLE, 1065 COEX_CNT_BT_POPEVENT, 1066 COEX_CNT_BT_SETUPLINK, 1067 COEX_CNT_BT_IGNWLANACT, 1068 COEX_CNT_BT_INQ, 1069 COEX_CNT_BT_PAGE, 1070 COEX_CNT_BT_ROLESWITCH, 1071 COEX_CNT_BT_AFHUPDATE, 1072 COEX_CNT_BT_INFOUPDATE, 1073 COEX_CNT_BT_IQK, 1074 COEX_CNT_BT_IQKFAIL, 1075 1076 COEX_CNT_BT_MAX 1077 }; 1078 1079 enum rtw_coex_wl_state_cnt { 1080 COEX_CNT_WL_CONNPKT, 1081 COEX_CNT_WL_COEXRUN, 1082 COEX_CNT_WL_NOISY0, 1083 COEX_CNT_WL_NOISY1, 1084 COEX_CNT_WL_NOISY2, 1085 COEX_CNT_WL_5MS_NOEXTEND, 1086 COEX_CNT_WL_FW_NOTIFY, 1087 1088 COEX_CNT_WL_MAX 1089 }; 1090 1091 struct rtw_coex_rfe { 1092 bool ant_switch_exist; 1093 bool ant_switch_diversity; 1094 bool ant_switch_with_bt; 1095 u8 rfe_module_type; 1096 u8 ant_switch_polarity; 1097 1098 /* true if WLG at BTG, else at WLAG */ 1099 bool wlg_at_btg; 1100 }; 1101 1102 struct rtw_coex_dm { 1103 bool cur_ps_tdma_on; 1104 bool cur_wl_rx_low_gain_en; 1105 1106 u8 reason; 1107 u8 bt_rssi_state[4]; 1108 u8 wl_rssi_state[4]; 1109 u8 wl_ch_info[3]; 1110 u8 cur_ps_tdma; 1111 u8 cur_table; 1112 u8 ps_tdma_para[5]; 1113 u8 cur_bt_pwr_lvl; 1114 u8 cur_bt_lna_lvl; 1115 u8 cur_wl_pwr_lvl; 1116 u8 bt_status; 1117 u32 cur_ant_pos_type; 1118 u32 cur_switch_status; 1119 u32 setting_tdma; 1120 }; 1121 1122 #define COEX_BTINFO_SRC_WL_FW 0x0 1123 #define COEX_BTINFO_SRC_BT_RSP 0x1 1124 #define COEX_BTINFO_SRC_BT_ACT 0x2 1125 #define COEX_BTINFO_SRC_BT_IQK 0x3 1126 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1127 #define COEX_BTINFO_SRC_MAX 0x5 1128 1129 #define COEX_INFO_FTP BIT(7) 1130 #define COEX_INFO_A2DP BIT(6) 1131 #define COEX_INFO_HID BIT(5) 1132 #define COEX_INFO_SCO_BUSY BIT(4) 1133 #define COEX_INFO_ACL_BUSY BIT(3) 1134 #define COEX_INFO_INQ_PAGE BIT(2) 1135 #define COEX_INFO_SCO_ESCO BIT(1) 1136 #define COEX_INFO_CONNECTION BIT(0) 1137 #define COEX_BTINFO_LENGTH_MAX 10 1138 1139 struct rtw_coex_stat { 1140 bool bt_disabled; 1141 bool bt_disabled_pre; 1142 bool bt_link_exist; 1143 bool bt_whck_test; 1144 bool bt_inq_page; 1145 bool bt_inq; 1146 bool bt_page; 1147 bool bt_ble_voice; 1148 bool bt_ble_exist; 1149 bool bt_hfp_exist; 1150 bool bt_a2dp_exist; 1151 bool bt_hid_exist; 1152 bool bt_pan_exist; /* PAN or OPP */ 1153 bool bt_opp_exist; /* OPP only */ 1154 bool bt_acl_busy; 1155 bool bt_fix_2M; 1156 bool bt_setup_link; 1157 bool bt_multi_link; 1158 bool bt_a2dp_sink; 1159 bool bt_a2dp_active; 1160 bool bt_reenable; 1161 bool bt_ble_scan_en; 1162 bool bt_init_scan; 1163 bool bt_slave; 1164 bool bt_418_hid_exist; 1165 bool bt_mailbox_reply; 1166 1167 bool wl_under_lps; 1168 bool wl_under_ips; 1169 bool wl_hi_pri_task1; 1170 bool wl_hi_pri_task2; 1171 bool wl_force_lps_ctrl; 1172 bool wl_gl_busy; 1173 bool wl_linkscan_proc; 1174 bool wl_ps_state_fail; 1175 bool wl_tx_limit_en; 1176 bool wl_ampdu_limit_en; 1177 bool wl_connected; 1178 bool wl_slot_extend; 1179 bool wl_cck_lock; 1180 bool wl_cck_lock_pre; 1181 bool wl_cck_lock_ever; 1182 1183 u32 bt_supported_version; 1184 u32 bt_supported_feature; 1185 s8 bt_rssi; 1186 u8 kt_ver; 1187 u8 gnt_workaround_state; 1188 u8 tdma_timer_base; 1189 u8 bt_profile_num; 1190 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1191 u8 bt_info_lb2; 1192 u8 bt_info_lb3; 1193 u8 bt_info_hb0; 1194 u8 bt_info_hb1; 1195 u8 bt_info_hb2; 1196 u8 bt_info_hb3; 1197 u8 bt_ble_scan_type; 1198 u8 bt_hid_pair_num; 1199 u8 bt_hid_slot; 1200 u8 bt_a2dp_bitpool; 1201 u8 bt_iqk_state; 1202 1203 u8 wl_noisy_level; 1204 u8 wl_fw_dbg_info[10]; 1205 u8 wl_fw_dbg_info_pre[10]; 1206 u8 wl_coex_mode; 1207 u8 ampdu_max_time; 1208 u8 wl_tput_dir; 1209 1210 u16 score_board; 1211 u16 retry_limit; 1212 1213 /* counters to record bt states */ 1214 u32 cnt_bt[COEX_CNT_BT_MAX]; 1215 1216 /* counters to record wifi states */ 1217 u32 cnt_wl[COEX_CNT_WL_MAX]; 1218 1219 u32 darfrc; 1220 u32 darfrch; 1221 }; 1222 1223 struct rtw_coex { 1224 /* protects coex info request section */ 1225 struct mutex mutex; 1226 struct sk_buff_head queue; 1227 wait_queue_head_t wait; 1228 1229 bool under_5g; 1230 bool stop_dm; 1231 bool freeze; 1232 bool freerun; 1233 bool wl_rf_off; 1234 1235 struct rtw_coex_stat stat; 1236 struct rtw_coex_dm dm; 1237 struct rtw_coex_rfe rfe; 1238 1239 struct delayed_work bt_relink_work; 1240 struct delayed_work bt_reenable_work; 1241 struct delayed_work defreeze_work; 1242 }; 1243 1244 #define DPK_RF_REG_NUM 7 1245 #define DPK_RF_PATH_NUM 2 1246 #define DPK_BB_REG_NUM 18 1247 #define DPK_CHANNEL_WIDTH_80 1 1248 1249 DECLARE_EWMA(thermal, 10, 4); 1250 1251 struct rtw_dpk_info { 1252 bool is_dpk_pwr_on; 1253 bool is_reload; 1254 1255 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1256 1257 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1258 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1259 1260 u32 gnt_control; 1261 u32 gnt_value; 1262 1263 u8 result[RTW_RF_PATH_MAX]; 1264 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1265 u32 coef[RTW_RF_PATH_MAX][20]; 1266 u16 dpk_gs[RTW_RF_PATH_MAX]; 1267 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1268 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1269 1270 u8 dpk_band; 1271 u8 dpk_ch; 1272 u8 dpk_bw; 1273 }; 1274 1275 struct rtw_phy_cck_pd_reg { 1276 u32 reg_pd; 1277 u32 mask_pd; 1278 u32 reg_cs; 1279 u32 mask_cs; 1280 }; 1281 1282 #define DACK_MSBK_BACKUP_NUM 0xf 1283 #define DACK_DCK_BACKUP_NUM 0x2 1284 1285 struct rtw_swing_table { 1286 const u8 *p[RTW_RF_PATH_MAX]; 1287 const u8 *n[RTW_RF_PATH_MAX]; 1288 }; 1289 1290 struct rtw_pkt_count { 1291 u16 num_bcn_pkt; 1292 u16 num_qry_pkt[DESC_RATE_MAX]; 1293 }; 1294 1295 DECLARE_EWMA(evm, 10, 4); 1296 DECLARE_EWMA(snr, 10, 4); 1297 1298 struct rtw_dm_info { 1299 u32 cck_fa_cnt; 1300 u32 ofdm_fa_cnt; 1301 u32 total_fa_cnt; 1302 u32 cck_cca_cnt; 1303 u32 ofdm_cca_cnt; 1304 u32 total_cca_cnt; 1305 1306 u32 cck_ok_cnt; 1307 u32 cck_err_cnt; 1308 u32 ofdm_ok_cnt; 1309 u32 ofdm_err_cnt; 1310 u32 ht_ok_cnt; 1311 u32 ht_err_cnt; 1312 u32 vht_ok_cnt; 1313 u32 vht_err_cnt; 1314 1315 u8 min_rssi; 1316 u8 pre_min_rssi; 1317 u16 fa_history[4]; 1318 u8 igi_history[4]; 1319 u8 igi_bitmap; 1320 bool damping; 1321 u8 damping_cnt; 1322 u8 damping_rssi; 1323 1324 u8 cck_gi_u_bnd; 1325 u8 cck_gi_l_bnd; 1326 1327 u8 tx_rate; 1328 u8 thermal_avg[RTW_RF_PATH_MAX]; 1329 u8 thermal_meter_k; 1330 s8 delta_power_index[RTW_RF_PATH_MAX]; 1331 u8 default_ofdm_index; 1332 bool pwr_trk_triggered; 1333 bool pwr_trk_init_trigger; 1334 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1335 1336 /* backup dack results for each path and I/Q */ 1337 u32 dack_adck[RTW_RF_PATH_MAX]; 1338 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1339 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1340 1341 struct rtw_dpk_info dpk_info; 1342 1343 /* [bandwidth 0:20M/1:40M][number of path] */ 1344 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1345 u32 cck_fa_avg; 1346 1347 /* save the last rx phy status for debug */ 1348 s8 rx_snr[RTW_RF_PATH_MAX]; 1349 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1350 s16 cfo_tail[RTW_RF_PATH_MAX]; 1351 u8 rssi[RTW_RF_PATH_MAX]; 1352 u8 curr_rx_rate; 1353 struct rtw_pkt_count cur_pkt_count; 1354 struct rtw_pkt_count last_pkt_count; 1355 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1356 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1357 }; 1358 1359 struct rtw_efuse { 1360 u32 size; 1361 u32 physical_size; 1362 u32 logical_size; 1363 u32 protect_size; 1364 1365 u8 addr[ETH_ALEN]; 1366 u8 channel_plan; 1367 u8 country_code[2]; 1368 u8 rf_board_option; 1369 u8 rfe_option; 1370 u8 power_track_type; 1371 u8 thermal_meter[RTW_RF_PATH_MAX]; 1372 u8 thermal_meter_k; 1373 u8 crystal_cap; 1374 u8 ant_div_cfg; 1375 u8 ant_div_type; 1376 u8 regd; 1377 1378 u8 lna_type_2g; 1379 u8 lna_type_5g; 1380 u8 glna_type; 1381 u8 alna_type; 1382 bool ext_lna_2g; 1383 bool ext_lna_5g; 1384 u8 pa_type_2g; 1385 u8 pa_type_5g; 1386 u8 gpa_type; 1387 u8 apa_type; 1388 bool ext_pa_2g; 1389 bool ext_pa_5g; 1390 1391 bool btcoex; 1392 /* bt share antenna with wifi */ 1393 bool share_ant; 1394 u8 bt_setting; 1395 1396 struct { 1397 u8 hci; 1398 u8 bw; 1399 u8 ptcl; 1400 u8 nss; 1401 u8 ant_num; 1402 } hw_cap; 1403 1404 struct rtw_txpwr_idx txpwr_idx_table[4]; 1405 }; 1406 1407 struct rtw_phy_cond { 1408 #ifdef __LITTLE_ENDIAN 1409 u32 rfe:8; 1410 u32 intf:4; 1411 u32 pkg:4; 1412 u32 plat:4; 1413 u32 intf_rsvd:4; 1414 u32 cut:4; 1415 u32 branch:2; 1416 u32 neg:1; 1417 u32 pos:1; 1418 #else 1419 u32 pos:1; 1420 u32 neg:1; 1421 u32 branch:2; 1422 u32 cut:4; 1423 u32 intf_rsvd:4; 1424 u32 plat:4; 1425 u32 pkg:4; 1426 u32 intf:4; 1427 u32 rfe:8; 1428 #endif 1429 /* for intf:4 */ 1430 #define INTF_PCIE BIT(0) 1431 #define INTF_USB BIT(1) 1432 #define INTF_SDIO BIT(2) 1433 /* for branch:2 */ 1434 #define BRANCH_IF 0 1435 #define BRANCH_ELIF 1 1436 #define BRANCH_ELSE 2 1437 #define BRANCH_ENDIF 3 1438 }; 1439 1440 struct rtw_fifo_conf { 1441 /* tx fifo information */ 1442 u16 rsvd_boundary; 1443 u16 rsvd_pg_num; 1444 u16 rsvd_drv_pg_num; 1445 u16 txff_pg_num; 1446 u16 acq_pg_num; 1447 u16 rsvd_drv_addr; 1448 u16 rsvd_h2c_info_addr; 1449 u16 rsvd_h2c_sta_info_addr; 1450 u16 rsvd_h2cq_addr; 1451 u16 rsvd_cpu_instr_addr; 1452 u16 rsvd_fw_txbuf_addr; 1453 u16 rsvd_csibuf_addr; 1454 struct rtw_rqpn *rqpn; 1455 }; 1456 1457 struct rtw_fw_state { 1458 const struct firmware *firmware; 1459 struct completion completion; 1460 u16 version; 1461 u8 sub_version; 1462 u8 sub_index; 1463 u16 h2c_version; 1464 }; 1465 1466 struct rtw_hal { 1467 u32 rcr; 1468 1469 u32 chip_version; 1470 u8 fab_version; 1471 u8 cut_version; 1472 u8 mp_chip; 1473 u8 oem_id; 1474 struct rtw_phy_cond phy_cond; 1475 1476 u8 ps_mode; 1477 u8 current_channel; 1478 u8 current_band_width; 1479 u8 current_band_type; 1480 1481 /* center channel for different available bandwidth, 1482 * val of (bw > current_band_width) is invalid 1483 */ 1484 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1485 1486 u8 sec_ch_offset; 1487 u8 rf_type; 1488 u8 rf_path_num; 1489 u8 antenna_tx; 1490 u8 antenna_rx; 1491 u8 bfee_sts_cap; 1492 1493 /* protect tx power section */ 1494 struct mutex tx_power_mutex; 1495 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1496 [DESC_RATE_MAX]; 1497 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1498 [DESC_RATE_MAX]; 1499 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1500 [RTW_RATE_SECTION_MAX]; 1501 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1502 [RTW_RATE_SECTION_MAX]; 1503 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1504 [RTW_CHANNEL_WIDTH_MAX] 1505 [RTW_RATE_SECTION_MAX] 1506 [RTW_MAX_CHANNEL_NUM_2G]; 1507 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1508 [RTW_CHANNEL_WIDTH_MAX] 1509 [RTW_RATE_SECTION_MAX] 1510 [RTW_MAX_CHANNEL_NUM_5G]; 1511 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1512 [DESC_RATE_MAX]; 1513 }; 1514 1515 struct rtw_dev { 1516 struct ieee80211_hw *hw; 1517 struct device *dev; 1518 1519 struct rtw_hci hci; 1520 1521 struct rtw_chip_info *chip; 1522 struct rtw_hal hal; 1523 struct rtw_fifo_conf fifo; 1524 struct rtw_fw_state fw; 1525 struct rtw_efuse efuse; 1526 struct rtw_sec_desc sec; 1527 struct rtw_traffic_stats stats; 1528 struct rtw_regulatory regd; 1529 struct rtw_bf_info bf_info; 1530 1531 struct rtw_dm_info dm_info; 1532 struct rtw_coex coex; 1533 1534 /* ensures exclusive access from mac80211 callbacks */ 1535 struct mutex mutex; 1536 1537 /* lock for dm to use */ 1538 spinlock_t dm_lock; 1539 1540 /* read/write rf register */ 1541 spinlock_t rf_lock; 1542 1543 /* watch dog every 2 sec */ 1544 struct delayed_work watch_dog_work; 1545 u32 watch_dog_cnt; 1546 1547 struct list_head rsvd_page_list; 1548 1549 /* c2h cmd queue & handler work */ 1550 struct sk_buff_head c2h_queue; 1551 struct work_struct c2h_work; 1552 1553 /* used to protect txqs list */ 1554 spinlock_t txq_lock; 1555 struct list_head txqs; 1556 struct tasklet_struct tx_tasklet; 1557 struct work_struct ba_work; 1558 1559 struct rtw_tx_report tx_report; 1560 1561 struct { 1562 /* incicate the mail box to use with fw */ 1563 u8 last_box_num; 1564 /* protect to send h2c to fw */ 1565 spinlock_t lock; 1566 u32 seq; 1567 } h2c; 1568 1569 /* lps power state & handler work */ 1570 struct rtw_lps_conf lps_conf; 1571 bool ps_enabled; 1572 1573 struct dentry *debugfs; 1574 1575 u8 sta_cnt; 1576 u32 rts_threshold; 1577 1578 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 1579 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 1580 1581 u8 mp_mode; 1582 1583 /* hci related data, must be last */ 1584 u8 priv[0] __aligned(sizeof(void *)); 1585 }; 1586 1587 #include "hci.h" 1588 1589 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 1590 { 1591 return !!rtwdev->sta_cnt; 1592 } 1593 1594 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 1595 { 1596 void *p = rtwtxq; 1597 1598 return container_of(p, struct ieee80211_txq, drv_priv); 1599 } 1600 1601 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 1602 { 1603 void *p = rtwvif; 1604 1605 return container_of(p, struct ieee80211_vif, drv_priv); 1606 } 1607 1608 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 1609 struct rtw_channel_params *ch_param); 1610 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 1611 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 1612 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 1613 void rtw_restore_reg(struct rtw_dev *rtwdev, 1614 struct rtw_backup_info *bckp, u32 num); 1615 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 1616 void rtw_set_channel(struct rtw_dev *rtwdev); 1617 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1618 u32 config); 1619 void rtw_tx_report_purge_timer(struct timer_list *t); 1620 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 1621 int rtw_core_start(struct rtw_dev *rtwdev); 1622 void rtw_core_stop(struct rtw_dev *rtwdev); 1623 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 1624 int rtw_core_init(struct rtw_dev *rtwdev); 1625 void rtw_core_deinit(struct rtw_dev *rtwdev); 1626 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1627 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 1628 u16 rtw_desc_to_bitrate(u8 desc_rate); 1629 1630 #endif 1631