1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 18 #include "util.h" 19 20 #define RTW_MAX_MAC_ID_NUM 32 21 #define RTW_MAX_SEC_CAM_NUM 32 22 #define MAX_PG_CAM_BACKUP_NUM 8 23 24 #define RTW_SCAN_MAX_SSIDS 4 25 26 #define RTW_MAX_PATTERN_NUM 12 27 #define RTW_MAX_PATTERN_MASK_SIZE 16 28 #define RTW_MAX_PATTERN_SIZE 128 29 30 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 31 32 #define RFREG_MASK 0xfffff 33 #define INV_RF_DATA 0xffffffff 34 #define TX_PAGE_SIZE_SHIFT 7 35 #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT) 36 37 #define RTW_CHANNEL_WIDTH_MAX 3 38 #define RTW_RF_PATH_MAX 4 39 #define HW_FEATURE_LEN 13 40 41 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 42 43 extern bool rtw_bf_support; 44 extern bool rtw_disable_lps_deep_mode; 45 extern unsigned int rtw_debug_mask; 46 extern bool rtw_edcca_enabled; 47 extern const struct ieee80211_ops rtw_ops; 48 49 #define RTW_MAX_CHANNEL_NUM_2G 14 50 #define RTW_MAX_CHANNEL_NUM_5G 49 51 52 struct rtw_dev; 53 54 enum rtw_hci_type { 55 RTW_HCI_TYPE_PCIE, 56 RTW_HCI_TYPE_USB, 57 RTW_HCI_TYPE_SDIO, 58 59 RTW_HCI_TYPE_UNDEFINE, 60 }; 61 62 struct rtw_hci { 63 struct rtw_hci_ops *ops; 64 enum rtw_hci_type type; 65 66 u32 rpwm_addr; 67 u32 cpwm_addr; 68 69 u8 bulkout_num; 70 }; 71 72 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 73 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 74 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 75 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 76 77 #define IS_CH_5G_BAND_MID(channel) \ 78 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 79 80 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 81 #define IS_CH_5G_BAND(channel) \ 82 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 83 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 84 85 enum rtw_supported_band { 86 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 87 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 88 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 89 }; 90 91 /* now, support up to 80M bw */ 92 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 93 94 enum rtw_bandwidth { 95 RTW_CHANNEL_WIDTH_20 = 0, 96 RTW_CHANNEL_WIDTH_40 = 1, 97 RTW_CHANNEL_WIDTH_80 = 2, 98 RTW_CHANNEL_WIDTH_160 = 3, 99 RTW_CHANNEL_WIDTH_80_80 = 4, 100 RTW_CHANNEL_WIDTH_5 = 5, 101 RTW_CHANNEL_WIDTH_10 = 6, 102 }; 103 104 enum rtw_sc_offset { 105 RTW_SC_DONT_CARE = 0, 106 RTW_SC_20_UPPER = 1, 107 RTW_SC_20_LOWER = 2, 108 RTW_SC_20_UPMOST = 3, 109 RTW_SC_20_LOWEST = 4, 110 RTW_SC_40_UPPER = 9, 111 RTW_SC_40_LOWER = 10, 112 }; 113 114 enum rtw_net_type { 115 RTW_NET_NO_LINK = 0, 116 RTW_NET_AD_HOC = 1, 117 RTW_NET_MGD_LINKED = 2, 118 RTW_NET_AP_MODE = 3, 119 }; 120 121 enum rtw_rf_type { 122 RF_1T1R = 0, 123 RF_1T2R = 1, 124 RF_2T2R = 2, 125 RF_2T3R = 3, 126 RF_2T4R = 4, 127 RF_3T3R = 5, 128 RF_3T4R = 6, 129 RF_4T4R = 7, 130 RF_TYPE_MAX, 131 }; 132 133 enum rtw_rf_path { 134 RF_PATH_A = 0, 135 RF_PATH_B = 1, 136 RF_PATH_C = 2, 137 RF_PATH_D = 3, 138 }; 139 140 enum rtw_bb_path { 141 BB_PATH_A = BIT(0), 142 BB_PATH_B = BIT(1), 143 BB_PATH_C = BIT(2), 144 BB_PATH_D = BIT(3), 145 146 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 147 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 148 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 149 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 150 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 151 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 152 153 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 154 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 155 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 156 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 157 158 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 159 }; 160 161 enum rtw_rate_section { 162 RTW_RATE_SECTION_CCK = 0, 163 RTW_RATE_SECTION_OFDM, 164 RTW_RATE_SECTION_HT_1S, 165 RTW_RATE_SECTION_HT_2S, 166 RTW_RATE_SECTION_VHT_1S, 167 RTW_RATE_SECTION_VHT_2S, 168 169 /* keep last */ 170 RTW_RATE_SECTION_MAX, 171 }; 172 173 enum rtw_wireless_set { 174 WIRELESS_CCK = 0x00000001, 175 WIRELESS_OFDM = 0x00000002, 176 WIRELESS_HT = 0x00000004, 177 WIRELESS_VHT = 0x00000008, 178 }; 179 180 #define HT_STBC_EN BIT(0) 181 #define VHT_STBC_EN BIT(1) 182 #define HT_LDPC_EN BIT(0) 183 #define VHT_LDPC_EN BIT(1) 184 185 enum rtw_chip_type { 186 RTW_CHIP_TYPE_8822B, 187 RTW_CHIP_TYPE_8822C, 188 RTW_CHIP_TYPE_8723D, 189 RTW_CHIP_TYPE_8821C, 190 }; 191 192 enum rtw_tx_queue_type { 193 /* the order of AC queues matters */ 194 RTW_TX_QUEUE_BK = 0x0, 195 RTW_TX_QUEUE_BE = 0x1, 196 RTW_TX_QUEUE_VI = 0x2, 197 RTW_TX_QUEUE_VO = 0x3, 198 199 RTW_TX_QUEUE_BCN = 0x4, 200 RTW_TX_QUEUE_MGMT = 0x5, 201 RTW_TX_QUEUE_HI0 = 0x6, 202 RTW_TX_QUEUE_H2C = 0x7, 203 /* keep it last */ 204 RTK_MAX_TX_QUEUE_NUM 205 }; 206 207 enum rtw_rx_queue_type { 208 RTW_RX_QUEUE_MPDU = 0x0, 209 RTW_RX_QUEUE_C2H = 0x1, 210 /* keep it last */ 211 RTK_MAX_RX_QUEUE_NUM 212 }; 213 214 enum rtw_fw_type { 215 RTW_NORMAL_FW = 0x0, 216 RTW_WOWLAN_FW = 0x1, 217 }; 218 219 enum rtw_rate_index { 220 RTW_RATEID_BGN_40M_2SS = 0, 221 RTW_RATEID_BGN_40M_1SS = 1, 222 RTW_RATEID_BGN_20M_2SS = 2, 223 RTW_RATEID_BGN_20M_1SS = 3, 224 RTW_RATEID_GN_N2SS = 4, 225 RTW_RATEID_GN_N1SS = 5, 226 RTW_RATEID_BG = 6, 227 RTW_RATEID_G = 7, 228 RTW_RATEID_B_20M = 8, 229 RTW_RATEID_ARFR0_AC_2SS = 9, 230 RTW_RATEID_ARFR1_AC_1SS = 10, 231 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 232 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 233 RTW_RATEID_ARFR4_AC_3SS = 13, 234 RTW_RATEID_ARFR5_N_3SS = 14, 235 RTW_RATEID_ARFR7_N_4SS = 15, 236 RTW_RATEID_ARFR6_AC_4SS = 16 237 }; 238 239 enum rtw_trx_desc_rate { 240 DESC_RATE1M = 0x00, 241 DESC_RATE2M = 0x01, 242 DESC_RATE5_5M = 0x02, 243 DESC_RATE11M = 0x03, 244 245 DESC_RATE6M = 0x04, 246 DESC_RATE9M = 0x05, 247 DESC_RATE12M = 0x06, 248 DESC_RATE18M = 0x07, 249 DESC_RATE24M = 0x08, 250 DESC_RATE36M = 0x09, 251 DESC_RATE48M = 0x0a, 252 DESC_RATE54M = 0x0b, 253 254 DESC_RATEMCS0 = 0x0c, 255 DESC_RATEMCS1 = 0x0d, 256 DESC_RATEMCS2 = 0x0e, 257 DESC_RATEMCS3 = 0x0f, 258 DESC_RATEMCS4 = 0x10, 259 DESC_RATEMCS5 = 0x11, 260 DESC_RATEMCS6 = 0x12, 261 DESC_RATEMCS7 = 0x13, 262 DESC_RATEMCS8 = 0x14, 263 DESC_RATEMCS9 = 0x15, 264 DESC_RATEMCS10 = 0x16, 265 DESC_RATEMCS11 = 0x17, 266 DESC_RATEMCS12 = 0x18, 267 DESC_RATEMCS13 = 0x19, 268 DESC_RATEMCS14 = 0x1a, 269 DESC_RATEMCS15 = 0x1b, 270 DESC_RATEMCS16 = 0x1c, 271 DESC_RATEMCS17 = 0x1d, 272 DESC_RATEMCS18 = 0x1e, 273 DESC_RATEMCS19 = 0x1f, 274 DESC_RATEMCS20 = 0x20, 275 DESC_RATEMCS21 = 0x21, 276 DESC_RATEMCS22 = 0x22, 277 DESC_RATEMCS23 = 0x23, 278 DESC_RATEMCS24 = 0x24, 279 DESC_RATEMCS25 = 0x25, 280 DESC_RATEMCS26 = 0x26, 281 DESC_RATEMCS27 = 0x27, 282 DESC_RATEMCS28 = 0x28, 283 DESC_RATEMCS29 = 0x29, 284 DESC_RATEMCS30 = 0x2a, 285 DESC_RATEMCS31 = 0x2b, 286 287 DESC_RATEVHT1SS_MCS0 = 0x2c, 288 DESC_RATEVHT1SS_MCS1 = 0x2d, 289 DESC_RATEVHT1SS_MCS2 = 0x2e, 290 DESC_RATEVHT1SS_MCS3 = 0x2f, 291 DESC_RATEVHT1SS_MCS4 = 0x30, 292 DESC_RATEVHT1SS_MCS5 = 0x31, 293 DESC_RATEVHT1SS_MCS6 = 0x32, 294 DESC_RATEVHT1SS_MCS7 = 0x33, 295 DESC_RATEVHT1SS_MCS8 = 0x34, 296 DESC_RATEVHT1SS_MCS9 = 0x35, 297 298 DESC_RATEVHT2SS_MCS0 = 0x36, 299 DESC_RATEVHT2SS_MCS1 = 0x37, 300 DESC_RATEVHT2SS_MCS2 = 0x38, 301 DESC_RATEVHT2SS_MCS3 = 0x39, 302 DESC_RATEVHT2SS_MCS4 = 0x3a, 303 DESC_RATEVHT2SS_MCS5 = 0x3b, 304 DESC_RATEVHT2SS_MCS6 = 0x3c, 305 DESC_RATEVHT2SS_MCS7 = 0x3d, 306 DESC_RATEVHT2SS_MCS8 = 0x3e, 307 DESC_RATEVHT2SS_MCS9 = 0x3f, 308 309 DESC_RATEVHT3SS_MCS0 = 0x40, 310 DESC_RATEVHT3SS_MCS1 = 0x41, 311 DESC_RATEVHT3SS_MCS2 = 0x42, 312 DESC_RATEVHT3SS_MCS3 = 0x43, 313 DESC_RATEVHT3SS_MCS4 = 0x44, 314 DESC_RATEVHT3SS_MCS5 = 0x45, 315 DESC_RATEVHT3SS_MCS6 = 0x46, 316 DESC_RATEVHT3SS_MCS7 = 0x47, 317 DESC_RATEVHT3SS_MCS8 = 0x48, 318 DESC_RATEVHT3SS_MCS9 = 0x49, 319 320 DESC_RATEVHT4SS_MCS0 = 0x4a, 321 DESC_RATEVHT4SS_MCS1 = 0x4b, 322 DESC_RATEVHT4SS_MCS2 = 0x4c, 323 DESC_RATEVHT4SS_MCS3 = 0x4d, 324 DESC_RATEVHT4SS_MCS4 = 0x4e, 325 DESC_RATEVHT4SS_MCS5 = 0x4f, 326 DESC_RATEVHT4SS_MCS6 = 0x50, 327 DESC_RATEVHT4SS_MCS7 = 0x51, 328 DESC_RATEVHT4SS_MCS8 = 0x52, 329 DESC_RATEVHT4SS_MCS9 = 0x53, 330 331 DESC_RATE_MAX, 332 }; 333 334 enum rtw_regulatory_domains { 335 RTW_REGD_FCC = 0, 336 RTW_REGD_MKK = 1, 337 RTW_REGD_ETSI = 2, 338 RTW_REGD_IC = 3, 339 RTW_REGD_KCC = 4, 340 RTW_REGD_ACMA = 5, 341 RTW_REGD_CHILE = 6, 342 RTW_REGD_UKRAINE = 7, 343 RTW_REGD_MEXICO = 8, 344 RTW_REGD_CN = 9, 345 RTW_REGD_WW, 346 347 RTW_REGD_MAX 348 }; 349 350 enum rtw_txq_flags { 351 RTW_TXQ_AMPDU, 352 RTW_TXQ_BLOCK_BA, 353 }; 354 355 enum rtw_flags { 356 RTW_FLAG_RUNNING, 357 RTW_FLAG_FW_RUNNING, 358 RTW_FLAG_SCANNING, 359 RTW_FLAG_POWERON, 360 RTW_FLAG_LEISURE_PS, 361 RTW_FLAG_LEISURE_PS_DEEP, 362 RTW_FLAG_DIG_DISABLE, 363 RTW_FLAG_BUSY_TRAFFIC, 364 RTW_FLAG_WOWLAN, 365 RTW_FLAG_RESTARTING, 366 RTW_FLAG_RESTART_TRIGGERING, 367 RTW_FLAG_FORCE_LOWEST_RATE, 368 369 NUM_OF_RTW_FLAGS, 370 }; 371 372 enum rtw_evm { 373 RTW_EVM_OFDM = 0, 374 RTW_EVM_1SS, 375 RTW_EVM_2SS_A, 376 RTW_EVM_2SS_B, 377 /* keep it last */ 378 RTW_EVM_NUM 379 }; 380 381 enum rtw_snr { 382 RTW_SNR_OFDM_A = 0, 383 RTW_SNR_OFDM_B, 384 RTW_SNR_OFDM_C, 385 RTW_SNR_OFDM_D, 386 RTW_SNR_1SS_A, 387 RTW_SNR_1SS_B, 388 RTW_SNR_1SS_C, 389 RTW_SNR_1SS_D, 390 RTW_SNR_2SS_A, 391 RTW_SNR_2SS_B, 392 RTW_SNR_2SS_C, 393 RTW_SNR_2SS_D, 394 /* keep it last */ 395 RTW_SNR_NUM 396 }; 397 398 enum rtw_port { 399 RTW_PORT_0 = 0, 400 RTW_PORT_1 = 1, 401 RTW_PORT_2 = 2, 402 RTW_PORT_3 = 3, 403 RTW_PORT_4 = 4, 404 RTW_PORT_NUM 405 }; 406 407 enum rtw_wow_flags { 408 RTW_WOW_FLAG_EN_MAGIC_PKT, 409 RTW_WOW_FLAG_EN_REKEY_PKT, 410 RTW_WOW_FLAG_EN_DISCONNECT, 411 412 /* keep it last */ 413 RTW_WOW_FLAG_MAX, 414 }; 415 416 /* the power index is represented by differences, which cck-1s & ht40-1s are 417 * the base values, so for 1s's differences, there are only ht20 & ofdm 418 */ 419 struct rtw_2g_1s_pwr_idx_diff { 420 #ifdef __LITTLE_ENDIAN 421 s8 ofdm:4; 422 s8 bw20:4; 423 #else 424 s8 bw20:4; 425 s8 ofdm:4; 426 #endif 427 } __packed; 428 429 struct rtw_2g_ns_pwr_idx_diff { 430 #ifdef __LITTLE_ENDIAN 431 s8 bw20:4; 432 s8 bw40:4; 433 s8 cck:4; 434 s8 ofdm:4; 435 #else 436 s8 ofdm:4; 437 s8 cck:4; 438 s8 bw40:4; 439 s8 bw20:4; 440 #endif 441 } __packed; 442 443 struct rtw_2g_txpwr_idx { 444 u8 cck_base[6]; 445 u8 bw40_base[5]; 446 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 447 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 448 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 449 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 450 }; 451 452 struct rtw_5g_ht_1s_pwr_idx_diff { 453 #ifdef __LITTLE_ENDIAN 454 s8 ofdm:4; 455 s8 bw20:4; 456 #else 457 s8 bw20:4; 458 s8 ofdm:4; 459 #endif 460 } __packed; 461 462 struct rtw_5g_ht_ns_pwr_idx_diff { 463 #ifdef __LITTLE_ENDIAN 464 s8 bw20:4; 465 s8 bw40:4; 466 #else 467 s8 bw40:4; 468 s8 bw20:4; 469 #endif 470 } __packed; 471 472 struct rtw_5g_ofdm_ns_pwr_idx_diff { 473 #ifdef __LITTLE_ENDIAN 474 s8 ofdm_3s:4; 475 s8 ofdm_2s:4; 476 s8 ofdm_4s:4; 477 s8 res:4; 478 #else 479 s8 res:4; 480 s8 ofdm_4s:4; 481 s8 ofdm_2s:4; 482 s8 ofdm_3s:4; 483 #endif 484 } __packed; 485 486 struct rtw_5g_vht_ns_pwr_idx_diff { 487 #ifdef __LITTLE_ENDIAN 488 s8 bw160:4; 489 s8 bw80:4; 490 #else 491 s8 bw80:4; 492 s8 bw160:4; 493 #endif 494 } __packed; 495 496 struct rtw_5g_txpwr_idx { 497 u8 bw40_base[14]; 498 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 499 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 500 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 501 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 502 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 503 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 504 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 505 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 506 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 507 }; 508 509 struct rtw_txpwr_idx { 510 struct rtw_2g_txpwr_idx pwr_idx_2g; 511 struct rtw_5g_txpwr_idx pwr_idx_5g; 512 }; 513 514 struct rtw_timer_list { 515 struct timer_list timer; 516 void (*function)(void *data); 517 void *args; 518 }; 519 520 struct rtw_channel_params { 521 u8 center_chan; 522 u8 primary_chan; 523 u8 bandwidth; 524 }; 525 526 struct rtw_hw_reg { 527 u32 addr; 528 u32 mask; 529 }; 530 531 struct rtw_ltecoex_addr { 532 u32 ctrl; 533 u32 wdata; 534 u32 rdata; 535 }; 536 537 struct rtw_reg_domain { 538 u32 addr; 539 u32 mask; 540 #define RTW_REG_DOMAIN_MAC32 0 541 #define RTW_REG_DOMAIN_MAC16 1 542 #define RTW_REG_DOMAIN_MAC8 2 543 #define RTW_REG_DOMAIN_RF_A 3 544 #define RTW_REG_DOMAIN_RF_B 4 545 #define RTW_REG_DOMAIN_NL 0xFF 546 u8 domain; 547 }; 548 549 struct rtw_rf_sipi_addr { 550 u32 hssi_1; 551 u32 hssi_2; 552 u32 lssi_read; 553 u32 lssi_read_pi; 554 }; 555 556 struct rtw_hw_reg_offset { 557 struct rtw_hw_reg hw_reg; 558 u8 offset; 559 }; 560 561 struct rtw_backup_info { 562 u8 len; 563 u32 reg; 564 u32 val; 565 }; 566 567 enum rtw_vif_port_set { 568 PORT_SET_MAC_ADDR = BIT(0), 569 PORT_SET_BSSID = BIT(1), 570 PORT_SET_NET_TYPE = BIT(2), 571 PORT_SET_AID = BIT(3), 572 PORT_SET_BCN_CTRL = BIT(4), 573 }; 574 575 struct rtw_vif_port { 576 struct rtw_hw_reg mac_addr; 577 struct rtw_hw_reg bssid; 578 struct rtw_hw_reg net_type; 579 struct rtw_hw_reg aid; 580 struct rtw_hw_reg bcn_ctrl; 581 }; 582 583 struct rtw_tx_pkt_info { 584 u32 tx_pkt_size; 585 u8 offset; 586 u8 pkt_offset; 587 u8 tim_offset; 588 u8 mac_id; 589 u8 rate_id; 590 u8 rate; 591 u8 qsel; 592 u8 bw; 593 u8 sec_type; 594 u8 sn; 595 bool ampdu_en; 596 u8 ampdu_factor; 597 u8 ampdu_density; 598 u16 seq; 599 bool stbc; 600 bool ldpc; 601 bool dis_rate_fallback; 602 bool bmc; 603 bool use_rate; 604 bool ls; 605 bool fs; 606 bool short_gi; 607 bool report; 608 bool rts; 609 bool dis_qselseq; 610 bool en_hwseq; 611 u8 hw_ssn_sel; 612 bool nav_use_hdr; 613 bool bt_null; 614 }; 615 616 struct rtw_rx_pkt_stat { 617 bool phy_status; 618 bool icv_err; 619 bool crc_err; 620 bool decrypted; 621 bool is_c2h; 622 623 s32 signal_power; 624 u16 pkt_len; 625 u8 bw; 626 u8 drv_info_sz; 627 u8 shift; 628 u8 rate; 629 u8 mac_id; 630 u8 cam_id; 631 u8 ppdu_cnt; 632 u32 tsf_low; 633 s8 rx_power[RTW_RF_PATH_MAX]; 634 u8 rssi; 635 u8 rxsc; 636 s8 rx_snr[RTW_RF_PATH_MAX]; 637 u8 rx_evm[RTW_RF_PATH_MAX]; 638 s8 cfo_tail[RTW_RF_PATH_MAX]; 639 u16 freq; 640 u8 band; 641 642 struct rtw_sta_info *si; 643 struct ieee80211_vif *vif; 644 struct ieee80211_hdr *hdr; 645 }; 646 647 DECLARE_EWMA(tp, 10, 2); 648 649 struct rtw_traffic_stats { 650 /* units in bytes */ 651 u64 tx_unicast; 652 u64 rx_unicast; 653 654 /* count for packets */ 655 u64 tx_cnt; 656 u64 rx_cnt; 657 658 /* units in Mbps */ 659 u32 tx_throughput; 660 u32 rx_throughput; 661 struct ewma_tp tx_ewma_tp; 662 struct ewma_tp rx_ewma_tp; 663 }; 664 665 enum rtw_lps_mode { 666 RTW_MODE_ACTIVE = 0, 667 RTW_MODE_LPS = 1, 668 RTW_MODE_WMM_PS = 2, 669 }; 670 671 enum rtw_lps_deep_mode { 672 LPS_DEEP_MODE_NONE = 0, 673 LPS_DEEP_MODE_LCLK = 1, 674 LPS_DEEP_MODE_PG = 2, 675 }; 676 677 enum rtw_pwr_state { 678 RTW_RF_OFF = 0x0, 679 RTW_RF_ON = 0x4, 680 RTW_ALL_ON = 0xc, 681 }; 682 683 struct rtw_lps_conf { 684 enum rtw_lps_mode mode; 685 enum rtw_lps_deep_mode deep_mode; 686 enum rtw_lps_deep_mode wow_deep_mode; 687 enum rtw_pwr_state state; 688 u8 awake_interval; 689 u8 rlbm; 690 u8 smart_ps; 691 u8 port_id; 692 bool sec_cam_backup; 693 bool pattern_cam_backup; 694 }; 695 696 enum rtw_hw_key_type { 697 RTW_CAM_NONE = 0, 698 RTW_CAM_WEP40 = 1, 699 RTW_CAM_TKIP = 2, 700 RTW_CAM_AES = 4, 701 RTW_CAM_WEP104 = 5, 702 }; 703 704 struct rtw_cam_entry { 705 bool valid; 706 bool group; 707 u8 addr[ETH_ALEN]; 708 u8 hw_key_type; 709 struct ieee80211_key_conf *key; 710 }; 711 712 struct rtw_sec_desc { 713 /* search strategy */ 714 bool default_key_search; 715 716 u32 total_cam_num; 717 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 718 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 719 }; 720 721 struct rtw_tx_report { 722 /* protect the tx report queue */ 723 spinlock_t q_lock; 724 struct sk_buff_head queue; 725 atomic_t sn; 726 struct timer_list purge_timer; 727 }; 728 729 struct rtw_ra_report { 730 struct rate_info txrate; 731 u32 bit_rate; 732 u8 desc_rate; 733 }; 734 735 struct rtw_txq { 736 struct list_head list; 737 738 unsigned long flags; 739 unsigned long last_push; 740 }; 741 742 #define RTW_BC_MC_MACID 1 743 DECLARE_EWMA(rssi, 10, 16); 744 745 struct rtw_sta_info { 746 struct ieee80211_sta *sta; 747 struct ieee80211_vif *vif; 748 749 struct ewma_rssi avg_rssi; 750 u8 rssi_level; 751 752 u8 mac_id; 753 u8 rate_id; 754 enum rtw_bandwidth bw_mode; 755 enum rtw_rf_type rf_type; 756 enum rtw_wireless_set wireless_set; 757 u8 stbc_en:2; 758 u8 ldpc_en:2; 759 bool sgi_enable; 760 bool vht_enable; 761 u8 init_ra_lv; 762 u64 ra_mask; 763 764 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 765 766 struct rtw_ra_report ra_report; 767 768 bool use_cfg_mask; 769 struct cfg80211_bitrate_mask *mask; 770 }; 771 772 enum rtw_bfee_role { 773 RTW_BFEE_NONE, 774 RTW_BFEE_SU, 775 RTW_BFEE_MU 776 }; 777 778 struct rtw_bfee { 779 enum rtw_bfee_role role; 780 781 u16 p_aid; 782 u8 g_id; 783 u8 mac_addr[ETH_ALEN]; 784 u8 sound_dim; 785 786 /* SU-MIMO */ 787 u8 su_reg_index; 788 789 /* MU-MIMO */ 790 u16 aid; 791 }; 792 793 struct rtw_bf_info { 794 u8 bfer_mu_cnt; 795 u8 bfer_su_cnt; 796 DECLARE_BITMAP(bfer_su_reg_maping, 2); 797 u8 cur_csi_rpt_rate; 798 }; 799 800 struct rtw_vif { 801 enum rtw_net_type net_type; 802 u16 aid; 803 u8 mac_addr[ETH_ALEN]; 804 u8 bssid[ETH_ALEN]; 805 u8 port; 806 u8 bcn_ctrl; 807 struct list_head rsvd_page_list; 808 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 809 const struct rtw_vif_port *conf; 810 struct cfg80211_scan_request *scan_req; 811 struct ieee80211_scan_ies *scan_ies; 812 813 struct rtw_traffic_stats stats; 814 815 struct rtw_bfee bfee; 816 }; 817 818 struct rtw_regulatory { 819 char alpha2[2]; 820 u8 txpwr_regd_2g; 821 u8 txpwr_regd_5g; 822 }; 823 824 enum rtw_regd_state { 825 RTW_REGD_STATE_WORLDWIDE, 826 RTW_REGD_STATE_PROGRAMMED, 827 RTW_REGD_STATE_SETTING, 828 829 RTW_REGD_STATE_NR, 830 }; 831 832 struct rtw_regd { 833 enum rtw_regd_state state; 834 const struct rtw_regulatory *regulatory; 835 enum nl80211_dfs_regions dfs_region; 836 }; 837 838 struct rtw_chip_ops { 839 int (*mac_init)(struct rtw_dev *rtwdev); 840 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 841 void (*shutdown)(struct rtw_dev *rtwdev); 842 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 843 void (*phy_set_param)(struct rtw_dev *rtwdev); 844 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 845 u8 bandwidth, u8 primary_chan_idx); 846 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 847 struct rtw_rx_pkt_stat *pkt_stat, 848 struct ieee80211_rx_status *rx_status); 849 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 850 u32 addr, u32 mask); 851 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 852 u32 addr, u32 mask, u32 data); 853 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 854 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 855 u32 size); 856 int (*set_antenna)(struct rtw_dev *rtwdev, 857 u32 antenna_tx, 858 u32 antenna_rx); 859 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 860 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 861 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 862 void (*phy_calibration)(struct rtw_dev *rtwdev); 863 void (*dpk_track)(struct rtw_dev *rtwdev); 864 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 865 void (*pwr_track)(struct rtw_dev *rtwdev); 866 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 867 struct rtw_bfee *bfee, bool enable); 868 void (*set_gid_table)(struct rtw_dev *rtwdev, 869 struct ieee80211_vif *vif, 870 struct ieee80211_bss_conf *conf); 871 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 872 u8 fixrate_en, u8 *new_rate); 873 void (*adaptivity_init)(struct rtw_dev *rtwdev); 874 void (*adaptivity)(struct rtw_dev *rtwdev); 875 void (*cfo_init)(struct rtw_dev *rtwdev); 876 void (*cfo_track)(struct rtw_dev *rtwdev); 877 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 878 enum rtw_bb_path tx_path_1ss, 879 enum rtw_bb_path tx_path_cck, 880 bool is_tx2_path); 881 void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path, 882 u8 rx_path, bool is_tx2_path); 883 /* for USB/SDIO only */ 884 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, 885 struct rtw_tx_pkt_info *pkt_info, 886 u8 *txdesc); 887 888 /* for coex */ 889 void (*coex_set_init)(struct rtw_dev *rtwdev); 890 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 891 u8 ctrl_type, u8 pos_type); 892 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 893 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 894 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 895 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 896 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 897 }; 898 899 #define RTW_PWR_POLLING_CNT 20000 900 901 #define RTW_PWR_CMD_READ 0x00 902 #define RTW_PWR_CMD_WRITE 0x01 903 #define RTW_PWR_CMD_POLLING 0x02 904 #define RTW_PWR_CMD_DELAY 0x03 905 #define RTW_PWR_CMD_END 0x04 906 907 /* define the base address of each block */ 908 #define RTW_PWR_ADDR_MAC 0x00 909 #define RTW_PWR_ADDR_USB 0x01 910 #define RTW_PWR_ADDR_PCIE 0x02 911 #define RTW_PWR_ADDR_SDIO 0x03 912 913 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 914 #define RTW_PWR_INTF_USB_MSK BIT(1) 915 #define RTW_PWR_INTF_PCI_MSK BIT(2) 916 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 917 918 #define RTW_PWR_CUT_TEST_MSK BIT(0) 919 #define RTW_PWR_CUT_A_MSK BIT(1) 920 #define RTW_PWR_CUT_B_MSK BIT(2) 921 #define RTW_PWR_CUT_C_MSK BIT(3) 922 #define RTW_PWR_CUT_D_MSK BIT(4) 923 #define RTW_PWR_CUT_E_MSK BIT(5) 924 #define RTW_PWR_CUT_F_MSK BIT(6) 925 #define RTW_PWR_CUT_G_MSK BIT(7) 926 #define RTW_PWR_CUT_ALL_MSK 0xFF 927 928 enum rtw_pwr_seq_cmd_delay_unit { 929 RTW_PWR_DELAY_US, 930 RTW_PWR_DELAY_MS, 931 }; 932 933 struct rtw_pwr_seq_cmd { 934 u16 offset; 935 u8 cut_mask; 936 u8 intf_mask; 937 u8 base:4; 938 u8 cmd:4; 939 u8 mask; 940 u8 value; 941 }; 942 943 enum rtw_chip_ver { 944 RTW_CHIP_VER_CUT_A = 0x00, 945 RTW_CHIP_VER_CUT_B = 0x01, 946 RTW_CHIP_VER_CUT_C = 0x02, 947 RTW_CHIP_VER_CUT_D = 0x03, 948 RTW_CHIP_VER_CUT_E = 0x04, 949 RTW_CHIP_VER_CUT_F = 0x05, 950 RTW_CHIP_VER_CUT_G = 0x06, 951 }; 952 953 #define RTW_INTF_PHY_PLATFORM_ALL 0 954 955 enum rtw_intf_phy_cut { 956 RTW_INTF_PHY_CUT_A = BIT(0), 957 RTW_INTF_PHY_CUT_B = BIT(1), 958 RTW_INTF_PHY_CUT_C = BIT(2), 959 RTW_INTF_PHY_CUT_D = BIT(3), 960 RTW_INTF_PHY_CUT_E = BIT(4), 961 RTW_INTF_PHY_CUT_F = BIT(5), 962 RTW_INTF_PHY_CUT_G = BIT(6), 963 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 964 }; 965 966 enum rtw_ip_sel { 967 RTW_IP_SEL_PHY = 0, 968 RTW_IP_SEL_MAC = 1, 969 RTW_IP_SEL_DBI = 2, 970 971 RTW_IP_SEL_UNDEF = 0xFFFF 972 }; 973 974 enum rtw_pq_map_id { 975 RTW_PQ_MAP_VO = 0x0, 976 RTW_PQ_MAP_VI = 0x1, 977 RTW_PQ_MAP_BE = 0x2, 978 RTW_PQ_MAP_BK = 0x3, 979 RTW_PQ_MAP_MG = 0x4, 980 RTW_PQ_MAP_HI = 0x5, 981 RTW_PQ_MAP_NUM = 0x6, 982 983 RTW_PQ_MAP_UNDEF, 984 }; 985 986 enum rtw_dma_mapping { 987 RTW_DMA_MAPPING_EXTRA = 0, 988 RTW_DMA_MAPPING_LOW = 1, 989 RTW_DMA_MAPPING_NORMAL = 2, 990 RTW_DMA_MAPPING_HIGH = 3, 991 992 RTW_DMA_MAPPING_MAX, 993 RTW_DMA_MAPPING_UNDEF, 994 }; 995 996 struct rtw_rqpn { 997 enum rtw_dma_mapping dma_map_vo; 998 enum rtw_dma_mapping dma_map_vi; 999 enum rtw_dma_mapping dma_map_be; 1000 enum rtw_dma_mapping dma_map_bk; 1001 enum rtw_dma_mapping dma_map_mg; 1002 enum rtw_dma_mapping dma_map_hi; 1003 }; 1004 1005 struct rtw_prioq_addr { 1006 u32 rsvd; 1007 u32 avail; 1008 }; 1009 1010 struct rtw_prioq_addrs { 1011 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1012 bool wsize; 1013 }; 1014 1015 struct rtw_page_table { 1016 u16 hq_num; 1017 u16 nq_num; 1018 u16 lq_num; 1019 u16 exq_num; 1020 u16 gapq_num; 1021 }; 1022 1023 struct rtw_intf_phy_para { 1024 u16 offset; 1025 u16 value; 1026 u16 ip_sel; 1027 u16 cut_mask; 1028 u16 platform; 1029 }; 1030 1031 struct rtw_wow_pattern { 1032 u16 crc; 1033 u8 type; 1034 u8 valid; 1035 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1036 }; 1037 1038 struct rtw_pno_request { 1039 bool inited; 1040 u32 match_set_cnt; 1041 struct cfg80211_match_set *match_sets; 1042 u8 channel_cnt; 1043 struct ieee80211_channel *channels; 1044 struct cfg80211_sched_scan_plan scan_plan; 1045 }; 1046 1047 struct rtw_wow_param { 1048 struct ieee80211_vif *wow_vif; 1049 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1050 u8 txpause; 1051 u8 pattern_cnt; 1052 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1053 1054 bool ips_enabled; 1055 struct rtw_pno_request pno_req; 1056 }; 1057 1058 struct rtw_intf_phy_para_table { 1059 const struct rtw_intf_phy_para *usb2_para; 1060 const struct rtw_intf_phy_para *usb3_para; 1061 const struct rtw_intf_phy_para *gen1_para; 1062 const struct rtw_intf_phy_para *gen2_para; 1063 u8 n_usb2_para; 1064 u8 n_usb3_para; 1065 u8 n_gen1_para; 1066 u8 n_gen2_para; 1067 }; 1068 1069 struct rtw_table { 1070 const void *data; 1071 const u32 size; 1072 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1073 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1074 u32 addr, u32 data); 1075 enum rtw_rf_path rf_path; 1076 }; 1077 1078 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1079 const struct rtw_table *tbl) 1080 { 1081 (*tbl->parse)(rtwdev, tbl); 1082 } 1083 1084 enum rtw_rfe_fem { 1085 RTW_RFE_IFEM, 1086 RTW_RFE_EFEM, 1087 RTW_RFE_IFEM2G_EFEM5G, 1088 RTW_RFE_NUM, 1089 }; 1090 1091 struct rtw_rfe_def { 1092 const struct rtw_table *phy_pg_tbl; 1093 const struct rtw_table *txpwr_lmt_tbl; 1094 const struct rtw_table *agc_btg_tbl; 1095 }; 1096 1097 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1098 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1099 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1100 } 1101 1102 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1103 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1104 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1105 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1106 } 1107 1108 #define RTW_PWR_TRK_5G_1 0 1109 #define RTW_PWR_TRK_5G_2 1 1110 #define RTW_PWR_TRK_5G_3 2 1111 #define RTW_PWR_TRK_5G_NUM 3 1112 1113 #define RTW_PWR_TRK_TBL_SZ 30 1114 1115 /* This table stores the values of TX power that will be adjusted by power 1116 * tracking. 1117 * 1118 * For 5G bands, there are 3 different settings. 1119 * For 2G there are cck rate and ofdm rate with different settings. 1120 */ 1121 struct rtw_pwr_track_tbl { 1122 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1123 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1124 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1125 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1126 const u8 *pwrtrk_2gb_n; 1127 const u8 *pwrtrk_2gb_p; 1128 const u8 *pwrtrk_2ga_n; 1129 const u8 *pwrtrk_2ga_p; 1130 const u8 *pwrtrk_2g_cckb_n; 1131 const u8 *pwrtrk_2g_cckb_p; 1132 const u8 *pwrtrk_2g_ccka_n; 1133 const u8 *pwrtrk_2g_ccka_p; 1134 const s8 *pwrtrk_xtal_n; 1135 const s8 *pwrtrk_xtal_p; 1136 }; 1137 1138 enum rtw_wlan_cpu { 1139 RTW_WCPU_11AC, 1140 RTW_WCPU_11N, 1141 }; 1142 1143 enum rtw_fw_fifo_sel { 1144 RTW_FW_FIFO_SEL_TX, 1145 RTW_FW_FIFO_SEL_RX, 1146 RTW_FW_FIFO_SEL_RSVD_PAGE, 1147 RTW_FW_FIFO_SEL_REPORT, 1148 RTW_FW_FIFO_SEL_LLT, 1149 RTW_FW_FIFO_SEL_RXBUF_FW, 1150 1151 RTW_FW_FIFO_MAX, 1152 }; 1153 1154 enum rtw_fwcd_item { 1155 RTW_FWCD_TLV, 1156 RTW_FWCD_REG, 1157 RTW_FWCD_ROM, 1158 RTW_FWCD_IMEM, 1159 RTW_FWCD_DMEM, 1160 RTW_FWCD_EMEM, 1161 }; 1162 1163 /* hardware configuration for each IC */ 1164 struct rtw_chip_info { 1165 struct rtw_chip_ops *ops; 1166 u8 id; 1167 1168 const char *fw_name; 1169 enum rtw_wlan_cpu wlan_cpu; 1170 u8 tx_pkt_desc_sz; 1171 u8 tx_buf_desc_sz; 1172 u8 rx_pkt_desc_sz; 1173 u8 rx_buf_desc_sz; 1174 u32 phy_efuse_size; 1175 u32 log_efuse_size; 1176 u32 ptct_efuse_size; 1177 u32 txff_size; 1178 u32 rxff_size; 1179 u32 fw_rxff_size; 1180 u16 rsvd_drv_pg_num; 1181 u8 band; 1182 u8 page_size; 1183 u8 csi_buf_pg_num; 1184 u8 dig_max; 1185 u8 dig_min; 1186 u8 txgi_factor; 1187 bool is_pwr_by_rate_dec; 1188 bool rx_ldpc; 1189 bool tx_stbc; 1190 u8 max_power_index; 1191 u8 ampdu_density; 1192 1193 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1194 const struct rtw_fwcd_segs *fwcd_segs; 1195 1196 u8 default_1ss_tx_path; 1197 1198 bool path_div_supported; 1199 bool ht_supported; 1200 bool vht_supported; 1201 u8 lps_deep_mode_supported; 1202 1203 /* init values */ 1204 u8 sys_func_en; 1205 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1206 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1207 const struct rtw_rqpn *rqpn_table; 1208 const struct rtw_prioq_addrs *prioq_addrs; 1209 const struct rtw_page_table *page_table; 1210 const struct rtw_intf_phy_para_table *intf_table; 1211 1212 const struct rtw_hw_reg *dig; 1213 const struct rtw_hw_reg *dig_cck; 1214 u32 rf_base_addr[2]; 1215 u32 rf_sipi_addr[2]; 1216 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1217 u8 fix_rf_phy_num; 1218 const struct rtw_ltecoex_addr *ltecoex_addr; 1219 1220 const struct rtw_table *mac_tbl; 1221 const struct rtw_table *agc_tbl; 1222 const struct rtw_table *bb_tbl; 1223 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1224 const struct rtw_table *rfk_init_tbl; 1225 1226 const struct rtw_rfe_def *rfe_defs; 1227 u32 rfe_defs_size; 1228 1229 bool en_dis_dpd; 1230 u16 dpd_ratemask; 1231 u8 iqk_threshold; 1232 u8 lck_threshold; 1233 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1234 1235 u8 bfer_su_max_num; 1236 u8 bfer_mu_max_num; 1237 1238 struct rtw_hw_reg_offset *edcca_th; 1239 s8 l2h_th_ini_cs; 1240 s8 l2h_th_ini_ad; 1241 1242 const char *wow_fw_name; 1243 const struct wiphy_wowlan_support *wowlan_stub; 1244 const u8 max_sched_scan_ssids; 1245 const u16 max_scan_ie_len; 1246 1247 /* coex paras */ 1248 u32 coex_para_ver; 1249 u8 bt_desired_ver; 1250 bool scbd_support; 1251 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1252 bool ble_hid_profile_support; 1253 bool wl_mimo_ps_support; 1254 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1255 u8 bt_rssi_type; 1256 u8 ant_isolation; 1257 u8 rssi_tolerance; 1258 u8 table_sant_num; 1259 u8 table_nsant_num; 1260 u8 tdma_sant_num; 1261 u8 tdma_nsant_num; 1262 u8 bt_afh_span_bw20; 1263 u8 bt_afh_span_bw40; 1264 u8 afh_5g_num; 1265 u8 wl_rf_para_num; 1266 u8 coex_info_hw_regs_num; 1267 const u8 *bt_rssi_step; 1268 const u8 *wl_rssi_step; 1269 const struct coex_table_para *table_nsant; 1270 const struct coex_table_para *table_sant; 1271 const struct coex_tdma_para *tdma_sant; 1272 const struct coex_tdma_para *tdma_nsant; 1273 const struct coex_rf_para *wl_rf_para_tx; 1274 const struct coex_rf_para *wl_rf_para_rx; 1275 const struct coex_5g_afh_map *afh_5g; 1276 const struct rtw_hw_reg *btg_reg; 1277 const struct rtw_reg_domain *coex_info_hw_regs; 1278 u32 wl_fw_desired_ver; 1279 }; 1280 1281 enum rtw_coex_bt_state_cnt { 1282 COEX_CNT_BT_RETRY, 1283 COEX_CNT_BT_REINIT, 1284 COEX_CNT_BT_REENABLE, 1285 COEX_CNT_BT_POPEVENT, 1286 COEX_CNT_BT_SETUPLINK, 1287 COEX_CNT_BT_IGNWLANACT, 1288 COEX_CNT_BT_INQ, 1289 COEX_CNT_BT_PAGE, 1290 COEX_CNT_BT_ROLESWITCH, 1291 COEX_CNT_BT_AFHUPDATE, 1292 COEX_CNT_BT_INFOUPDATE, 1293 COEX_CNT_BT_IQK, 1294 COEX_CNT_BT_IQKFAIL, 1295 1296 COEX_CNT_BT_MAX 1297 }; 1298 1299 enum rtw_coex_wl_state_cnt { 1300 COEX_CNT_WL_SCANAP, 1301 COEX_CNT_WL_CONNPKT, 1302 COEX_CNT_WL_COEXRUN, 1303 COEX_CNT_WL_NOISY0, 1304 COEX_CNT_WL_NOISY1, 1305 COEX_CNT_WL_NOISY2, 1306 COEX_CNT_WL_5MS_NOEXTEND, 1307 COEX_CNT_WL_FW_NOTIFY, 1308 1309 COEX_CNT_WL_MAX 1310 }; 1311 1312 struct rtw_coex_rfe { 1313 bool ant_switch_exist; 1314 bool ant_switch_diversity; 1315 bool ant_switch_with_bt; 1316 u8 rfe_module_type; 1317 u8 ant_switch_polarity; 1318 1319 /* true if WLG at BTG, else at WLAG */ 1320 bool wlg_at_btg; 1321 }; 1322 1323 #define COEX_WL_TDMA_PARA_LENGTH 5 1324 1325 struct rtw_coex_dm { 1326 bool cur_ps_tdma_on; 1327 bool cur_wl_rx_low_gain_en; 1328 bool ignore_wl_act; 1329 1330 u8 reason; 1331 u8 bt_rssi_state[4]; 1332 u8 wl_rssi_state[4]; 1333 u8 wl_ch_info[3]; 1334 u8 cur_ps_tdma; 1335 u8 cur_table; 1336 u8 ps_tdma_para[5]; 1337 u8 cur_bt_pwr_lvl; 1338 u8 cur_bt_lna_lvl; 1339 u8 cur_wl_pwr_lvl; 1340 u8 bt_status; 1341 u32 cur_ant_pos_type; 1342 u32 cur_switch_status; 1343 u32 setting_tdma; 1344 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1345 }; 1346 1347 #define COEX_BTINFO_SRC_WL_FW 0x0 1348 #define COEX_BTINFO_SRC_BT_RSP 0x1 1349 #define COEX_BTINFO_SRC_BT_ACT 0x2 1350 #define COEX_BTINFO_SRC_BT_IQK 0x3 1351 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1352 #define COEX_BTINFO_SRC_H2C60 0x5 1353 #define COEX_BTINFO_SRC_MAX 0x6 1354 1355 #define COEX_INFO_FTP BIT(7) 1356 #define COEX_INFO_A2DP BIT(6) 1357 #define COEX_INFO_HID BIT(5) 1358 #define COEX_INFO_SCO_BUSY BIT(4) 1359 #define COEX_INFO_ACL_BUSY BIT(3) 1360 #define COEX_INFO_INQ_PAGE BIT(2) 1361 #define COEX_INFO_SCO_ESCO BIT(1) 1362 #define COEX_INFO_CONNECTION BIT(0) 1363 #define COEX_BTINFO_LENGTH_MAX 10 1364 #define COEX_BTINFO_LENGTH 7 1365 1366 #define COEX_BT_HIDINFO_LIST 0x0 1367 #define COEX_BT_HIDINFO_A 0x1 1368 #define COEX_BT_HIDINFO_NAME 3 1369 1370 #define COEX_BT_HIDINFO_LENGTH 6 1371 #define COEX_BT_HIDINFO_HANDLE_NUM 4 1372 #define COEX_BT_HIDINFO_C2H_HANDLE 0 1373 #define COEX_BT_HIDINFO_C2H_VENDOR 1 1374 #define COEX_BT_BLE_HANDLE_THRS 0x10 1375 #define COEX_BT_HIDINFO_NOTCON 0xff 1376 1377 struct rtw_coex_hid { 1378 u8 hid_handle; 1379 u8 hid_vendor; 1380 u8 hid_name[COEX_BT_HIDINFO_NAME]; 1381 bool hid_info_completed; 1382 bool is_game_hid; 1383 }; 1384 1385 struct rtw_coex_hid_handle_list { 1386 u8 cmd_id; 1387 u8 len; 1388 u8 subid; 1389 u8 handle_cnt; 1390 u8 handle[COEX_BT_HIDINFO_HANDLE_NUM]; 1391 } __packed; 1392 1393 struct rtw_coex_hid_info_a { 1394 u8 cmd_id; 1395 u8 len; 1396 u8 subid; 1397 u8 handle; 1398 u8 vendor; 1399 u8 name[COEX_BT_HIDINFO_NAME]; 1400 } __packed; 1401 1402 struct rtw_coex_stat { 1403 bool bt_disabled; 1404 bool bt_disabled_pre; 1405 bool bt_link_exist; 1406 bool bt_whck_test; 1407 bool bt_inq_page; 1408 bool bt_inq_remain; 1409 bool bt_inq; 1410 bool bt_page; 1411 bool bt_ble_voice; 1412 bool bt_ble_exist; 1413 bool bt_hfp_exist; 1414 bool bt_a2dp_exist; 1415 bool bt_hid_exist; 1416 bool bt_pan_exist; /* PAN or OPP */ 1417 bool bt_opp_exist; /* OPP only */ 1418 bool bt_acl_busy; 1419 bool bt_fix_2M; 1420 bool bt_setup_link; 1421 bool bt_multi_link; 1422 bool bt_multi_link_pre; 1423 bool bt_multi_link_remain; 1424 bool bt_a2dp_sink; 1425 bool bt_a2dp_active; 1426 bool bt_reenable; 1427 bool bt_ble_scan_en; 1428 bool bt_init_scan; 1429 bool bt_slave; 1430 bool bt_418_hid_exist; 1431 bool bt_ble_hid_exist; 1432 bool bt_game_hid_exist; 1433 bool bt_hid_handle_cnt; 1434 bool bt_mailbox_reply; 1435 1436 bool wl_under_lps; 1437 bool wl_under_ips; 1438 bool wl_hi_pri_task1; 1439 bool wl_hi_pri_task2; 1440 bool wl_force_lps_ctrl; 1441 bool wl_gl_busy; 1442 bool wl_linkscan_proc; 1443 bool wl_ps_state_fail; 1444 bool wl_tx_limit_en; 1445 bool wl_ampdu_limit_en; 1446 bool wl_connected; 1447 bool wl_slot_extend; 1448 bool wl_cck_lock; 1449 bool wl_cck_lock_pre; 1450 bool wl_cck_lock_ever; 1451 bool wl_connecting; 1452 bool wl_slot_toggle; 1453 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1454 bool wl_mimo_ps; 1455 1456 u32 bt_supported_version; 1457 u32 bt_supported_feature; 1458 u32 hi_pri_tx; 1459 u32 hi_pri_rx; 1460 u32 lo_pri_tx; 1461 u32 lo_pri_rx; 1462 u32 patch_ver; 1463 u16 bt_reg_vendor_ae; 1464 u16 bt_reg_vendor_ac; 1465 s8 bt_rssi; 1466 u8 kt_ver; 1467 u8 gnt_workaround_state; 1468 u8 tdma_timer_base; 1469 u8 bt_profile_num; 1470 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1471 u8 bt_info_lb2; 1472 u8 bt_info_lb3; 1473 u8 bt_info_hb0; 1474 u8 bt_info_hb1; 1475 u8 bt_info_hb2; 1476 u8 bt_info_hb3; 1477 u8 bt_ble_scan_type; 1478 u8 bt_hid_pair_num; 1479 u8 bt_hid_slot; 1480 u8 bt_a2dp_bitpool; 1481 u8 bt_iqk_state; 1482 1483 u16 wl_beacon_interval; 1484 u8 wl_noisy_level; 1485 u8 wl_fw_dbg_info[10]; 1486 u8 wl_fw_dbg_info_pre[10]; 1487 u8 wl_rx_rate; 1488 u8 wl_tx_rate; 1489 u8 wl_rts_rx_rate; 1490 u8 wl_coex_mode; 1491 u8 wl_iot_peer; 1492 u8 ampdu_max_time; 1493 u8 wl_tput_dir; 1494 1495 u8 wl_toggle_para[6]; 1496 u8 wl_toggle_interval; 1497 1498 u16 score_board; 1499 u16 retry_limit; 1500 1501 /* counters to record bt states */ 1502 u32 cnt_bt[COEX_CNT_BT_MAX]; 1503 1504 /* counters to record wifi states */ 1505 u32 cnt_wl[COEX_CNT_WL_MAX]; 1506 1507 /* counters to record bt c2h data */ 1508 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1509 1510 u32 darfrc; 1511 u32 darfrch; 1512 1513 struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM]; 1514 struct rtw_coex_hid_handle_list hid_handle_list; 1515 }; 1516 1517 struct rtw_coex { 1518 struct sk_buff_head queue; 1519 wait_queue_head_t wait; 1520 1521 bool under_5g; 1522 bool stop_dm; 1523 bool freeze; 1524 bool freerun; 1525 bool wl_rf_off; 1526 bool manual_control; 1527 1528 struct rtw_coex_stat stat; 1529 struct rtw_coex_dm dm; 1530 struct rtw_coex_rfe rfe; 1531 1532 struct delayed_work bt_relink_work; 1533 struct delayed_work bt_reenable_work; 1534 struct delayed_work defreeze_work; 1535 struct delayed_work wl_remain_work; 1536 struct delayed_work bt_remain_work; 1537 struct delayed_work wl_connecting_work; 1538 struct delayed_work bt_multi_link_remain_work; 1539 struct delayed_work wl_ccklock_work; 1540 1541 }; 1542 1543 #define DPK_RF_REG_NUM 7 1544 #define DPK_RF_PATH_NUM 2 1545 #define DPK_BB_REG_NUM 18 1546 #define DPK_CHANNEL_WIDTH_80 1 1547 1548 DECLARE_EWMA(thermal, 10, 4); 1549 1550 struct rtw_dpk_info { 1551 bool is_dpk_pwr_on; 1552 bool is_reload; 1553 1554 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1555 1556 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1557 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1558 1559 u32 gnt_control; 1560 u32 gnt_value; 1561 1562 u8 result[RTW_RF_PATH_MAX]; 1563 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1564 u32 coef[RTW_RF_PATH_MAX][20]; 1565 u16 dpk_gs[RTW_RF_PATH_MAX]; 1566 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1567 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1568 1569 u8 dpk_band; 1570 u8 dpk_ch; 1571 u8 dpk_bw; 1572 }; 1573 1574 struct rtw_phy_cck_pd_reg { 1575 u32 reg_pd; 1576 u32 mask_pd; 1577 u32 reg_cs; 1578 u32 mask_cs; 1579 }; 1580 1581 #define DACK_MSBK_BACKUP_NUM 0xf 1582 #define DACK_DCK_BACKUP_NUM 0x2 1583 1584 struct rtw_swing_table { 1585 const u8 *p[RTW_RF_PATH_MAX]; 1586 const u8 *n[RTW_RF_PATH_MAX]; 1587 }; 1588 1589 struct rtw_pkt_count { 1590 u16 num_bcn_pkt; 1591 u16 num_qry_pkt[DESC_RATE_MAX]; 1592 }; 1593 1594 DECLARE_EWMA(evm, 10, 4); 1595 DECLARE_EWMA(snr, 10, 4); 1596 1597 struct rtw_iqk_info { 1598 bool done; 1599 struct { 1600 u32 s1_x; 1601 u32 s1_y; 1602 u32 s0_x; 1603 u32 s0_y; 1604 } result; 1605 }; 1606 1607 enum rtw_rf_band { 1608 RF_BAND_2G_CCK, 1609 RF_BAND_2G_OFDM, 1610 RF_BAND_5G_L, 1611 RF_BAND_5G_M, 1612 RF_BAND_5G_H, 1613 RF_BAND_MAX 1614 }; 1615 1616 #define RF_GAIN_NUM 11 1617 #define RF_HW_OFFSET_NUM 10 1618 1619 struct rtw_gapk_info { 1620 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1621 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1622 bool txgapk_bp_done; 1623 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1624 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1625 u8 read_txgain; 1626 u8 channel; 1627 }; 1628 1629 #define EDCCA_TH_L2H_IDX 0 1630 #define EDCCA_TH_H2L_IDX 1 1631 #define EDCCA_TH_L2H_LB 48 1632 #define EDCCA_ADC_BACKOFF 12 1633 #define EDCCA_IGI_BASE 50 1634 #define EDCCA_IGI_L2H_DIFF 8 1635 #define EDCCA_L2H_H2L_DIFF 7 1636 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1637 1638 enum rtw_edcca_mode { 1639 RTW_EDCCA_NORMAL = 0, 1640 RTW_EDCCA_ADAPTIVITY = 1, 1641 }; 1642 1643 struct rtw_cfo_track { 1644 bool is_adjust; 1645 u8 crystal_cap; 1646 s32 cfo_tail[RTW_RF_PATH_MAX]; 1647 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1648 u32 packet_count; 1649 u32 packet_count_pre; 1650 }; 1651 1652 #define RRSR_INIT_2G 0x15f 1653 #define RRSR_INIT_5G 0x150 1654 1655 enum rtw_dm_cap { 1656 RTW_DM_CAP_NA, 1657 RTW_DM_CAP_TXGAPK, 1658 RTW_DM_CAP_NUM 1659 }; 1660 1661 struct rtw_dm_info { 1662 u32 cck_fa_cnt; 1663 u32 ofdm_fa_cnt; 1664 u32 total_fa_cnt; 1665 u32 cck_cca_cnt; 1666 u32 ofdm_cca_cnt; 1667 u32 total_cca_cnt; 1668 1669 u32 cck_ok_cnt; 1670 u32 cck_err_cnt; 1671 u32 ofdm_ok_cnt; 1672 u32 ofdm_err_cnt; 1673 u32 ht_ok_cnt; 1674 u32 ht_err_cnt; 1675 u32 vht_ok_cnt; 1676 u32 vht_err_cnt; 1677 1678 u8 min_rssi; 1679 u8 pre_min_rssi; 1680 u16 fa_history[4]; 1681 u8 igi_history[4]; 1682 u8 igi_bitmap; 1683 bool damping; 1684 u8 damping_cnt; 1685 u8 damping_rssi; 1686 1687 u8 cck_gi_u_bnd; 1688 u8 cck_gi_l_bnd; 1689 1690 u8 fix_rate; 1691 u8 tx_rate; 1692 u32 rrsr_val_init; 1693 u32 rrsr_mask_min; 1694 u8 thermal_avg[RTW_RF_PATH_MAX]; 1695 u8 thermal_meter_k; 1696 u8 thermal_meter_lck; 1697 s8 delta_power_index[RTW_RF_PATH_MAX]; 1698 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1699 u8 default_ofdm_index; 1700 bool pwr_trk_triggered; 1701 bool pwr_trk_init_trigger; 1702 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1703 s8 txagc_remnant_cck; 1704 s8 txagc_remnant_ofdm; 1705 1706 /* backup dack results for each path and I/Q */ 1707 u32 dack_adck[RTW_RF_PATH_MAX]; 1708 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1709 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1710 1711 struct rtw_dpk_info dpk_info; 1712 struct rtw_cfo_track cfo_track; 1713 1714 /* [bandwidth 0:20M/1:40M][number of path] */ 1715 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1716 u32 cck_fa_avg; 1717 u8 cck_pd_default; 1718 1719 /* save the last rx phy status for debug */ 1720 s8 rx_snr[RTW_RF_PATH_MAX]; 1721 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1722 s16 cfo_tail[RTW_RF_PATH_MAX]; 1723 u8 rssi[RTW_RF_PATH_MAX]; 1724 u8 curr_rx_rate; 1725 struct rtw_pkt_count cur_pkt_count; 1726 struct rtw_pkt_count last_pkt_count; 1727 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1728 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1729 1730 u32 dm_flags; /* enum rtw_dm_cap */ 1731 struct rtw_iqk_info iqk; 1732 struct rtw_gapk_info gapk; 1733 bool is_bt_iqk_timeout; 1734 1735 s8 l2h_th_ini; 1736 enum rtw_edcca_mode edcca_mode; 1737 u8 scan_density; 1738 }; 1739 1740 struct rtw_efuse { 1741 u32 size; 1742 u32 physical_size; 1743 u32 logical_size; 1744 u32 protect_size; 1745 1746 u8 addr[ETH_ALEN]; 1747 u8 channel_plan; 1748 u8 country_code[2]; 1749 u8 rf_board_option; 1750 u8 rfe_option; 1751 u8 power_track_type; 1752 u8 thermal_meter[RTW_RF_PATH_MAX]; 1753 u8 thermal_meter_k; 1754 u8 crystal_cap; 1755 u8 ant_div_cfg; 1756 u8 ant_div_type; 1757 u8 regd; 1758 u8 afe; 1759 1760 u8 lna_type_2g; 1761 u8 lna_type_5g; 1762 u8 glna_type; 1763 u8 alna_type; 1764 bool ext_lna_2g; 1765 bool ext_lna_5g; 1766 u8 pa_type_2g; 1767 u8 pa_type_5g; 1768 u8 gpa_type; 1769 u8 apa_type; 1770 bool ext_pa_2g; 1771 bool ext_pa_5g; 1772 u8 tx_bb_swing_setting_2g; 1773 u8 tx_bb_swing_setting_5g; 1774 1775 bool btcoex; 1776 /* bt share antenna with wifi */ 1777 bool share_ant; 1778 u8 bt_setting; 1779 1780 struct { 1781 u8 hci; 1782 u8 bw; 1783 u8 ptcl; 1784 u8 nss; 1785 u8 ant_num; 1786 } hw_cap; 1787 1788 struct rtw_txpwr_idx txpwr_idx_table[4]; 1789 }; 1790 1791 struct rtw_phy_cond { 1792 #ifdef __LITTLE_ENDIAN 1793 u32 rfe:8; 1794 u32 intf:4; 1795 u32 pkg:4; 1796 u32 plat:4; 1797 u32 intf_rsvd:4; 1798 u32 cut:4; 1799 u32 branch:2; 1800 u32 neg:1; 1801 u32 pos:1; 1802 #else 1803 u32 pos:1; 1804 u32 neg:1; 1805 u32 branch:2; 1806 u32 cut:4; 1807 u32 intf_rsvd:4; 1808 u32 plat:4; 1809 u32 pkg:4; 1810 u32 intf:4; 1811 u32 rfe:8; 1812 #endif 1813 /* for intf:4 */ 1814 #define INTF_PCIE BIT(0) 1815 #define INTF_USB BIT(1) 1816 #define INTF_SDIO BIT(2) 1817 /* for branch:2 */ 1818 #define BRANCH_IF 0 1819 #define BRANCH_ELIF 1 1820 #define BRANCH_ELSE 2 1821 #define BRANCH_ENDIF 3 1822 }; 1823 1824 struct rtw_fifo_conf { 1825 /* tx fifo information */ 1826 u16 rsvd_boundary; 1827 u16 rsvd_pg_num; 1828 u16 rsvd_drv_pg_num; 1829 u16 txff_pg_num; 1830 u16 acq_pg_num; 1831 u16 rsvd_drv_addr; 1832 u16 rsvd_h2c_info_addr; 1833 u16 rsvd_h2c_sta_info_addr; 1834 u16 rsvd_h2cq_addr; 1835 u16 rsvd_cpu_instr_addr; 1836 u16 rsvd_fw_txbuf_addr; 1837 u16 rsvd_csibuf_addr; 1838 const struct rtw_rqpn *rqpn; 1839 }; 1840 1841 struct rtw_fwcd_desc { 1842 u32 size; 1843 u8 *next; 1844 u8 *data; 1845 }; 1846 1847 struct rtw_fwcd_segs { 1848 const u32 *segs; 1849 u8 num; 1850 }; 1851 1852 #define FW_CD_TYPE 0xffff 1853 #define FW_CD_LEN 4 1854 #define FW_CD_VAL 0xaabbccdd 1855 struct rtw_fw_state { 1856 const struct firmware *firmware; 1857 struct rtw_dev *rtwdev; 1858 struct completion completion; 1859 struct rtw_fwcd_desc fwcd_desc; 1860 u16 version; 1861 u8 sub_version; 1862 u8 sub_index; 1863 u16 h2c_version; 1864 u32 feature; 1865 u32 feature_ext; 1866 enum rtw_fw_type type; 1867 }; 1868 1869 enum rtw_sar_sources { 1870 RTW_SAR_SOURCE_NONE, 1871 RTW_SAR_SOURCE_COMMON, 1872 }; 1873 1874 enum rtw_sar_bands { 1875 RTW_SAR_BAND_0, 1876 RTW_SAR_BAND_1, 1877 /* RTW_SAR_BAND_2, not used now */ 1878 RTW_SAR_BAND_3, 1879 RTW_SAR_BAND_4, 1880 1881 RTW_SAR_BAND_NR, 1882 }; 1883 1884 /* the union is reserved for other kinds of SAR sources 1885 * which might not re-use same format with array common. 1886 */ 1887 union rtw_sar_cfg { 1888 s8 common[RTW_SAR_BAND_NR]; 1889 }; 1890 1891 struct rtw_sar { 1892 enum rtw_sar_sources src; 1893 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1894 }; 1895 1896 struct rtw_hal { 1897 u32 rcr; 1898 1899 u32 chip_version; 1900 u8 cut_version; 1901 u8 mp_chip; 1902 u8 oem_id; 1903 u8 pkg_type; 1904 struct rtw_phy_cond phy_cond; 1905 bool rfe_btg; 1906 1907 u8 ps_mode; 1908 u8 current_channel; 1909 u8 current_primary_channel_index; 1910 u8 current_band_width; 1911 u8 current_band_type; 1912 u8 primary_channel; 1913 1914 /* center channel for different available bandwidth, 1915 * val of (bw > current_band_width) is invalid 1916 */ 1917 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1918 1919 u8 sec_ch_offset; 1920 u8 rf_type; 1921 u8 rf_path_num; 1922 u8 rf_phy_num; 1923 u32 antenna_tx; 1924 u32 antenna_rx; 1925 u8 bfee_sts_cap; 1926 bool txrx_1ss; 1927 1928 /* protect tx power section */ 1929 struct mutex tx_power_mutex; 1930 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1931 [DESC_RATE_MAX]; 1932 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1933 [DESC_RATE_MAX]; 1934 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1935 [RTW_RATE_SECTION_MAX]; 1936 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1937 [RTW_RATE_SECTION_MAX]; 1938 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1939 [RTW_CHANNEL_WIDTH_MAX] 1940 [RTW_RATE_SECTION_MAX] 1941 [RTW_MAX_CHANNEL_NUM_2G]; 1942 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1943 [RTW_CHANNEL_WIDTH_MAX] 1944 [RTW_RATE_SECTION_MAX] 1945 [RTW_MAX_CHANNEL_NUM_5G]; 1946 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1947 [DESC_RATE_MAX]; 1948 1949 enum rtw_sar_bands sar_band; 1950 struct rtw_sar sar; 1951 1952 /* for 8821c set channel */ 1953 u32 ch_param[3]; 1954 }; 1955 1956 struct rtw_path_div { 1957 enum rtw_bb_path current_tx_path; 1958 u32 path_a_sum; 1959 u32 path_b_sum; 1960 u16 path_a_cnt; 1961 u16 path_b_cnt; 1962 }; 1963 1964 struct rtw_chan_info { 1965 int pri_ch_idx; 1966 int action_id; 1967 int bw; 1968 u8 extra_info; 1969 u8 channel; 1970 u16 timeout; 1971 }; 1972 1973 struct rtw_chan_list { 1974 u32 buf_size; 1975 u32 ch_num; 1976 u32 size; 1977 u16 addr; 1978 }; 1979 1980 struct rtw_hw_scan_info { 1981 struct ieee80211_vif *scanning_vif; 1982 u8 probe_pg_size; 1983 u8 op_pri_ch_idx; 1984 u8 op_pri_ch; 1985 u8 op_chan; 1986 u8 op_bw; 1987 }; 1988 1989 struct rtw_dev { 1990 struct ieee80211_hw *hw; 1991 struct device *dev; 1992 1993 struct rtw_hci hci; 1994 1995 struct rtw_hw_scan_info scan_info; 1996 const struct rtw_chip_info *chip; 1997 struct rtw_hal hal; 1998 struct rtw_fifo_conf fifo; 1999 struct rtw_fw_state fw; 2000 struct rtw_efuse efuse; 2001 struct rtw_sec_desc sec; 2002 struct rtw_traffic_stats stats; 2003 struct rtw_regd regd; 2004 struct rtw_bf_info bf_info; 2005 2006 struct rtw_dm_info dm_info; 2007 struct rtw_coex coex; 2008 2009 /* ensures exclusive access from mac80211 callbacks */ 2010 struct mutex mutex; 2011 2012 /* watch dog every 2 sec */ 2013 struct delayed_work watch_dog_work; 2014 u32 watch_dog_cnt; 2015 2016 struct list_head rsvd_page_list; 2017 2018 /* c2h cmd queue & handler work */ 2019 struct sk_buff_head c2h_queue; 2020 struct work_struct c2h_work; 2021 struct work_struct ips_work; 2022 struct work_struct fw_recovery_work; 2023 struct work_struct update_beacon_work; 2024 2025 /* used to protect txqs list */ 2026 spinlock_t txq_lock; 2027 struct list_head txqs; 2028 struct workqueue_struct *tx_wq; 2029 struct work_struct tx_work; 2030 struct work_struct ba_work; 2031 2032 struct rtw_tx_report tx_report; 2033 2034 struct { 2035 /* indicate the mail box to use with fw */ 2036 u8 last_box_num; 2037 u32 seq; 2038 } h2c; 2039 2040 /* lps power state & handler work */ 2041 struct rtw_lps_conf lps_conf; 2042 bool ps_enabled; 2043 bool beacon_loss; 2044 struct completion lps_leave_check; 2045 2046 struct dentry *debugfs; 2047 2048 u8 sta_cnt; 2049 u32 rts_threshold; 2050 2051 DECLARE_BITMAP(hw_port, RTW_PORT_NUM); 2052 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2053 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2054 2055 u8 mp_mode; 2056 struct rtw_path_div dm_path_div; 2057 2058 struct rtw_fw_state wow_fw; 2059 struct rtw_wow_param wow; 2060 2061 bool need_rfk; 2062 struct completion fw_scan_density; 2063 bool ap_active; 2064 2065 /* hci related data, must be last */ 2066 u8 priv[] __aligned(sizeof(void *)); 2067 }; 2068 2069 #include "hci.h" 2070 2071 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2072 { 2073 return !!rtwdev->sta_cnt; 2074 } 2075 2076 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2077 { 2078 void *p = rtwtxq; 2079 2080 return container_of(p, struct ieee80211_txq, drv_priv); 2081 } 2082 2083 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2084 { 2085 void *p = rtwvif; 2086 2087 return container_of(p, struct ieee80211_vif, drv_priv); 2088 } 2089 2090 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 2091 struct cfg80211_ssid *b) 2092 { 2093 if (!a || !b || a->ssid_len != b->ssid_len) 2094 return false; 2095 2096 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 2097 return false; 2098 2099 return true; 2100 } 2101 2102 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2103 { 2104 if (rtwdev->chip->ops->efuse_grant) 2105 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2106 } 2107 2108 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2109 { 2110 if (rtwdev->chip->ops->efuse_grant) 2111 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2112 } 2113 2114 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2115 { 2116 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2117 } 2118 2119 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2120 { 2121 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2122 } 2123 2124 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2125 { 2126 return rtwdev->chip->rx_ldpc; 2127 } 2128 2129 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2130 { 2131 return rtwdev->chip->tx_stbc; 2132 } 2133 2134 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2135 { 2136 clear_bit(mac_id, rtwdev->mac_id_map); 2137 } 2138 2139 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2140 { 2141 if (rtwdev->chip->ops->dump_fw_crash) 2142 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2143 2144 return 0; 2145 } 2146 2147 static inline 2148 enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band) 2149 { 2150 switch (hw_band) { 2151 default: 2152 case RTW_BAND_2G: 2153 return NL80211_BAND_2GHZ; 2154 case RTW_BAND_5G: 2155 return NL80211_BAND_5GHZ; 2156 case RTW_BAND_60G: 2157 return NL80211_BAND_60GHZ; 2158 } 2159 } 2160 2161 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2162 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period); 2163 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2164 struct rtw_channel_params *ch_param); 2165 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2166 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2167 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2168 void rtw_restore_reg(struct rtw_dev *rtwdev, 2169 struct rtw_backup_info *bckp, u32 num); 2170 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2171 void rtw_set_channel(struct rtw_dev *rtwdev); 2172 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2173 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2174 u32 config); 2175 void rtw_tx_report_purge_timer(struct timer_list *t); 2176 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 2177 bool reset_ra_mask); 2178 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2179 const u8 *mac_addr, bool hw_scan); 2180 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 2181 bool hw_scan); 2182 int rtw_core_start(struct rtw_dev *rtwdev); 2183 void rtw_core_stop(struct rtw_dev *rtwdev); 2184 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2185 int rtw_core_init(struct rtw_dev *rtwdev); 2186 void rtw_core_deinit(struct rtw_dev *rtwdev); 2187 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2188 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2189 u16 rtw_desc_to_bitrate(u8 desc_rate); 2190 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2191 struct ieee80211_bss_conf *conf); 2192 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2193 struct ieee80211_vif *vif); 2194 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2195 bool fw_exist); 2196 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2197 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2198 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2199 u32 fwcd_item); 2200 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2201 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss); 2202 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 2203 u8 primary_channel, enum rtw_supported_band band, 2204 enum rtw_bandwidth bandwidth); 2205 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2206 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev); 2207 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable); 2208 #endif 2209