1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 21 bool rtw_disable_lps_deep_mode; 22 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 23 bool rtw_bf_support = true; 24 unsigned int rtw_debug_mask; 25 EXPORT_SYMBOL(rtw_debug_mask); 26 /* EDCCA is enabled during normal behavior. For debugging purpose in 27 * a noisy environment, it can be disabled via edcca debugfs. Because 28 * all rtw88 devices will probably be affected if environment is noisy, 29 * rtw_edcca_enabled is just declared by driver instead of by device. 30 * So, turning it off will take effect for all rtw88 devices before 31 * there is a tough reason to maintain rtw_edcca_enabled by device. 32 */ 33 bool rtw_edcca_enabled = true; 34 35 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 36 module_param_named(support_bf, rtw_bf_support, bool, 0644); 37 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 38 39 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 40 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 41 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 42 43 static struct ieee80211_channel rtw_channeltable_2g[] = { 44 {.center_freq = 2412, .hw_value = 1,}, 45 {.center_freq = 2417, .hw_value = 2,}, 46 {.center_freq = 2422, .hw_value = 3,}, 47 {.center_freq = 2427, .hw_value = 4,}, 48 {.center_freq = 2432, .hw_value = 5,}, 49 {.center_freq = 2437, .hw_value = 6,}, 50 {.center_freq = 2442, .hw_value = 7,}, 51 {.center_freq = 2447, .hw_value = 8,}, 52 {.center_freq = 2452, .hw_value = 9,}, 53 {.center_freq = 2457, .hw_value = 10,}, 54 {.center_freq = 2462, .hw_value = 11,}, 55 {.center_freq = 2467, .hw_value = 12,}, 56 {.center_freq = 2472, .hw_value = 13,}, 57 {.center_freq = 2484, .hw_value = 14,}, 58 }; 59 60 static struct ieee80211_channel rtw_channeltable_5g[] = { 61 {.center_freq = 5180, .hw_value = 36,}, 62 {.center_freq = 5200, .hw_value = 40,}, 63 {.center_freq = 5220, .hw_value = 44,}, 64 {.center_freq = 5240, .hw_value = 48,}, 65 {.center_freq = 5260, .hw_value = 52,}, 66 {.center_freq = 5280, .hw_value = 56,}, 67 {.center_freq = 5300, .hw_value = 60,}, 68 {.center_freq = 5320, .hw_value = 64,}, 69 {.center_freq = 5500, .hw_value = 100,}, 70 {.center_freq = 5520, .hw_value = 104,}, 71 {.center_freq = 5540, .hw_value = 108,}, 72 {.center_freq = 5560, .hw_value = 112,}, 73 {.center_freq = 5580, .hw_value = 116,}, 74 {.center_freq = 5600, .hw_value = 120,}, 75 {.center_freq = 5620, .hw_value = 124,}, 76 {.center_freq = 5640, .hw_value = 128,}, 77 {.center_freq = 5660, .hw_value = 132,}, 78 {.center_freq = 5680, .hw_value = 136,}, 79 {.center_freq = 5700, .hw_value = 140,}, 80 {.center_freq = 5720, .hw_value = 144,}, 81 {.center_freq = 5745, .hw_value = 149,}, 82 {.center_freq = 5765, .hw_value = 153,}, 83 {.center_freq = 5785, .hw_value = 157,}, 84 {.center_freq = 5805, .hw_value = 161,}, 85 {.center_freq = 5825, .hw_value = 165, 86 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 87 }; 88 89 static struct ieee80211_rate rtw_ratetable[] = { 90 {.bitrate = 10, .hw_value = 0x00,}, 91 {.bitrate = 20, .hw_value = 0x01,}, 92 {.bitrate = 55, .hw_value = 0x02,}, 93 {.bitrate = 110, .hw_value = 0x03,}, 94 {.bitrate = 60, .hw_value = 0x04,}, 95 {.bitrate = 90, .hw_value = 0x05,}, 96 {.bitrate = 120, .hw_value = 0x06,}, 97 {.bitrate = 180, .hw_value = 0x07,}, 98 {.bitrate = 240, .hw_value = 0x08,}, 99 {.bitrate = 360, .hw_value = 0x09,}, 100 {.bitrate = 480, .hw_value = 0x0a,}, 101 {.bitrate = 540, .hw_value = 0x0b,}, 102 }; 103 104 u16 rtw_desc_to_bitrate(u8 desc_rate) 105 { 106 struct ieee80211_rate rate; 107 108 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 109 return 0; 110 111 rate = rtw_ratetable[desc_rate]; 112 113 return rate.bitrate; 114 } 115 116 static struct ieee80211_supported_band rtw_band_2ghz = { 117 .band = NL80211_BAND_2GHZ, 118 119 .channels = rtw_channeltable_2g, 120 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 121 122 .bitrates = rtw_ratetable, 123 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 124 125 .ht_cap = {0}, 126 .vht_cap = {0}, 127 }; 128 129 static struct ieee80211_supported_band rtw_band_5ghz = { 130 .band = NL80211_BAND_5GHZ, 131 132 .channels = rtw_channeltable_5g, 133 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 134 135 /* 5G has no CCK rates */ 136 .bitrates = rtw_ratetable + 4, 137 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 138 139 .ht_cap = {0}, 140 .vht_cap = {0}, 141 }; 142 143 struct rtw_watch_dog_iter_data { 144 struct rtw_dev *rtwdev; 145 struct rtw_vif *rtwvif; 146 }; 147 148 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 149 { 150 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 151 u8 fix_rate_enable = 0; 152 u8 new_csi_rate_idx; 153 154 if (rtwvif->bfee.role != RTW_BFEE_SU && 155 rtwvif->bfee.role != RTW_BFEE_MU) 156 return; 157 158 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 159 bf_info->cur_csi_rpt_rate, 160 fix_rate_enable, &new_csi_rate_idx); 161 162 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 163 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 164 } 165 166 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 167 struct ieee80211_vif *vif) 168 { 169 struct rtw_watch_dog_iter_data *iter_data = data; 170 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 171 172 if (vif->type == NL80211_IFTYPE_STATION) 173 if (vif->bss_conf.assoc) 174 iter_data->rtwvif = rtwvif; 175 176 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 177 178 rtwvif->stats.tx_unicast = 0; 179 rtwvif->stats.rx_unicast = 0; 180 rtwvif->stats.tx_cnt = 0; 181 rtwvif->stats.rx_cnt = 0; 182 } 183 184 /* process TX/RX statistics periodically for hardware, 185 * the information helps hardware to enhance performance 186 */ 187 static void rtw_watch_dog_work(struct work_struct *work) 188 { 189 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 190 watch_dog_work.work); 191 struct rtw_traffic_stats *stats = &rtwdev->stats; 192 struct rtw_watch_dog_iter_data data = {}; 193 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 194 bool ps_active; 195 196 mutex_lock(&rtwdev->mutex); 197 198 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 199 goto unlock; 200 201 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 202 RTW_WATCH_DOG_DELAY_TIME); 203 204 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 205 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 206 else 207 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 208 209 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 210 rtw_coex_wl_status_change_notify(rtwdev, 0); 211 212 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 213 stats->rx_cnt > RTW_LPS_THRESHOLD) 214 ps_active = true; 215 else 216 ps_active = false; 217 218 ewma_tp_add(&stats->tx_ewma_tp, 219 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 220 ewma_tp_add(&stats->rx_ewma_tp, 221 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 222 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 223 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 224 225 /* reset tx/rx statictics */ 226 stats->tx_unicast = 0; 227 stats->rx_unicast = 0; 228 stats->tx_cnt = 0; 229 stats->rx_cnt = 0; 230 231 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 232 goto unlock; 233 234 /* make sure BB/RF is working for dynamic mech */ 235 rtw_leave_lps(rtwdev); 236 237 rtw_phy_dynamic_mechanism(rtwdev); 238 239 data.rtwdev = rtwdev; 240 /* use atomic version to avoid taking local->iflist_mtx mutex */ 241 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 242 243 /* fw supports only one station associated to enter lps, if there are 244 * more than two stations associated to the AP, then we can not enter 245 * lps, because fw does not handle the overlapped beacon interval 246 * 247 * mac80211 should iterate vifs and determine if driver can enter 248 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 249 * get that vif and check if device is having traffic more than the 250 * threshold. 251 */ 252 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 253 !rtwdev->beacon_loss) 254 rtw_enter_lps(rtwdev, data.rtwvif->port); 255 256 rtwdev->watch_dog_cnt++; 257 258 unlock: 259 mutex_unlock(&rtwdev->mutex); 260 } 261 262 static void rtw_c2h_work(struct work_struct *work) 263 { 264 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 265 struct sk_buff *skb, *tmp; 266 267 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 268 skb_unlink(skb, &rtwdev->c2h_queue); 269 rtw_fw_c2h_cmd_handle(rtwdev, skb); 270 dev_kfree_skb_any(skb); 271 } 272 } 273 274 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 275 { 276 unsigned long mac_id; 277 278 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 279 if (mac_id < RTW_MAX_MAC_ID_NUM) 280 set_bit(mac_id, rtwdev->mac_id_map); 281 282 return mac_id; 283 } 284 285 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 286 struct ieee80211_vif *vif) 287 { 288 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 289 int i; 290 291 si->mac_id = rtw_acquire_macid(rtwdev); 292 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 293 return -ENOSPC; 294 295 si->sta = sta; 296 si->vif = vif; 297 si->init_ra_lv = 1; 298 ewma_rssi_init(&si->avg_rssi); 299 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 300 rtw_txq_init(rtwdev, sta->txq[i]); 301 302 rtw_update_sta_info(rtwdev, si); 303 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 304 305 rtwdev->sta_cnt++; 306 rtwdev->beacon_loss = false; 307 rtw_info(rtwdev, "sta %pM joined with macid %d\n", 308 sta->addr, si->mac_id); 309 310 return 0; 311 } 312 313 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 314 bool fw_exist) 315 { 316 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 317 int i; 318 319 rtw_release_macid(rtwdev, si->mac_id); 320 if (fw_exist) 321 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 322 323 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 324 rtw_txq_cleanup(rtwdev, sta->txq[i]); 325 326 kfree(si->mask); 327 328 rtwdev->sta_cnt--; 329 rtw_info(rtwdev, "sta %pM with macid %d left\n", 330 sta->addr, si->mac_id); 331 } 332 333 struct rtw_fwcd_hdr { 334 u32 item; 335 u32 size; 336 u32 padding1; 337 u32 padding2; 338 } __packed; 339 340 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 341 { 342 struct rtw_chip_info *chip = rtwdev->chip; 343 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 344 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 345 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 346 u8 i; 347 348 if (segs) { 349 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 350 351 for (i = 0; i < segs->num; i++) 352 prep_size += segs->segs[i]; 353 } 354 355 desc->data = vmalloc(prep_size); 356 if (!desc->data) 357 return -ENOMEM; 358 359 desc->size = prep_size; 360 desc->next = desc->data; 361 362 return 0; 363 } 364 365 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 366 { 367 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 368 struct rtw_fwcd_hdr *hdr; 369 u8 *next; 370 371 if (!desc->data) { 372 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 373 return NULL; 374 } 375 376 next = desc->next + sizeof(struct rtw_fwcd_hdr); 377 if (next - desc->data + size > desc->size) { 378 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 379 return NULL; 380 } 381 382 hdr = (struct rtw_fwcd_hdr *)(desc->next); 383 hdr->item = item; 384 hdr->size = size; 385 hdr->padding1 = 0x01234567; 386 hdr->padding2 = 0x89abcdef; 387 desc->next = next + size; 388 389 return next; 390 } 391 392 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 393 { 394 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 395 396 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 397 398 /* Data will be freed after lifetime of device coredump. After calling 399 * dev_coredump, data is supposed to be handled by the device coredump 400 * framework. Note that a new dump will be discarded if a previous one 401 * hasn't been released yet. 402 */ 403 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 404 } 405 406 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 407 { 408 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 409 410 if (free_self) { 411 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 412 vfree(desc->data); 413 } 414 415 desc->data = NULL; 416 desc->next = NULL; 417 } 418 419 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 420 { 421 u32 size = rtwdev->chip->fw_rxff_size; 422 u32 *buf; 423 u8 seq; 424 425 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 426 if (!buf) 427 return -ENOMEM; 428 429 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 430 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 431 return -EINVAL; 432 } 433 434 if (GET_FW_DUMP_LEN(buf) == 0) { 435 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 436 return -EINVAL; 437 } 438 439 seq = GET_FW_DUMP_SEQ(buf); 440 if (seq > 0) { 441 rtw_dbg(rtwdev, RTW_DBG_FW, 442 "fw crash dump's seq is wrong: %d\n", seq); 443 return -EINVAL; 444 } 445 446 return 0; 447 } 448 449 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 450 u32 fwcd_item) 451 { 452 u32 rxff = rtwdev->chip->fw_rxff_size; 453 u32 dump_size, done_size = 0; 454 u8 *buf; 455 int ret; 456 457 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 458 if (!buf) 459 return -ENOMEM; 460 461 while (size) { 462 dump_size = size > rxff ? rxff : size; 463 464 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 465 dump_size); 466 if (ret) { 467 rtw_err(rtwdev, 468 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 469 ocp_src, done_size); 470 return ret; 471 } 472 473 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 474 dump_size, (u32 *)(buf + done_size)); 475 if (ret) { 476 rtw_err(rtwdev, 477 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 478 ocp_src, done_size); 479 return ret; 480 } 481 482 size -= dump_size; 483 done_size += dump_size; 484 } 485 486 return 0; 487 } 488 EXPORT_SYMBOL(rtw_dump_fw); 489 490 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 491 { 492 u8 *buf; 493 u32 i; 494 495 if (addr & 0x3) { 496 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 497 return -EINVAL; 498 } 499 500 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 501 if (!buf) 502 return -ENOMEM; 503 504 for (i = 0; i < size; i += 4) 505 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 506 507 return 0; 508 } 509 EXPORT_SYMBOL(rtw_dump_reg); 510 511 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 512 struct ieee80211_bss_conf *conf) 513 { 514 if (conf && conf->assoc) { 515 rtwvif->aid = conf->aid; 516 rtwvif->net_type = RTW_NET_MGD_LINKED; 517 } else { 518 rtwvif->aid = 0; 519 rtwvif->net_type = RTW_NET_NO_LINK; 520 } 521 } 522 523 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 524 struct ieee80211_vif *vif, 525 struct ieee80211_sta *sta, 526 struct ieee80211_key_conf *key, 527 void *data) 528 { 529 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 530 struct rtw_sec_desc *sec = &rtwdev->sec; 531 532 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 533 } 534 535 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 536 { 537 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 538 539 if (rtwdev->sta_cnt == 0) { 540 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 541 return; 542 } 543 rtw_sta_remove(rtwdev, sta, false); 544 } 545 546 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 547 { 548 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 549 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 550 551 rtw_bf_disassoc(rtwdev, vif, NULL); 552 rtw_vif_assoc_changed(rtwvif, NULL); 553 rtw_txq_cleanup(rtwdev, vif->txq); 554 } 555 556 void rtw_fw_recovery(struct rtw_dev *rtwdev) 557 { 558 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 559 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 560 } 561 562 static void __fw_recovery_work(struct rtw_dev *rtwdev) 563 { 564 int ret = 0; 565 566 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 567 568 ret = rtw_fwcd_prep(rtwdev); 569 if (ret) 570 goto free; 571 ret = rtw_fw_dump_crash_log(rtwdev); 572 if (ret) 573 goto free; 574 ret = rtw_chip_dump_fw_crash(rtwdev); 575 if (ret) 576 goto free; 577 578 rtw_fwcd_dump(rtwdev); 579 free: 580 rtw_fwcd_free(rtwdev, !!ret); 581 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 582 583 WARN(1, "firmware crash, start reset and recover\n"); 584 585 rcu_read_lock(); 586 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 587 rcu_read_unlock(); 588 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 589 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 590 rtw_enter_ips(rtwdev); 591 } 592 593 static void rtw_fw_recovery_work(struct work_struct *work) 594 { 595 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 596 fw_recovery_work); 597 598 mutex_lock(&rtwdev->mutex); 599 __fw_recovery_work(rtwdev); 600 mutex_unlock(&rtwdev->mutex); 601 602 ieee80211_restart_hw(rtwdev->hw); 603 } 604 605 struct rtw_txq_ba_iter_data { 606 }; 607 608 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 609 { 610 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 611 int ret; 612 u8 tid; 613 614 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 615 while (tid != IEEE80211_NUM_TIDS) { 616 clear_bit(tid, si->tid_ba); 617 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 618 if (ret == -EINVAL) { 619 struct ieee80211_txq *txq; 620 struct rtw_txq *rtwtxq; 621 622 txq = sta->txq[tid]; 623 rtwtxq = (struct rtw_txq *)txq->drv_priv; 624 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 625 } 626 627 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 628 } 629 } 630 631 static void rtw_txq_ba_work(struct work_struct *work) 632 { 633 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 634 struct rtw_txq_ba_iter_data data; 635 636 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 637 } 638 639 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 640 struct rtw_channel_params *chan_params) 641 { 642 struct ieee80211_channel *channel = chandef->chan; 643 enum nl80211_chan_width width = chandef->width; 644 u8 *cch_by_bw = chan_params->cch_by_bw; 645 u32 primary_freq, center_freq; 646 u8 center_chan; 647 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 648 u8 primary_chan_idx = 0; 649 u8 i; 650 651 center_chan = channel->hw_value; 652 primary_freq = channel->center_freq; 653 center_freq = chandef->center_freq1; 654 655 /* assign the center channel used while 20M bw is selected */ 656 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 657 658 switch (width) { 659 case NL80211_CHAN_WIDTH_20_NOHT: 660 case NL80211_CHAN_WIDTH_20: 661 bandwidth = RTW_CHANNEL_WIDTH_20; 662 primary_chan_idx = RTW_SC_DONT_CARE; 663 break; 664 case NL80211_CHAN_WIDTH_40: 665 bandwidth = RTW_CHANNEL_WIDTH_40; 666 if (primary_freq > center_freq) { 667 primary_chan_idx = RTW_SC_20_UPPER; 668 center_chan -= 2; 669 } else { 670 primary_chan_idx = RTW_SC_20_LOWER; 671 center_chan += 2; 672 } 673 break; 674 case NL80211_CHAN_WIDTH_80: 675 bandwidth = RTW_CHANNEL_WIDTH_80; 676 if (primary_freq > center_freq) { 677 if (primary_freq - center_freq == 10) { 678 primary_chan_idx = RTW_SC_20_UPPER; 679 center_chan -= 2; 680 } else { 681 primary_chan_idx = RTW_SC_20_UPMOST; 682 center_chan -= 6; 683 } 684 /* assign the center channel used 685 * while 40M bw is selected 686 */ 687 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 688 } else { 689 if (center_freq - primary_freq == 10) { 690 primary_chan_idx = RTW_SC_20_LOWER; 691 center_chan += 2; 692 } else { 693 primary_chan_idx = RTW_SC_20_LOWEST; 694 center_chan += 6; 695 } 696 /* assign the center channel used 697 * while 40M bw is selected 698 */ 699 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 700 } 701 break; 702 default: 703 center_chan = 0; 704 break; 705 } 706 707 chan_params->center_chan = center_chan; 708 chan_params->bandwidth = bandwidth; 709 chan_params->primary_chan_idx = primary_chan_idx; 710 711 /* assign the center channel used while current bw is selected */ 712 cch_by_bw[bandwidth] = center_chan; 713 714 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 715 cch_by_bw[i] = 0; 716 } 717 718 void rtw_set_channel(struct rtw_dev *rtwdev) 719 { 720 struct ieee80211_hw *hw = rtwdev->hw; 721 struct rtw_hal *hal = &rtwdev->hal; 722 struct rtw_chip_info *chip = rtwdev->chip; 723 struct rtw_channel_params ch_param; 724 u8 center_chan, bandwidth, primary_chan_idx; 725 u8 i; 726 727 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 728 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 729 return; 730 731 center_chan = ch_param.center_chan; 732 bandwidth = ch_param.bandwidth; 733 primary_chan_idx = ch_param.primary_chan_idx; 734 735 hal->current_band_width = bandwidth; 736 hal->current_channel = center_chan; 737 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 738 739 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 740 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 741 742 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 743 744 if (hal->current_band_type == RTW_BAND_5G) { 745 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 746 } else { 747 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 748 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 749 else 750 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 751 } 752 753 rtw_phy_set_tx_power_level(rtwdev, center_chan); 754 755 /* if the channel isn't set for scanning, we will do RF calibration 756 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 757 * during scanning on each channel takes too long. 758 */ 759 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 760 rtwdev->need_rfk = true; 761 } 762 763 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 764 { 765 struct rtw_chip_info *chip = rtwdev->chip; 766 767 if (rtwdev->need_rfk) { 768 rtwdev->need_rfk = false; 769 chip->ops->phy_calibration(rtwdev); 770 } 771 } 772 773 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 774 { 775 int i; 776 777 for (i = 0; i < ETH_ALEN; i++) 778 rtw_write8(rtwdev, start + i, addr[i]); 779 } 780 781 void rtw_vif_port_config(struct rtw_dev *rtwdev, 782 struct rtw_vif *rtwvif, 783 u32 config) 784 { 785 u32 addr, mask; 786 787 if (config & PORT_SET_MAC_ADDR) { 788 addr = rtwvif->conf->mac_addr.addr; 789 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 790 } 791 if (config & PORT_SET_BSSID) { 792 addr = rtwvif->conf->bssid.addr; 793 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 794 } 795 if (config & PORT_SET_NET_TYPE) { 796 addr = rtwvif->conf->net_type.addr; 797 mask = rtwvif->conf->net_type.mask; 798 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 799 } 800 if (config & PORT_SET_AID) { 801 addr = rtwvif->conf->aid.addr; 802 mask = rtwvif->conf->aid.mask; 803 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 804 } 805 if (config & PORT_SET_BCN_CTRL) { 806 addr = rtwvif->conf->bcn_ctrl.addr; 807 mask = rtwvif->conf->bcn_ctrl.mask; 808 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 809 } 810 } 811 812 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 813 { 814 u8 bw = 0; 815 816 switch (bw_cap) { 817 case EFUSE_HW_CAP_IGNORE: 818 case EFUSE_HW_CAP_SUPP_BW80: 819 bw |= BIT(RTW_CHANNEL_WIDTH_80); 820 fallthrough; 821 case EFUSE_HW_CAP_SUPP_BW40: 822 bw |= BIT(RTW_CHANNEL_WIDTH_40); 823 fallthrough; 824 default: 825 bw |= BIT(RTW_CHANNEL_WIDTH_20); 826 break; 827 } 828 829 return bw; 830 } 831 832 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 833 { 834 struct rtw_hal *hal = &rtwdev->hal; 835 struct rtw_chip_info *chip = rtwdev->chip; 836 837 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 838 hw_ant_num >= hal->rf_path_num) 839 return; 840 841 switch (hw_ant_num) { 842 case 1: 843 hal->rf_type = RF_1T1R; 844 hal->rf_path_num = 1; 845 if (!chip->fix_rf_phy_num) 846 hal->rf_phy_num = hal->rf_path_num; 847 hal->antenna_tx = BB_PATH_A; 848 hal->antenna_rx = BB_PATH_A; 849 break; 850 default: 851 WARN(1, "invalid hw configuration from efuse\n"); 852 break; 853 } 854 } 855 856 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 857 { 858 u64 ra_mask = 0; 859 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 860 u8 vht_mcs_cap; 861 int i, nss; 862 863 /* 4SS, every two bits for MCS7/8/9 */ 864 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 865 vht_mcs_cap = mcs_map & 0x3; 866 switch (vht_mcs_cap) { 867 case 2: /* MCS9 */ 868 ra_mask |= 0x3ffULL << nss; 869 break; 870 case 1: /* MCS8 */ 871 ra_mask |= 0x1ffULL << nss; 872 break; 873 case 0: /* MCS7 */ 874 ra_mask |= 0x0ffULL << nss; 875 break; 876 default: 877 break; 878 } 879 } 880 881 return ra_mask; 882 } 883 884 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 885 { 886 u8 rate_id = 0; 887 888 switch (wireless_set) { 889 case WIRELESS_CCK: 890 rate_id = RTW_RATEID_B_20M; 891 break; 892 case WIRELESS_OFDM: 893 rate_id = RTW_RATEID_G; 894 break; 895 case WIRELESS_CCK | WIRELESS_OFDM: 896 rate_id = RTW_RATEID_BG; 897 break; 898 case WIRELESS_OFDM | WIRELESS_HT: 899 if (tx_num == 1) 900 rate_id = RTW_RATEID_GN_N1SS; 901 else if (tx_num == 2) 902 rate_id = RTW_RATEID_GN_N2SS; 903 else if (tx_num == 3) 904 rate_id = RTW_RATEID_ARFR5_N_3SS; 905 break; 906 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 907 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 908 if (tx_num == 1) 909 rate_id = RTW_RATEID_BGN_40M_1SS; 910 else if (tx_num == 2) 911 rate_id = RTW_RATEID_BGN_40M_2SS; 912 else if (tx_num == 3) 913 rate_id = RTW_RATEID_ARFR5_N_3SS; 914 else if (tx_num == 4) 915 rate_id = RTW_RATEID_ARFR7_N_4SS; 916 } else { 917 if (tx_num == 1) 918 rate_id = RTW_RATEID_BGN_20M_1SS; 919 else if (tx_num == 2) 920 rate_id = RTW_RATEID_BGN_20M_2SS; 921 else if (tx_num == 3) 922 rate_id = RTW_RATEID_ARFR5_N_3SS; 923 else if (tx_num == 4) 924 rate_id = RTW_RATEID_ARFR7_N_4SS; 925 } 926 break; 927 case WIRELESS_OFDM | WIRELESS_VHT: 928 if (tx_num == 1) 929 rate_id = RTW_RATEID_ARFR1_AC_1SS; 930 else if (tx_num == 2) 931 rate_id = RTW_RATEID_ARFR0_AC_2SS; 932 else if (tx_num == 3) 933 rate_id = RTW_RATEID_ARFR4_AC_3SS; 934 else if (tx_num == 4) 935 rate_id = RTW_RATEID_ARFR6_AC_4SS; 936 break; 937 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 938 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 939 if (tx_num == 1) 940 rate_id = RTW_RATEID_ARFR1_AC_1SS; 941 else if (tx_num == 2) 942 rate_id = RTW_RATEID_ARFR0_AC_2SS; 943 else if (tx_num == 3) 944 rate_id = RTW_RATEID_ARFR4_AC_3SS; 945 else if (tx_num == 4) 946 rate_id = RTW_RATEID_ARFR6_AC_4SS; 947 } else { 948 if (tx_num == 1) 949 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 950 else if (tx_num == 2) 951 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 952 else if (tx_num == 3) 953 rate_id = RTW_RATEID_ARFR4_AC_3SS; 954 else if (tx_num == 4) 955 rate_id = RTW_RATEID_ARFR6_AC_4SS; 956 } 957 break; 958 default: 959 break; 960 } 961 962 return rate_id; 963 } 964 965 #define RA_MASK_CCK_RATES 0x0000f 966 #define RA_MASK_OFDM_RATES 0x00ff0 967 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 968 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 969 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 970 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 971 RA_MASK_HT_RATES_2SS | \ 972 RA_MASK_HT_RATES_3SS) 973 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 974 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 975 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 976 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 977 RA_MASK_VHT_RATES_2SS | \ 978 RA_MASK_VHT_RATES_3SS) 979 #define RA_MASK_CCK_IN_HT 0x00005 980 #define RA_MASK_CCK_IN_VHT 0x00005 981 #define RA_MASK_OFDM_IN_VHT 0x00010 982 #define RA_MASK_OFDM_IN_HT_2G 0x00010 983 #define RA_MASK_OFDM_IN_HT_5G 0x00030 984 985 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, 986 struct rtw_sta_info *si, 987 u64 ra_mask, bool is_vht_enable, 988 u8 wireless_set) 989 { 990 struct rtw_hal *hal = &rtwdev->hal; 991 const struct cfg80211_bitrate_mask *mask = si->mask; 992 u64 cfg_mask = GENMASK_ULL(63, 0); 993 u8 rssi_level, band; 994 995 if (wireless_set != WIRELESS_CCK) { 996 rssi_level = si->rssi_level; 997 if (rssi_level == 0) 998 ra_mask &= 0xffffffffffffffffULL; 999 else if (rssi_level == 1) 1000 ra_mask &= 0xfffffffffffffff0ULL; 1001 else if (rssi_level == 2) 1002 ra_mask &= 0xffffffffffffefe0ULL; 1003 else if (rssi_level == 3) 1004 ra_mask &= 0xffffffffffffcfc0ULL; 1005 else if (rssi_level == 4) 1006 ra_mask &= 0xffffffffffff8f80ULL; 1007 else if (rssi_level >= 5) 1008 ra_mask &= 0xffffffffffff0f00ULL; 1009 } 1010 1011 if (!si->use_cfg_mask) 1012 return ra_mask; 1013 1014 band = hal->current_band_type; 1015 if (band == RTW_BAND_2G) { 1016 band = NL80211_BAND_2GHZ; 1017 cfg_mask = mask->control[band].legacy; 1018 } else if (band == RTW_BAND_5G) { 1019 band = NL80211_BAND_5GHZ; 1020 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1021 RA_MASK_OFDM_RATES); 1022 } 1023 1024 if (!is_vht_enable) { 1025 if (ra_mask & RA_MASK_HT_RATES_1SS) 1026 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1027 RA_MASK_HT_RATES_1SS); 1028 if (ra_mask & RA_MASK_HT_RATES_2SS) 1029 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1030 RA_MASK_HT_RATES_2SS); 1031 } else { 1032 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1033 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1034 RA_MASK_VHT_RATES_1SS); 1035 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1036 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1037 RA_MASK_VHT_RATES_2SS); 1038 } 1039 1040 ra_mask &= cfg_mask; 1041 1042 return ra_mask; 1043 } 1044 1045 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 1046 { 1047 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1048 struct ieee80211_sta *sta = si->sta; 1049 struct rtw_efuse *efuse = &rtwdev->efuse; 1050 struct rtw_hal *hal = &rtwdev->hal; 1051 u8 wireless_set; 1052 u8 bw_mode; 1053 u8 rate_id; 1054 u8 rf_type = RF_1T1R; 1055 u8 stbc_en = 0; 1056 u8 ldpc_en = 0; 1057 u8 tx_num = 1; 1058 u64 ra_mask = 0; 1059 bool is_vht_enable = false; 1060 bool is_support_sgi = false; 1061 1062 if (sta->vht_cap.vht_supported) { 1063 is_vht_enable = true; 1064 ra_mask |= get_vht_ra_mask(sta); 1065 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1066 stbc_en = VHT_STBC_EN; 1067 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1068 ldpc_en = VHT_LDPC_EN; 1069 } else if (sta->ht_cap.ht_supported) { 1070 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 1071 (sta->ht_cap.mcs.rx_mask[0] << 12); 1072 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1073 stbc_en = HT_STBC_EN; 1074 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1075 ldpc_en = HT_LDPC_EN; 1076 } 1077 1078 if (efuse->hw_cap.nss == 1) 1079 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1080 1081 if (hal->current_band_type == RTW_BAND_5G) { 1082 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 1083 if (sta->vht_cap.vht_supported) { 1084 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1085 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1086 } else if (sta->ht_cap.ht_supported) { 1087 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1088 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1089 } else { 1090 wireless_set = WIRELESS_OFDM; 1091 } 1092 dm_info->rrsr_val_init = RRSR_INIT_5G; 1093 } else if (hal->current_band_type == RTW_BAND_2G) { 1094 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 1095 if (sta->vht_cap.vht_supported) { 1096 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1097 RA_MASK_OFDM_IN_VHT; 1098 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1099 WIRELESS_HT | WIRELESS_VHT; 1100 } else if (sta->ht_cap.ht_supported) { 1101 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1102 RA_MASK_OFDM_IN_HT_2G; 1103 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1104 WIRELESS_HT; 1105 } else if (sta->supp_rates[0] <= 0xf) { 1106 wireless_set = WIRELESS_CCK; 1107 } else { 1108 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1109 } 1110 dm_info->rrsr_val_init = RRSR_INIT_2G; 1111 } else { 1112 rtw_err(rtwdev, "Unknown band type\n"); 1113 wireless_set = 0; 1114 } 1115 1116 switch (sta->bandwidth) { 1117 case IEEE80211_STA_RX_BW_80: 1118 bw_mode = RTW_CHANNEL_WIDTH_80; 1119 is_support_sgi = sta->vht_cap.vht_supported && 1120 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1121 break; 1122 case IEEE80211_STA_RX_BW_40: 1123 bw_mode = RTW_CHANNEL_WIDTH_40; 1124 is_support_sgi = sta->ht_cap.ht_supported && 1125 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1126 break; 1127 default: 1128 bw_mode = RTW_CHANNEL_WIDTH_20; 1129 is_support_sgi = sta->ht_cap.ht_supported && 1130 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1131 break; 1132 } 1133 1134 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 1135 tx_num = 2; 1136 rf_type = RF_2T2R; 1137 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 1138 tx_num = 2; 1139 rf_type = RF_2T2R; 1140 } 1141 1142 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1143 1144 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, 1145 wireless_set); 1146 1147 si->bw_mode = bw_mode; 1148 si->stbc_en = stbc_en; 1149 si->ldpc_en = ldpc_en; 1150 si->rf_type = rf_type; 1151 si->wireless_set = wireless_set; 1152 si->sgi_enable = is_support_sgi; 1153 si->vht_enable = is_vht_enable; 1154 si->ra_mask = ra_mask; 1155 si->rate_id = rate_id; 1156 1157 rtw_fw_send_ra_info(rtwdev, si); 1158 } 1159 1160 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1161 { 1162 struct rtw_chip_info *chip = rtwdev->chip; 1163 struct rtw_fw_state *fw; 1164 1165 fw = &rtwdev->fw; 1166 wait_for_completion(&fw->completion); 1167 if (!fw->firmware) 1168 return -EINVAL; 1169 1170 if (chip->wow_fw_name) { 1171 fw = &rtwdev->wow_fw; 1172 wait_for_completion(&fw->completion); 1173 if (!fw->firmware) 1174 return -EINVAL; 1175 } 1176 1177 return 0; 1178 } 1179 1180 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1181 struct rtw_fw_state *fw) 1182 { 1183 struct rtw_chip_info *chip = rtwdev->chip; 1184 1185 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1186 !fw->feature) 1187 return LPS_DEEP_MODE_NONE; 1188 1189 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1190 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1191 return LPS_DEEP_MODE_PG; 1192 1193 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1194 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1195 return LPS_DEEP_MODE_LCLK; 1196 1197 return LPS_DEEP_MODE_NONE; 1198 } 1199 1200 static int rtw_power_on(struct rtw_dev *rtwdev) 1201 { 1202 struct rtw_chip_info *chip = rtwdev->chip; 1203 struct rtw_fw_state *fw = &rtwdev->fw; 1204 bool wifi_only; 1205 int ret; 1206 1207 ret = rtw_hci_setup(rtwdev); 1208 if (ret) { 1209 rtw_err(rtwdev, "failed to setup hci\n"); 1210 goto err; 1211 } 1212 1213 /* power on MAC before firmware downloaded */ 1214 ret = rtw_mac_power_on(rtwdev); 1215 if (ret) { 1216 rtw_err(rtwdev, "failed to power on mac\n"); 1217 goto err; 1218 } 1219 1220 ret = rtw_wait_firmware_completion(rtwdev); 1221 if (ret) { 1222 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1223 goto err_off; 1224 } 1225 1226 ret = rtw_download_firmware(rtwdev, fw); 1227 if (ret) { 1228 rtw_err(rtwdev, "failed to download firmware\n"); 1229 goto err_off; 1230 } 1231 1232 /* config mac after firmware downloaded */ 1233 ret = rtw_mac_init(rtwdev); 1234 if (ret) { 1235 rtw_err(rtwdev, "failed to configure mac\n"); 1236 goto err_off; 1237 } 1238 1239 chip->ops->phy_set_param(rtwdev); 1240 1241 ret = rtw_hci_start(rtwdev); 1242 if (ret) { 1243 rtw_err(rtwdev, "failed to start hci\n"); 1244 goto err_off; 1245 } 1246 1247 /* send H2C after HCI has started */ 1248 rtw_fw_send_general_info(rtwdev); 1249 rtw_fw_send_phydm_info(rtwdev); 1250 1251 wifi_only = !rtwdev->efuse.btcoex; 1252 rtw_coex_power_on_setting(rtwdev); 1253 rtw_coex_init_hw_config(rtwdev, wifi_only); 1254 1255 return 0; 1256 1257 err_off: 1258 rtw_mac_power_off(rtwdev); 1259 1260 err: 1261 return ret; 1262 } 1263 1264 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1265 { 1266 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1267 return; 1268 1269 if (start) { 1270 rtw_fw_scan_notify(rtwdev, true); 1271 } else { 1272 reinit_completion(&rtwdev->fw_scan_density); 1273 rtw_fw_scan_notify(rtwdev, false); 1274 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1275 SCAN_NOTIFY_TIMEOUT)) 1276 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1277 } 1278 } 1279 1280 int rtw_core_start(struct rtw_dev *rtwdev) 1281 { 1282 int ret; 1283 1284 ret = rtw_power_on(rtwdev); 1285 if (ret) 1286 return ret; 1287 1288 rtw_sec_enable_sec_engine(rtwdev); 1289 1290 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1291 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1292 1293 /* rcr reset after powered on */ 1294 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1295 1296 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1297 RTW_WATCH_DOG_DELAY_TIME); 1298 1299 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1300 1301 return 0; 1302 } 1303 1304 static void rtw_power_off(struct rtw_dev *rtwdev) 1305 { 1306 rtw_hci_stop(rtwdev); 1307 rtw_coex_power_off_setting(rtwdev); 1308 rtw_mac_power_off(rtwdev); 1309 } 1310 1311 void rtw_core_stop(struct rtw_dev *rtwdev) 1312 { 1313 struct rtw_coex *coex = &rtwdev->coex; 1314 1315 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1316 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1317 1318 mutex_unlock(&rtwdev->mutex); 1319 1320 cancel_work_sync(&rtwdev->c2h_work); 1321 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1322 cancel_delayed_work_sync(&coex->bt_relink_work); 1323 cancel_delayed_work_sync(&coex->bt_reenable_work); 1324 cancel_delayed_work_sync(&coex->defreeze_work); 1325 cancel_delayed_work_sync(&coex->wl_remain_work); 1326 cancel_delayed_work_sync(&coex->bt_remain_work); 1327 cancel_delayed_work_sync(&coex->wl_connecting_work); 1328 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1329 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1330 1331 mutex_lock(&rtwdev->mutex); 1332 1333 rtw_power_off(rtwdev); 1334 } 1335 1336 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1337 struct ieee80211_sta_ht_cap *ht_cap) 1338 { 1339 struct rtw_efuse *efuse = &rtwdev->efuse; 1340 1341 ht_cap->ht_supported = true; 1342 ht_cap->cap = 0; 1343 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1344 IEEE80211_HT_CAP_MAX_AMSDU | 1345 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1346 1347 if (rtw_chip_has_rx_ldpc(rtwdev)) 1348 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1349 if (rtw_chip_has_tx_stbc(rtwdev)) 1350 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1351 1352 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1353 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1354 IEEE80211_HT_CAP_DSSSCCK40 | 1355 IEEE80211_HT_CAP_SGI_40; 1356 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1357 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 1358 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1359 if (efuse->hw_cap.nss > 1) { 1360 ht_cap->mcs.rx_mask[0] = 0xFF; 1361 ht_cap->mcs.rx_mask[1] = 0xFF; 1362 ht_cap->mcs.rx_mask[4] = 0x01; 1363 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1364 } else { 1365 ht_cap->mcs.rx_mask[0] = 0xFF; 1366 ht_cap->mcs.rx_mask[1] = 0x00; 1367 ht_cap->mcs.rx_mask[4] = 0x01; 1368 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1369 } 1370 } 1371 1372 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1373 struct ieee80211_sta_vht_cap *vht_cap) 1374 { 1375 struct rtw_efuse *efuse = &rtwdev->efuse; 1376 u16 mcs_map; 1377 __le16 highest; 1378 1379 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1380 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1381 return; 1382 1383 vht_cap->vht_supported = true; 1384 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1385 IEEE80211_VHT_CAP_SHORT_GI_80 | 1386 IEEE80211_VHT_CAP_RXSTBC_1 | 1387 IEEE80211_VHT_CAP_HTC_VHT | 1388 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1389 0; 1390 if (rtwdev->hal.rf_path_num > 1) 1391 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1392 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1393 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1394 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1395 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1396 1397 if (rtw_chip_has_rx_ldpc(rtwdev)) 1398 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1399 1400 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1401 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1402 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1403 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1404 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1405 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1406 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1407 if (efuse->hw_cap.nss > 1) { 1408 highest = cpu_to_le16(780); 1409 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1410 } else { 1411 highest = cpu_to_le16(390); 1412 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1413 } 1414 1415 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1416 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1417 vht_cap->vht_mcs.rx_highest = highest; 1418 vht_cap->vht_mcs.tx_highest = highest; 1419 } 1420 1421 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1422 struct rtw_chip_info *chip) 1423 { 1424 struct rtw_dev *rtwdev = hw->priv; 1425 struct ieee80211_supported_band *sband; 1426 1427 if (chip->band & RTW_BAND_2G) { 1428 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1429 if (!sband) 1430 goto err_out; 1431 if (chip->ht_supported) 1432 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1433 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1434 } 1435 1436 if (chip->band & RTW_BAND_5G) { 1437 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1438 if (!sband) 1439 goto err_out; 1440 if (chip->ht_supported) 1441 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1442 if (chip->vht_supported) 1443 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1444 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1445 } 1446 1447 return; 1448 1449 err_out: 1450 rtw_err(rtwdev, "failed to set supported band\n"); 1451 } 1452 1453 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1454 struct rtw_chip_info *chip) 1455 { 1456 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1457 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1458 } 1459 1460 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1461 struct rtw_fw_state *fw) 1462 { 1463 u32 feature; 1464 const struct rtw_fw_hdr *fw_hdr = 1465 (const struct rtw_fw_hdr *)fw->firmware->data; 1466 1467 feature = le32_to_cpu(fw_hdr->feature); 1468 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1469 } 1470 1471 static void __update_firmware_info(struct rtw_dev *rtwdev, 1472 struct rtw_fw_state *fw) 1473 { 1474 const struct rtw_fw_hdr *fw_hdr = 1475 (const struct rtw_fw_hdr *)fw->firmware->data; 1476 1477 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1478 fw->version = le16_to_cpu(fw_hdr->version); 1479 fw->sub_version = fw_hdr->subversion; 1480 fw->sub_index = fw_hdr->subindex; 1481 1482 __update_firmware_feature(rtwdev, fw); 1483 } 1484 1485 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1486 struct rtw_fw_state *fw) 1487 { 1488 struct rtw_fw_hdr_legacy *legacy = 1489 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1490 1491 fw->h2c_version = 0; 1492 fw->version = le16_to_cpu(legacy->version); 1493 fw->sub_version = legacy->subversion1; 1494 fw->sub_index = legacy->subversion2; 1495 } 1496 1497 static void update_firmware_info(struct rtw_dev *rtwdev, 1498 struct rtw_fw_state *fw) 1499 { 1500 if (rtw_chip_wcpu_11n(rtwdev)) 1501 __update_firmware_info_legacy(rtwdev, fw); 1502 else 1503 __update_firmware_info(rtwdev, fw); 1504 } 1505 1506 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1507 { 1508 struct rtw_fw_state *fw = context; 1509 struct rtw_dev *rtwdev = fw->rtwdev; 1510 1511 if (!firmware || !firmware->data) { 1512 rtw_err(rtwdev, "failed to request firmware\n"); 1513 complete_all(&fw->completion); 1514 return; 1515 } 1516 1517 fw->firmware = firmware; 1518 update_firmware_info(rtwdev, fw); 1519 complete_all(&fw->completion); 1520 1521 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1522 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1523 } 1524 1525 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1526 { 1527 const char *fw_name; 1528 struct rtw_fw_state *fw; 1529 int ret; 1530 1531 switch (type) { 1532 case RTW_WOWLAN_FW: 1533 fw = &rtwdev->wow_fw; 1534 fw_name = rtwdev->chip->wow_fw_name; 1535 break; 1536 1537 case RTW_NORMAL_FW: 1538 fw = &rtwdev->fw; 1539 fw_name = rtwdev->chip->fw_name; 1540 break; 1541 1542 default: 1543 rtw_warn(rtwdev, "unsupported firmware type\n"); 1544 return -ENOENT; 1545 } 1546 1547 fw->rtwdev = rtwdev; 1548 init_completion(&fw->completion); 1549 1550 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1551 GFP_KERNEL, fw, rtw_load_firmware_cb); 1552 if (ret) { 1553 rtw_err(rtwdev, "failed to async firmware request\n"); 1554 return ret; 1555 } 1556 1557 return 0; 1558 } 1559 1560 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1561 { 1562 struct rtw_chip_info *chip = rtwdev->chip; 1563 struct rtw_hal *hal = &rtwdev->hal; 1564 struct rtw_efuse *efuse = &rtwdev->efuse; 1565 1566 switch (rtw_hci_type(rtwdev)) { 1567 case RTW_HCI_TYPE_PCIE: 1568 rtwdev->hci.rpwm_addr = 0x03d9; 1569 rtwdev->hci.cpwm_addr = 0x03da; 1570 break; 1571 default: 1572 rtw_err(rtwdev, "unsupported hci type\n"); 1573 return -EINVAL; 1574 } 1575 1576 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1577 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1578 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1579 if (hal->chip_version & BIT_RF_TYPE_ID) { 1580 hal->rf_type = RF_2T2R; 1581 hal->rf_path_num = 2; 1582 hal->antenna_tx = BB_PATH_AB; 1583 hal->antenna_rx = BB_PATH_AB; 1584 } else { 1585 hal->rf_type = RF_1T1R; 1586 hal->rf_path_num = 1; 1587 hal->antenna_tx = BB_PATH_A; 1588 hal->antenna_rx = BB_PATH_A; 1589 } 1590 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1591 hal->rf_path_num; 1592 1593 efuse->physical_size = chip->phy_efuse_size; 1594 efuse->logical_size = chip->log_efuse_size; 1595 efuse->protect_size = chip->ptct_efuse_size; 1596 1597 /* default use ack */ 1598 rtwdev->hal.rcr |= BIT_VHT_DACK; 1599 1600 hal->bfee_sts_cap = 3; 1601 1602 return 0; 1603 } 1604 1605 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1606 { 1607 struct rtw_fw_state *fw = &rtwdev->fw; 1608 int ret; 1609 1610 ret = rtw_hci_setup(rtwdev); 1611 if (ret) { 1612 rtw_err(rtwdev, "failed to setup hci\n"); 1613 goto err; 1614 } 1615 1616 ret = rtw_mac_power_on(rtwdev); 1617 if (ret) { 1618 rtw_err(rtwdev, "failed to power on mac\n"); 1619 goto err; 1620 } 1621 1622 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1623 1624 wait_for_completion(&fw->completion); 1625 if (!fw->firmware) { 1626 ret = -EINVAL; 1627 rtw_err(rtwdev, "failed to load firmware\n"); 1628 goto err; 1629 } 1630 1631 ret = rtw_download_firmware(rtwdev, fw); 1632 if (ret) { 1633 rtw_err(rtwdev, "failed to download firmware\n"); 1634 goto err_off; 1635 } 1636 1637 return 0; 1638 1639 err_off: 1640 rtw_mac_power_off(rtwdev); 1641 1642 err: 1643 return ret; 1644 } 1645 1646 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1647 { 1648 struct rtw_efuse *efuse = &rtwdev->efuse; 1649 u8 hw_feature[HW_FEATURE_LEN]; 1650 u8 id; 1651 u8 bw; 1652 int i; 1653 1654 id = rtw_read8(rtwdev, REG_C2HEVT); 1655 if (id != C2H_HW_FEATURE_REPORT) { 1656 rtw_err(rtwdev, "failed to read hw feature report\n"); 1657 return -EBUSY; 1658 } 1659 1660 for (i = 0; i < HW_FEATURE_LEN; i++) 1661 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1662 1663 rtw_write8(rtwdev, REG_C2HEVT, 0); 1664 1665 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1666 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1667 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1668 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1669 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1670 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1671 1672 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1673 1674 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1675 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1676 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1677 1678 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1679 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1680 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1681 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1682 1683 return 0; 1684 } 1685 1686 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1687 { 1688 rtw_hci_stop(rtwdev); 1689 rtw_mac_power_off(rtwdev); 1690 } 1691 1692 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1693 { 1694 struct rtw_efuse *efuse = &rtwdev->efuse; 1695 int ret; 1696 1697 mutex_lock(&rtwdev->mutex); 1698 1699 /* power on mac to read efuse */ 1700 ret = rtw_chip_efuse_enable(rtwdev); 1701 if (ret) 1702 goto out_unlock; 1703 1704 ret = rtw_parse_efuse_map(rtwdev); 1705 if (ret) 1706 goto out_disable; 1707 1708 ret = rtw_dump_hw_feature(rtwdev); 1709 if (ret) 1710 goto out_disable; 1711 1712 ret = rtw_check_supported_rfe(rtwdev); 1713 if (ret) 1714 goto out_disable; 1715 1716 if (efuse->crystal_cap == 0xff) 1717 efuse->crystal_cap = 0; 1718 if (efuse->pa_type_2g == 0xff) 1719 efuse->pa_type_2g = 0; 1720 if (efuse->pa_type_5g == 0xff) 1721 efuse->pa_type_5g = 0; 1722 if (efuse->lna_type_2g == 0xff) 1723 efuse->lna_type_2g = 0; 1724 if (efuse->lna_type_5g == 0xff) 1725 efuse->lna_type_5g = 0; 1726 if (efuse->channel_plan == 0xff) 1727 efuse->channel_plan = 0x7f; 1728 if (efuse->rf_board_option == 0xff) 1729 efuse->rf_board_option = 0; 1730 if (efuse->bt_setting & BIT(0)) 1731 efuse->share_ant = true; 1732 if (efuse->regd == 0xff) 1733 efuse->regd = 0; 1734 if (efuse->tx_bb_swing_setting_2g == 0xff) 1735 efuse->tx_bb_swing_setting_2g = 0; 1736 if (efuse->tx_bb_swing_setting_5g == 0xff) 1737 efuse->tx_bb_swing_setting_5g = 0; 1738 1739 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1740 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1741 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1742 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1743 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1744 1745 out_disable: 1746 rtw_chip_efuse_disable(rtwdev); 1747 1748 out_unlock: 1749 mutex_unlock(&rtwdev->mutex); 1750 return ret; 1751 } 1752 1753 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1754 { 1755 struct rtw_hal *hal = &rtwdev->hal; 1756 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1757 1758 if (!rfe_def) 1759 return -ENODEV; 1760 1761 rtw_phy_setup_phy_cond(rtwdev, 0); 1762 1763 rtw_phy_init_tx_power(rtwdev); 1764 if (rfe_def->agc_btg_tbl) 1765 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1766 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1767 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1768 rtw_phy_tx_power_by_rate_config(hal); 1769 rtw_phy_tx_power_limit_config(hal); 1770 1771 return 0; 1772 } 1773 1774 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1775 { 1776 int ret; 1777 1778 ret = rtw_chip_parameter_setup(rtwdev); 1779 if (ret) { 1780 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1781 goto err_out; 1782 } 1783 1784 ret = rtw_chip_efuse_info_setup(rtwdev); 1785 if (ret) { 1786 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1787 goto err_out; 1788 } 1789 1790 ret = rtw_chip_board_info_setup(rtwdev); 1791 if (ret) { 1792 rtw_err(rtwdev, "failed to setup chip board info\n"); 1793 goto err_out; 1794 } 1795 1796 return 0; 1797 1798 err_out: 1799 return ret; 1800 } 1801 EXPORT_SYMBOL(rtw_chip_info_setup); 1802 1803 static void rtw_stats_init(struct rtw_dev *rtwdev) 1804 { 1805 struct rtw_traffic_stats *stats = &rtwdev->stats; 1806 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1807 int i; 1808 1809 ewma_tp_init(&stats->tx_ewma_tp); 1810 ewma_tp_init(&stats->rx_ewma_tp); 1811 1812 for (i = 0; i < RTW_EVM_NUM; i++) 1813 ewma_evm_init(&dm_info->ewma_evm[i]); 1814 for (i = 0; i < RTW_SNR_NUM; i++) 1815 ewma_snr_init(&dm_info->ewma_snr[i]); 1816 } 1817 1818 int rtw_core_init(struct rtw_dev *rtwdev) 1819 { 1820 struct rtw_chip_info *chip = rtwdev->chip; 1821 struct rtw_coex *coex = &rtwdev->coex; 1822 int ret; 1823 1824 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1825 INIT_LIST_HEAD(&rtwdev->txqs); 1826 1827 timer_setup(&rtwdev->tx_report.purge_timer, 1828 rtw_tx_report_purge_timer, 0); 1829 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1830 1831 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1832 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1833 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1834 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1835 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1836 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1837 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1838 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1839 rtw_coex_bt_multi_link_remain_work); 1840 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 1841 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 1842 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1843 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 1844 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1845 skb_queue_head_init(&rtwdev->c2h_queue); 1846 skb_queue_head_init(&rtwdev->coex.queue); 1847 skb_queue_head_init(&rtwdev->tx_report.queue); 1848 1849 spin_lock_init(&rtwdev->rf_lock); 1850 spin_lock_init(&rtwdev->h2c.lock); 1851 spin_lock_init(&rtwdev->txq_lock); 1852 spin_lock_init(&rtwdev->tx_report.q_lock); 1853 1854 mutex_init(&rtwdev->mutex); 1855 mutex_init(&rtwdev->coex.mutex); 1856 mutex_init(&rtwdev->hal.tx_power_mutex); 1857 1858 init_waitqueue_head(&rtwdev->coex.wait); 1859 init_completion(&rtwdev->lps_leave_check); 1860 init_completion(&rtwdev->fw_scan_density); 1861 1862 rtwdev->sec.total_cam_num = 32; 1863 rtwdev->hal.current_channel = 1; 1864 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1865 1866 rtw_stats_init(rtwdev); 1867 1868 /* default rx filter setting */ 1869 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1870 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1871 BIT_AB | BIT_AM | BIT_APM; 1872 1873 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 1874 if (ret) { 1875 rtw_warn(rtwdev, "no firmware loaded\n"); 1876 return ret; 1877 } 1878 1879 if (chip->wow_fw_name) { 1880 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 1881 if (ret) { 1882 rtw_warn(rtwdev, "no wow firmware loaded\n"); 1883 wait_for_completion(&rtwdev->fw.completion); 1884 if (rtwdev->fw.firmware) 1885 release_firmware(rtwdev->fw.firmware); 1886 return ret; 1887 } 1888 } 1889 1890 return 0; 1891 } 1892 EXPORT_SYMBOL(rtw_core_init); 1893 1894 void rtw_core_deinit(struct rtw_dev *rtwdev) 1895 { 1896 struct rtw_fw_state *fw = &rtwdev->fw; 1897 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 1898 struct rtw_rsvd_page *rsvd_pkt, *tmp; 1899 unsigned long flags; 1900 1901 rtw_wait_firmware_completion(rtwdev); 1902 1903 if (fw->firmware) 1904 release_firmware(fw->firmware); 1905 1906 if (wow_fw->firmware) 1907 release_firmware(wow_fw->firmware); 1908 1909 destroy_workqueue(rtwdev->tx_wq); 1910 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 1911 skb_queue_purge(&rtwdev->tx_report.queue); 1912 skb_queue_purge(&rtwdev->coex.queue); 1913 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 1914 1915 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 1916 build_list) { 1917 list_del(&rsvd_pkt->build_list); 1918 kfree(rsvd_pkt); 1919 } 1920 1921 mutex_destroy(&rtwdev->mutex); 1922 mutex_destroy(&rtwdev->coex.mutex); 1923 mutex_destroy(&rtwdev->hal.tx_power_mutex); 1924 } 1925 EXPORT_SYMBOL(rtw_core_deinit); 1926 1927 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1928 { 1929 struct rtw_hal *hal = &rtwdev->hal; 1930 int max_tx_headroom = 0; 1931 int ret; 1932 1933 /* TODO: USB & SDIO may need extra room? */ 1934 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 1935 1936 hw->extra_tx_headroom = max_tx_headroom; 1937 hw->queues = IEEE80211_NUM_ACS; 1938 hw->txq_data_size = sizeof(struct rtw_txq); 1939 hw->sta_data_size = sizeof(struct rtw_sta_info); 1940 hw->vif_data_size = sizeof(struct rtw_vif); 1941 1942 ieee80211_hw_set(hw, SIGNAL_DBM); 1943 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 1944 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 1945 ieee80211_hw_set(hw, MFP_CAPABLE); 1946 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 1947 ieee80211_hw_set(hw, SUPPORTS_PS); 1948 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 1949 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 1950 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 1951 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 1952 ieee80211_hw_set(hw, TX_AMSDU); 1953 1954 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1955 BIT(NL80211_IFTYPE_AP) | 1956 BIT(NL80211_IFTYPE_ADHOC) | 1957 BIT(NL80211_IFTYPE_MESH_POINT); 1958 hw->wiphy->available_antennas_tx = hal->antenna_tx; 1959 hw->wiphy->available_antennas_rx = hal->antenna_rx; 1960 1961 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 1962 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 1963 1964 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 1965 1966 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 1967 1968 #ifdef CONFIG_PM 1969 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 1970 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 1971 #endif 1972 rtw_set_supported_band(hw, rtwdev->chip); 1973 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 1974 1975 ret = rtw_regd_init(rtwdev); 1976 if (ret) { 1977 rtw_err(rtwdev, "failed to init regd\n"); 1978 return ret; 1979 } 1980 1981 ret = ieee80211_register_hw(hw); 1982 if (ret) { 1983 rtw_err(rtwdev, "failed to register hw\n"); 1984 return ret; 1985 } 1986 1987 ret = rtw_regd_hint(rtwdev); 1988 if (ret) { 1989 rtw_err(rtwdev, "failed to hint regd\n"); 1990 return ret; 1991 } 1992 1993 rtw_debugfs_init(rtwdev); 1994 1995 rtwdev->bf_info.bfer_mu_cnt = 0; 1996 rtwdev->bf_info.bfer_su_cnt = 0; 1997 1998 return 0; 1999 } 2000 EXPORT_SYMBOL(rtw_register_hw); 2001 2002 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2003 { 2004 struct rtw_chip_info *chip = rtwdev->chip; 2005 2006 ieee80211_unregister_hw(hw); 2007 rtw_unset_supported_band(hw, chip); 2008 } 2009 EXPORT_SYMBOL(rtw_unregister_hw); 2010 2011 MODULE_AUTHOR("Realtek Corporation"); 2012 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2013 MODULE_LICENSE("Dual BSD/GPL"); 2014