1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "regd.h" 7 #include "fw.h" 8 #include "ps.h" 9 #include "sec.h" 10 #include "mac.h" 11 #include "coex.h" 12 #include "phy.h" 13 #include "reg.h" 14 #include "efuse.h" 15 #include "tx.h" 16 #include "debug.h" 17 #include "bf.h" 18 19 unsigned int rtw_fw_lps_deep_mode; 20 EXPORT_SYMBOL(rtw_fw_lps_deep_mode); 21 bool rtw_bf_support = true; 22 unsigned int rtw_debug_mask; 23 EXPORT_SYMBOL(rtw_debug_mask); 24 25 module_param_named(lps_deep_mode, rtw_fw_lps_deep_mode, uint, 0644); 26 module_param_named(support_bf, rtw_bf_support, bool, 0644); 27 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 28 29 MODULE_PARM_DESC(lps_deep_mode, "Deeper PS mode. If 0, deep PS is disabled"); 30 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 31 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 32 33 static struct ieee80211_channel rtw_channeltable_2g[] = { 34 {.center_freq = 2412, .hw_value = 1,}, 35 {.center_freq = 2417, .hw_value = 2,}, 36 {.center_freq = 2422, .hw_value = 3,}, 37 {.center_freq = 2427, .hw_value = 4,}, 38 {.center_freq = 2432, .hw_value = 5,}, 39 {.center_freq = 2437, .hw_value = 6,}, 40 {.center_freq = 2442, .hw_value = 7,}, 41 {.center_freq = 2447, .hw_value = 8,}, 42 {.center_freq = 2452, .hw_value = 9,}, 43 {.center_freq = 2457, .hw_value = 10,}, 44 {.center_freq = 2462, .hw_value = 11,}, 45 {.center_freq = 2467, .hw_value = 12,}, 46 {.center_freq = 2472, .hw_value = 13,}, 47 {.center_freq = 2484, .hw_value = 14,}, 48 }; 49 50 static struct ieee80211_channel rtw_channeltable_5g[] = { 51 {.center_freq = 5180, .hw_value = 36,}, 52 {.center_freq = 5200, .hw_value = 40,}, 53 {.center_freq = 5220, .hw_value = 44,}, 54 {.center_freq = 5240, .hw_value = 48,}, 55 {.center_freq = 5260, .hw_value = 52,}, 56 {.center_freq = 5280, .hw_value = 56,}, 57 {.center_freq = 5300, .hw_value = 60,}, 58 {.center_freq = 5320, .hw_value = 64,}, 59 {.center_freq = 5500, .hw_value = 100,}, 60 {.center_freq = 5520, .hw_value = 104,}, 61 {.center_freq = 5540, .hw_value = 108,}, 62 {.center_freq = 5560, .hw_value = 112,}, 63 {.center_freq = 5580, .hw_value = 116,}, 64 {.center_freq = 5600, .hw_value = 120,}, 65 {.center_freq = 5620, .hw_value = 124,}, 66 {.center_freq = 5640, .hw_value = 128,}, 67 {.center_freq = 5660, .hw_value = 132,}, 68 {.center_freq = 5680, .hw_value = 136,}, 69 {.center_freq = 5700, .hw_value = 140,}, 70 {.center_freq = 5745, .hw_value = 149,}, 71 {.center_freq = 5765, .hw_value = 153,}, 72 {.center_freq = 5785, .hw_value = 157,}, 73 {.center_freq = 5805, .hw_value = 161,}, 74 {.center_freq = 5825, .hw_value = 165, 75 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 76 }; 77 78 static struct ieee80211_rate rtw_ratetable[] = { 79 {.bitrate = 10, .hw_value = 0x00,}, 80 {.bitrate = 20, .hw_value = 0x01,}, 81 {.bitrate = 55, .hw_value = 0x02,}, 82 {.bitrate = 110, .hw_value = 0x03,}, 83 {.bitrate = 60, .hw_value = 0x04,}, 84 {.bitrate = 90, .hw_value = 0x05,}, 85 {.bitrate = 120, .hw_value = 0x06,}, 86 {.bitrate = 180, .hw_value = 0x07,}, 87 {.bitrate = 240, .hw_value = 0x08,}, 88 {.bitrate = 360, .hw_value = 0x09,}, 89 {.bitrate = 480, .hw_value = 0x0a,}, 90 {.bitrate = 540, .hw_value = 0x0b,}, 91 }; 92 93 u16 rtw_desc_to_bitrate(u8 desc_rate) 94 { 95 struct ieee80211_rate rate; 96 97 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 98 return 0; 99 100 rate = rtw_ratetable[desc_rate]; 101 102 return rate.bitrate; 103 } 104 105 static struct ieee80211_supported_band rtw_band_2ghz = { 106 .band = NL80211_BAND_2GHZ, 107 108 .channels = rtw_channeltable_2g, 109 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 110 111 .bitrates = rtw_ratetable, 112 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 113 114 .ht_cap = {0}, 115 .vht_cap = {0}, 116 }; 117 118 static struct ieee80211_supported_band rtw_band_5ghz = { 119 .band = NL80211_BAND_5GHZ, 120 121 .channels = rtw_channeltable_5g, 122 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 123 124 /* 5G has no CCK rates */ 125 .bitrates = rtw_ratetable + 4, 126 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 127 128 .ht_cap = {0}, 129 .vht_cap = {0}, 130 }; 131 132 struct rtw_watch_dog_iter_data { 133 struct rtw_dev *rtwdev; 134 struct rtw_vif *rtwvif; 135 }; 136 137 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 138 { 139 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 140 struct rtw_chip_info *chip = rtwdev->chip; 141 u8 fix_rate_enable = 0; 142 u8 new_csi_rate_idx; 143 144 if (rtwvif->bfee.role != RTW_BFEE_SU && 145 rtwvif->bfee.role != RTW_BFEE_MU) 146 return; 147 148 chip->ops->cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 149 bf_info->cur_csi_rpt_rate, 150 fix_rate_enable, &new_csi_rate_idx); 151 152 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 153 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 154 } 155 156 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 157 struct ieee80211_vif *vif) 158 { 159 struct rtw_watch_dog_iter_data *iter_data = data; 160 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 161 162 if (vif->type == NL80211_IFTYPE_STATION) 163 if (vif->bss_conf.assoc) 164 iter_data->rtwvif = rtwvif; 165 166 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 167 168 rtwvif->stats.tx_unicast = 0; 169 rtwvif->stats.rx_unicast = 0; 170 rtwvif->stats.tx_cnt = 0; 171 rtwvif->stats.rx_cnt = 0; 172 } 173 174 /* process TX/RX statistics periodically for hardware, 175 * the information helps hardware to enhance performance 176 */ 177 static void rtw_watch_dog_work(struct work_struct *work) 178 { 179 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 180 watch_dog_work.work); 181 struct rtw_traffic_stats *stats = &rtwdev->stats; 182 struct rtw_watch_dog_iter_data data = {}; 183 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 184 bool ps_active; 185 186 mutex_lock(&rtwdev->mutex); 187 188 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 189 goto unlock; 190 191 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 192 RTW_WATCH_DOG_DELAY_TIME); 193 194 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 195 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 196 else 197 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 198 199 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 200 rtw_coex_wl_status_change_notify(rtwdev); 201 202 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 203 stats->rx_cnt > RTW_LPS_THRESHOLD) 204 ps_active = true; 205 else 206 ps_active = false; 207 208 ewma_tp_add(&stats->tx_ewma_tp, 209 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 210 ewma_tp_add(&stats->rx_ewma_tp, 211 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 212 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 213 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 214 215 /* reset tx/rx statictics */ 216 stats->tx_unicast = 0; 217 stats->rx_unicast = 0; 218 stats->tx_cnt = 0; 219 stats->rx_cnt = 0; 220 221 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 222 goto unlock; 223 224 /* make sure BB/RF is working for dynamic mech */ 225 rtw_leave_lps(rtwdev); 226 227 rtw_phy_dynamic_mechanism(rtwdev); 228 229 data.rtwdev = rtwdev; 230 /* use atomic version to avoid taking local->iflist_mtx mutex */ 231 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 232 233 /* fw supports only one station associated to enter lps, if there are 234 * more than two stations associated to the AP, then we can not enter 235 * lps, because fw does not handle the overlapped beacon interval 236 * 237 * mac80211 should iterate vifs and determine if driver can enter 238 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 239 * get that vif and check if device is having traffic more than the 240 * threshold. 241 */ 242 if (rtwdev->ps_enabled && data.rtwvif && !ps_active) 243 rtw_enter_lps(rtwdev, data.rtwvif->port); 244 245 rtwdev->watch_dog_cnt++; 246 247 unlock: 248 mutex_unlock(&rtwdev->mutex); 249 } 250 251 static void rtw_c2h_work(struct work_struct *work) 252 { 253 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 254 struct sk_buff *skb, *tmp; 255 256 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 257 skb_unlink(skb, &rtwdev->c2h_queue); 258 rtw_fw_c2h_cmd_handle(rtwdev, skb); 259 dev_kfree_skb_any(skb); 260 } 261 } 262 263 struct rtw_txq_ba_iter_data { 264 }; 265 266 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 267 { 268 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 269 int ret; 270 u8 tid; 271 272 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 273 while (tid != IEEE80211_NUM_TIDS) { 274 clear_bit(tid, si->tid_ba); 275 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 276 if (ret == -EINVAL) { 277 struct ieee80211_txq *txq; 278 struct rtw_txq *rtwtxq; 279 280 txq = sta->txq[tid]; 281 rtwtxq = (struct rtw_txq *)txq->drv_priv; 282 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 283 } 284 285 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 286 } 287 } 288 289 static void rtw_txq_ba_work(struct work_struct *work) 290 { 291 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 292 struct rtw_txq_ba_iter_data data; 293 294 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 295 } 296 297 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 298 struct rtw_channel_params *chan_params) 299 { 300 struct ieee80211_channel *channel = chandef->chan; 301 enum nl80211_chan_width width = chandef->width; 302 u8 *cch_by_bw = chan_params->cch_by_bw; 303 u32 primary_freq, center_freq; 304 u8 center_chan; 305 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 306 u8 primary_chan_idx = 0; 307 u8 i; 308 309 center_chan = channel->hw_value; 310 primary_freq = channel->center_freq; 311 center_freq = chandef->center_freq1; 312 313 /* assign the center channel used while 20M bw is selected */ 314 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 315 316 switch (width) { 317 case NL80211_CHAN_WIDTH_20_NOHT: 318 case NL80211_CHAN_WIDTH_20: 319 bandwidth = RTW_CHANNEL_WIDTH_20; 320 primary_chan_idx = 0; 321 break; 322 case NL80211_CHAN_WIDTH_40: 323 bandwidth = RTW_CHANNEL_WIDTH_40; 324 if (primary_freq > center_freq) { 325 primary_chan_idx = 1; 326 center_chan -= 2; 327 } else { 328 primary_chan_idx = 2; 329 center_chan += 2; 330 } 331 break; 332 case NL80211_CHAN_WIDTH_80: 333 bandwidth = RTW_CHANNEL_WIDTH_80; 334 if (primary_freq > center_freq) { 335 if (primary_freq - center_freq == 10) { 336 primary_chan_idx = 1; 337 center_chan -= 2; 338 } else { 339 primary_chan_idx = 3; 340 center_chan -= 6; 341 } 342 /* assign the center channel used 343 * while 40M bw is selected 344 */ 345 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 346 } else { 347 if (center_freq - primary_freq == 10) { 348 primary_chan_idx = 2; 349 center_chan += 2; 350 } else { 351 primary_chan_idx = 4; 352 center_chan += 6; 353 } 354 /* assign the center channel used 355 * while 40M bw is selected 356 */ 357 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 358 } 359 break; 360 default: 361 center_chan = 0; 362 break; 363 } 364 365 chan_params->center_chan = center_chan; 366 chan_params->bandwidth = bandwidth; 367 chan_params->primary_chan_idx = primary_chan_idx; 368 369 /* assign the center channel used while current bw is selected */ 370 cch_by_bw[bandwidth] = center_chan; 371 372 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 373 cch_by_bw[i] = 0; 374 } 375 376 void rtw_set_channel(struct rtw_dev *rtwdev) 377 { 378 struct ieee80211_hw *hw = rtwdev->hw; 379 struct rtw_hal *hal = &rtwdev->hal; 380 struct rtw_chip_info *chip = rtwdev->chip; 381 struct rtw_channel_params ch_param; 382 u8 center_chan, bandwidth, primary_chan_idx; 383 u8 i; 384 385 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 386 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 387 return; 388 389 center_chan = ch_param.center_chan; 390 bandwidth = ch_param.bandwidth; 391 primary_chan_idx = ch_param.primary_chan_idx; 392 393 hal->current_band_width = bandwidth; 394 hal->current_channel = center_chan; 395 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 396 397 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 398 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 399 400 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 401 402 if (hal->current_band_type == RTW_BAND_5G) { 403 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 404 } else { 405 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 406 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 407 else 408 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 409 } 410 411 rtw_phy_set_tx_power_level(rtwdev, center_chan); 412 } 413 414 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 415 { 416 int i; 417 418 for (i = 0; i < ETH_ALEN; i++) 419 rtw_write8(rtwdev, start + i, addr[i]); 420 } 421 422 void rtw_vif_port_config(struct rtw_dev *rtwdev, 423 struct rtw_vif *rtwvif, 424 u32 config) 425 { 426 u32 addr, mask; 427 428 if (config & PORT_SET_MAC_ADDR) { 429 addr = rtwvif->conf->mac_addr.addr; 430 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 431 } 432 if (config & PORT_SET_BSSID) { 433 addr = rtwvif->conf->bssid.addr; 434 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 435 } 436 if (config & PORT_SET_NET_TYPE) { 437 addr = rtwvif->conf->net_type.addr; 438 mask = rtwvif->conf->net_type.mask; 439 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 440 } 441 if (config & PORT_SET_AID) { 442 addr = rtwvif->conf->aid.addr; 443 mask = rtwvif->conf->aid.mask; 444 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 445 } 446 if (config & PORT_SET_BCN_CTRL) { 447 addr = rtwvif->conf->bcn_ctrl.addr; 448 mask = rtwvif->conf->bcn_ctrl.mask; 449 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 450 } 451 } 452 453 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 454 { 455 u8 bw = 0; 456 457 switch (bw_cap) { 458 case EFUSE_HW_CAP_IGNORE: 459 case EFUSE_HW_CAP_SUPP_BW80: 460 bw |= BIT(RTW_CHANNEL_WIDTH_80); 461 /* fall through */ 462 case EFUSE_HW_CAP_SUPP_BW40: 463 bw |= BIT(RTW_CHANNEL_WIDTH_40); 464 /* fall through */ 465 default: 466 bw |= BIT(RTW_CHANNEL_WIDTH_20); 467 break; 468 } 469 470 return bw; 471 } 472 473 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 474 { 475 struct rtw_hal *hal = &rtwdev->hal; 476 477 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 478 hw_ant_num >= hal->rf_path_num) 479 return; 480 481 switch (hw_ant_num) { 482 case 1: 483 hal->rf_type = RF_1T1R; 484 hal->rf_path_num = 1; 485 hal->antenna_tx = BB_PATH_A; 486 hal->antenna_rx = BB_PATH_A; 487 break; 488 default: 489 WARN(1, "invalid hw configuration from efuse\n"); 490 break; 491 } 492 } 493 494 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 495 { 496 u64 ra_mask = 0; 497 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 498 u8 vht_mcs_cap; 499 int i, nss; 500 501 /* 4SS, every two bits for MCS7/8/9 */ 502 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 503 vht_mcs_cap = mcs_map & 0x3; 504 switch (vht_mcs_cap) { 505 case 2: /* MCS9 */ 506 ra_mask |= 0x3ffULL << nss; 507 break; 508 case 1: /* MCS8 */ 509 ra_mask |= 0x1ffULL << nss; 510 break; 511 case 0: /* MCS7 */ 512 ra_mask |= 0x0ffULL << nss; 513 break; 514 default: 515 break; 516 } 517 } 518 519 return ra_mask; 520 } 521 522 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 523 { 524 u8 rate_id = 0; 525 526 switch (wireless_set) { 527 case WIRELESS_CCK: 528 rate_id = RTW_RATEID_B_20M; 529 break; 530 case WIRELESS_OFDM: 531 rate_id = RTW_RATEID_G; 532 break; 533 case WIRELESS_CCK | WIRELESS_OFDM: 534 rate_id = RTW_RATEID_BG; 535 break; 536 case WIRELESS_OFDM | WIRELESS_HT: 537 if (tx_num == 1) 538 rate_id = RTW_RATEID_GN_N1SS; 539 else if (tx_num == 2) 540 rate_id = RTW_RATEID_GN_N2SS; 541 else if (tx_num == 3) 542 rate_id = RTW_RATEID_ARFR5_N_3SS; 543 break; 544 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 545 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 546 if (tx_num == 1) 547 rate_id = RTW_RATEID_BGN_40M_1SS; 548 else if (tx_num == 2) 549 rate_id = RTW_RATEID_BGN_40M_2SS; 550 else if (tx_num == 3) 551 rate_id = RTW_RATEID_ARFR5_N_3SS; 552 else if (tx_num == 4) 553 rate_id = RTW_RATEID_ARFR7_N_4SS; 554 } else { 555 if (tx_num == 1) 556 rate_id = RTW_RATEID_BGN_20M_1SS; 557 else if (tx_num == 2) 558 rate_id = RTW_RATEID_BGN_20M_2SS; 559 else if (tx_num == 3) 560 rate_id = RTW_RATEID_ARFR5_N_3SS; 561 else if (tx_num == 4) 562 rate_id = RTW_RATEID_ARFR7_N_4SS; 563 } 564 break; 565 case WIRELESS_OFDM | WIRELESS_VHT: 566 if (tx_num == 1) 567 rate_id = RTW_RATEID_ARFR1_AC_1SS; 568 else if (tx_num == 2) 569 rate_id = RTW_RATEID_ARFR0_AC_2SS; 570 else if (tx_num == 3) 571 rate_id = RTW_RATEID_ARFR4_AC_3SS; 572 else if (tx_num == 4) 573 rate_id = RTW_RATEID_ARFR6_AC_4SS; 574 break; 575 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 576 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 577 if (tx_num == 1) 578 rate_id = RTW_RATEID_ARFR1_AC_1SS; 579 else if (tx_num == 2) 580 rate_id = RTW_RATEID_ARFR0_AC_2SS; 581 else if (tx_num == 3) 582 rate_id = RTW_RATEID_ARFR4_AC_3SS; 583 else if (tx_num == 4) 584 rate_id = RTW_RATEID_ARFR6_AC_4SS; 585 } else { 586 if (tx_num == 1) 587 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 588 else if (tx_num == 2) 589 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 590 else if (tx_num == 3) 591 rate_id = RTW_RATEID_ARFR4_AC_3SS; 592 else if (tx_num == 4) 593 rate_id = RTW_RATEID_ARFR6_AC_4SS; 594 } 595 break; 596 default: 597 break; 598 } 599 600 return rate_id; 601 } 602 603 #define RA_MASK_CCK_RATES 0x0000f 604 #define RA_MASK_OFDM_RATES 0x00ff0 605 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 606 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 607 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 608 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 609 RA_MASK_HT_RATES_2SS | \ 610 RA_MASK_HT_RATES_3SS) 611 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 612 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 613 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 614 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 615 RA_MASK_VHT_RATES_2SS | \ 616 RA_MASK_VHT_RATES_3SS) 617 #define RA_MASK_CCK_IN_HT 0x00005 618 #define RA_MASK_CCK_IN_VHT 0x00005 619 #define RA_MASK_OFDM_IN_VHT 0x00010 620 #define RA_MASK_OFDM_IN_HT_2G 0x00010 621 #define RA_MASK_OFDM_IN_HT_5G 0x00030 622 623 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, 624 struct rtw_sta_info *si, 625 u64 ra_mask, bool is_vht_enable, 626 u8 wireless_set) 627 { 628 struct rtw_hal *hal = &rtwdev->hal; 629 const struct cfg80211_bitrate_mask *mask = si->mask; 630 u64 cfg_mask = GENMASK_ULL(63, 0); 631 u8 rssi_level, band; 632 633 if (wireless_set != WIRELESS_CCK) { 634 rssi_level = si->rssi_level; 635 if (rssi_level == 0) 636 ra_mask &= 0xffffffffffffffffULL; 637 else if (rssi_level == 1) 638 ra_mask &= 0xfffffffffffffff0ULL; 639 else if (rssi_level == 2) 640 ra_mask &= 0xffffffffffffefe0ULL; 641 else if (rssi_level == 3) 642 ra_mask &= 0xffffffffffffcfc0ULL; 643 else if (rssi_level == 4) 644 ra_mask &= 0xffffffffffff8f80ULL; 645 else if (rssi_level >= 5) 646 ra_mask &= 0xffffffffffff0f00ULL; 647 } 648 649 if (!si->use_cfg_mask) 650 return ra_mask; 651 652 band = hal->current_band_type; 653 if (band == RTW_BAND_2G) { 654 band = NL80211_BAND_2GHZ; 655 cfg_mask = mask->control[band].legacy; 656 } else if (band == RTW_BAND_5G) { 657 band = NL80211_BAND_5GHZ; 658 cfg_mask = u64_encode_bits(mask->control[band].legacy, 659 RA_MASK_OFDM_RATES); 660 } 661 662 if (!is_vht_enable) { 663 if (ra_mask & RA_MASK_HT_RATES_1SS) 664 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 665 RA_MASK_HT_RATES_1SS); 666 if (ra_mask & RA_MASK_HT_RATES_2SS) 667 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 668 RA_MASK_HT_RATES_2SS); 669 } else { 670 if (ra_mask & RA_MASK_VHT_RATES_1SS) 671 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 672 RA_MASK_VHT_RATES_1SS); 673 if (ra_mask & RA_MASK_VHT_RATES_2SS) 674 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 675 RA_MASK_VHT_RATES_2SS); 676 } 677 678 ra_mask &= cfg_mask; 679 680 return ra_mask; 681 } 682 683 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 684 { 685 struct ieee80211_sta *sta = si->sta; 686 struct rtw_efuse *efuse = &rtwdev->efuse; 687 struct rtw_hal *hal = &rtwdev->hal; 688 u8 wireless_set; 689 u8 bw_mode; 690 u8 rate_id; 691 u8 rf_type = RF_1T1R; 692 u8 stbc_en = 0; 693 u8 ldpc_en = 0; 694 u8 tx_num = 1; 695 u64 ra_mask = 0; 696 bool is_vht_enable = false; 697 bool is_support_sgi = false; 698 699 if (sta->vht_cap.vht_supported) { 700 is_vht_enable = true; 701 ra_mask |= get_vht_ra_mask(sta); 702 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 703 stbc_en = VHT_STBC_EN; 704 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 705 ldpc_en = VHT_LDPC_EN; 706 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) 707 is_support_sgi = true; 708 } else if (sta->ht_cap.ht_supported) { 709 ra_mask |= (sta->ht_cap.mcs.rx_mask[NL80211_BAND_5GHZ] << 20) | 710 (sta->ht_cap.mcs.rx_mask[NL80211_BAND_2GHZ] << 12); 711 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 712 stbc_en = HT_STBC_EN; 713 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 714 ldpc_en = HT_LDPC_EN; 715 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20 || 716 sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 717 is_support_sgi = true; 718 } 719 720 if (hal->current_band_type == RTW_BAND_5G) { 721 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 722 if (sta->vht_cap.vht_supported) { 723 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 724 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 725 } else if (sta->ht_cap.ht_supported) { 726 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 727 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 728 } else { 729 wireless_set = WIRELESS_OFDM; 730 } 731 } else if (hal->current_band_type == RTW_BAND_2G) { 732 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 733 if (sta->vht_cap.vht_supported) { 734 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 735 RA_MASK_OFDM_IN_VHT; 736 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 737 WIRELESS_HT | WIRELESS_VHT; 738 } else if (sta->ht_cap.ht_supported) { 739 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 740 RA_MASK_OFDM_IN_HT_2G; 741 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 742 WIRELESS_HT; 743 } else if (sta->supp_rates[0] <= 0xf) { 744 wireless_set = WIRELESS_CCK; 745 } else { 746 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 747 } 748 } else { 749 rtw_err(rtwdev, "Unknown band type\n"); 750 wireless_set = 0; 751 } 752 753 if (efuse->hw_cap.nss == 1) { 754 ra_mask &= RA_MASK_VHT_RATES_1SS; 755 ra_mask &= RA_MASK_HT_RATES_1SS; 756 } 757 758 switch (sta->bandwidth) { 759 case IEEE80211_STA_RX_BW_80: 760 bw_mode = RTW_CHANNEL_WIDTH_80; 761 break; 762 case IEEE80211_STA_RX_BW_40: 763 bw_mode = RTW_CHANNEL_WIDTH_40; 764 break; 765 default: 766 bw_mode = RTW_CHANNEL_WIDTH_20; 767 break; 768 } 769 770 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 771 tx_num = 2; 772 rf_type = RF_2T2R; 773 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 774 tx_num = 2; 775 rf_type = RF_2T2R; 776 } 777 778 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 779 780 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, 781 wireless_set); 782 783 si->bw_mode = bw_mode; 784 si->stbc_en = stbc_en; 785 si->ldpc_en = ldpc_en; 786 si->rf_type = rf_type; 787 si->wireless_set = wireless_set; 788 si->sgi_enable = is_support_sgi; 789 si->vht_enable = is_vht_enable; 790 si->ra_mask = ra_mask; 791 si->rate_id = rate_id; 792 793 rtw_fw_send_ra_info(rtwdev, si); 794 } 795 796 static int rtw_power_on(struct rtw_dev *rtwdev) 797 { 798 struct rtw_chip_info *chip = rtwdev->chip; 799 struct rtw_fw_state *fw = &rtwdev->fw; 800 bool wifi_only; 801 int ret; 802 803 ret = rtw_hci_setup(rtwdev); 804 if (ret) { 805 rtw_err(rtwdev, "failed to setup hci\n"); 806 goto err; 807 } 808 809 /* power on MAC before firmware downloaded */ 810 ret = rtw_mac_power_on(rtwdev); 811 if (ret) { 812 rtw_err(rtwdev, "failed to power on mac\n"); 813 goto err; 814 } 815 816 wait_for_completion(&fw->completion); 817 if (!fw->firmware) { 818 ret = -EINVAL; 819 rtw_err(rtwdev, "failed to load firmware\n"); 820 goto err; 821 } 822 823 ret = rtw_download_firmware(rtwdev, fw); 824 if (ret) { 825 rtw_err(rtwdev, "failed to download firmware\n"); 826 goto err_off; 827 } 828 829 /* config mac after firmware downloaded */ 830 ret = rtw_mac_init(rtwdev); 831 if (ret) { 832 rtw_err(rtwdev, "failed to configure mac\n"); 833 goto err_off; 834 } 835 836 chip->ops->phy_set_param(rtwdev); 837 838 ret = rtw_hci_start(rtwdev); 839 if (ret) { 840 rtw_err(rtwdev, "failed to start hci\n"); 841 goto err_off; 842 } 843 844 /* send H2C after HCI has started */ 845 rtw_fw_send_general_info(rtwdev); 846 rtw_fw_send_phydm_info(rtwdev); 847 848 wifi_only = !rtwdev->efuse.btcoex; 849 rtw_coex_power_on_setting(rtwdev); 850 rtw_coex_init_hw_config(rtwdev, wifi_only); 851 852 return 0; 853 854 err_off: 855 rtw_mac_power_off(rtwdev); 856 857 err: 858 return ret; 859 } 860 861 int rtw_core_start(struct rtw_dev *rtwdev) 862 { 863 int ret; 864 865 ret = rtw_power_on(rtwdev); 866 if (ret) 867 return ret; 868 869 rtw_sec_enable_sec_engine(rtwdev); 870 871 /* rcr reset after powered on */ 872 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 873 874 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 875 RTW_WATCH_DOG_DELAY_TIME); 876 877 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 878 879 return 0; 880 } 881 882 static void rtw_power_off(struct rtw_dev *rtwdev) 883 { 884 rtwdev->hci.ops->stop(rtwdev); 885 rtw_mac_power_off(rtwdev); 886 } 887 888 void rtw_core_stop(struct rtw_dev *rtwdev) 889 { 890 struct rtw_coex *coex = &rtwdev->coex; 891 892 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 893 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 894 895 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 896 cancel_delayed_work_sync(&coex->bt_relink_work); 897 cancel_delayed_work_sync(&coex->bt_reenable_work); 898 cancel_delayed_work_sync(&coex->defreeze_work); 899 900 rtw_power_off(rtwdev); 901 } 902 903 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 904 struct ieee80211_sta_ht_cap *ht_cap) 905 { 906 struct rtw_efuse *efuse = &rtwdev->efuse; 907 908 ht_cap->ht_supported = true; 909 ht_cap->cap = 0; 910 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 911 IEEE80211_HT_CAP_MAX_AMSDU | 912 IEEE80211_HT_CAP_LDPC_CODING | 913 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 914 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 915 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 916 IEEE80211_HT_CAP_DSSSCCK40 | 917 IEEE80211_HT_CAP_SGI_40; 918 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 919 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 920 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 921 if (efuse->hw_cap.nss > 1) { 922 ht_cap->mcs.rx_mask[0] = 0xFF; 923 ht_cap->mcs.rx_mask[1] = 0xFF; 924 ht_cap->mcs.rx_mask[4] = 0x01; 925 ht_cap->mcs.rx_highest = cpu_to_le16(300); 926 } else { 927 ht_cap->mcs.rx_mask[0] = 0xFF; 928 ht_cap->mcs.rx_mask[1] = 0x00; 929 ht_cap->mcs.rx_mask[4] = 0x01; 930 ht_cap->mcs.rx_highest = cpu_to_le16(150); 931 } 932 } 933 934 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 935 struct ieee80211_sta_vht_cap *vht_cap) 936 { 937 struct rtw_efuse *efuse = &rtwdev->efuse; 938 u16 mcs_map; 939 __le16 highest; 940 941 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 942 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 943 return; 944 945 vht_cap->vht_supported = true; 946 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 947 IEEE80211_VHT_CAP_RXLDPC | 948 IEEE80211_VHT_CAP_SHORT_GI_80 | 949 IEEE80211_VHT_CAP_TXSTBC | 950 IEEE80211_VHT_CAP_RXSTBC_1 | 951 IEEE80211_VHT_CAP_HTC_VHT | 952 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 953 0; 954 955 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 956 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 957 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 958 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 959 960 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 961 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 962 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 963 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 964 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 965 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 966 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 967 if (efuse->hw_cap.nss > 1) { 968 highest = cpu_to_le16(780); 969 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 970 } else { 971 highest = cpu_to_le16(390); 972 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 973 } 974 975 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 976 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 977 vht_cap->vht_mcs.rx_highest = highest; 978 vht_cap->vht_mcs.tx_highest = highest; 979 } 980 981 static void rtw_set_supported_band(struct ieee80211_hw *hw, 982 struct rtw_chip_info *chip) 983 { 984 struct rtw_dev *rtwdev = hw->priv; 985 struct ieee80211_supported_band *sband; 986 987 if (chip->band & RTW_BAND_2G) { 988 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 989 if (!sband) 990 goto err_out; 991 if (chip->ht_supported) 992 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 993 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 994 } 995 996 if (chip->band & RTW_BAND_5G) { 997 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 998 if (!sband) 999 goto err_out; 1000 if (chip->ht_supported) 1001 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1002 if (chip->vht_supported) 1003 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1004 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1005 } 1006 1007 return; 1008 1009 err_out: 1010 rtw_err(rtwdev, "failed to set supported band\n"); 1011 kfree(sband); 1012 } 1013 1014 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1015 struct rtw_chip_info *chip) 1016 { 1017 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1018 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1019 } 1020 1021 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1022 { 1023 struct rtw_dev *rtwdev = context; 1024 struct rtw_fw_state *fw = &rtwdev->fw; 1025 const struct rtw_fw_hdr *fw_hdr; 1026 1027 if (!firmware || !firmware->data) { 1028 rtw_err(rtwdev, "failed to request firmware\n"); 1029 complete_all(&fw->completion); 1030 return; 1031 } 1032 1033 fw_hdr = (const struct rtw_fw_hdr *)firmware->data; 1034 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1035 fw->version = le16_to_cpu(fw_hdr->version); 1036 fw->sub_version = fw_hdr->subversion; 1037 fw->sub_index = fw_hdr->subindex; 1038 1039 fw->firmware = firmware; 1040 complete_all(&fw->completion); 1041 1042 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1043 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1044 } 1045 1046 static int rtw_load_firmware(struct rtw_dev *rtwdev, const char *fw_name) 1047 { 1048 struct rtw_fw_state *fw = &rtwdev->fw; 1049 int ret; 1050 1051 init_completion(&fw->completion); 1052 1053 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1054 GFP_KERNEL, rtwdev, rtw_load_firmware_cb); 1055 if (ret) { 1056 rtw_err(rtwdev, "async firmware request failed\n"); 1057 return ret; 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1064 { 1065 struct rtw_chip_info *chip = rtwdev->chip; 1066 struct rtw_hal *hal = &rtwdev->hal; 1067 struct rtw_efuse *efuse = &rtwdev->efuse; 1068 int ret = 0; 1069 1070 switch (rtw_hci_type(rtwdev)) { 1071 case RTW_HCI_TYPE_PCIE: 1072 rtwdev->hci.rpwm_addr = 0x03d9; 1073 rtwdev->hci.cpwm_addr = 0x03da; 1074 break; 1075 default: 1076 rtw_err(rtwdev, "unsupported hci type\n"); 1077 return -EINVAL; 1078 } 1079 1080 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1081 hal->fab_version = BIT_GET_VENDOR_ID(hal->chip_version) >> 2; 1082 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1083 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1084 if (hal->chip_version & BIT_RF_TYPE_ID) { 1085 hal->rf_type = RF_2T2R; 1086 hal->rf_path_num = 2; 1087 hal->antenna_tx = BB_PATH_AB; 1088 hal->antenna_rx = BB_PATH_AB; 1089 } else { 1090 hal->rf_type = RF_1T1R; 1091 hal->rf_path_num = 1; 1092 hal->antenna_tx = BB_PATH_A; 1093 hal->antenna_rx = BB_PATH_A; 1094 } 1095 1096 if (hal->fab_version == 2) 1097 hal->fab_version = 1; 1098 else if (hal->fab_version == 1) 1099 hal->fab_version = 2; 1100 1101 efuse->physical_size = chip->phy_efuse_size; 1102 efuse->logical_size = chip->log_efuse_size; 1103 efuse->protect_size = chip->ptct_efuse_size; 1104 1105 /* default use ack */ 1106 rtwdev->hal.rcr |= BIT_VHT_DACK; 1107 1108 hal->bfee_sts_cap = 3; 1109 1110 return ret; 1111 } 1112 1113 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1114 { 1115 struct rtw_fw_state *fw = &rtwdev->fw; 1116 int ret; 1117 1118 ret = rtw_hci_setup(rtwdev); 1119 if (ret) { 1120 rtw_err(rtwdev, "failed to setup hci\n"); 1121 goto err; 1122 } 1123 1124 ret = rtw_mac_power_on(rtwdev); 1125 if (ret) { 1126 rtw_err(rtwdev, "failed to power on mac\n"); 1127 goto err; 1128 } 1129 1130 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1131 1132 wait_for_completion(&fw->completion); 1133 if (!fw->firmware) { 1134 ret = -EINVAL; 1135 rtw_err(rtwdev, "failed to load firmware\n"); 1136 goto err; 1137 } 1138 1139 ret = rtw_download_firmware(rtwdev, fw); 1140 if (ret) { 1141 rtw_err(rtwdev, "failed to download firmware\n"); 1142 goto err_off; 1143 } 1144 1145 return 0; 1146 1147 err_off: 1148 rtw_mac_power_off(rtwdev); 1149 1150 err: 1151 return ret; 1152 } 1153 1154 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1155 { 1156 struct rtw_efuse *efuse = &rtwdev->efuse; 1157 u8 hw_feature[HW_FEATURE_LEN]; 1158 u8 id; 1159 u8 bw; 1160 int i; 1161 1162 id = rtw_read8(rtwdev, REG_C2HEVT); 1163 if (id != C2H_HW_FEATURE_REPORT) { 1164 rtw_err(rtwdev, "failed to read hw feature report\n"); 1165 return -EBUSY; 1166 } 1167 1168 for (i = 0; i < HW_FEATURE_LEN; i++) 1169 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1170 1171 rtw_write8(rtwdev, REG_C2HEVT, 0); 1172 1173 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1174 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1175 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1176 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1177 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1178 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1179 1180 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1181 1182 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1183 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1184 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1185 1186 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1187 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1188 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1189 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1190 1191 return 0; 1192 } 1193 1194 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1195 { 1196 rtw_hci_stop(rtwdev); 1197 rtw_mac_power_off(rtwdev); 1198 } 1199 1200 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1201 { 1202 struct rtw_efuse *efuse = &rtwdev->efuse; 1203 int ret; 1204 1205 mutex_lock(&rtwdev->mutex); 1206 1207 /* power on mac to read efuse */ 1208 ret = rtw_chip_efuse_enable(rtwdev); 1209 if (ret) 1210 goto out_unlock; 1211 1212 ret = rtw_parse_efuse_map(rtwdev); 1213 if (ret) 1214 goto out_disable; 1215 1216 ret = rtw_dump_hw_feature(rtwdev); 1217 if (ret) 1218 goto out_disable; 1219 1220 ret = rtw_check_supported_rfe(rtwdev); 1221 if (ret) 1222 goto out_disable; 1223 1224 if (efuse->crystal_cap == 0xff) 1225 efuse->crystal_cap = 0; 1226 if (efuse->pa_type_2g == 0xff) 1227 efuse->pa_type_2g = 0; 1228 if (efuse->pa_type_5g == 0xff) 1229 efuse->pa_type_5g = 0; 1230 if (efuse->lna_type_2g == 0xff) 1231 efuse->lna_type_2g = 0; 1232 if (efuse->lna_type_5g == 0xff) 1233 efuse->lna_type_5g = 0; 1234 if (efuse->channel_plan == 0xff) 1235 efuse->channel_plan = 0x7f; 1236 if (efuse->rf_board_option == 0xff) 1237 efuse->rf_board_option = 0; 1238 if (efuse->bt_setting & BIT(0)) 1239 efuse->share_ant = true; 1240 if (efuse->regd == 0xff) 1241 efuse->regd = 0; 1242 1243 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1244 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1245 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1246 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1247 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1248 1249 out_disable: 1250 rtw_chip_efuse_disable(rtwdev); 1251 1252 out_unlock: 1253 mutex_unlock(&rtwdev->mutex); 1254 return ret; 1255 } 1256 1257 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1258 { 1259 struct rtw_hal *hal = &rtwdev->hal; 1260 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1261 1262 if (!rfe_def) 1263 return -ENODEV; 1264 1265 rtw_phy_setup_phy_cond(rtwdev, 0); 1266 1267 rtw_phy_init_tx_power(rtwdev); 1268 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1269 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1270 rtw_phy_tx_power_by_rate_config(hal); 1271 rtw_phy_tx_power_limit_config(hal); 1272 1273 return 0; 1274 } 1275 1276 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1277 { 1278 int ret; 1279 1280 ret = rtw_chip_parameter_setup(rtwdev); 1281 if (ret) { 1282 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1283 goto err_out; 1284 } 1285 1286 ret = rtw_chip_efuse_info_setup(rtwdev); 1287 if (ret) { 1288 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1289 goto err_out; 1290 } 1291 1292 ret = rtw_chip_board_info_setup(rtwdev); 1293 if (ret) { 1294 rtw_err(rtwdev, "failed to setup chip board info\n"); 1295 goto err_out; 1296 } 1297 1298 return 0; 1299 1300 err_out: 1301 return ret; 1302 } 1303 EXPORT_SYMBOL(rtw_chip_info_setup); 1304 1305 static void rtw_stats_init(struct rtw_dev *rtwdev) 1306 { 1307 struct rtw_traffic_stats *stats = &rtwdev->stats; 1308 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1309 int i; 1310 1311 ewma_tp_init(&stats->tx_ewma_tp); 1312 ewma_tp_init(&stats->rx_ewma_tp); 1313 1314 for (i = 0; i < RTW_EVM_NUM; i++) 1315 ewma_evm_init(&dm_info->ewma_evm[i]); 1316 for (i = 0; i < RTW_SNR_NUM; i++) 1317 ewma_snr_init(&dm_info->ewma_snr[i]); 1318 } 1319 1320 int rtw_core_init(struct rtw_dev *rtwdev) 1321 { 1322 struct rtw_chip_info *chip = rtwdev->chip; 1323 struct rtw_coex *coex = &rtwdev->coex; 1324 int ret; 1325 1326 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1327 INIT_LIST_HEAD(&rtwdev->txqs); 1328 1329 timer_setup(&rtwdev->tx_report.purge_timer, 1330 rtw_tx_report_purge_timer, 0); 1331 tasklet_init(&rtwdev->tx_tasklet, rtw_tx_tasklet, 1332 (unsigned long)rtwdev); 1333 1334 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1335 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1336 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1337 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1338 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1339 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1340 skb_queue_head_init(&rtwdev->c2h_queue); 1341 skb_queue_head_init(&rtwdev->coex.queue); 1342 skb_queue_head_init(&rtwdev->tx_report.queue); 1343 1344 spin_lock_init(&rtwdev->dm_lock); 1345 spin_lock_init(&rtwdev->rf_lock); 1346 spin_lock_init(&rtwdev->h2c.lock); 1347 spin_lock_init(&rtwdev->txq_lock); 1348 spin_lock_init(&rtwdev->tx_report.q_lock); 1349 1350 mutex_init(&rtwdev->mutex); 1351 mutex_init(&rtwdev->coex.mutex); 1352 mutex_init(&rtwdev->hal.tx_power_mutex); 1353 1354 init_waitqueue_head(&rtwdev->coex.wait); 1355 1356 rtwdev->sec.total_cam_num = 32; 1357 rtwdev->hal.current_channel = 1; 1358 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1359 if (!(BIT(rtw_fw_lps_deep_mode) & chip->lps_deep_mode_supported)) 1360 rtwdev->lps_conf.deep_mode = LPS_DEEP_MODE_NONE; 1361 else 1362 rtwdev->lps_conf.deep_mode = rtw_fw_lps_deep_mode; 1363 1364 mutex_lock(&rtwdev->mutex); 1365 rtw_add_rsvd_page(rtwdev, RSVD_BEACON, false); 1366 mutex_unlock(&rtwdev->mutex); 1367 1368 rtw_stats_init(rtwdev); 1369 1370 /* default rx filter setting */ 1371 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1372 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1373 BIT_AB | BIT_AM | BIT_APM; 1374 1375 ret = rtw_load_firmware(rtwdev, rtwdev->chip->fw_name); 1376 if (ret) { 1377 rtw_warn(rtwdev, "no firmware loaded\n"); 1378 return ret; 1379 } 1380 1381 return 0; 1382 } 1383 EXPORT_SYMBOL(rtw_core_init); 1384 1385 void rtw_core_deinit(struct rtw_dev *rtwdev) 1386 { 1387 struct rtw_fw_state *fw = &rtwdev->fw; 1388 struct rtw_rsvd_page *rsvd_pkt, *tmp; 1389 unsigned long flags; 1390 1391 if (fw->firmware) 1392 release_firmware(fw->firmware); 1393 1394 tasklet_kill(&rtwdev->tx_tasklet); 1395 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 1396 skb_queue_purge(&rtwdev->tx_report.queue); 1397 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 1398 1399 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, list) { 1400 list_del(&rsvd_pkt->list); 1401 kfree(rsvd_pkt); 1402 } 1403 1404 mutex_destroy(&rtwdev->mutex); 1405 mutex_destroy(&rtwdev->coex.mutex); 1406 mutex_destroy(&rtwdev->hal.tx_power_mutex); 1407 } 1408 EXPORT_SYMBOL(rtw_core_deinit); 1409 1410 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1411 { 1412 int max_tx_headroom = 0; 1413 int ret; 1414 1415 /* TODO: USB & SDIO may need extra room? */ 1416 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 1417 1418 hw->extra_tx_headroom = max_tx_headroom; 1419 hw->queues = IEEE80211_NUM_ACS; 1420 hw->txq_data_size = sizeof(struct rtw_txq); 1421 hw->sta_data_size = sizeof(struct rtw_sta_info); 1422 hw->vif_data_size = sizeof(struct rtw_vif); 1423 1424 ieee80211_hw_set(hw, SIGNAL_DBM); 1425 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 1426 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 1427 ieee80211_hw_set(hw, MFP_CAPABLE); 1428 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 1429 ieee80211_hw_set(hw, SUPPORTS_PS); 1430 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 1431 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 1432 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 1433 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 1434 ieee80211_hw_set(hw, TX_AMSDU); 1435 1436 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1437 BIT(NL80211_IFTYPE_AP) | 1438 BIT(NL80211_IFTYPE_ADHOC) | 1439 BIT(NL80211_IFTYPE_MESH_POINT); 1440 1441 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 1442 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 1443 1444 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 1445 1446 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 1447 1448 rtw_set_supported_band(hw, rtwdev->chip); 1449 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 1450 1451 rtw_regd_init(rtwdev, rtw_regd_notifier); 1452 1453 ret = ieee80211_register_hw(hw); 1454 if (ret) { 1455 rtw_err(rtwdev, "failed to register hw\n"); 1456 return ret; 1457 } 1458 1459 if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2)) 1460 rtw_err(rtwdev, "regulatory_hint fail\n"); 1461 1462 rtw_debugfs_init(rtwdev); 1463 1464 rtwdev->bf_info.bfer_mu_cnt = 0; 1465 rtwdev->bf_info.bfer_su_cnt = 0; 1466 1467 return 0; 1468 } 1469 EXPORT_SYMBOL(rtw_register_hw); 1470 1471 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1472 { 1473 struct rtw_chip_info *chip = rtwdev->chip; 1474 1475 ieee80211_unregister_hw(hw); 1476 rtw_unset_supported_band(hw, chip); 1477 } 1478 EXPORT_SYMBOL(rtw_unregister_hw); 1479 1480 MODULE_AUTHOR("Realtek Corporation"); 1481 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 1482 MODULE_LICENSE("Dual BSD/GPL"); 1483