1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 22 bool rtw_disable_lps_deep_mode; 23 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 24 bool rtw_bf_support = true; 25 unsigned int rtw_debug_mask; 26 EXPORT_SYMBOL(rtw_debug_mask); 27 /* EDCCA is enabled during normal behavior. For debugging purpose in 28 * a noisy environment, it can be disabled via edcca debugfs. Because 29 * all rtw88 devices will probably be affected if environment is noisy, 30 * rtw_edcca_enabled is just declared by driver instead of by device. 31 * So, turning it off will take effect for all rtw88 devices before 32 * there is a tough reason to maintain rtw_edcca_enabled by device. 33 */ 34 bool rtw_edcca_enabled = true; 35 36 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 37 module_param_named(support_bf, rtw_bf_support, bool, 0644); 38 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 39 40 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 41 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 42 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 43 44 static struct ieee80211_channel rtw_channeltable_2g[] = { 45 {.center_freq = 2412, .hw_value = 1,}, 46 {.center_freq = 2417, .hw_value = 2,}, 47 {.center_freq = 2422, .hw_value = 3,}, 48 {.center_freq = 2427, .hw_value = 4,}, 49 {.center_freq = 2432, .hw_value = 5,}, 50 {.center_freq = 2437, .hw_value = 6,}, 51 {.center_freq = 2442, .hw_value = 7,}, 52 {.center_freq = 2447, .hw_value = 8,}, 53 {.center_freq = 2452, .hw_value = 9,}, 54 {.center_freq = 2457, .hw_value = 10,}, 55 {.center_freq = 2462, .hw_value = 11,}, 56 {.center_freq = 2467, .hw_value = 12,}, 57 {.center_freq = 2472, .hw_value = 13,}, 58 {.center_freq = 2484, .hw_value = 14,}, 59 }; 60 61 static struct ieee80211_channel rtw_channeltable_5g[] = { 62 {.center_freq = 5180, .hw_value = 36,}, 63 {.center_freq = 5200, .hw_value = 40,}, 64 {.center_freq = 5220, .hw_value = 44,}, 65 {.center_freq = 5240, .hw_value = 48,}, 66 {.center_freq = 5260, .hw_value = 52,}, 67 {.center_freq = 5280, .hw_value = 56,}, 68 {.center_freq = 5300, .hw_value = 60,}, 69 {.center_freq = 5320, .hw_value = 64,}, 70 {.center_freq = 5500, .hw_value = 100,}, 71 {.center_freq = 5520, .hw_value = 104,}, 72 {.center_freq = 5540, .hw_value = 108,}, 73 {.center_freq = 5560, .hw_value = 112,}, 74 {.center_freq = 5580, .hw_value = 116,}, 75 {.center_freq = 5600, .hw_value = 120,}, 76 {.center_freq = 5620, .hw_value = 124,}, 77 {.center_freq = 5640, .hw_value = 128,}, 78 {.center_freq = 5660, .hw_value = 132,}, 79 {.center_freq = 5680, .hw_value = 136,}, 80 {.center_freq = 5700, .hw_value = 140,}, 81 {.center_freq = 5720, .hw_value = 144,}, 82 {.center_freq = 5745, .hw_value = 149,}, 83 {.center_freq = 5765, .hw_value = 153,}, 84 {.center_freq = 5785, .hw_value = 157,}, 85 {.center_freq = 5805, .hw_value = 161,}, 86 {.center_freq = 5825, .hw_value = 165, 87 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 88 }; 89 90 static struct ieee80211_rate rtw_ratetable[] = { 91 {.bitrate = 10, .hw_value = 0x00,}, 92 {.bitrate = 20, .hw_value = 0x01,}, 93 {.bitrate = 55, .hw_value = 0x02,}, 94 {.bitrate = 110, .hw_value = 0x03,}, 95 {.bitrate = 60, .hw_value = 0x04,}, 96 {.bitrate = 90, .hw_value = 0x05,}, 97 {.bitrate = 120, .hw_value = 0x06,}, 98 {.bitrate = 180, .hw_value = 0x07,}, 99 {.bitrate = 240, .hw_value = 0x08,}, 100 {.bitrate = 360, .hw_value = 0x09,}, 101 {.bitrate = 480, .hw_value = 0x0a,}, 102 {.bitrate = 540, .hw_value = 0x0b,}, 103 }; 104 105 u16 rtw_desc_to_bitrate(u8 desc_rate) 106 { 107 struct ieee80211_rate rate; 108 109 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 110 return 0; 111 112 rate = rtw_ratetable[desc_rate]; 113 114 return rate.bitrate; 115 } 116 117 static struct ieee80211_supported_band rtw_band_2ghz = { 118 .band = NL80211_BAND_2GHZ, 119 120 .channels = rtw_channeltable_2g, 121 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 122 123 .bitrates = rtw_ratetable, 124 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 125 126 .ht_cap = {0}, 127 .vht_cap = {0}, 128 }; 129 130 static struct ieee80211_supported_band rtw_band_5ghz = { 131 .band = NL80211_BAND_5GHZ, 132 133 .channels = rtw_channeltable_5g, 134 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 135 136 /* 5G has no CCK rates */ 137 .bitrates = rtw_ratetable + 4, 138 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 139 140 .ht_cap = {0}, 141 .vht_cap = {0}, 142 }; 143 144 struct rtw_watch_dog_iter_data { 145 struct rtw_dev *rtwdev; 146 struct rtw_vif *rtwvif; 147 }; 148 149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 150 { 151 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 152 u8 fix_rate_enable = 0; 153 u8 new_csi_rate_idx; 154 155 if (rtwvif->bfee.role != RTW_BFEE_SU && 156 rtwvif->bfee.role != RTW_BFEE_MU) 157 return; 158 159 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 160 bf_info->cur_csi_rpt_rate, 161 fix_rate_enable, &new_csi_rate_idx); 162 163 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 164 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 165 } 166 167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 168 struct ieee80211_vif *vif) 169 { 170 struct rtw_watch_dog_iter_data *iter_data = data; 171 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 172 173 if (vif->type == NL80211_IFTYPE_STATION) 174 if (vif->bss_conf.assoc) 175 iter_data->rtwvif = rtwvif; 176 177 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 178 179 rtwvif->stats.tx_unicast = 0; 180 rtwvif->stats.rx_unicast = 0; 181 rtwvif->stats.tx_cnt = 0; 182 rtwvif->stats.rx_cnt = 0; 183 } 184 185 /* process TX/RX statistics periodically for hardware, 186 * the information helps hardware to enhance performance 187 */ 188 static void rtw_watch_dog_work(struct work_struct *work) 189 { 190 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 191 watch_dog_work.work); 192 struct rtw_traffic_stats *stats = &rtwdev->stats; 193 struct rtw_watch_dog_iter_data data = {}; 194 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 195 bool ps_active; 196 197 mutex_lock(&rtwdev->mutex); 198 199 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 200 goto unlock; 201 202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 203 RTW_WATCH_DOG_DELAY_TIME); 204 205 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 206 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 207 else 208 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 209 210 rtw_coex_wl_status_check(rtwdev); 211 rtw_coex_query_bt_hid_list(rtwdev); 212 213 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 214 rtw_coex_wl_status_change_notify(rtwdev, 0); 215 216 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 217 stats->rx_cnt > RTW_LPS_THRESHOLD) 218 ps_active = true; 219 else 220 ps_active = false; 221 222 ewma_tp_add(&stats->tx_ewma_tp, 223 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 224 ewma_tp_add(&stats->rx_ewma_tp, 225 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 226 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 227 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 228 229 /* reset tx/rx statictics */ 230 stats->tx_unicast = 0; 231 stats->rx_unicast = 0; 232 stats->tx_cnt = 0; 233 stats->rx_cnt = 0; 234 235 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 236 goto unlock; 237 238 /* make sure BB/RF is working for dynamic mech */ 239 rtw_leave_lps(rtwdev); 240 241 rtw_phy_dynamic_mechanism(rtwdev); 242 243 data.rtwdev = rtwdev; 244 /* use atomic version to avoid taking local->iflist_mtx mutex */ 245 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 246 247 /* fw supports only one station associated to enter lps, if there are 248 * more than two stations associated to the AP, then we can not enter 249 * lps, because fw does not handle the overlapped beacon interval 250 * 251 * mac80211 should iterate vifs and determine if driver can enter 252 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 253 * get that vif and check if device is having traffic more than the 254 * threshold. 255 */ 256 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 257 !rtwdev->beacon_loss) 258 rtw_enter_lps(rtwdev, data.rtwvif->port); 259 260 rtwdev->watch_dog_cnt++; 261 262 unlock: 263 mutex_unlock(&rtwdev->mutex); 264 } 265 266 static void rtw_c2h_work(struct work_struct *work) 267 { 268 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 269 struct sk_buff *skb, *tmp; 270 271 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 272 skb_unlink(skb, &rtwdev->c2h_queue); 273 rtw_fw_c2h_cmd_handle(rtwdev, skb); 274 dev_kfree_skb_any(skb); 275 } 276 } 277 278 static void rtw_ips_work(struct work_struct *work) 279 { 280 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 281 282 mutex_lock(&rtwdev->mutex); 283 rtw_enter_ips(rtwdev); 284 mutex_unlock(&rtwdev->mutex); 285 } 286 287 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 288 { 289 unsigned long mac_id; 290 291 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 292 if (mac_id < RTW_MAX_MAC_ID_NUM) 293 set_bit(mac_id, rtwdev->mac_id_map); 294 295 return mac_id; 296 } 297 298 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 299 struct ieee80211_vif *vif) 300 { 301 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 302 int i; 303 304 si->mac_id = rtw_acquire_macid(rtwdev); 305 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 306 return -ENOSPC; 307 308 si->sta = sta; 309 si->vif = vif; 310 si->init_ra_lv = 1; 311 ewma_rssi_init(&si->avg_rssi); 312 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 313 rtw_txq_init(rtwdev, sta->txq[i]); 314 315 rtw_update_sta_info(rtwdev, si); 316 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 317 318 rtwdev->sta_cnt++; 319 rtwdev->beacon_loss = false; 320 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 321 sta->addr, si->mac_id); 322 323 return 0; 324 } 325 326 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 327 bool fw_exist) 328 { 329 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 330 int i; 331 332 rtw_release_macid(rtwdev, si->mac_id); 333 if (fw_exist) 334 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 335 336 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 337 rtw_txq_cleanup(rtwdev, sta->txq[i]); 338 339 kfree(si->mask); 340 341 rtwdev->sta_cnt--; 342 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 343 sta->addr, si->mac_id); 344 } 345 346 struct rtw_fwcd_hdr { 347 u32 item; 348 u32 size; 349 u32 padding1; 350 u32 padding2; 351 } __packed; 352 353 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 354 { 355 struct rtw_chip_info *chip = rtwdev->chip; 356 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 357 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 358 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 359 u8 i; 360 361 if (segs) { 362 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 363 364 for (i = 0; i < segs->num; i++) 365 prep_size += segs->segs[i]; 366 } 367 368 desc->data = vmalloc(prep_size); 369 if (!desc->data) 370 return -ENOMEM; 371 372 desc->size = prep_size; 373 desc->next = desc->data; 374 375 return 0; 376 } 377 378 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 379 { 380 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 381 struct rtw_fwcd_hdr *hdr; 382 u8 *next; 383 384 if (!desc->data) { 385 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 386 return NULL; 387 } 388 389 next = desc->next + sizeof(struct rtw_fwcd_hdr); 390 if (next - desc->data + size > desc->size) { 391 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 392 return NULL; 393 } 394 395 hdr = (struct rtw_fwcd_hdr *)(desc->next); 396 hdr->item = item; 397 hdr->size = size; 398 hdr->padding1 = 0x01234567; 399 hdr->padding2 = 0x89abcdef; 400 desc->next = next + size; 401 402 return next; 403 } 404 405 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 406 { 407 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 408 409 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 410 411 /* Data will be freed after lifetime of device coredump. After calling 412 * dev_coredump, data is supposed to be handled by the device coredump 413 * framework. Note that a new dump will be discarded if a previous one 414 * hasn't been released yet. 415 */ 416 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 417 } 418 419 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 420 { 421 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 422 423 if (free_self) { 424 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 425 vfree(desc->data); 426 } 427 428 desc->data = NULL; 429 desc->next = NULL; 430 } 431 432 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 433 { 434 u32 size = rtwdev->chip->fw_rxff_size; 435 u32 *buf; 436 u8 seq; 437 438 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 439 if (!buf) 440 return -ENOMEM; 441 442 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 443 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 444 return -EINVAL; 445 } 446 447 if (GET_FW_DUMP_LEN(buf) == 0) { 448 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 449 return -EINVAL; 450 } 451 452 seq = GET_FW_DUMP_SEQ(buf); 453 if (seq > 0) { 454 rtw_dbg(rtwdev, RTW_DBG_FW, 455 "fw crash dump's seq is wrong: %d\n", seq); 456 return -EINVAL; 457 } 458 459 return 0; 460 } 461 462 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 463 u32 fwcd_item) 464 { 465 u32 rxff = rtwdev->chip->fw_rxff_size; 466 u32 dump_size, done_size = 0; 467 u8 *buf; 468 int ret; 469 470 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 471 if (!buf) 472 return -ENOMEM; 473 474 while (size) { 475 dump_size = size > rxff ? rxff : size; 476 477 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 478 dump_size); 479 if (ret) { 480 rtw_err(rtwdev, 481 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 482 ocp_src, done_size); 483 return ret; 484 } 485 486 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 487 dump_size, (u32 *)(buf + done_size)); 488 if (ret) { 489 rtw_err(rtwdev, 490 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 491 ocp_src, done_size); 492 return ret; 493 } 494 495 size -= dump_size; 496 done_size += dump_size; 497 } 498 499 return 0; 500 } 501 EXPORT_SYMBOL(rtw_dump_fw); 502 503 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 504 { 505 u8 *buf; 506 u32 i; 507 508 if (addr & 0x3) { 509 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 510 return -EINVAL; 511 } 512 513 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 514 if (!buf) 515 return -ENOMEM; 516 517 for (i = 0; i < size; i += 4) 518 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 519 520 return 0; 521 } 522 EXPORT_SYMBOL(rtw_dump_reg); 523 524 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 525 struct ieee80211_bss_conf *conf) 526 { 527 if (conf && conf->assoc) { 528 rtwvif->aid = conf->aid; 529 rtwvif->net_type = RTW_NET_MGD_LINKED; 530 } else { 531 rtwvif->aid = 0; 532 rtwvif->net_type = RTW_NET_NO_LINK; 533 } 534 } 535 536 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 537 struct ieee80211_vif *vif, 538 struct ieee80211_sta *sta, 539 struct ieee80211_key_conf *key, 540 void *data) 541 { 542 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 543 struct rtw_sec_desc *sec = &rtwdev->sec; 544 545 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 546 } 547 548 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 549 { 550 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 551 552 if (rtwdev->sta_cnt == 0) { 553 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 554 return; 555 } 556 rtw_sta_remove(rtwdev, sta, false); 557 } 558 559 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 560 { 561 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 562 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 563 564 rtw_bf_disassoc(rtwdev, vif, NULL); 565 rtw_vif_assoc_changed(rtwvif, NULL); 566 rtw_txq_cleanup(rtwdev, vif->txq); 567 } 568 569 void rtw_fw_recovery(struct rtw_dev *rtwdev) 570 { 571 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 572 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 573 } 574 575 static void __fw_recovery_work(struct rtw_dev *rtwdev) 576 { 577 int ret = 0; 578 579 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 580 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 581 582 ret = rtw_fwcd_prep(rtwdev); 583 if (ret) 584 goto free; 585 ret = rtw_fw_dump_crash_log(rtwdev); 586 if (ret) 587 goto free; 588 ret = rtw_chip_dump_fw_crash(rtwdev); 589 if (ret) 590 goto free; 591 592 rtw_fwcd_dump(rtwdev); 593 free: 594 rtw_fwcd_free(rtwdev, !!ret); 595 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 596 597 WARN(1, "firmware crash, start reset and recover\n"); 598 599 rcu_read_lock(); 600 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 601 rcu_read_unlock(); 602 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 603 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 604 rtw_enter_ips(rtwdev); 605 } 606 607 static void rtw_fw_recovery_work(struct work_struct *work) 608 { 609 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 610 fw_recovery_work); 611 612 mutex_lock(&rtwdev->mutex); 613 __fw_recovery_work(rtwdev); 614 mutex_unlock(&rtwdev->mutex); 615 616 ieee80211_restart_hw(rtwdev->hw); 617 } 618 619 struct rtw_txq_ba_iter_data { 620 }; 621 622 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 623 { 624 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 625 int ret; 626 u8 tid; 627 628 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 629 while (tid != IEEE80211_NUM_TIDS) { 630 clear_bit(tid, si->tid_ba); 631 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 632 if (ret == -EINVAL) { 633 struct ieee80211_txq *txq; 634 struct rtw_txq *rtwtxq; 635 636 txq = sta->txq[tid]; 637 rtwtxq = (struct rtw_txq *)txq->drv_priv; 638 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 639 } 640 641 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 642 } 643 } 644 645 static void rtw_txq_ba_work(struct work_struct *work) 646 { 647 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 648 struct rtw_txq_ba_iter_data data; 649 650 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 651 } 652 653 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 654 { 655 if (IS_CH_2G_BAND(channel)) 656 pkt_stat->band = NL80211_BAND_2GHZ; 657 else if (IS_CH_5G_BAND(channel)) 658 pkt_stat->band = NL80211_BAND_5GHZ; 659 else 660 return; 661 662 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 663 } 664 EXPORT_SYMBOL(rtw_set_rx_freq_band); 665 666 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 667 struct rtw_channel_params *chan_params) 668 { 669 struct ieee80211_channel *channel = chandef->chan; 670 enum nl80211_chan_width width = chandef->width; 671 u8 *cch_by_bw = chan_params->cch_by_bw; 672 u32 primary_freq, center_freq; 673 u8 center_chan; 674 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 675 u8 primary_chan_idx = 0; 676 u8 i; 677 678 center_chan = channel->hw_value; 679 primary_freq = channel->center_freq; 680 center_freq = chandef->center_freq1; 681 682 /* assign the center channel used while 20M bw is selected */ 683 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 684 685 switch (width) { 686 case NL80211_CHAN_WIDTH_20_NOHT: 687 case NL80211_CHAN_WIDTH_20: 688 bandwidth = RTW_CHANNEL_WIDTH_20; 689 primary_chan_idx = RTW_SC_DONT_CARE; 690 break; 691 case NL80211_CHAN_WIDTH_40: 692 bandwidth = RTW_CHANNEL_WIDTH_40; 693 if (primary_freq > center_freq) { 694 primary_chan_idx = RTW_SC_20_UPPER; 695 center_chan -= 2; 696 } else { 697 primary_chan_idx = RTW_SC_20_LOWER; 698 center_chan += 2; 699 } 700 break; 701 case NL80211_CHAN_WIDTH_80: 702 bandwidth = RTW_CHANNEL_WIDTH_80; 703 if (primary_freq > center_freq) { 704 if (primary_freq - center_freq == 10) { 705 primary_chan_idx = RTW_SC_20_UPPER; 706 center_chan -= 2; 707 } else { 708 primary_chan_idx = RTW_SC_20_UPMOST; 709 center_chan -= 6; 710 } 711 /* assign the center channel used 712 * while 40M bw is selected 713 */ 714 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 715 } else { 716 if (center_freq - primary_freq == 10) { 717 primary_chan_idx = RTW_SC_20_LOWER; 718 center_chan += 2; 719 } else { 720 primary_chan_idx = RTW_SC_20_LOWEST; 721 center_chan += 6; 722 } 723 /* assign the center channel used 724 * while 40M bw is selected 725 */ 726 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 727 } 728 break; 729 default: 730 center_chan = 0; 731 break; 732 } 733 734 chan_params->center_chan = center_chan; 735 chan_params->bandwidth = bandwidth; 736 chan_params->primary_chan_idx = primary_chan_idx; 737 738 /* assign the center channel used while current bw is selected */ 739 cch_by_bw[bandwidth] = center_chan; 740 741 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 742 cch_by_bw[i] = 0; 743 } 744 745 void rtw_set_channel(struct rtw_dev *rtwdev) 746 { 747 struct ieee80211_hw *hw = rtwdev->hw; 748 struct rtw_hal *hal = &rtwdev->hal; 749 struct rtw_chip_info *chip = rtwdev->chip; 750 struct rtw_channel_params ch_param; 751 u8 center_chan, bandwidth, primary_chan_idx; 752 u8 i; 753 754 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 755 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 756 return; 757 758 center_chan = ch_param.center_chan; 759 bandwidth = ch_param.bandwidth; 760 primary_chan_idx = ch_param.primary_chan_idx; 761 762 hal->current_band_width = bandwidth; 763 hal->current_channel = center_chan; 764 hal->current_primary_channel_index = primary_chan_idx; 765 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 766 767 switch (center_chan) { 768 case 1 ... 14: 769 hal->sar_band = RTW_SAR_BAND_0; 770 break; 771 case 36 ... 64: 772 hal->sar_band = RTW_SAR_BAND_1; 773 break; 774 case 100 ... 144: 775 hal->sar_band = RTW_SAR_BAND_3; 776 break; 777 case 149 ... 177: 778 hal->sar_band = RTW_SAR_BAND_4; 779 break; 780 default: 781 WARN(1, "unknown ch(%u) to SAR band\n", center_chan); 782 hal->sar_band = RTW_SAR_BAND_0; 783 break; 784 } 785 786 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 787 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 788 789 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 790 791 if (hal->current_band_type == RTW_BAND_5G) { 792 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 793 } else { 794 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 795 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 796 else 797 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 798 } 799 800 rtw_phy_set_tx_power_level(rtwdev, center_chan); 801 802 /* if the channel isn't set for scanning, we will do RF calibration 803 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 804 * during scanning on each channel takes too long. 805 */ 806 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 807 rtwdev->need_rfk = true; 808 } 809 810 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 811 { 812 struct rtw_chip_info *chip = rtwdev->chip; 813 814 if (rtwdev->need_rfk) { 815 rtwdev->need_rfk = false; 816 chip->ops->phy_calibration(rtwdev); 817 } 818 } 819 820 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 821 { 822 int i; 823 824 for (i = 0; i < ETH_ALEN; i++) 825 rtw_write8(rtwdev, start + i, addr[i]); 826 } 827 828 void rtw_vif_port_config(struct rtw_dev *rtwdev, 829 struct rtw_vif *rtwvif, 830 u32 config) 831 { 832 u32 addr, mask; 833 834 if (config & PORT_SET_MAC_ADDR) { 835 addr = rtwvif->conf->mac_addr.addr; 836 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 837 } 838 if (config & PORT_SET_BSSID) { 839 addr = rtwvif->conf->bssid.addr; 840 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 841 } 842 if (config & PORT_SET_NET_TYPE) { 843 addr = rtwvif->conf->net_type.addr; 844 mask = rtwvif->conf->net_type.mask; 845 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 846 } 847 if (config & PORT_SET_AID) { 848 addr = rtwvif->conf->aid.addr; 849 mask = rtwvif->conf->aid.mask; 850 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 851 } 852 if (config & PORT_SET_BCN_CTRL) { 853 addr = rtwvif->conf->bcn_ctrl.addr; 854 mask = rtwvif->conf->bcn_ctrl.mask; 855 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 856 } 857 } 858 859 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 860 { 861 u8 bw = 0; 862 863 switch (bw_cap) { 864 case EFUSE_HW_CAP_IGNORE: 865 case EFUSE_HW_CAP_SUPP_BW80: 866 bw |= BIT(RTW_CHANNEL_WIDTH_80); 867 fallthrough; 868 case EFUSE_HW_CAP_SUPP_BW40: 869 bw |= BIT(RTW_CHANNEL_WIDTH_40); 870 fallthrough; 871 default: 872 bw |= BIT(RTW_CHANNEL_WIDTH_20); 873 break; 874 } 875 876 return bw; 877 } 878 879 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 880 { 881 struct rtw_hal *hal = &rtwdev->hal; 882 struct rtw_chip_info *chip = rtwdev->chip; 883 884 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 885 hw_ant_num >= hal->rf_path_num) 886 return; 887 888 switch (hw_ant_num) { 889 case 1: 890 hal->rf_type = RF_1T1R; 891 hal->rf_path_num = 1; 892 if (!chip->fix_rf_phy_num) 893 hal->rf_phy_num = hal->rf_path_num; 894 hal->antenna_tx = BB_PATH_A; 895 hal->antenna_rx = BB_PATH_A; 896 break; 897 default: 898 WARN(1, "invalid hw configuration from efuse\n"); 899 break; 900 } 901 } 902 903 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 904 { 905 u64 ra_mask = 0; 906 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 907 u8 vht_mcs_cap; 908 int i, nss; 909 910 /* 4SS, every two bits for MCS7/8/9 */ 911 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 912 vht_mcs_cap = mcs_map & 0x3; 913 switch (vht_mcs_cap) { 914 case 2: /* MCS9 */ 915 ra_mask |= 0x3ffULL << nss; 916 break; 917 case 1: /* MCS8 */ 918 ra_mask |= 0x1ffULL << nss; 919 break; 920 case 0: /* MCS7 */ 921 ra_mask |= 0x0ffULL << nss; 922 break; 923 default: 924 break; 925 } 926 } 927 928 return ra_mask; 929 } 930 931 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 932 { 933 u8 rate_id = 0; 934 935 switch (wireless_set) { 936 case WIRELESS_CCK: 937 rate_id = RTW_RATEID_B_20M; 938 break; 939 case WIRELESS_OFDM: 940 rate_id = RTW_RATEID_G; 941 break; 942 case WIRELESS_CCK | WIRELESS_OFDM: 943 rate_id = RTW_RATEID_BG; 944 break; 945 case WIRELESS_OFDM | WIRELESS_HT: 946 if (tx_num == 1) 947 rate_id = RTW_RATEID_GN_N1SS; 948 else if (tx_num == 2) 949 rate_id = RTW_RATEID_GN_N2SS; 950 else if (tx_num == 3) 951 rate_id = RTW_RATEID_ARFR5_N_3SS; 952 break; 953 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 954 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 955 if (tx_num == 1) 956 rate_id = RTW_RATEID_BGN_40M_1SS; 957 else if (tx_num == 2) 958 rate_id = RTW_RATEID_BGN_40M_2SS; 959 else if (tx_num == 3) 960 rate_id = RTW_RATEID_ARFR5_N_3SS; 961 else if (tx_num == 4) 962 rate_id = RTW_RATEID_ARFR7_N_4SS; 963 } else { 964 if (tx_num == 1) 965 rate_id = RTW_RATEID_BGN_20M_1SS; 966 else if (tx_num == 2) 967 rate_id = RTW_RATEID_BGN_20M_2SS; 968 else if (tx_num == 3) 969 rate_id = RTW_RATEID_ARFR5_N_3SS; 970 else if (tx_num == 4) 971 rate_id = RTW_RATEID_ARFR7_N_4SS; 972 } 973 break; 974 case WIRELESS_OFDM | WIRELESS_VHT: 975 if (tx_num == 1) 976 rate_id = RTW_RATEID_ARFR1_AC_1SS; 977 else if (tx_num == 2) 978 rate_id = RTW_RATEID_ARFR0_AC_2SS; 979 else if (tx_num == 3) 980 rate_id = RTW_RATEID_ARFR4_AC_3SS; 981 else if (tx_num == 4) 982 rate_id = RTW_RATEID_ARFR6_AC_4SS; 983 break; 984 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 985 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 986 if (tx_num == 1) 987 rate_id = RTW_RATEID_ARFR1_AC_1SS; 988 else if (tx_num == 2) 989 rate_id = RTW_RATEID_ARFR0_AC_2SS; 990 else if (tx_num == 3) 991 rate_id = RTW_RATEID_ARFR4_AC_3SS; 992 else if (tx_num == 4) 993 rate_id = RTW_RATEID_ARFR6_AC_4SS; 994 } else { 995 if (tx_num == 1) 996 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 997 else if (tx_num == 2) 998 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 999 else if (tx_num == 3) 1000 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1001 else if (tx_num == 4) 1002 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1003 } 1004 break; 1005 default: 1006 break; 1007 } 1008 1009 return rate_id; 1010 } 1011 1012 #define RA_MASK_CCK_RATES 0x0000f 1013 #define RA_MASK_OFDM_RATES 0x00ff0 1014 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1015 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1016 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1017 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1018 RA_MASK_HT_RATES_2SS | \ 1019 RA_MASK_HT_RATES_3SS) 1020 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1021 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1022 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1023 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1024 RA_MASK_VHT_RATES_2SS | \ 1025 RA_MASK_VHT_RATES_3SS) 1026 #define RA_MASK_CCK_IN_BG 0x00005 1027 #define RA_MASK_CCK_IN_HT 0x00005 1028 #define RA_MASK_CCK_IN_VHT 0x00005 1029 #define RA_MASK_OFDM_IN_VHT 0x00010 1030 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1031 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1032 1033 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1034 { 1035 u8 rssi_level = si->rssi_level; 1036 1037 if (wireless_set == WIRELESS_CCK) 1038 return 0xffffffffffffffffULL; 1039 1040 if (rssi_level == 0) 1041 return 0xffffffffffffffffULL; 1042 else if (rssi_level == 1) 1043 return 0xfffffffffffffff0ULL; 1044 else if (rssi_level == 2) 1045 return 0xffffffffffffefe0ULL; 1046 else if (rssi_level == 3) 1047 return 0xffffffffffffcfc0ULL; 1048 else if (rssi_level == 4) 1049 return 0xffffffffffff8f80ULL; 1050 else 1051 return 0xffffffffffff0f00ULL; 1052 } 1053 1054 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1055 { 1056 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1057 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1058 1059 if (ra_mask == 0) 1060 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1061 1062 return ra_mask; 1063 } 1064 1065 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1066 u64 ra_mask, bool is_vht_enable) 1067 { 1068 struct rtw_hal *hal = &rtwdev->hal; 1069 const struct cfg80211_bitrate_mask *mask = si->mask; 1070 u64 cfg_mask = GENMASK_ULL(63, 0); 1071 u8 band; 1072 1073 if (!si->use_cfg_mask) 1074 return ra_mask; 1075 1076 band = hal->current_band_type; 1077 if (band == RTW_BAND_2G) { 1078 band = NL80211_BAND_2GHZ; 1079 cfg_mask = mask->control[band].legacy; 1080 } else if (band == RTW_BAND_5G) { 1081 band = NL80211_BAND_5GHZ; 1082 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1083 RA_MASK_OFDM_RATES); 1084 } 1085 1086 if (!is_vht_enable) { 1087 if (ra_mask & RA_MASK_HT_RATES_1SS) 1088 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1089 RA_MASK_HT_RATES_1SS); 1090 if (ra_mask & RA_MASK_HT_RATES_2SS) 1091 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1092 RA_MASK_HT_RATES_2SS); 1093 } else { 1094 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1095 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1096 RA_MASK_VHT_RATES_1SS); 1097 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1098 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1099 RA_MASK_VHT_RATES_2SS); 1100 } 1101 1102 ra_mask &= cfg_mask; 1103 1104 return ra_mask; 1105 } 1106 1107 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 1108 { 1109 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1110 struct ieee80211_sta *sta = si->sta; 1111 struct rtw_efuse *efuse = &rtwdev->efuse; 1112 struct rtw_hal *hal = &rtwdev->hal; 1113 u8 wireless_set; 1114 u8 bw_mode; 1115 u8 rate_id; 1116 u8 rf_type = RF_1T1R; 1117 u8 stbc_en = 0; 1118 u8 ldpc_en = 0; 1119 u8 tx_num = 1; 1120 u64 ra_mask = 0; 1121 u64 ra_mask_bak = 0; 1122 bool is_vht_enable = false; 1123 bool is_support_sgi = false; 1124 1125 if (sta->vht_cap.vht_supported) { 1126 is_vht_enable = true; 1127 ra_mask |= get_vht_ra_mask(sta); 1128 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1129 stbc_en = VHT_STBC_EN; 1130 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1131 ldpc_en = VHT_LDPC_EN; 1132 } else if (sta->ht_cap.ht_supported) { 1133 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 1134 (sta->ht_cap.mcs.rx_mask[0] << 12); 1135 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1136 stbc_en = HT_STBC_EN; 1137 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1138 ldpc_en = HT_LDPC_EN; 1139 } 1140 1141 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1142 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1143 1144 if (hal->current_band_type == RTW_BAND_5G) { 1145 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 1146 ra_mask_bak = ra_mask; 1147 if (sta->vht_cap.vht_supported) { 1148 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1149 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1150 } else if (sta->ht_cap.ht_supported) { 1151 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1152 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1153 } else { 1154 wireless_set = WIRELESS_OFDM; 1155 } 1156 dm_info->rrsr_val_init = RRSR_INIT_5G; 1157 } else if (hal->current_band_type == RTW_BAND_2G) { 1158 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 1159 ra_mask_bak = ra_mask; 1160 if (sta->vht_cap.vht_supported) { 1161 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1162 RA_MASK_OFDM_IN_VHT; 1163 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1164 WIRELESS_HT | WIRELESS_VHT; 1165 } else if (sta->ht_cap.ht_supported) { 1166 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1167 RA_MASK_OFDM_IN_HT_2G; 1168 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1169 WIRELESS_HT; 1170 } else if (sta->supp_rates[0] <= 0xf) { 1171 wireless_set = WIRELESS_CCK; 1172 } else { 1173 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1174 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1175 } 1176 dm_info->rrsr_val_init = RRSR_INIT_2G; 1177 } else { 1178 rtw_err(rtwdev, "Unknown band type\n"); 1179 ra_mask_bak = ra_mask; 1180 wireless_set = 0; 1181 } 1182 1183 switch (sta->bandwidth) { 1184 case IEEE80211_STA_RX_BW_80: 1185 bw_mode = RTW_CHANNEL_WIDTH_80; 1186 is_support_sgi = sta->vht_cap.vht_supported && 1187 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1188 break; 1189 case IEEE80211_STA_RX_BW_40: 1190 bw_mode = RTW_CHANNEL_WIDTH_40; 1191 is_support_sgi = sta->ht_cap.ht_supported && 1192 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1193 break; 1194 default: 1195 bw_mode = RTW_CHANNEL_WIDTH_20; 1196 is_support_sgi = sta->ht_cap.ht_supported && 1197 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1198 break; 1199 } 1200 1201 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 1202 tx_num = 2; 1203 rf_type = RF_2T2R; 1204 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 1205 tx_num = 2; 1206 rf_type = RF_2T2R; 1207 } 1208 1209 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1210 1211 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1212 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1213 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1214 1215 si->bw_mode = bw_mode; 1216 si->stbc_en = stbc_en; 1217 si->ldpc_en = ldpc_en; 1218 si->rf_type = rf_type; 1219 si->wireless_set = wireless_set; 1220 si->sgi_enable = is_support_sgi; 1221 si->vht_enable = is_vht_enable; 1222 si->ra_mask = ra_mask; 1223 si->rate_id = rate_id; 1224 1225 rtw_fw_send_ra_info(rtwdev, si); 1226 } 1227 1228 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1229 { 1230 struct rtw_chip_info *chip = rtwdev->chip; 1231 struct rtw_fw_state *fw; 1232 1233 fw = &rtwdev->fw; 1234 wait_for_completion(&fw->completion); 1235 if (!fw->firmware) 1236 return -EINVAL; 1237 1238 if (chip->wow_fw_name) { 1239 fw = &rtwdev->wow_fw; 1240 wait_for_completion(&fw->completion); 1241 if (!fw->firmware) 1242 return -EINVAL; 1243 } 1244 1245 return 0; 1246 } 1247 1248 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1249 struct rtw_fw_state *fw) 1250 { 1251 struct rtw_chip_info *chip = rtwdev->chip; 1252 1253 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1254 !fw->feature) 1255 return LPS_DEEP_MODE_NONE; 1256 1257 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1258 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1259 return LPS_DEEP_MODE_PG; 1260 1261 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1262 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1263 return LPS_DEEP_MODE_LCLK; 1264 1265 return LPS_DEEP_MODE_NONE; 1266 } 1267 1268 static int rtw_power_on(struct rtw_dev *rtwdev) 1269 { 1270 struct rtw_chip_info *chip = rtwdev->chip; 1271 struct rtw_fw_state *fw = &rtwdev->fw; 1272 bool wifi_only; 1273 int ret; 1274 1275 ret = rtw_hci_setup(rtwdev); 1276 if (ret) { 1277 rtw_err(rtwdev, "failed to setup hci\n"); 1278 goto err; 1279 } 1280 1281 /* power on MAC before firmware downloaded */ 1282 ret = rtw_mac_power_on(rtwdev); 1283 if (ret) { 1284 rtw_err(rtwdev, "failed to power on mac\n"); 1285 goto err; 1286 } 1287 1288 ret = rtw_wait_firmware_completion(rtwdev); 1289 if (ret) { 1290 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1291 goto err_off; 1292 } 1293 1294 ret = rtw_download_firmware(rtwdev, fw); 1295 if (ret) { 1296 rtw_err(rtwdev, "failed to download firmware\n"); 1297 goto err_off; 1298 } 1299 1300 /* config mac after firmware downloaded */ 1301 ret = rtw_mac_init(rtwdev); 1302 if (ret) { 1303 rtw_err(rtwdev, "failed to configure mac\n"); 1304 goto err_off; 1305 } 1306 1307 chip->ops->phy_set_param(rtwdev); 1308 1309 ret = rtw_hci_start(rtwdev); 1310 if (ret) { 1311 rtw_err(rtwdev, "failed to start hci\n"); 1312 goto err_off; 1313 } 1314 1315 /* send H2C after HCI has started */ 1316 rtw_fw_send_general_info(rtwdev); 1317 rtw_fw_send_phydm_info(rtwdev); 1318 1319 wifi_only = !rtwdev->efuse.btcoex; 1320 rtw_coex_power_on_setting(rtwdev); 1321 rtw_coex_init_hw_config(rtwdev, wifi_only); 1322 1323 return 0; 1324 1325 err_off: 1326 rtw_mac_power_off(rtwdev); 1327 1328 err: 1329 return ret; 1330 } 1331 1332 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1333 { 1334 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1335 return; 1336 1337 if (start) { 1338 rtw_fw_scan_notify(rtwdev, true); 1339 } else { 1340 reinit_completion(&rtwdev->fw_scan_density); 1341 rtw_fw_scan_notify(rtwdev, false); 1342 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1343 SCAN_NOTIFY_TIMEOUT)) 1344 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1345 } 1346 } 1347 1348 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1349 const u8 *mac_addr, bool hw_scan) 1350 { 1351 u32 config = 0; 1352 int ret = 0; 1353 1354 rtw_leave_lps(rtwdev); 1355 1356 if (hw_scan && rtwvif->net_type == RTW_NET_NO_LINK) { 1357 ret = rtw_leave_ips(rtwdev); 1358 if (ret) { 1359 rtw_err(rtwdev, "failed to leave idle state\n"); 1360 return; 1361 } 1362 } 1363 1364 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1365 config |= PORT_SET_MAC_ADDR; 1366 rtw_vif_port_config(rtwdev, rtwvif, config); 1367 1368 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1369 rtw_core_fw_scan_notify(rtwdev, true); 1370 1371 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1372 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1373 } 1374 1375 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1376 bool hw_scan) 1377 { 1378 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 1379 u32 config = 0; 1380 1381 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1382 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1383 1384 rtw_core_fw_scan_notify(rtwdev, false); 1385 1386 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1387 config |= PORT_SET_MAC_ADDR; 1388 rtw_vif_port_config(rtwdev, rtwvif, config); 1389 1390 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1391 1392 if (rtwvif->net_type == RTW_NET_NO_LINK && hw_scan) 1393 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1394 } 1395 1396 int rtw_core_start(struct rtw_dev *rtwdev) 1397 { 1398 int ret; 1399 1400 ret = rtw_power_on(rtwdev); 1401 if (ret) 1402 return ret; 1403 1404 rtw_sec_enable_sec_engine(rtwdev); 1405 1406 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1407 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1408 1409 /* rcr reset after powered on */ 1410 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1411 1412 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1413 RTW_WATCH_DOG_DELAY_TIME); 1414 1415 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1416 1417 return 0; 1418 } 1419 1420 static void rtw_power_off(struct rtw_dev *rtwdev) 1421 { 1422 rtw_hci_stop(rtwdev); 1423 rtw_coex_power_off_setting(rtwdev); 1424 rtw_mac_power_off(rtwdev); 1425 } 1426 1427 void rtw_core_stop(struct rtw_dev *rtwdev) 1428 { 1429 struct rtw_coex *coex = &rtwdev->coex; 1430 1431 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1432 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1433 1434 mutex_unlock(&rtwdev->mutex); 1435 1436 cancel_work_sync(&rtwdev->c2h_work); 1437 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1438 cancel_delayed_work_sync(&coex->bt_relink_work); 1439 cancel_delayed_work_sync(&coex->bt_reenable_work); 1440 cancel_delayed_work_sync(&coex->defreeze_work); 1441 cancel_delayed_work_sync(&coex->wl_remain_work); 1442 cancel_delayed_work_sync(&coex->bt_remain_work); 1443 cancel_delayed_work_sync(&coex->wl_connecting_work); 1444 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1445 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1446 1447 mutex_lock(&rtwdev->mutex); 1448 1449 rtw_power_off(rtwdev); 1450 } 1451 1452 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1453 struct ieee80211_sta_ht_cap *ht_cap) 1454 { 1455 struct rtw_efuse *efuse = &rtwdev->efuse; 1456 1457 ht_cap->ht_supported = true; 1458 ht_cap->cap = 0; 1459 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1460 IEEE80211_HT_CAP_MAX_AMSDU | 1461 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1462 1463 if (rtw_chip_has_rx_ldpc(rtwdev)) 1464 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1465 if (rtw_chip_has_tx_stbc(rtwdev)) 1466 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1467 1468 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1469 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1470 IEEE80211_HT_CAP_DSSSCCK40 | 1471 IEEE80211_HT_CAP_SGI_40; 1472 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1473 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 1474 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1475 if (efuse->hw_cap.nss > 1) { 1476 ht_cap->mcs.rx_mask[0] = 0xFF; 1477 ht_cap->mcs.rx_mask[1] = 0xFF; 1478 ht_cap->mcs.rx_mask[4] = 0x01; 1479 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1480 } else { 1481 ht_cap->mcs.rx_mask[0] = 0xFF; 1482 ht_cap->mcs.rx_mask[1] = 0x00; 1483 ht_cap->mcs.rx_mask[4] = 0x01; 1484 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1485 } 1486 } 1487 1488 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1489 struct ieee80211_sta_vht_cap *vht_cap) 1490 { 1491 struct rtw_efuse *efuse = &rtwdev->efuse; 1492 u16 mcs_map; 1493 __le16 highest; 1494 1495 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1496 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1497 return; 1498 1499 vht_cap->vht_supported = true; 1500 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1501 IEEE80211_VHT_CAP_SHORT_GI_80 | 1502 IEEE80211_VHT_CAP_RXSTBC_1 | 1503 IEEE80211_VHT_CAP_HTC_VHT | 1504 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1505 0; 1506 if (rtwdev->hal.rf_path_num > 1) 1507 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1508 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1509 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1510 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1511 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1512 1513 if (rtw_chip_has_rx_ldpc(rtwdev)) 1514 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1515 1516 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1517 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1520 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1521 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1522 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1523 if (efuse->hw_cap.nss > 1) { 1524 highest = cpu_to_le16(780); 1525 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1526 } else { 1527 highest = cpu_to_le16(390); 1528 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1529 } 1530 1531 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1532 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1533 vht_cap->vht_mcs.rx_highest = highest; 1534 vht_cap->vht_mcs.tx_highest = highest; 1535 } 1536 1537 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1538 struct rtw_chip_info *chip) 1539 { 1540 struct rtw_dev *rtwdev = hw->priv; 1541 struct ieee80211_supported_band *sband; 1542 1543 if (chip->band & RTW_BAND_2G) { 1544 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1545 if (!sband) 1546 goto err_out; 1547 if (chip->ht_supported) 1548 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1549 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1550 } 1551 1552 if (chip->band & RTW_BAND_5G) { 1553 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1554 if (!sband) 1555 goto err_out; 1556 if (chip->ht_supported) 1557 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1558 if (chip->vht_supported) 1559 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1560 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1561 } 1562 1563 return; 1564 1565 err_out: 1566 rtw_err(rtwdev, "failed to set supported band\n"); 1567 } 1568 1569 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1570 struct rtw_chip_info *chip) 1571 { 1572 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1573 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1574 } 1575 1576 static void rtw_vif_smps_iter(void *data, u8 *mac, 1577 struct ieee80211_vif *vif) 1578 { 1579 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1580 1581 if (vif->type != NL80211_IFTYPE_STATION || !vif->bss_conf.assoc) 1582 return; 1583 1584 if (rtwdev->hal.txrx_1ss) 1585 ieee80211_request_smps(vif, IEEE80211_SMPS_STATIC); 1586 else 1587 ieee80211_request_smps(vif, IEEE80211_SMPS_OFF); 1588 } 1589 1590 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1591 { 1592 struct rtw_chip_info *chip = rtwdev->chip; 1593 struct rtw_hal *hal = &rtwdev->hal; 1594 1595 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1596 return; 1597 1598 rtwdev->hal.txrx_1ss = txrx_1ss; 1599 if (txrx_1ss) 1600 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1601 else 1602 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1603 hal->antenna_rx, false); 1604 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1605 } 1606 1607 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1608 struct rtw_fw_state *fw) 1609 { 1610 u32 feature; 1611 const struct rtw_fw_hdr *fw_hdr = 1612 (const struct rtw_fw_hdr *)fw->firmware->data; 1613 1614 feature = le32_to_cpu(fw_hdr->feature); 1615 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1616 } 1617 1618 static void __update_firmware_info(struct rtw_dev *rtwdev, 1619 struct rtw_fw_state *fw) 1620 { 1621 const struct rtw_fw_hdr *fw_hdr = 1622 (const struct rtw_fw_hdr *)fw->firmware->data; 1623 1624 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1625 fw->version = le16_to_cpu(fw_hdr->version); 1626 fw->sub_version = fw_hdr->subversion; 1627 fw->sub_index = fw_hdr->subindex; 1628 1629 __update_firmware_feature(rtwdev, fw); 1630 } 1631 1632 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1633 struct rtw_fw_state *fw) 1634 { 1635 struct rtw_fw_hdr_legacy *legacy = 1636 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1637 1638 fw->h2c_version = 0; 1639 fw->version = le16_to_cpu(legacy->version); 1640 fw->sub_version = legacy->subversion1; 1641 fw->sub_index = legacy->subversion2; 1642 } 1643 1644 static void update_firmware_info(struct rtw_dev *rtwdev, 1645 struct rtw_fw_state *fw) 1646 { 1647 if (rtw_chip_wcpu_11n(rtwdev)) 1648 __update_firmware_info_legacy(rtwdev, fw); 1649 else 1650 __update_firmware_info(rtwdev, fw); 1651 } 1652 1653 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1654 { 1655 struct rtw_fw_state *fw = context; 1656 struct rtw_dev *rtwdev = fw->rtwdev; 1657 1658 if (!firmware || !firmware->data) { 1659 rtw_err(rtwdev, "failed to request firmware\n"); 1660 complete_all(&fw->completion); 1661 return; 1662 } 1663 1664 fw->firmware = firmware; 1665 update_firmware_info(rtwdev, fw); 1666 complete_all(&fw->completion); 1667 1668 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1669 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1670 } 1671 1672 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1673 { 1674 const char *fw_name; 1675 struct rtw_fw_state *fw; 1676 int ret; 1677 1678 switch (type) { 1679 case RTW_WOWLAN_FW: 1680 fw = &rtwdev->wow_fw; 1681 fw_name = rtwdev->chip->wow_fw_name; 1682 break; 1683 1684 case RTW_NORMAL_FW: 1685 fw = &rtwdev->fw; 1686 fw_name = rtwdev->chip->fw_name; 1687 break; 1688 1689 default: 1690 rtw_warn(rtwdev, "unsupported firmware type\n"); 1691 return -ENOENT; 1692 } 1693 1694 fw->rtwdev = rtwdev; 1695 init_completion(&fw->completion); 1696 1697 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1698 GFP_KERNEL, fw, rtw_load_firmware_cb); 1699 if (ret) { 1700 rtw_err(rtwdev, "failed to async firmware request\n"); 1701 return ret; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1708 { 1709 struct rtw_chip_info *chip = rtwdev->chip; 1710 struct rtw_hal *hal = &rtwdev->hal; 1711 struct rtw_efuse *efuse = &rtwdev->efuse; 1712 1713 switch (rtw_hci_type(rtwdev)) { 1714 case RTW_HCI_TYPE_PCIE: 1715 rtwdev->hci.rpwm_addr = 0x03d9; 1716 rtwdev->hci.cpwm_addr = 0x03da; 1717 break; 1718 default: 1719 rtw_err(rtwdev, "unsupported hci type\n"); 1720 return -EINVAL; 1721 } 1722 1723 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1724 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1725 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1726 if (hal->chip_version & BIT_RF_TYPE_ID) { 1727 hal->rf_type = RF_2T2R; 1728 hal->rf_path_num = 2; 1729 hal->antenna_tx = BB_PATH_AB; 1730 hal->antenna_rx = BB_PATH_AB; 1731 } else { 1732 hal->rf_type = RF_1T1R; 1733 hal->rf_path_num = 1; 1734 hal->antenna_tx = BB_PATH_A; 1735 hal->antenna_rx = BB_PATH_A; 1736 } 1737 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1738 hal->rf_path_num; 1739 1740 efuse->physical_size = chip->phy_efuse_size; 1741 efuse->logical_size = chip->log_efuse_size; 1742 efuse->protect_size = chip->ptct_efuse_size; 1743 1744 /* default use ack */ 1745 rtwdev->hal.rcr |= BIT_VHT_DACK; 1746 1747 hal->bfee_sts_cap = 3; 1748 1749 return 0; 1750 } 1751 1752 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1753 { 1754 struct rtw_fw_state *fw = &rtwdev->fw; 1755 int ret; 1756 1757 ret = rtw_hci_setup(rtwdev); 1758 if (ret) { 1759 rtw_err(rtwdev, "failed to setup hci\n"); 1760 goto err; 1761 } 1762 1763 ret = rtw_mac_power_on(rtwdev); 1764 if (ret) { 1765 rtw_err(rtwdev, "failed to power on mac\n"); 1766 goto err; 1767 } 1768 1769 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1770 1771 wait_for_completion(&fw->completion); 1772 if (!fw->firmware) { 1773 ret = -EINVAL; 1774 rtw_err(rtwdev, "failed to load firmware\n"); 1775 goto err; 1776 } 1777 1778 ret = rtw_download_firmware(rtwdev, fw); 1779 if (ret) { 1780 rtw_err(rtwdev, "failed to download firmware\n"); 1781 goto err_off; 1782 } 1783 1784 return 0; 1785 1786 err_off: 1787 rtw_mac_power_off(rtwdev); 1788 1789 err: 1790 return ret; 1791 } 1792 1793 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1794 { 1795 struct rtw_efuse *efuse = &rtwdev->efuse; 1796 u8 hw_feature[HW_FEATURE_LEN]; 1797 u8 id; 1798 u8 bw; 1799 int i; 1800 1801 id = rtw_read8(rtwdev, REG_C2HEVT); 1802 if (id != C2H_HW_FEATURE_REPORT) { 1803 rtw_err(rtwdev, "failed to read hw feature report\n"); 1804 return -EBUSY; 1805 } 1806 1807 for (i = 0; i < HW_FEATURE_LEN; i++) 1808 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1809 1810 rtw_write8(rtwdev, REG_C2HEVT, 0); 1811 1812 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1813 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1814 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1815 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1816 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1817 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1818 1819 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1820 1821 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1822 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1823 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1824 1825 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1826 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1827 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1828 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1829 1830 return 0; 1831 } 1832 1833 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1834 { 1835 rtw_hci_stop(rtwdev); 1836 rtw_mac_power_off(rtwdev); 1837 } 1838 1839 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1840 { 1841 struct rtw_efuse *efuse = &rtwdev->efuse; 1842 int ret; 1843 1844 mutex_lock(&rtwdev->mutex); 1845 1846 /* power on mac to read efuse */ 1847 ret = rtw_chip_efuse_enable(rtwdev); 1848 if (ret) 1849 goto out_unlock; 1850 1851 ret = rtw_parse_efuse_map(rtwdev); 1852 if (ret) 1853 goto out_disable; 1854 1855 ret = rtw_dump_hw_feature(rtwdev); 1856 if (ret) 1857 goto out_disable; 1858 1859 ret = rtw_check_supported_rfe(rtwdev); 1860 if (ret) 1861 goto out_disable; 1862 1863 if (efuse->crystal_cap == 0xff) 1864 efuse->crystal_cap = 0; 1865 if (efuse->pa_type_2g == 0xff) 1866 efuse->pa_type_2g = 0; 1867 if (efuse->pa_type_5g == 0xff) 1868 efuse->pa_type_5g = 0; 1869 if (efuse->lna_type_2g == 0xff) 1870 efuse->lna_type_2g = 0; 1871 if (efuse->lna_type_5g == 0xff) 1872 efuse->lna_type_5g = 0; 1873 if (efuse->channel_plan == 0xff) 1874 efuse->channel_plan = 0x7f; 1875 if (efuse->rf_board_option == 0xff) 1876 efuse->rf_board_option = 0; 1877 if (efuse->bt_setting & BIT(0)) 1878 efuse->share_ant = true; 1879 if (efuse->regd == 0xff) 1880 efuse->regd = 0; 1881 if (efuse->tx_bb_swing_setting_2g == 0xff) 1882 efuse->tx_bb_swing_setting_2g = 0; 1883 if (efuse->tx_bb_swing_setting_5g == 0xff) 1884 efuse->tx_bb_swing_setting_5g = 0; 1885 1886 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1887 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1888 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1889 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1890 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1891 1892 out_disable: 1893 rtw_chip_efuse_disable(rtwdev); 1894 1895 out_unlock: 1896 mutex_unlock(&rtwdev->mutex); 1897 return ret; 1898 } 1899 1900 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1901 { 1902 struct rtw_hal *hal = &rtwdev->hal; 1903 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1904 1905 if (!rfe_def) 1906 return -ENODEV; 1907 1908 rtw_phy_setup_phy_cond(rtwdev, 0); 1909 1910 rtw_phy_init_tx_power(rtwdev); 1911 if (rfe_def->agc_btg_tbl) 1912 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1913 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1914 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1915 rtw_phy_tx_power_by_rate_config(hal); 1916 rtw_phy_tx_power_limit_config(hal); 1917 1918 return 0; 1919 } 1920 1921 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1922 { 1923 int ret; 1924 1925 ret = rtw_chip_parameter_setup(rtwdev); 1926 if (ret) { 1927 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1928 goto err_out; 1929 } 1930 1931 ret = rtw_chip_efuse_info_setup(rtwdev); 1932 if (ret) { 1933 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1934 goto err_out; 1935 } 1936 1937 ret = rtw_chip_board_info_setup(rtwdev); 1938 if (ret) { 1939 rtw_err(rtwdev, "failed to setup chip board info\n"); 1940 goto err_out; 1941 } 1942 1943 return 0; 1944 1945 err_out: 1946 return ret; 1947 } 1948 EXPORT_SYMBOL(rtw_chip_info_setup); 1949 1950 static void rtw_stats_init(struct rtw_dev *rtwdev) 1951 { 1952 struct rtw_traffic_stats *stats = &rtwdev->stats; 1953 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1954 int i; 1955 1956 ewma_tp_init(&stats->tx_ewma_tp); 1957 ewma_tp_init(&stats->rx_ewma_tp); 1958 1959 for (i = 0; i < RTW_EVM_NUM; i++) 1960 ewma_evm_init(&dm_info->ewma_evm[i]); 1961 for (i = 0; i < RTW_SNR_NUM; i++) 1962 ewma_snr_init(&dm_info->ewma_snr[i]); 1963 } 1964 1965 int rtw_core_init(struct rtw_dev *rtwdev) 1966 { 1967 struct rtw_chip_info *chip = rtwdev->chip; 1968 struct rtw_coex *coex = &rtwdev->coex; 1969 int ret; 1970 1971 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1972 INIT_LIST_HEAD(&rtwdev->txqs); 1973 1974 timer_setup(&rtwdev->tx_report.purge_timer, 1975 rtw_tx_report_purge_timer, 0); 1976 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1977 1978 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1979 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1980 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1981 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1982 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1983 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1984 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1985 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1986 rtw_coex_bt_multi_link_remain_work); 1987 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 1988 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 1989 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1990 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 1991 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 1992 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1993 skb_queue_head_init(&rtwdev->c2h_queue); 1994 skb_queue_head_init(&rtwdev->coex.queue); 1995 skb_queue_head_init(&rtwdev->tx_report.queue); 1996 1997 spin_lock_init(&rtwdev->rf_lock); 1998 spin_lock_init(&rtwdev->h2c.lock); 1999 spin_lock_init(&rtwdev->txq_lock); 2000 spin_lock_init(&rtwdev->tx_report.q_lock); 2001 2002 mutex_init(&rtwdev->mutex); 2003 mutex_init(&rtwdev->coex.mutex); 2004 mutex_init(&rtwdev->hal.tx_power_mutex); 2005 2006 init_waitqueue_head(&rtwdev->coex.wait); 2007 init_completion(&rtwdev->lps_leave_check); 2008 init_completion(&rtwdev->fw_scan_density); 2009 2010 rtwdev->sec.total_cam_num = 32; 2011 rtwdev->hal.current_channel = 1; 2012 rtwdev->dm_info.fix_rate = U8_MAX; 2013 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2014 2015 rtw_stats_init(rtwdev); 2016 2017 /* default rx filter setting */ 2018 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2019 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2020 BIT_AB | BIT_AM | BIT_APM; 2021 2022 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2023 if (ret) { 2024 rtw_warn(rtwdev, "no firmware loaded\n"); 2025 return ret; 2026 } 2027 2028 if (chip->wow_fw_name) { 2029 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2030 if (ret) { 2031 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2032 wait_for_completion(&rtwdev->fw.completion); 2033 if (rtwdev->fw.firmware) 2034 release_firmware(rtwdev->fw.firmware); 2035 return ret; 2036 } 2037 } 2038 2039 return 0; 2040 } 2041 EXPORT_SYMBOL(rtw_core_init); 2042 2043 void rtw_core_deinit(struct rtw_dev *rtwdev) 2044 { 2045 struct rtw_fw_state *fw = &rtwdev->fw; 2046 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2047 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2048 unsigned long flags; 2049 2050 rtw_wait_firmware_completion(rtwdev); 2051 2052 if (fw->firmware) 2053 release_firmware(fw->firmware); 2054 2055 if (wow_fw->firmware) 2056 release_firmware(wow_fw->firmware); 2057 2058 destroy_workqueue(rtwdev->tx_wq); 2059 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2060 skb_queue_purge(&rtwdev->tx_report.queue); 2061 skb_queue_purge(&rtwdev->coex.queue); 2062 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2063 2064 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2065 build_list) { 2066 list_del(&rsvd_pkt->build_list); 2067 kfree(rsvd_pkt); 2068 } 2069 2070 mutex_destroy(&rtwdev->mutex); 2071 mutex_destroy(&rtwdev->coex.mutex); 2072 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2073 } 2074 EXPORT_SYMBOL(rtw_core_deinit); 2075 2076 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2077 { 2078 struct rtw_hal *hal = &rtwdev->hal; 2079 int max_tx_headroom = 0; 2080 int ret; 2081 2082 /* TODO: USB & SDIO may need extra room? */ 2083 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2084 2085 hw->extra_tx_headroom = max_tx_headroom; 2086 hw->queues = IEEE80211_NUM_ACS; 2087 hw->txq_data_size = sizeof(struct rtw_txq); 2088 hw->sta_data_size = sizeof(struct rtw_sta_info); 2089 hw->vif_data_size = sizeof(struct rtw_vif); 2090 2091 ieee80211_hw_set(hw, SIGNAL_DBM); 2092 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2093 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2094 ieee80211_hw_set(hw, MFP_CAPABLE); 2095 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2096 ieee80211_hw_set(hw, SUPPORTS_PS); 2097 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2098 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2099 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2100 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2101 ieee80211_hw_set(hw, TX_AMSDU); 2102 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2103 2104 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2105 BIT(NL80211_IFTYPE_AP) | 2106 BIT(NL80211_IFTYPE_ADHOC) | 2107 BIT(NL80211_IFTYPE_MESH_POINT); 2108 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2109 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2110 2111 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2112 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2113 2114 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2115 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2116 hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN; 2117 2118 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2119 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2120 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2121 2122 #ifdef CONFIG_PM 2123 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2124 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2125 #endif 2126 rtw_set_supported_band(hw, rtwdev->chip); 2127 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2128 2129 hw->wiphy->sar_capa = &rtw_sar_capa; 2130 2131 ret = rtw_regd_init(rtwdev); 2132 if (ret) { 2133 rtw_err(rtwdev, "failed to init regd\n"); 2134 return ret; 2135 } 2136 2137 ret = ieee80211_register_hw(hw); 2138 if (ret) { 2139 rtw_err(rtwdev, "failed to register hw\n"); 2140 return ret; 2141 } 2142 2143 ret = rtw_regd_hint(rtwdev); 2144 if (ret) { 2145 rtw_err(rtwdev, "failed to hint regd\n"); 2146 return ret; 2147 } 2148 2149 rtw_debugfs_init(rtwdev); 2150 2151 rtwdev->bf_info.bfer_mu_cnt = 0; 2152 rtwdev->bf_info.bfer_su_cnt = 0; 2153 2154 return 0; 2155 } 2156 EXPORT_SYMBOL(rtw_register_hw); 2157 2158 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2159 { 2160 struct rtw_chip_info *chip = rtwdev->chip; 2161 2162 ieee80211_unregister_hw(hw); 2163 rtw_unset_supported_band(hw, chip); 2164 } 2165 EXPORT_SYMBOL(rtw_unregister_hw); 2166 2167 MODULE_AUTHOR("Realtek Corporation"); 2168 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2169 MODULE_LICENSE("Dual BSD/GPL"); 2170