1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 22 bool rtw_disable_lps_deep_mode; 23 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 24 bool rtw_bf_support = true; 25 unsigned int rtw_debug_mask; 26 EXPORT_SYMBOL(rtw_debug_mask); 27 /* EDCCA is enabled during normal behavior. For debugging purpose in 28 * a noisy environment, it can be disabled via edcca debugfs. Because 29 * all rtw88 devices will probably be affected if environment is noisy, 30 * rtw_edcca_enabled is just declared by driver instead of by device. 31 * So, turning it off will take effect for all rtw88 devices before 32 * there is a tough reason to maintain rtw_edcca_enabled by device. 33 */ 34 bool rtw_edcca_enabled = true; 35 36 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 37 module_param_named(support_bf, rtw_bf_support, bool, 0644); 38 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 39 40 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 41 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 42 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 43 44 static struct ieee80211_channel rtw_channeltable_2g[] = { 45 {.center_freq = 2412, .hw_value = 1,}, 46 {.center_freq = 2417, .hw_value = 2,}, 47 {.center_freq = 2422, .hw_value = 3,}, 48 {.center_freq = 2427, .hw_value = 4,}, 49 {.center_freq = 2432, .hw_value = 5,}, 50 {.center_freq = 2437, .hw_value = 6,}, 51 {.center_freq = 2442, .hw_value = 7,}, 52 {.center_freq = 2447, .hw_value = 8,}, 53 {.center_freq = 2452, .hw_value = 9,}, 54 {.center_freq = 2457, .hw_value = 10,}, 55 {.center_freq = 2462, .hw_value = 11,}, 56 {.center_freq = 2467, .hw_value = 12,}, 57 {.center_freq = 2472, .hw_value = 13,}, 58 {.center_freq = 2484, .hw_value = 14,}, 59 }; 60 61 static struct ieee80211_channel rtw_channeltable_5g[] = { 62 {.center_freq = 5180, .hw_value = 36,}, 63 {.center_freq = 5200, .hw_value = 40,}, 64 {.center_freq = 5220, .hw_value = 44,}, 65 {.center_freq = 5240, .hw_value = 48,}, 66 {.center_freq = 5260, .hw_value = 52,}, 67 {.center_freq = 5280, .hw_value = 56,}, 68 {.center_freq = 5300, .hw_value = 60,}, 69 {.center_freq = 5320, .hw_value = 64,}, 70 {.center_freq = 5500, .hw_value = 100,}, 71 {.center_freq = 5520, .hw_value = 104,}, 72 {.center_freq = 5540, .hw_value = 108,}, 73 {.center_freq = 5560, .hw_value = 112,}, 74 {.center_freq = 5580, .hw_value = 116,}, 75 {.center_freq = 5600, .hw_value = 120,}, 76 {.center_freq = 5620, .hw_value = 124,}, 77 {.center_freq = 5640, .hw_value = 128,}, 78 {.center_freq = 5660, .hw_value = 132,}, 79 {.center_freq = 5680, .hw_value = 136,}, 80 {.center_freq = 5700, .hw_value = 140,}, 81 {.center_freq = 5720, .hw_value = 144,}, 82 {.center_freq = 5745, .hw_value = 149,}, 83 {.center_freq = 5765, .hw_value = 153,}, 84 {.center_freq = 5785, .hw_value = 157,}, 85 {.center_freq = 5805, .hw_value = 161,}, 86 {.center_freq = 5825, .hw_value = 165, 87 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 88 }; 89 90 static struct ieee80211_rate rtw_ratetable[] = { 91 {.bitrate = 10, .hw_value = 0x00,}, 92 {.bitrate = 20, .hw_value = 0x01,}, 93 {.bitrate = 55, .hw_value = 0x02,}, 94 {.bitrate = 110, .hw_value = 0x03,}, 95 {.bitrate = 60, .hw_value = 0x04,}, 96 {.bitrate = 90, .hw_value = 0x05,}, 97 {.bitrate = 120, .hw_value = 0x06,}, 98 {.bitrate = 180, .hw_value = 0x07,}, 99 {.bitrate = 240, .hw_value = 0x08,}, 100 {.bitrate = 360, .hw_value = 0x09,}, 101 {.bitrate = 480, .hw_value = 0x0a,}, 102 {.bitrate = 540, .hw_value = 0x0b,}, 103 }; 104 105 u16 rtw_desc_to_bitrate(u8 desc_rate) 106 { 107 struct ieee80211_rate rate; 108 109 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 110 return 0; 111 112 rate = rtw_ratetable[desc_rate]; 113 114 return rate.bitrate; 115 } 116 117 static struct ieee80211_supported_band rtw_band_2ghz = { 118 .band = NL80211_BAND_2GHZ, 119 120 .channels = rtw_channeltable_2g, 121 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 122 123 .bitrates = rtw_ratetable, 124 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 125 126 .ht_cap = {0}, 127 .vht_cap = {0}, 128 }; 129 130 static struct ieee80211_supported_band rtw_band_5ghz = { 131 .band = NL80211_BAND_5GHZ, 132 133 .channels = rtw_channeltable_5g, 134 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 135 136 /* 5G has no CCK rates */ 137 .bitrates = rtw_ratetable + 4, 138 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 139 140 .ht_cap = {0}, 141 .vht_cap = {0}, 142 }; 143 144 struct rtw_watch_dog_iter_data { 145 struct rtw_dev *rtwdev; 146 struct rtw_vif *rtwvif; 147 }; 148 149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 150 { 151 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 152 u8 fix_rate_enable = 0; 153 u8 new_csi_rate_idx; 154 155 if (rtwvif->bfee.role != RTW_BFEE_SU && 156 rtwvif->bfee.role != RTW_BFEE_MU) 157 return; 158 159 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 160 bf_info->cur_csi_rpt_rate, 161 fix_rate_enable, &new_csi_rate_idx); 162 163 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 164 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 165 } 166 167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 168 struct ieee80211_vif *vif) 169 { 170 struct rtw_watch_dog_iter_data *iter_data = data; 171 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 172 173 if (vif->type == NL80211_IFTYPE_STATION) 174 if (vif->bss_conf.assoc) 175 iter_data->rtwvif = rtwvif; 176 177 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 178 179 rtwvif->stats.tx_unicast = 0; 180 rtwvif->stats.rx_unicast = 0; 181 rtwvif->stats.tx_cnt = 0; 182 rtwvif->stats.rx_cnt = 0; 183 } 184 185 /* process TX/RX statistics periodically for hardware, 186 * the information helps hardware to enhance performance 187 */ 188 static void rtw_watch_dog_work(struct work_struct *work) 189 { 190 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 191 watch_dog_work.work); 192 struct rtw_traffic_stats *stats = &rtwdev->stats; 193 struct rtw_watch_dog_iter_data data = {}; 194 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 195 bool ps_active; 196 197 mutex_lock(&rtwdev->mutex); 198 199 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 200 goto unlock; 201 202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 203 RTW_WATCH_DOG_DELAY_TIME); 204 205 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 206 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 207 else 208 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 209 210 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 211 rtw_coex_wl_status_change_notify(rtwdev, 0); 212 213 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 214 stats->rx_cnt > RTW_LPS_THRESHOLD) 215 ps_active = true; 216 else 217 ps_active = false; 218 219 ewma_tp_add(&stats->tx_ewma_tp, 220 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 221 ewma_tp_add(&stats->rx_ewma_tp, 222 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 223 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 224 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 225 226 /* reset tx/rx statictics */ 227 stats->tx_unicast = 0; 228 stats->rx_unicast = 0; 229 stats->tx_cnt = 0; 230 stats->rx_cnt = 0; 231 232 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 233 goto unlock; 234 235 /* make sure BB/RF is working for dynamic mech */ 236 rtw_leave_lps(rtwdev); 237 238 rtw_phy_dynamic_mechanism(rtwdev); 239 240 data.rtwdev = rtwdev; 241 /* use atomic version to avoid taking local->iflist_mtx mutex */ 242 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 243 244 /* fw supports only one station associated to enter lps, if there are 245 * more than two stations associated to the AP, then we can not enter 246 * lps, because fw does not handle the overlapped beacon interval 247 * 248 * mac80211 should iterate vifs and determine if driver can enter 249 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 250 * get that vif and check if device is having traffic more than the 251 * threshold. 252 */ 253 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 254 !rtwdev->beacon_loss) 255 rtw_enter_lps(rtwdev, data.rtwvif->port); 256 257 rtwdev->watch_dog_cnt++; 258 259 unlock: 260 mutex_unlock(&rtwdev->mutex); 261 } 262 263 static void rtw_c2h_work(struct work_struct *work) 264 { 265 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 266 struct sk_buff *skb, *tmp; 267 268 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 269 skb_unlink(skb, &rtwdev->c2h_queue); 270 rtw_fw_c2h_cmd_handle(rtwdev, skb); 271 dev_kfree_skb_any(skb); 272 } 273 } 274 275 static void rtw_ips_work(struct work_struct *work) 276 { 277 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 278 279 mutex_lock(&rtwdev->mutex); 280 rtw_enter_ips(rtwdev); 281 mutex_unlock(&rtwdev->mutex); 282 } 283 284 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 285 { 286 unsigned long mac_id; 287 288 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 289 if (mac_id < RTW_MAX_MAC_ID_NUM) 290 set_bit(mac_id, rtwdev->mac_id_map); 291 292 return mac_id; 293 } 294 295 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 296 struct ieee80211_vif *vif) 297 { 298 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 299 int i; 300 301 si->mac_id = rtw_acquire_macid(rtwdev); 302 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 303 return -ENOSPC; 304 305 si->sta = sta; 306 si->vif = vif; 307 si->init_ra_lv = 1; 308 ewma_rssi_init(&si->avg_rssi); 309 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 310 rtw_txq_init(rtwdev, sta->txq[i]); 311 312 rtw_update_sta_info(rtwdev, si); 313 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 314 315 rtwdev->sta_cnt++; 316 rtwdev->beacon_loss = false; 317 rtw_info(rtwdev, "sta %pM joined with macid %d\n", 318 sta->addr, si->mac_id); 319 320 return 0; 321 } 322 323 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 324 bool fw_exist) 325 { 326 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 327 int i; 328 329 rtw_release_macid(rtwdev, si->mac_id); 330 if (fw_exist) 331 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 332 333 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 334 rtw_txq_cleanup(rtwdev, sta->txq[i]); 335 336 kfree(si->mask); 337 338 rtwdev->sta_cnt--; 339 rtw_info(rtwdev, "sta %pM with macid %d left\n", 340 sta->addr, si->mac_id); 341 } 342 343 struct rtw_fwcd_hdr { 344 u32 item; 345 u32 size; 346 u32 padding1; 347 u32 padding2; 348 } __packed; 349 350 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 351 { 352 struct rtw_chip_info *chip = rtwdev->chip; 353 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 354 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 355 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 356 u8 i; 357 358 if (segs) { 359 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 360 361 for (i = 0; i < segs->num; i++) 362 prep_size += segs->segs[i]; 363 } 364 365 desc->data = vmalloc(prep_size); 366 if (!desc->data) 367 return -ENOMEM; 368 369 desc->size = prep_size; 370 desc->next = desc->data; 371 372 return 0; 373 } 374 375 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 376 { 377 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 378 struct rtw_fwcd_hdr *hdr; 379 u8 *next; 380 381 if (!desc->data) { 382 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 383 return NULL; 384 } 385 386 next = desc->next + sizeof(struct rtw_fwcd_hdr); 387 if (next - desc->data + size > desc->size) { 388 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 389 return NULL; 390 } 391 392 hdr = (struct rtw_fwcd_hdr *)(desc->next); 393 hdr->item = item; 394 hdr->size = size; 395 hdr->padding1 = 0x01234567; 396 hdr->padding2 = 0x89abcdef; 397 desc->next = next + size; 398 399 return next; 400 } 401 402 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 403 { 404 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 405 406 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 407 408 /* Data will be freed after lifetime of device coredump. After calling 409 * dev_coredump, data is supposed to be handled by the device coredump 410 * framework. Note that a new dump will be discarded if a previous one 411 * hasn't been released yet. 412 */ 413 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 414 } 415 416 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 417 { 418 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 419 420 if (free_self) { 421 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 422 vfree(desc->data); 423 } 424 425 desc->data = NULL; 426 desc->next = NULL; 427 } 428 429 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 430 { 431 u32 size = rtwdev->chip->fw_rxff_size; 432 u32 *buf; 433 u8 seq; 434 435 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 436 if (!buf) 437 return -ENOMEM; 438 439 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 440 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 441 return -EINVAL; 442 } 443 444 if (GET_FW_DUMP_LEN(buf) == 0) { 445 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 446 return -EINVAL; 447 } 448 449 seq = GET_FW_DUMP_SEQ(buf); 450 if (seq > 0) { 451 rtw_dbg(rtwdev, RTW_DBG_FW, 452 "fw crash dump's seq is wrong: %d\n", seq); 453 return -EINVAL; 454 } 455 456 return 0; 457 } 458 459 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 460 u32 fwcd_item) 461 { 462 u32 rxff = rtwdev->chip->fw_rxff_size; 463 u32 dump_size, done_size = 0; 464 u8 *buf; 465 int ret; 466 467 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 468 if (!buf) 469 return -ENOMEM; 470 471 while (size) { 472 dump_size = size > rxff ? rxff : size; 473 474 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 475 dump_size); 476 if (ret) { 477 rtw_err(rtwdev, 478 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 479 ocp_src, done_size); 480 return ret; 481 } 482 483 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 484 dump_size, (u32 *)(buf + done_size)); 485 if (ret) { 486 rtw_err(rtwdev, 487 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 488 ocp_src, done_size); 489 return ret; 490 } 491 492 size -= dump_size; 493 done_size += dump_size; 494 } 495 496 return 0; 497 } 498 EXPORT_SYMBOL(rtw_dump_fw); 499 500 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 501 { 502 u8 *buf; 503 u32 i; 504 505 if (addr & 0x3) { 506 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 507 return -EINVAL; 508 } 509 510 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 511 if (!buf) 512 return -ENOMEM; 513 514 for (i = 0; i < size; i += 4) 515 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 516 517 return 0; 518 } 519 EXPORT_SYMBOL(rtw_dump_reg); 520 521 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 522 struct ieee80211_bss_conf *conf) 523 { 524 if (conf && conf->assoc) { 525 rtwvif->aid = conf->aid; 526 rtwvif->net_type = RTW_NET_MGD_LINKED; 527 } else { 528 rtwvif->aid = 0; 529 rtwvif->net_type = RTW_NET_NO_LINK; 530 } 531 } 532 533 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 534 struct ieee80211_vif *vif, 535 struct ieee80211_sta *sta, 536 struct ieee80211_key_conf *key, 537 void *data) 538 { 539 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 540 struct rtw_sec_desc *sec = &rtwdev->sec; 541 542 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 543 } 544 545 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 546 { 547 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 548 549 if (rtwdev->sta_cnt == 0) { 550 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 551 return; 552 } 553 rtw_sta_remove(rtwdev, sta, false); 554 } 555 556 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 557 { 558 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 559 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 560 561 rtw_bf_disassoc(rtwdev, vif, NULL); 562 rtw_vif_assoc_changed(rtwvif, NULL); 563 rtw_txq_cleanup(rtwdev, vif->txq); 564 } 565 566 void rtw_fw_recovery(struct rtw_dev *rtwdev) 567 { 568 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 569 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 570 } 571 572 static void __fw_recovery_work(struct rtw_dev *rtwdev) 573 { 574 int ret = 0; 575 576 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 577 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 578 579 ret = rtw_fwcd_prep(rtwdev); 580 if (ret) 581 goto free; 582 ret = rtw_fw_dump_crash_log(rtwdev); 583 if (ret) 584 goto free; 585 ret = rtw_chip_dump_fw_crash(rtwdev); 586 if (ret) 587 goto free; 588 589 rtw_fwcd_dump(rtwdev); 590 free: 591 rtw_fwcd_free(rtwdev, !!ret); 592 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 593 594 WARN(1, "firmware crash, start reset and recover\n"); 595 596 rcu_read_lock(); 597 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 598 rcu_read_unlock(); 599 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 600 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 601 rtw_enter_ips(rtwdev); 602 } 603 604 static void rtw_fw_recovery_work(struct work_struct *work) 605 { 606 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 607 fw_recovery_work); 608 609 mutex_lock(&rtwdev->mutex); 610 __fw_recovery_work(rtwdev); 611 mutex_unlock(&rtwdev->mutex); 612 613 ieee80211_restart_hw(rtwdev->hw); 614 } 615 616 struct rtw_txq_ba_iter_data { 617 }; 618 619 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 620 { 621 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 622 int ret; 623 u8 tid; 624 625 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 626 while (tid != IEEE80211_NUM_TIDS) { 627 clear_bit(tid, si->tid_ba); 628 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 629 if (ret == -EINVAL) { 630 struct ieee80211_txq *txq; 631 struct rtw_txq *rtwtxq; 632 633 txq = sta->txq[tid]; 634 rtwtxq = (struct rtw_txq *)txq->drv_priv; 635 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 636 } 637 638 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 639 } 640 } 641 642 static void rtw_txq_ba_work(struct work_struct *work) 643 { 644 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 645 struct rtw_txq_ba_iter_data data; 646 647 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 648 } 649 650 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 651 { 652 if (IS_CH_2G_BAND(channel)) 653 pkt_stat->band = NL80211_BAND_2GHZ; 654 else if (IS_CH_5G_BAND(channel)) 655 pkt_stat->band = NL80211_BAND_5GHZ; 656 else 657 return; 658 659 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 660 } 661 EXPORT_SYMBOL(rtw_set_rx_freq_band); 662 663 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 664 struct rtw_channel_params *chan_params) 665 { 666 struct ieee80211_channel *channel = chandef->chan; 667 enum nl80211_chan_width width = chandef->width; 668 u8 *cch_by_bw = chan_params->cch_by_bw; 669 u32 primary_freq, center_freq; 670 u8 center_chan; 671 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 672 u8 primary_chan_idx = 0; 673 u8 i; 674 675 center_chan = channel->hw_value; 676 primary_freq = channel->center_freq; 677 center_freq = chandef->center_freq1; 678 679 /* assign the center channel used while 20M bw is selected */ 680 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 681 682 switch (width) { 683 case NL80211_CHAN_WIDTH_20_NOHT: 684 case NL80211_CHAN_WIDTH_20: 685 bandwidth = RTW_CHANNEL_WIDTH_20; 686 primary_chan_idx = RTW_SC_DONT_CARE; 687 break; 688 case NL80211_CHAN_WIDTH_40: 689 bandwidth = RTW_CHANNEL_WIDTH_40; 690 if (primary_freq > center_freq) { 691 primary_chan_idx = RTW_SC_20_UPPER; 692 center_chan -= 2; 693 } else { 694 primary_chan_idx = RTW_SC_20_LOWER; 695 center_chan += 2; 696 } 697 break; 698 case NL80211_CHAN_WIDTH_80: 699 bandwidth = RTW_CHANNEL_WIDTH_80; 700 if (primary_freq > center_freq) { 701 if (primary_freq - center_freq == 10) { 702 primary_chan_idx = RTW_SC_20_UPPER; 703 center_chan -= 2; 704 } else { 705 primary_chan_idx = RTW_SC_20_UPMOST; 706 center_chan -= 6; 707 } 708 /* assign the center channel used 709 * while 40M bw is selected 710 */ 711 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 712 } else { 713 if (center_freq - primary_freq == 10) { 714 primary_chan_idx = RTW_SC_20_LOWER; 715 center_chan += 2; 716 } else { 717 primary_chan_idx = RTW_SC_20_LOWEST; 718 center_chan += 6; 719 } 720 /* assign the center channel used 721 * while 40M bw is selected 722 */ 723 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 724 } 725 break; 726 default: 727 center_chan = 0; 728 break; 729 } 730 731 chan_params->center_chan = center_chan; 732 chan_params->bandwidth = bandwidth; 733 chan_params->primary_chan_idx = primary_chan_idx; 734 735 /* assign the center channel used while current bw is selected */ 736 cch_by_bw[bandwidth] = center_chan; 737 738 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 739 cch_by_bw[i] = 0; 740 } 741 742 void rtw_set_channel(struct rtw_dev *rtwdev) 743 { 744 struct ieee80211_hw *hw = rtwdev->hw; 745 struct rtw_hal *hal = &rtwdev->hal; 746 struct rtw_chip_info *chip = rtwdev->chip; 747 struct rtw_channel_params ch_param; 748 u8 center_chan, bandwidth, primary_chan_idx; 749 u8 i; 750 751 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 752 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 753 return; 754 755 center_chan = ch_param.center_chan; 756 bandwidth = ch_param.bandwidth; 757 primary_chan_idx = ch_param.primary_chan_idx; 758 759 hal->current_band_width = bandwidth; 760 hal->current_channel = center_chan; 761 hal->current_primary_channel_index = primary_chan_idx; 762 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 763 764 switch (center_chan) { 765 case 1 ... 14: 766 hal->sar_band = RTW_SAR_BAND_0; 767 break; 768 case 36 ... 64: 769 hal->sar_band = RTW_SAR_BAND_1; 770 break; 771 case 100 ... 144: 772 hal->sar_band = RTW_SAR_BAND_3; 773 break; 774 case 149 ... 177: 775 hal->sar_band = RTW_SAR_BAND_4; 776 break; 777 default: 778 WARN(1, "unknown ch(%u) to SAR band\n", center_chan); 779 hal->sar_band = RTW_SAR_BAND_0; 780 break; 781 } 782 783 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 784 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 785 786 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 787 788 if (hal->current_band_type == RTW_BAND_5G) { 789 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 790 } else { 791 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 792 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 793 else 794 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 795 } 796 797 rtw_phy_set_tx_power_level(rtwdev, center_chan); 798 799 /* if the channel isn't set for scanning, we will do RF calibration 800 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 801 * during scanning on each channel takes too long. 802 */ 803 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 804 rtwdev->need_rfk = true; 805 } 806 807 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 808 { 809 struct rtw_chip_info *chip = rtwdev->chip; 810 811 if (rtwdev->need_rfk) { 812 rtwdev->need_rfk = false; 813 chip->ops->phy_calibration(rtwdev); 814 } 815 } 816 817 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 818 { 819 int i; 820 821 for (i = 0; i < ETH_ALEN; i++) 822 rtw_write8(rtwdev, start + i, addr[i]); 823 } 824 825 void rtw_vif_port_config(struct rtw_dev *rtwdev, 826 struct rtw_vif *rtwvif, 827 u32 config) 828 { 829 u32 addr, mask; 830 831 if (config & PORT_SET_MAC_ADDR) { 832 addr = rtwvif->conf->mac_addr.addr; 833 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 834 } 835 if (config & PORT_SET_BSSID) { 836 addr = rtwvif->conf->bssid.addr; 837 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 838 } 839 if (config & PORT_SET_NET_TYPE) { 840 addr = rtwvif->conf->net_type.addr; 841 mask = rtwvif->conf->net_type.mask; 842 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 843 } 844 if (config & PORT_SET_AID) { 845 addr = rtwvif->conf->aid.addr; 846 mask = rtwvif->conf->aid.mask; 847 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 848 } 849 if (config & PORT_SET_BCN_CTRL) { 850 addr = rtwvif->conf->bcn_ctrl.addr; 851 mask = rtwvif->conf->bcn_ctrl.mask; 852 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 853 } 854 } 855 856 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 857 { 858 u8 bw = 0; 859 860 switch (bw_cap) { 861 case EFUSE_HW_CAP_IGNORE: 862 case EFUSE_HW_CAP_SUPP_BW80: 863 bw |= BIT(RTW_CHANNEL_WIDTH_80); 864 fallthrough; 865 case EFUSE_HW_CAP_SUPP_BW40: 866 bw |= BIT(RTW_CHANNEL_WIDTH_40); 867 fallthrough; 868 default: 869 bw |= BIT(RTW_CHANNEL_WIDTH_20); 870 break; 871 } 872 873 return bw; 874 } 875 876 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 877 { 878 struct rtw_hal *hal = &rtwdev->hal; 879 struct rtw_chip_info *chip = rtwdev->chip; 880 881 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 882 hw_ant_num >= hal->rf_path_num) 883 return; 884 885 switch (hw_ant_num) { 886 case 1: 887 hal->rf_type = RF_1T1R; 888 hal->rf_path_num = 1; 889 if (!chip->fix_rf_phy_num) 890 hal->rf_phy_num = hal->rf_path_num; 891 hal->antenna_tx = BB_PATH_A; 892 hal->antenna_rx = BB_PATH_A; 893 break; 894 default: 895 WARN(1, "invalid hw configuration from efuse\n"); 896 break; 897 } 898 } 899 900 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 901 { 902 u64 ra_mask = 0; 903 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 904 u8 vht_mcs_cap; 905 int i, nss; 906 907 /* 4SS, every two bits for MCS7/8/9 */ 908 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 909 vht_mcs_cap = mcs_map & 0x3; 910 switch (vht_mcs_cap) { 911 case 2: /* MCS9 */ 912 ra_mask |= 0x3ffULL << nss; 913 break; 914 case 1: /* MCS8 */ 915 ra_mask |= 0x1ffULL << nss; 916 break; 917 case 0: /* MCS7 */ 918 ra_mask |= 0x0ffULL << nss; 919 break; 920 default: 921 break; 922 } 923 } 924 925 return ra_mask; 926 } 927 928 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 929 { 930 u8 rate_id = 0; 931 932 switch (wireless_set) { 933 case WIRELESS_CCK: 934 rate_id = RTW_RATEID_B_20M; 935 break; 936 case WIRELESS_OFDM: 937 rate_id = RTW_RATEID_G; 938 break; 939 case WIRELESS_CCK | WIRELESS_OFDM: 940 rate_id = RTW_RATEID_BG; 941 break; 942 case WIRELESS_OFDM | WIRELESS_HT: 943 if (tx_num == 1) 944 rate_id = RTW_RATEID_GN_N1SS; 945 else if (tx_num == 2) 946 rate_id = RTW_RATEID_GN_N2SS; 947 else if (tx_num == 3) 948 rate_id = RTW_RATEID_ARFR5_N_3SS; 949 break; 950 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 951 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 952 if (tx_num == 1) 953 rate_id = RTW_RATEID_BGN_40M_1SS; 954 else if (tx_num == 2) 955 rate_id = RTW_RATEID_BGN_40M_2SS; 956 else if (tx_num == 3) 957 rate_id = RTW_RATEID_ARFR5_N_3SS; 958 else if (tx_num == 4) 959 rate_id = RTW_RATEID_ARFR7_N_4SS; 960 } else { 961 if (tx_num == 1) 962 rate_id = RTW_RATEID_BGN_20M_1SS; 963 else if (tx_num == 2) 964 rate_id = RTW_RATEID_BGN_20M_2SS; 965 else if (tx_num == 3) 966 rate_id = RTW_RATEID_ARFR5_N_3SS; 967 else if (tx_num == 4) 968 rate_id = RTW_RATEID_ARFR7_N_4SS; 969 } 970 break; 971 case WIRELESS_OFDM | WIRELESS_VHT: 972 if (tx_num == 1) 973 rate_id = RTW_RATEID_ARFR1_AC_1SS; 974 else if (tx_num == 2) 975 rate_id = RTW_RATEID_ARFR0_AC_2SS; 976 else if (tx_num == 3) 977 rate_id = RTW_RATEID_ARFR4_AC_3SS; 978 else if (tx_num == 4) 979 rate_id = RTW_RATEID_ARFR6_AC_4SS; 980 break; 981 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 982 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 983 if (tx_num == 1) 984 rate_id = RTW_RATEID_ARFR1_AC_1SS; 985 else if (tx_num == 2) 986 rate_id = RTW_RATEID_ARFR0_AC_2SS; 987 else if (tx_num == 3) 988 rate_id = RTW_RATEID_ARFR4_AC_3SS; 989 else if (tx_num == 4) 990 rate_id = RTW_RATEID_ARFR6_AC_4SS; 991 } else { 992 if (tx_num == 1) 993 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 994 else if (tx_num == 2) 995 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 996 else if (tx_num == 3) 997 rate_id = RTW_RATEID_ARFR4_AC_3SS; 998 else if (tx_num == 4) 999 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1000 } 1001 break; 1002 default: 1003 break; 1004 } 1005 1006 return rate_id; 1007 } 1008 1009 #define RA_MASK_CCK_RATES 0x0000f 1010 #define RA_MASK_OFDM_RATES 0x00ff0 1011 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1012 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1013 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1014 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1015 RA_MASK_HT_RATES_2SS | \ 1016 RA_MASK_HT_RATES_3SS) 1017 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1018 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1019 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1020 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1021 RA_MASK_VHT_RATES_2SS | \ 1022 RA_MASK_VHT_RATES_3SS) 1023 #define RA_MASK_CCK_IN_BG 0x00005 1024 #define RA_MASK_CCK_IN_HT 0x00005 1025 #define RA_MASK_CCK_IN_VHT 0x00005 1026 #define RA_MASK_OFDM_IN_VHT 0x00010 1027 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1028 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1029 1030 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1031 { 1032 u8 rssi_level = si->rssi_level; 1033 1034 if (wireless_set == WIRELESS_CCK) 1035 return 0xffffffffffffffffULL; 1036 1037 if (rssi_level == 0) 1038 return 0xffffffffffffffffULL; 1039 else if (rssi_level == 1) 1040 return 0xfffffffffffffff0ULL; 1041 else if (rssi_level == 2) 1042 return 0xffffffffffffefe0ULL; 1043 else if (rssi_level == 3) 1044 return 0xffffffffffffcfc0ULL; 1045 else if (rssi_level == 4) 1046 return 0xffffffffffff8f80ULL; 1047 else 1048 return 0xffffffffffff0f00ULL; 1049 } 1050 1051 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1052 { 1053 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1054 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1055 1056 if (ra_mask == 0) 1057 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1058 1059 return ra_mask; 1060 } 1061 1062 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1063 u64 ra_mask, bool is_vht_enable) 1064 { 1065 struct rtw_hal *hal = &rtwdev->hal; 1066 const struct cfg80211_bitrate_mask *mask = si->mask; 1067 u64 cfg_mask = GENMASK_ULL(63, 0); 1068 u8 band; 1069 1070 if (!si->use_cfg_mask) 1071 return ra_mask; 1072 1073 band = hal->current_band_type; 1074 if (band == RTW_BAND_2G) { 1075 band = NL80211_BAND_2GHZ; 1076 cfg_mask = mask->control[band].legacy; 1077 } else if (band == RTW_BAND_5G) { 1078 band = NL80211_BAND_5GHZ; 1079 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1080 RA_MASK_OFDM_RATES); 1081 } 1082 1083 if (!is_vht_enable) { 1084 if (ra_mask & RA_MASK_HT_RATES_1SS) 1085 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1086 RA_MASK_HT_RATES_1SS); 1087 if (ra_mask & RA_MASK_HT_RATES_2SS) 1088 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1089 RA_MASK_HT_RATES_2SS); 1090 } else { 1091 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1092 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1093 RA_MASK_VHT_RATES_1SS); 1094 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1095 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1096 RA_MASK_VHT_RATES_2SS); 1097 } 1098 1099 ra_mask &= cfg_mask; 1100 1101 return ra_mask; 1102 } 1103 1104 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 1105 { 1106 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1107 struct ieee80211_sta *sta = si->sta; 1108 struct rtw_efuse *efuse = &rtwdev->efuse; 1109 struct rtw_hal *hal = &rtwdev->hal; 1110 u8 wireless_set; 1111 u8 bw_mode; 1112 u8 rate_id; 1113 u8 rf_type = RF_1T1R; 1114 u8 stbc_en = 0; 1115 u8 ldpc_en = 0; 1116 u8 tx_num = 1; 1117 u64 ra_mask = 0; 1118 u64 ra_mask_bak = 0; 1119 bool is_vht_enable = false; 1120 bool is_support_sgi = false; 1121 1122 if (sta->vht_cap.vht_supported) { 1123 is_vht_enable = true; 1124 ra_mask |= get_vht_ra_mask(sta); 1125 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1126 stbc_en = VHT_STBC_EN; 1127 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1128 ldpc_en = VHT_LDPC_EN; 1129 } else if (sta->ht_cap.ht_supported) { 1130 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 1131 (sta->ht_cap.mcs.rx_mask[0] << 12); 1132 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1133 stbc_en = HT_STBC_EN; 1134 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1135 ldpc_en = HT_LDPC_EN; 1136 } 1137 1138 if (efuse->hw_cap.nss == 1) 1139 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1140 1141 if (hal->current_band_type == RTW_BAND_5G) { 1142 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 1143 ra_mask_bak = ra_mask; 1144 if (sta->vht_cap.vht_supported) { 1145 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1146 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1147 } else if (sta->ht_cap.ht_supported) { 1148 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1149 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1150 } else { 1151 wireless_set = WIRELESS_OFDM; 1152 } 1153 dm_info->rrsr_val_init = RRSR_INIT_5G; 1154 } else if (hal->current_band_type == RTW_BAND_2G) { 1155 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 1156 ra_mask_bak = ra_mask; 1157 if (sta->vht_cap.vht_supported) { 1158 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1159 RA_MASK_OFDM_IN_VHT; 1160 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1161 WIRELESS_HT | WIRELESS_VHT; 1162 } else if (sta->ht_cap.ht_supported) { 1163 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1164 RA_MASK_OFDM_IN_HT_2G; 1165 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1166 WIRELESS_HT; 1167 } else if (sta->supp_rates[0] <= 0xf) { 1168 wireless_set = WIRELESS_CCK; 1169 } else { 1170 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1171 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1172 } 1173 dm_info->rrsr_val_init = RRSR_INIT_2G; 1174 } else { 1175 rtw_err(rtwdev, "Unknown band type\n"); 1176 ra_mask_bak = ra_mask; 1177 wireless_set = 0; 1178 } 1179 1180 switch (sta->bandwidth) { 1181 case IEEE80211_STA_RX_BW_80: 1182 bw_mode = RTW_CHANNEL_WIDTH_80; 1183 is_support_sgi = sta->vht_cap.vht_supported && 1184 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1185 break; 1186 case IEEE80211_STA_RX_BW_40: 1187 bw_mode = RTW_CHANNEL_WIDTH_40; 1188 is_support_sgi = sta->ht_cap.ht_supported && 1189 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1190 break; 1191 default: 1192 bw_mode = RTW_CHANNEL_WIDTH_20; 1193 is_support_sgi = sta->ht_cap.ht_supported && 1194 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1195 break; 1196 } 1197 1198 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 1199 tx_num = 2; 1200 rf_type = RF_2T2R; 1201 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 1202 tx_num = 2; 1203 rf_type = RF_2T2R; 1204 } 1205 1206 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1207 1208 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1209 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1210 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1211 1212 si->bw_mode = bw_mode; 1213 si->stbc_en = stbc_en; 1214 si->ldpc_en = ldpc_en; 1215 si->rf_type = rf_type; 1216 si->wireless_set = wireless_set; 1217 si->sgi_enable = is_support_sgi; 1218 si->vht_enable = is_vht_enable; 1219 si->ra_mask = ra_mask; 1220 si->rate_id = rate_id; 1221 1222 rtw_fw_send_ra_info(rtwdev, si); 1223 } 1224 1225 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1226 { 1227 struct rtw_chip_info *chip = rtwdev->chip; 1228 struct rtw_fw_state *fw; 1229 1230 fw = &rtwdev->fw; 1231 wait_for_completion(&fw->completion); 1232 if (!fw->firmware) 1233 return -EINVAL; 1234 1235 if (chip->wow_fw_name) { 1236 fw = &rtwdev->wow_fw; 1237 wait_for_completion(&fw->completion); 1238 if (!fw->firmware) 1239 return -EINVAL; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1246 struct rtw_fw_state *fw) 1247 { 1248 struct rtw_chip_info *chip = rtwdev->chip; 1249 1250 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1251 !fw->feature) 1252 return LPS_DEEP_MODE_NONE; 1253 1254 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1255 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1256 return LPS_DEEP_MODE_PG; 1257 1258 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1259 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1260 return LPS_DEEP_MODE_LCLK; 1261 1262 return LPS_DEEP_MODE_NONE; 1263 } 1264 1265 static int rtw_power_on(struct rtw_dev *rtwdev) 1266 { 1267 struct rtw_chip_info *chip = rtwdev->chip; 1268 struct rtw_fw_state *fw = &rtwdev->fw; 1269 bool wifi_only; 1270 int ret; 1271 1272 ret = rtw_hci_setup(rtwdev); 1273 if (ret) { 1274 rtw_err(rtwdev, "failed to setup hci\n"); 1275 goto err; 1276 } 1277 1278 /* power on MAC before firmware downloaded */ 1279 ret = rtw_mac_power_on(rtwdev); 1280 if (ret) { 1281 rtw_err(rtwdev, "failed to power on mac\n"); 1282 goto err; 1283 } 1284 1285 ret = rtw_wait_firmware_completion(rtwdev); 1286 if (ret) { 1287 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1288 goto err_off; 1289 } 1290 1291 ret = rtw_download_firmware(rtwdev, fw); 1292 if (ret) { 1293 rtw_err(rtwdev, "failed to download firmware\n"); 1294 goto err_off; 1295 } 1296 1297 /* config mac after firmware downloaded */ 1298 ret = rtw_mac_init(rtwdev); 1299 if (ret) { 1300 rtw_err(rtwdev, "failed to configure mac\n"); 1301 goto err_off; 1302 } 1303 1304 chip->ops->phy_set_param(rtwdev); 1305 1306 ret = rtw_hci_start(rtwdev); 1307 if (ret) { 1308 rtw_err(rtwdev, "failed to start hci\n"); 1309 goto err_off; 1310 } 1311 1312 /* send H2C after HCI has started */ 1313 rtw_fw_send_general_info(rtwdev); 1314 rtw_fw_send_phydm_info(rtwdev); 1315 1316 wifi_only = !rtwdev->efuse.btcoex; 1317 rtw_coex_power_on_setting(rtwdev); 1318 rtw_coex_init_hw_config(rtwdev, wifi_only); 1319 1320 return 0; 1321 1322 err_off: 1323 rtw_mac_power_off(rtwdev); 1324 1325 err: 1326 return ret; 1327 } 1328 1329 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1330 { 1331 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1332 return; 1333 1334 if (start) { 1335 rtw_fw_scan_notify(rtwdev, true); 1336 } else { 1337 reinit_completion(&rtwdev->fw_scan_density); 1338 rtw_fw_scan_notify(rtwdev, false); 1339 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1340 SCAN_NOTIFY_TIMEOUT)) 1341 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1342 } 1343 } 1344 1345 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1346 const u8 *mac_addr, bool hw_scan) 1347 { 1348 u32 config = 0; 1349 int ret = 0; 1350 1351 rtw_leave_lps(rtwdev); 1352 1353 if (hw_scan && rtwvif->net_type == RTW_NET_NO_LINK) { 1354 ret = rtw_leave_ips(rtwdev); 1355 if (ret) { 1356 rtw_err(rtwdev, "failed to leave idle state\n"); 1357 return; 1358 } 1359 } 1360 1361 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1362 config |= PORT_SET_MAC_ADDR; 1363 rtw_vif_port_config(rtwdev, rtwvif, config); 1364 1365 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1366 rtw_core_fw_scan_notify(rtwdev, true); 1367 1368 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1369 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1370 } 1371 1372 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1373 bool hw_scan) 1374 { 1375 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 1376 u32 config = 0; 1377 1378 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1379 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1380 1381 rtw_core_fw_scan_notify(rtwdev, false); 1382 1383 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1384 config |= PORT_SET_MAC_ADDR; 1385 rtw_vif_port_config(rtwdev, rtwvif, config); 1386 1387 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1388 1389 if (rtwvif->net_type == RTW_NET_NO_LINK && hw_scan) 1390 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1391 } 1392 1393 int rtw_core_start(struct rtw_dev *rtwdev) 1394 { 1395 int ret; 1396 1397 ret = rtw_power_on(rtwdev); 1398 if (ret) 1399 return ret; 1400 1401 rtw_sec_enable_sec_engine(rtwdev); 1402 1403 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1404 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1405 1406 /* rcr reset after powered on */ 1407 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1408 1409 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1410 RTW_WATCH_DOG_DELAY_TIME); 1411 1412 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1413 1414 return 0; 1415 } 1416 1417 static void rtw_power_off(struct rtw_dev *rtwdev) 1418 { 1419 rtw_hci_stop(rtwdev); 1420 rtw_coex_power_off_setting(rtwdev); 1421 rtw_mac_power_off(rtwdev); 1422 } 1423 1424 void rtw_core_stop(struct rtw_dev *rtwdev) 1425 { 1426 struct rtw_coex *coex = &rtwdev->coex; 1427 1428 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1429 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1430 1431 mutex_unlock(&rtwdev->mutex); 1432 1433 cancel_work_sync(&rtwdev->c2h_work); 1434 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1435 cancel_delayed_work_sync(&coex->bt_relink_work); 1436 cancel_delayed_work_sync(&coex->bt_reenable_work); 1437 cancel_delayed_work_sync(&coex->defreeze_work); 1438 cancel_delayed_work_sync(&coex->wl_remain_work); 1439 cancel_delayed_work_sync(&coex->bt_remain_work); 1440 cancel_delayed_work_sync(&coex->wl_connecting_work); 1441 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1442 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1443 1444 mutex_lock(&rtwdev->mutex); 1445 1446 rtw_power_off(rtwdev); 1447 } 1448 1449 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1450 struct ieee80211_sta_ht_cap *ht_cap) 1451 { 1452 struct rtw_efuse *efuse = &rtwdev->efuse; 1453 1454 ht_cap->ht_supported = true; 1455 ht_cap->cap = 0; 1456 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1457 IEEE80211_HT_CAP_MAX_AMSDU | 1458 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1459 1460 if (rtw_chip_has_rx_ldpc(rtwdev)) 1461 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1462 if (rtw_chip_has_tx_stbc(rtwdev)) 1463 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1464 1465 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1466 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1467 IEEE80211_HT_CAP_DSSSCCK40 | 1468 IEEE80211_HT_CAP_SGI_40; 1469 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1470 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 1471 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1472 if (efuse->hw_cap.nss > 1) { 1473 ht_cap->mcs.rx_mask[0] = 0xFF; 1474 ht_cap->mcs.rx_mask[1] = 0xFF; 1475 ht_cap->mcs.rx_mask[4] = 0x01; 1476 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1477 } else { 1478 ht_cap->mcs.rx_mask[0] = 0xFF; 1479 ht_cap->mcs.rx_mask[1] = 0x00; 1480 ht_cap->mcs.rx_mask[4] = 0x01; 1481 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1482 } 1483 } 1484 1485 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1486 struct ieee80211_sta_vht_cap *vht_cap) 1487 { 1488 struct rtw_efuse *efuse = &rtwdev->efuse; 1489 u16 mcs_map; 1490 __le16 highest; 1491 1492 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1493 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1494 return; 1495 1496 vht_cap->vht_supported = true; 1497 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1498 IEEE80211_VHT_CAP_SHORT_GI_80 | 1499 IEEE80211_VHT_CAP_RXSTBC_1 | 1500 IEEE80211_VHT_CAP_HTC_VHT | 1501 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1502 0; 1503 if (rtwdev->hal.rf_path_num > 1) 1504 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1505 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1506 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1507 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1508 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1509 1510 if (rtw_chip_has_rx_ldpc(rtwdev)) 1511 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1512 1513 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1514 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1515 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1516 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1517 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1518 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1519 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1520 if (efuse->hw_cap.nss > 1) { 1521 highest = cpu_to_le16(780); 1522 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1523 } else { 1524 highest = cpu_to_le16(390); 1525 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1526 } 1527 1528 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1529 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1530 vht_cap->vht_mcs.rx_highest = highest; 1531 vht_cap->vht_mcs.tx_highest = highest; 1532 } 1533 1534 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1535 struct rtw_chip_info *chip) 1536 { 1537 struct rtw_dev *rtwdev = hw->priv; 1538 struct ieee80211_supported_band *sband; 1539 1540 if (chip->band & RTW_BAND_2G) { 1541 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1542 if (!sband) 1543 goto err_out; 1544 if (chip->ht_supported) 1545 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1546 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1547 } 1548 1549 if (chip->band & RTW_BAND_5G) { 1550 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1551 if (!sband) 1552 goto err_out; 1553 if (chip->ht_supported) 1554 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1555 if (chip->vht_supported) 1556 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1557 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1558 } 1559 1560 return; 1561 1562 err_out: 1563 rtw_err(rtwdev, "failed to set supported band\n"); 1564 } 1565 1566 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1567 struct rtw_chip_info *chip) 1568 { 1569 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1570 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1571 } 1572 1573 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1574 struct rtw_fw_state *fw) 1575 { 1576 u32 feature; 1577 const struct rtw_fw_hdr *fw_hdr = 1578 (const struct rtw_fw_hdr *)fw->firmware->data; 1579 1580 feature = le32_to_cpu(fw_hdr->feature); 1581 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1582 } 1583 1584 static void __update_firmware_info(struct rtw_dev *rtwdev, 1585 struct rtw_fw_state *fw) 1586 { 1587 const struct rtw_fw_hdr *fw_hdr = 1588 (const struct rtw_fw_hdr *)fw->firmware->data; 1589 1590 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1591 fw->version = le16_to_cpu(fw_hdr->version); 1592 fw->sub_version = fw_hdr->subversion; 1593 fw->sub_index = fw_hdr->subindex; 1594 1595 __update_firmware_feature(rtwdev, fw); 1596 } 1597 1598 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1599 struct rtw_fw_state *fw) 1600 { 1601 struct rtw_fw_hdr_legacy *legacy = 1602 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1603 1604 fw->h2c_version = 0; 1605 fw->version = le16_to_cpu(legacy->version); 1606 fw->sub_version = legacy->subversion1; 1607 fw->sub_index = legacy->subversion2; 1608 } 1609 1610 static void update_firmware_info(struct rtw_dev *rtwdev, 1611 struct rtw_fw_state *fw) 1612 { 1613 if (rtw_chip_wcpu_11n(rtwdev)) 1614 __update_firmware_info_legacy(rtwdev, fw); 1615 else 1616 __update_firmware_info(rtwdev, fw); 1617 } 1618 1619 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1620 { 1621 struct rtw_fw_state *fw = context; 1622 struct rtw_dev *rtwdev = fw->rtwdev; 1623 1624 if (!firmware || !firmware->data) { 1625 rtw_err(rtwdev, "failed to request firmware\n"); 1626 complete_all(&fw->completion); 1627 return; 1628 } 1629 1630 fw->firmware = firmware; 1631 update_firmware_info(rtwdev, fw); 1632 complete_all(&fw->completion); 1633 1634 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1635 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1636 } 1637 1638 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1639 { 1640 const char *fw_name; 1641 struct rtw_fw_state *fw; 1642 int ret; 1643 1644 switch (type) { 1645 case RTW_WOWLAN_FW: 1646 fw = &rtwdev->wow_fw; 1647 fw_name = rtwdev->chip->wow_fw_name; 1648 break; 1649 1650 case RTW_NORMAL_FW: 1651 fw = &rtwdev->fw; 1652 fw_name = rtwdev->chip->fw_name; 1653 break; 1654 1655 default: 1656 rtw_warn(rtwdev, "unsupported firmware type\n"); 1657 return -ENOENT; 1658 } 1659 1660 fw->rtwdev = rtwdev; 1661 init_completion(&fw->completion); 1662 1663 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1664 GFP_KERNEL, fw, rtw_load_firmware_cb); 1665 if (ret) { 1666 rtw_err(rtwdev, "failed to async firmware request\n"); 1667 return ret; 1668 } 1669 1670 return 0; 1671 } 1672 1673 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1674 { 1675 struct rtw_chip_info *chip = rtwdev->chip; 1676 struct rtw_hal *hal = &rtwdev->hal; 1677 struct rtw_efuse *efuse = &rtwdev->efuse; 1678 1679 switch (rtw_hci_type(rtwdev)) { 1680 case RTW_HCI_TYPE_PCIE: 1681 rtwdev->hci.rpwm_addr = 0x03d9; 1682 rtwdev->hci.cpwm_addr = 0x03da; 1683 break; 1684 default: 1685 rtw_err(rtwdev, "unsupported hci type\n"); 1686 return -EINVAL; 1687 } 1688 1689 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1690 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1691 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1692 if (hal->chip_version & BIT_RF_TYPE_ID) { 1693 hal->rf_type = RF_2T2R; 1694 hal->rf_path_num = 2; 1695 hal->antenna_tx = BB_PATH_AB; 1696 hal->antenna_rx = BB_PATH_AB; 1697 } else { 1698 hal->rf_type = RF_1T1R; 1699 hal->rf_path_num = 1; 1700 hal->antenna_tx = BB_PATH_A; 1701 hal->antenna_rx = BB_PATH_A; 1702 } 1703 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1704 hal->rf_path_num; 1705 1706 efuse->physical_size = chip->phy_efuse_size; 1707 efuse->logical_size = chip->log_efuse_size; 1708 efuse->protect_size = chip->ptct_efuse_size; 1709 1710 /* default use ack */ 1711 rtwdev->hal.rcr |= BIT_VHT_DACK; 1712 1713 hal->bfee_sts_cap = 3; 1714 1715 return 0; 1716 } 1717 1718 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1719 { 1720 struct rtw_fw_state *fw = &rtwdev->fw; 1721 int ret; 1722 1723 ret = rtw_hci_setup(rtwdev); 1724 if (ret) { 1725 rtw_err(rtwdev, "failed to setup hci\n"); 1726 goto err; 1727 } 1728 1729 ret = rtw_mac_power_on(rtwdev); 1730 if (ret) { 1731 rtw_err(rtwdev, "failed to power on mac\n"); 1732 goto err; 1733 } 1734 1735 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1736 1737 wait_for_completion(&fw->completion); 1738 if (!fw->firmware) { 1739 ret = -EINVAL; 1740 rtw_err(rtwdev, "failed to load firmware\n"); 1741 goto err; 1742 } 1743 1744 ret = rtw_download_firmware(rtwdev, fw); 1745 if (ret) { 1746 rtw_err(rtwdev, "failed to download firmware\n"); 1747 goto err_off; 1748 } 1749 1750 return 0; 1751 1752 err_off: 1753 rtw_mac_power_off(rtwdev); 1754 1755 err: 1756 return ret; 1757 } 1758 1759 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1760 { 1761 struct rtw_efuse *efuse = &rtwdev->efuse; 1762 u8 hw_feature[HW_FEATURE_LEN]; 1763 u8 id; 1764 u8 bw; 1765 int i; 1766 1767 id = rtw_read8(rtwdev, REG_C2HEVT); 1768 if (id != C2H_HW_FEATURE_REPORT) { 1769 rtw_err(rtwdev, "failed to read hw feature report\n"); 1770 return -EBUSY; 1771 } 1772 1773 for (i = 0; i < HW_FEATURE_LEN; i++) 1774 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1775 1776 rtw_write8(rtwdev, REG_C2HEVT, 0); 1777 1778 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1779 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1780 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1781 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1782 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1783 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1784 1785 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1786 1787 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1788 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1789 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1790 1791 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1792 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1793 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1794 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1795 1796 return 0; 1797 } 1798 1799 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1800 { 1801 rtw_hci_stop(rtwdev); 1802 rtw_mac_power_off(rtwdev); 1803 } 1804 1805 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1806 { 1807 struct rtw_efuse *efuse = &rtwdev->efuse; 1808 int ret; 1809 1810 mutex_lock(&rtwdev->mutex); 1811 1812 /* power on mac to read efuse */ 1813 ret = rtw_chip_efuse_enable(rtwdev); 1814 if (ret) 1815 goto out_unlock; 1816 1817 ret = rtw_parse_efuse_map(rtwdev); 1818 if (ret) 1819 goto out_disable; 1820 1821 ret = rtw_dump_hw_feature(rtwdev); 1822 if (ret) 1823 goto out_disable; 1824 1825 ret = rtw_check_supported_rfe(rtwdev); 1826 if (ret) 1827 goto out_disable; 1828 1829 if (efuse->crystal_cap == 0xff) 1830 efuse->crystal_cap = 0; 1831 if (efuse->pa_type_2g == 0xff) 1832 efuse->pa_type_2g = 0; 1833 if (efuse->pa_type_5g == 0xff) 1834 efuse->pa_type_5g = 0; 1835 if (efuse->lna_type_2g == 0xff) 1836 efuse->lna_type_2g = 0; 1837 if (efuse->lna_type_5g == 0xff) 1838 efuse->lna_type_5g = 0; 1839 if (efuse->channel_plan == 0xff) 1840 efuse->channel_plan = 0x7f; 1841 if (efuse->rf_board_option == 0xff) 1842 efuse->rf_board_option = 0; 1843 if (efuse->bt_setting & BIT(0)) 1844 efuse->share_ant = true; 1845 if (efuse->regd == 0xff) 1846 efuse->regd = 0; 1847 if (efuse->tx_bb_swing_setting_2g == 0xff) 1848 efuse->tx_bb_swing_setting_2g = 0; 1849 if (efuse->tx_bb_swing_setting_5g == 0xff) 1850 efuse->tx_bb_swing_setting_5g = 0; 1851 1852 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1853 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1854 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1855 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1856 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1857 1858 out_disable: 1859 rtw_chip_efuse_disable(rtwdev); 1860 1861 out_unlock: 1862 mutex_unlock(&rtwdev->mutex); 1863 return ret; 1864 } 1865 1866 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1867 { 1868 struct rtw_hal *hal = &rtwdev->hal; 1869 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1870 1871 if (!rfe_def) 1872 return -ENODEV; 1873 1874 rtw_phy_setup_phy_cond(rtwdev, 0); 1875 1876 rtw_phy_init_tx_power(rtwdev); 1877 if (rfe_def->agc_btg_tbl) 1878 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1879 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1880 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1881 rtw_phy_tx_power_by_rate_config(hal); 1882 rtw_phy_tx_power_limit_config(hal); 1883 1884 return 0; 1885 } 1886 1887 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1888 { 1889 int ret; 1890 1891 ret = rtw_chip_parameter_setup(rtwdev); 1892 if (ret) { 1893 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1894 goto err_out; 1895 } 1896 1897 ret = rtw_chip_efuse_info_setup(rtwdev); 1898 if (ret) { 1899 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1900 goto err_out; 1901 } 1902 1903 ret = rtw_chip_board_info_setup(rtwdev); 1904 if (ret) { 1905 rtw_err(rtwdev, "failed to setup chip board info\n"); 1906 goto err_out; 1907 } 1908 1909 return 0; 1910 1911 err_out: 1912 return ret; 1913 } 1914 EXPORT_SYMBOL(rtw_chip_info_setup); 1915 1916 static void rtw_stats_init(struct rtw_dev *rtwdev) 1917 { 1918 struct rtw_traffic_stats *stats = &rtwdev->stats; 1919 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1920 int i; 1921 1922 ewma_tp_init(&stats->tx_ewma_tp); 1923 ewma_tp_init(&stats->rx_ewma_tp); 1924 1925 for (i = 0; i < RTW_EVM_NUM; i++) 1926 ewma_evm_init(&dm_info->ewma_evm[i]); 1927 for (i = 0; i < RTW_SNR_NUM; i++) 1928 ewma_snr_init(&dm_info->ewma_snr[i]); 1929 } 1930 1931 int rtw_core_init(struct rtw_dev *rtwdev) 1932 { 1933 struct rtw_chip_info *chip = rtwdev->chip; 1934 struct rtw_coex *coex = &rtwdev->coex; 1935 int ret; 1936 1937 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1938 INIT_LIST_HEAD(&rtwdev->txqs); 1939 1940 timer_setup(&rtwdev->tx_report.purge_timer, 1941 rtw_tx_report_purge_timer, 0); 1942 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1943 1944 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1945 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1946 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1947 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1948 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1949 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1950 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1951 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1952 rtw_coex_bt_multi_link_remain_work); 1953 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 1954 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 1955 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1956 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 1957 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 1958 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1959 skb_queue_head_init(&rtwdev->c2h_queue); 1960 skb_queue_head_init(&rtwdev->coex.queue); 1961 skb_queue_head_init(&rtwdev->tx_report.queue); 1962 1963 spin_lock_init(&rtwdev->rf_lock); 1964 spin_lock_init(&rtwdev->h2c.lock); 1965 spin_lock_init(&rtwdev->txq_lock); 1966 spin_lock_init(&rtwdev->tx_report.q_lock); 1967 1968 mutex_init(&rtwdev->mutex); 1969 mutex_init(&rtwdev->coex.mutex); 1970 mutex_init(&rtwdev->hal.tx_power_mutex); 1971 1972 init_waitqueue_head(&rtwdev->coex.wait); 1973 init_completion(&rtwdev->lps_leave_check); 1974 init_completion(&rtwdev->fw_scan_density); 1975 1976 rtwdev->sec.total_cam_num = 32; 1977 rtwdev->hal.current_channel = 1; 1978 rtwdev->dm_info.fix_rate = U8_MAX; 1979 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1980 1981 rtw_stats_init(rtwdev); 1982 1983 /* default rx filter setting */ 1984 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1985 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1986 BIT_AB | BIT_AM | BIT_APM; 1987 1988 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 1989 if (ret) { 1990 rtw_warn(rtwdev, "no firmware loaded\n"); 1991 return ret; 1992 } 1993 1994 if (chip->wow_fw_name) { 1995 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 1996 if (ret) { 1997 rtw_warn(rtwdev, "no wow firmware loaded\n"); 1998 wait_for_completion(&rtwdev->fw.completion); 1999 if (rtwdev->fw.firmware) 2000 release_firmware(rtwdev->fw.firmware); 2001 return ret; 2002 } 2003 } 2004 2005 return 0; 2006 } 2007 EXPORT_SYMBOL(rtw_core_init); 2008 2009 void rtw_core_deinit(struct rtw_dev *rtwdev) 2010 { 2011 struct rtw_fw_state *fw = &rtwdev->fw; 2012 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2013 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2014 unsigned long flags; 2015 2016 rtw_wait_firmware_completion(rtwdev); 2017 2018 if (fw->firmware) 2019 release_firmware(fw->firmware); 2020 2021 if (wow_fw->firmware) 2022 release_firmware(wow_fw->firmware); 2023 2024 destroy_workqueue(rtwdev->tx_wq); 2025 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2026 skb_queue_purge(&rtwdev->tx_report.queue); 2027 skb_queue_purge(&rtwdev->coex.queue); 2028 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2029 2030 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2031 build_list) { 2032 list_del(&rsvd_pkt->build_list); 2033 kfree(rsvd_pkt); 2034 } 2035 2036 mutex_destroy(&rtwdev->mutex); 2037 mutex_destroy(&rtwdev->coex.mutex); 2038 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2039 } 2040 EXPORT_SYMBOL(rtw_core_deinit); 2041 2042 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2043 { 2044 struct rtw_hal *hal = &rtwdev->hal; 2045 int max_tx_headroom = 0; 2046 int ret; 2047 2048 /* TODO: USB & SDIO may need extra room? */ 2049 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2050 2051 hw->extra_tx_headroom = max_tx_headroom; 2052 hw->queues = IEEE80211_NUM_ACS; 2053 hw->txq_data_size = sizeof(struct rtw_txq); 2054 hw->sta_data_size = sizeof(struct rtw_sta_info); 2055 hw->vif_data_size = sizeof(struct rtw_vif); 2056 2057 ieee80211_hw_set(hw, SIGNAL_DBM); 2058 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2059 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2060 ieee80211_hw_set(hw, MFP_CAPABLE); 2061 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2062 ieee80211_hw_set(hw, SUPPORTS_PS); 2063 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2064 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2065 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2066 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2067 ieee80211_hw_set(hw, TX_AMSDU); 2068 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2069 2070 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2071 BIT(NL80211_IFTYPE_AP) | 2072 BIT(NL80211_IFTYPE_ADHOC) | 2073 BIT(NL80211_IFTYPE_MESH_POINT); 2074 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2075 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2076 2077 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2078 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2079 2080 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2081 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2082 hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN; 2083 2084 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2085 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2086 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2087 2088 #ifdef CONFIG_PM 2089 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2090 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2091 #endif 2092 rtw_set_supported_band(hw, rtwdev->chip); 2093 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2094 2095 hw->wiphy->sar_capa = &rtw_sar_capa; 2096 2097 ret = rtw_regd_init(rtwdev); 2098 if (ret) { 2099 rtw_err(rtwdev, "failed to init regd\n"); 2100 return ret; 2101 } 2102 2103 ret = ieee80211_register_hw(hw); 2104 if (ret) { 2105 rtw_err(rtwdev, "failed to register hw\n"); 2106 return ret; 2107 } 2108 2109 ret = rtw_regd_hint(rtwdev); 2110 if (ret) { 2111 rtw_err(rtwdev, "failed to hint regd\n"); 2112 return ret; 2113 } 2114 2115 rtw_debugfs_init(rtwdev); 2116 2117 rtwdev->bf_info.bfer_mu_cnt = 0; 2118 rtwdev->bf_info.bfer_su_cnt = 0; 2119 2120 return 0; 2121 } 2122 EXPORT_SYMBOL(rtw_register_hw); 2123 2124 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2125 { 2126 struct rtw_chip_info *chip = rtwdev->chip; 2127 2128 ieee80211_unregister_hw(hw); 2129 rtw_unset_supported_band(hw, chip); 2130 } 2131 EXPORT_SYMBOL(rtw_unregister_hw); 2132 2133 MODULE_AUTHOR("Realtek Corporation"); 2134 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2135 MODULE_LICENSE("Dual BSD/GPL"); 2136