1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 21 bool rtw_disable_lps_deep_mode; 22 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 23 bool rtw_bf_support = true; 24 unsigned int rtw_debug_mask; 25 EXPORT_SYMBOL(rtw_debug_mask); 26 /* EDCCA is enabled during normal behavior. For debugging purpose in 27 * a noisy environment, it can be disabled via edcca debugfs. Because 28 * all rtw88 devices will probably be affected if environment is noisy, 29 * rtw_edcca_enabled is just declared by driver instead of by device. 30 * So, turning it off will take effect for all rtw88 devices before 31 * there is a tough reason to maintain rtw_edcca_enabled by device. 32 */ 33 bool rtw_edcca_enabled = true; 34 35 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 36 module_param_named(support_bf, rtw_bf_support, bool, 0644); 37 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 38 39 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 40 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 41 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 42 43 static struct ieee80211_channel rtw_channeltable_2g[] = { 44 {.center_freq = 2412, .hw_value = 1,}, 45 {.center_freq = 2417, .hw_value = 2,}, 46 {.center_freq = 2422, .hw_value = 3,}, 47 {.center_freq = 2427, .hw_value = 4,}, 48 {.center_freq = 2432, .hw_value = 5,}, 49 {.center_freq = 2437, .hw_value = 6,}, 50 {.center_freq = 2442, .hw_value = 7,}, 51 {.center_freq = 2447, .hw_value = 8,}, 52 {.center_freq = 2452, .hw_value = 9,}, 53 {.center_freq = 2457, .hw_value = 10,}, 54 {.center_freq = 2462, .hw_value = 11,}, 55 {.center_freq = 2467, .hw_value = 12,}, 56 {.center_freq = 2472, .hw_value = 13,}, 57 {.center_freq = 2484, .hw_value = 14,}, 58 }; 59 60 static struct ieee80211_channel rtw_channeltable_5g[] = { 61 {.center_freq = 5180, .hw_value = 36,}, 62 {.center_freq = 5200, .hw_value = 40,}, 63 {.center_freq = 5220, .hw_value = 44,}, 64 {.center_freq = 5240, .hw_value = 48,}, 65 {.center_freq = 5260, .hw_value = 52,}, 66 {.center_freq = 5280, .hw_value = 56,}, 67 {.center_freq = 5300, .hw_value = 60,}, 68 {.center_freq = 5320, .hw_value = 64,}, 69 {.center_freq = 5500, .hw_value = 100,}, 70 {.center_freq = 5520, .hw_value = 104,}, 71 {.center_freq = 5540, .hw_value = 108,}, 72 {.center_freq = 5560, .hw_value = 112,}, 73 {.center_freq = 5580, .hw_value = 116,}, 74 {.center_freq = 5600, .hw_value = 120,}, 75 {.center_freq = 5620, .hw_value = 124,}, 76 {.center_freq = 5640, .hw_value = 128,}, 77 {.center_freq = 5660, .hw_value = 132,}, 78 {.center_freq = 5680, .hw_value = 136,}, 79 {.center_freq = 5700, .hw_value = 140,}, 80 {.center_freq = 5720, .hw_value = 144,}, 81 {.center_freq = 5745, .hw_value = 149,}, 82 {.center_freq = 5765, .hw_value = 153,}, 83 {.center_freq = 5785, .hw_value = 157,}, 84 {.center_freq = 5805, .hw_value = 161,}, 85 {.center_freq = 5825, .hw_value = 165, 86 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 87 }; 88 89 static struct ieee80211_rate rtw_ratetable[] = { 90 {.bitrate = 10, .hw_value = 0x00,}, 91 {.bitrate = 20, .hw_value = 0x01,}, 92 {.bitrate = 55, .hw_value = 0x02,}, 93 {.bitrate = 110, .hw_value = 0x03,}, 94 {.bitrate = 60, .hw_value = 0x04,}, 95 {.bitrate = 90, .hw_value = 0x05,}, 96 {.bitrate = 120, .hw_value = 0x06,}, 97 {.bitrate = 180, .hw_value = 0x07,}, 98 {.bitrate = 240, .hw_value = 0x08,}, 99 {.bitrate = 360, .hw_value = 0x09,}, 100 {.bitrate = 480, .hw_value = 0x0a,}, 101 {.bitrate = 540, .hw_value = 0x0b,}, 102 }; 103 104 u16 rtw_desc_to_bitrate(u8 desc_rate) 105 { 106 struct ieee80211_rate rate; 107 108 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 109 return 0; 110 111 rate = rtw_ratetable[desc_rate]; 112 113 return rate.bitrate; 114 } 115 116 static struct ieee80211_supported_band rtw_band_2ghz = { 117 .band = NL80211_BAND_2GHZ, 118 119 .channels = rtw_channeltable_2g, 120 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 121 122 .bitrates = rtw_ratetable, 123 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 124 125 .ht_cap = {0}, 126 .vht_cap = {0}, 127 }; 128 129 static struct ieee80211_supported_band rtw_band_5ghz = { 130 .band = NL80211_BAND_5GHZ, 131 132 .channels = rtw_channeltable_5g, 133 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 134 135 /* 5G has no CCK rates */ 136 .bitrates = rtw_ratetable + 4, 137 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 138 139 .ht_cap = {0}, 140 .vht_cap = {0}, 141 }; 142 143 struct rtw_watch_dog_iter_data { 144 struct rtw_dev *rtwdev; 145 struct rtw_vif *rtwvif; 146 }; 147 148 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 149 { 150 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 151 u8 fix_rate_enable = 0; 152 u8 new_csi_rate_idx; 153 154 if (rtwvif->bfee.role != RTW_BFEE_SU && 155 rtwvif->bfee.role != RTW_BFEE_MU) 156 return; 157 158 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 159 bf_info->cur_csi_rpt_rate, 160 fix_rate_enable, &new_csi_rate_idx); 161 162 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 163 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 164 } 165 166 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 167 struct ieee80211_vif *vif) 168 { 169 struct rtw_watch_dog_iter_data *iter_data = data; 170 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 171 172 if (vif->type == NL80211_IFTYPE_STATION) 173 if (vif->bss_conf.assoc) 174 iter_data->rtwvif = rtwvif; 175 176 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 177 178 rtwvif->stats.tx_unicast = 0; 179 rtwvif->stats.rx_unicast = 0; 180 rtwvif->stats.tx_cnt = 0; 181 rtwvif->stats.rx_cnt = 0; 182 } 183 184 /* process TX/RX statistics periodically for hardware, 185 * the information helps hardware to enhance performance 186 */ 187 static void rtw_watch_dog_work(struct work_struct *work) 188 { 189 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 190 watch_dog_work.work); 191 struct rtw_traffic_stats *stats = &rtwdev->stats; 192 struct rtw_watch_dog_iter_data data = {}; 193 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 194 bool ps_active; 195 196 mutex_lock(&rtwdev->mutex); 197 198 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 199 goto unlock; 200 201 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 202 RTW_WATCH_DOG_DELAY_TIME); 203 204 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 205 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 206 else 207 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 208 209 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 210 rtw_coex_wl_status_change_notify(rtwdev, 0); 211 212 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 213 stats->rx_cnt > RTW_LPS_THRESHOLD) 214 ps_active = true; 215 else 216 ps_active = false; 217 218 ewma_tp_add(&stats->tx_ewma_tp, 219 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 220 ewma_tp_add(&stats->rx_ewma_tp, 221 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 222 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 223 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 224 225 /* reset tx/rx statictics */ 226 stats->tx_unicast = 0; 227 stats->rx_unicast = 0; 228 stats->tx_cnt = 0; 229 stats->rx_cnt = 0; 230 231 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 232 goto unlock; 233 234 /* make sure BB/RF is working for dynamic mech */ 235 rtw_leave_lps(rtwdev); 236 237 rtw_phy_dynamic_mechanism(rtwdev); 238 239 data.rtwdev = rtwdev; 240 /* use atomic version to avoid taking local->iflist_mtx mutex */ 241 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 242 243 /* fw supports only one station associated to enter lps, if there are 244 * more than two stations associated to the AP, then we can not enter 245 * lps, because fw does not handle the overlapped beacon interval 246 * 247 * mac80211 should iterate vifs and determine if driver can enter 248 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 249 * get that vif and check if device is having traffic more than the 250 * threshold. 251 */ 252 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 253 !rtwdev->beacon_loss) 254 rtw_enter_lps(rtwdev, data.rtwvif->port); 255 256 rtwdev->watch_dog_cnt++; 257 258 unlock: 259 mutex_unlock(&rtwdev->mutex); 260 } 261 262 static void rtw_c2h_work(struct work_struct *work) 263 { 264 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 265 struct sk_buff *skb, *tmp; 266 267 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 268 skb_unlink(skb, &rtwdev->c2h_queue); 269 rtw_fw_c2h_cmd_handle(rtwdev, skb); 270 dev_kfree_skb_any(skb); 271 } 272 } 273 274 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 275 { 276 unsigned long mac_id; 277 278 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 279 if (mac_id < RTW_MAX_MAC_ID_NUM) 280 set_bit(mac_id, rtwdev->mac_id_map); 281 282 return mac_id; 283 } 284 285 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 286 struct ieee80211_vif *vif) 287 { 288 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 289 int i; 290 291 si->mac_id = rtw_acquire_macid(rtwdev); 292 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 293 return -ENOSPC; 294 295 si->sta = sta; 296 si->vif = vif; 297 si->init_ra_lv = 1; 298 ewma_rssi_init(&si->avg_rssi); 299 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 300 rtw_txq_init(rtwdev, sta->txq[i]); 301 302 rtw_update_sta_info(rtwdev, si); 303 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 304 305 rtwdev->sta_cnt++; 306 rtwdev->beacon_loss = false; 307 rtw_info(rtwdev, "sta %pM joined with macid %d\n", 308 sta->addr, si->mac_id); 309 310 return 0; 311 } 312 313 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 314 bool fw_exist) 315 { 316 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 317 int i; 318 319 rtw_release_macid(rtwdev, si->mac_id); 320 if (fw_exist) 321 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 322 323 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 324 rtw_txq_cleanup(rtwdev, sta->txq[i]); 325 326 kfree(si->mask); 327 328 rtwdev->sta_cnt--; 329 rtw_info(rtwdev, "sta %pM with macid %d left\n", 330 sta->addr, si->mac_id); 331 } 332 333 struct rtw_fwcd_hdr { 334 u32 item; 335 u32 size; 336 u32 padding1; 337 u32 padding2; 338 } __packed; 339 340 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 341 { 342 struct rtw_chip_info *chip = rtwdev->chip; 343 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 344 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 345 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 346 u8 i; 347 348 if (segs) { 349 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 350 351 for (i = 0; i < segs->num; i++) 352 prep_size += segs->segs[i]; 353 } 354 355 desc->data = vmalloc(prep_size); 356 if (!desc->data) 357 return -ENOMEM; 358 359 desc->size = prep_size; 360 desc->next = desc->data; 361 362 return 0; 363 } 364 365 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 366 { 367 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 368 struct rtw_fwcd_hdr *hdr; 369 u8 *next; 370 371 if (!desc->data) { 372 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 373 return NULL; 374 } 375 376 next = desc->next + sizeof(struct rtw_fwcd_hdr); 377 if (next - desc->data + size > desc->size) { 378 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 379 return NULL; 380 } 381 382 hdr = (struct rtw_fwcd_hdr *)(desc->next); 383 hdr->item = item; 384 hdr->size = size; 385 hdr->padding1 = 0x01234567; 386 hdr->padding2 = 0x89abcdef; 387 desc->next = next + size; 388 389 return next; 390 } 391 392 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 393 { 394 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 395 396 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 397 398 /* Data will be freed after lifetime of device coredump. After calling 399 * dev_coredump, data is supposed to be handled by the device coredump 400 * framework. Note that a new dump will be discarded if a previous one 401 * hasn't been released yet. 402 */ 403 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 404 } 405 406 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 407 { 408 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 409 410 if (free_self) { 411 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 412 vfree(desc->data); 413 } 414 415 desc->data = NULL; 416 desc->next = NULL; 417 } 418 419 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 420 { 421 u32 size = rtwdev->chip->fw_rxff_size; 422 u32 *buf; 423 u8 seq; 424 425 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 426 if (!buf) 427 return -ENOMEM; 428 429 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 430 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 431 return -EINVAL; 432 } 433 434 if (GET_FW_DUMP_LEN(buf) == 0) { 435 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 436 return -EINVAL; 437 } 438 439 seq = GET_FW_DUMP_SEQ(buf); 440 if (seq > 0) { 441 rtw_dbg(rtwdev, RTW_DBG_FW, 442 "fw crash dump's seq is wrong: %d\n", seq); 443 return -EINVAL; 444 } 445 446 return 0; 447 } 448 449 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 450 u32 fwcd_item) 451 { 452 u32 rxff = rtwdev->chip->fw_rxff_size; 453 u32 dump_size, done_size = 0; 454 u8 *buf; 455 int ret; 456 457 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 458 if (!buf) 459 return -ENOMEM; 460 461 while (size) { 462 dump_size = size > rxff ? rxff : size; 463 464 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 465 dump_size); 466 if (ret) { 467 rtw_err(rtwdev, 468 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 469 ocp_src, done_size); 470 return ret; 471 } 472 473 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 474 dump_size, (u32 *)(buf + done_size)); 475 if (ret) { 476 rtw_err(rtwdev, 477 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 478 ocp_src, done_size); 479 return ret; 480 } 481 482 size -= dump_size; 483 done_size += dump_size; 484 } 485 486 return 0; 487 } 488 EXPORT_SYMBOL(rtw_dump_fw); 489 490 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 491 { 492 u8 *buf; 493 u32 i; 494 495 if (addr & 0x3) { 496 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 497 return -EINVAL; 498 } 499 500 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 501 if (!buf) 502 return -ENOMEM; 503 504 for (i = 0; i < size; i += 4) 505 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 506 507 return 0; 508 } 509 EXPORT_SYMBOL(rtw_dump_reg); 510 511 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 512 struct ieee80211_bss_conf *conf) 513 { 514 if (conf && conf->assoc) { 515 rtwvif->aid = conf->aid; 516 rtwvif->net_type = RTW_NET_MGD_LINKED; 517 } else { 518 rtwvif->aid = 0; 519 rtwvif->net_type = RTW_NET_NO_LINK; 520 } 521 } 522 523 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 524 struct ieee80211_vif *vif, 525 struct ieee80211_sta *sta, 526 struct ieee80211_key_conf *key, 527 void *data) 528 { 529 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 530 struct rtw_sec_desc *sec = &rtwdev->sec; 531 532 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 533 } 534 535 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 536 { 537 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 538 539 if (rtwdev->sta_cnt == 0) { 540 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 541 return; 542 } 543 rtw_sta_remove(rtwdev, sta, false); 544 } 545 546 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 547 { 548 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 549 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 550 551 rtw_bf_disassoc(rtwdev, vif, NULL); 552 rtw_vif_assoc_changed(rtwvif, NULL); 553 rtw_txq_cleanup(rtwdev, vif->txq); 554 } 555 556 void rtw_fw_recovery(struct rtw_dev *rtwdev) 557 { 558 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 559 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 560 } 561 562 static void __fw_recovery_work(struct rtw_dev *rtwdev) 563 { 564 int ret = 0; 565 566 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 567 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 568 569 ret = rtw_fwcd_prep(rtwdev); 570 if (ret) 571 goto free; 572 ret = rtw_fw_dump_crash_log(rtwdev); 573 if (ret) 574 goto free; 575 ret = rtw_chip_dump_fw_crash(rtwdev); 576 if (ret) 577 goto free; 578 579 rtw_fwcd_dump(rtwdev); 580 free: 581 rtw_fwcd_free(rtwdev, !!ret); 582 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 583 584 WARN(1, "firmware crash, start reset and recover\n"); 585 586 rcu_read_lock(); 587 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 588 rcu_read_unlock(); 589 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 590 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 591 rtw_enter_ips(rtwdev); 592 } 593 594 static void rtw_fw_recovery_work(struct work_struct *work) 595 { 596 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 597 fw_recovery_work); 598 599 mutex_lock(&rtwdev->mutex); 600 __fw_recovery_work(rtwdev); 601 mutex_unlock(&rtwdev->mutex); 602 603 ieee80211_restart_hw(rtwdev->hw); 604 } 605 606 struct rtw_txq_ba_iter_data { 607 }; 608 609 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 610 { 611 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 612 int ret; 613 u8 tid; 614 615 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 616 while (tid != IEEE80211_NUM_TIDS) { 617 clear_bit(tid, si->tid_ba); 618 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 619 if (ret == -EINVAL) { 620 struct ieee80211_txq *txq; 621 struct rtw_txq *rtwtxq; 622 623 txq = sta->txq[tid]; 624 rtwtxq = (struct rtw_txq *)txq->drv_priv; 625 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 626 } 627 628 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 629 } 630 } 631 632 static void rtw_txq_ba_work(struct work_struct *work) 633 { 634 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 635 struct rtw_txq_ba_iter_data data; 636 637 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 638 } 639 640 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 641 struct rtw_channel_params *chan_params) 642 { 643 struct ieee80211_channel *channel = chandef->chan; 644 enum nl80211_chan_width width = chandef->width; 645 u8 *cch_by_bw = chan_params->cch_by_bw; 646 u32 primary_freq, center_freq; 647 u8 center_chan; 648 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 649 u8 primary_chan_idx = 0; 650 u8 i; 651 652 center_chan = channel->hw_value; 653 primary_freq = channel->center_freq; 654 center_freq = chandef->center_freq1; 655 656 /* assign the center channel used while 20M bw is selected */ 657 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 658 659 switch (width) { 660 case NL80211_CHAN_WIDTH_20_NOHT: 661 case NL80211_CHAN_WIDTH_20: 662 bandwidth = RTW_CHANNEL_WIDTH_20; 663 primary_chan_idx = RTW_SC_DONT_CARE; 664 break; 665 case NL80211_CHAN_WIDTH_40: 666 bandwidth = RTW_CHANNEL_WIDTH_40; 667 if (primary_freq > center_freq) { 668 primary_chan_idx = RTW_SC_20_UPPER; 669 center_chan -= 2; 670 } else { 671 primary_chan_idx = RTW_SC_20_LOWER; 672 center_chan += 2; 673 } 674 break; 675 case NL80211_CHAN_WIDTH_80: 676 bandwidth = RTW_CHANNEL_WIDTH_80; 677 if (primary_freq > center_freq) { 678 if (primary_freq - center_freq == 10) { 679 primary_chan_idx = RTW_SC_20_UPPER; 680 center_chan -= 2; 681 } else { 682 primary_chan_idx = RTW_SC_20_UPMOST; 683 center_chan -= 6; 684 } 685 /* assign the center channel used 686 * while 40M bw is selected 687 */ 688 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 689 } else { 690 if (center_freq - primary_freq == 10) { 691 primary_chan_idx = RTW_SC_20_LOWER; 692 center_chan += 2; 693 } else { 694 primary_chan_idx = RTW_SC_20_LOWEST; 695 center_chan += 6; 696 } 697 /* assign the center channel used 698 * while 40M bw is selected 699 */ 700 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 701 } 702 break; 703 default: 704 center_chan = 0; 705 break; 706 } 707 708 chan_params->center_chan = center_chan; 709 chan_params->bandwidth = bandwidth; 710 chan_params->primary_chan_idx = primary_chan_idx; 711 712 /* assign the center channel used while current bw is selected */ 713 cch_by_bw[bandwidth] = center_chan; 714 715 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 716 cch_by_bw[i] = 0; 717 } 718 719 void rtw_set_channel(struct rtw_dev *rtwdev) 720 { 721 struct ieee80211_hw *hw = rtwdev->hw; 722 struct rtw_hal *hal = &rtwdev->hal; 723 struct rtw_chip_info *chip = rtwdev->chip; 724 struct rtw_channel_params ch_param; 725 u8 center_chan, bandwidth, primary_chan_idx; 726 u8 i; 727 728 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 729 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 730 return; 731 732 center_chan = ch_param.center_chan; 733 bandwidth = ch_param.bandwidth; 734 primary_chan_idx = ch_param.primary_chan_idx; 735 736 hal->current_band_width = bandwidth; 737 hal->current_channel = center_chan; 738 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 739 740 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 741 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 742 743 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 744 745 if (hal->current_band_type == RTW_BAND_5G) { 746 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 747 } else { 748 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 749 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 750 else 751 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 752 } 753 754 rtw_phy_set_tx_power_level(rtwdev, center_chan); 755 756 /* if the channel isn't set for scanning, we will do RF calibration 757 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 758 * during scanning on each channel takes too long. 759 */ 760 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 761 rtwdev->need_rfk = true; 762 } 763 764 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 765 { 766 struct rtw_chip_info *chip = rtwdev->chip; 767 768 if (rtwdev->need_rfk) { 769 rtwdev->need_rfk = false; 770 chip->ops->phy_calibration(rtwdev); 771 } 772 } 773 774 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 775 { 776 int i; 777 778 for (i = 0; i < ETH_ALEN; i++) 779 rtw_write8(rtwdev, start + i, addr[i]); 780 } 781 782 void rtw_vif_port_config(struct rtw_dev *rtwdev, 783 struct rtw_vif *rtwvif, 784 u32 config) 785 { 786 u32 addr, mask; 787 788 if (config & PORT_SET_MAC_ADDR) { 789 addr = rtwvif->conf->mac_addr.addr; 790 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 791 } 792 if (config & PORT_SET_BSSID) { 793 addr = rtwvif->conf->bssid.addr; 794 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 795 } 796 if (config & PORT_SET_NET_TYPE) { 797 addr = rtwvif->conf->net_type.addr; 798 mask = rtwvif->conf->net_type.mask; 799 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 800 } 801 if (config & PORT_SET_AID) { 802 addr = rtwvif->conf->aid.addr; 803 mask = rtwvif->conf->aid.mask; 804 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 805 } 806 if (config & PORT_SET_BCN_CTRL) { 807 addr = rtwvif->conf->bcn_ctrl.addr; 808 mask = rtwvif->conf->bcn_ctrl.mask; 809 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 810 } 811 } 812 813 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 814 { 815 u8 bw = 0; 816 817 switch (bw_cap) { 818 case EFUSE_HW_CAP_IGNORE: 819 case EFUSE_HW_CAP_SUPP_BW80: 820 bw |= BIT(RTW_CHANNEL_WIDTH_80); 821 fallthrough; 822 case EFUSE_HW_CAP_SUPP_BW40: 823 bw |= BIT(RTW_CHANNEL_WIDTH_40); 824 fallthrough; 825 default: 826 bw |= BIT(RTW_CHANNEL_WIDTH_20); 827 break; 828 } 829 830 return bw; 831 } 832 833 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 834 { 835 struct rtw_hal *hal = &rtwdev->hal; 836 struct rtw_chip_info *chip = rtwdev->chip; 837 838 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 839 hw_ant_num >= hal->rf_path_num) 840 return; 841 842 switch (hw_ant_num) { 843 case 1: 844 hal->rf_type = RF_1T1R; 845 hal->rf_path_num = 1; 846 if (!chip->fix_rf_phy_num) 847 hal->rf_phy_num = hal->rf_path_num; 848 hal->antenna_tx = BB_PATH_A; 849 hal->antenna_rx = BB_PATH_A; 850 break; 851 default: 852 WARN(1, "invalid hw configuration from efuse\n"); 853 break; 854 } 855 } 856 857 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 858 { 859 u64 ra_mask = 0; 860 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 861 u8 vht_mcs_cap; 862 int i, nss; 863 864 /* 4SS, every two bits for MCS7/8/9 */ 865 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 866 vht_mcs_cap = mcs_map & 0x3; 867 switch (vht_mcs_cap) { 868 case 2: /* MCS9 */ 869 ra_mask |= 0x3ffULL << nss; 870 break; 871 case 1: /* MCS8 */ 872 ra_mask |= 0x1ffULL << nss; 873 break; 874 case 0: /* MCS7 */ 875 ra_mask |= 0x0ffULL << nss; 876 break; 877 default: 878 break; 879 } 880 } 881 882 return ra_mask; 883 } 884 885 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 886 { 887 u8 rate_id = 0; 888 889 switch (wireless_set) { 890 case WIRELESS_CCK: 891 rate_id = RTW_RATEID_B_20M; 892 break; 893 case WIRELESS_OFDM: 894 rate_id = RTW_RATEID_G; 895 break; 896 case WIRELESS_CCK | WIRELESS_OFDM: 897 rate_id = RTW_RATEID_BG; 898 break; 899 case WIRELESS_OFDM | WIRELESS_HT: 900 if (tx_num == 1) 901 rate_id = RTW_RATEID_GN_N1SS; 902 else if (tx_num == 2) 903 rate_id = RTW_RATEID_GN_N2SS; 904 else if (tx_num == 3) 905 rate_id = RTW_RATEID_ARFR5_N_3SS; 906 break; 907 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 908 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 909 if (tx_num == 1) 910 rate_id = RTW_RATEID_BGN_40M_1SS; 911 else if (tx_num == 2) 912 rate_id = RTW_RATEID_BGN_40M_2SS; 913 else if (tx_num == 3) 914 rate_id = RTW_RATEID_ARFR5_N_3SS; 915 else if (tx_num == 4) 916 rate_id = RTW_RATEID_ARFR7_N_4SS; 917 } else { 918 if (tx_num == 1) 919 rate_id = RTW_RATEID_BGN_20M_1SS; 920 else if (tx_num == 2) 921 rate_id = RTW_RATEID_BGN_20M_2SS; 922 else if (tx_num == 3) 923 rate_id = RTW_RATEID_ARFR5_N_3SS; 924 else if (tx_num == 4) 925 rate_id = RTW_RATEID_ARFR7_N_4SS; 926 } 927 break; 928 case WIRELESS_OFDM | WIRELESS_VHT: 929 if (tx_num == 1) 930 rate_id = RTW_RATEID_ARFR1_AC_1SS; 931 else if (tx_num == 2) 932 rate_id = RTW_RATEID_ARFR0_AC_2SS; 933 else if (tx_num == 3) 934 rate_id = RTW_RATEID_ARFR4_AC_3SS; 935 else if (tx_num == 4) 936 rate_id = RTW_RATEID_ARFR6_AC_4SS; 937 break; 938 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 939 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 940 if (tx_num == 1) 941 rate_id = RTW_RATEID_ARFR1_AC_1SS; 942 else if (tx_num == 2) 943 rate_id = RTW_RATEID_ARFR0_AC_2SS; 944 else if (tx_num == 3) 945 rate_id = RTW_RATEID_ARFR4_AC_3SS; 946 else if (tx_num == 4) 947 rate_id = RTW_RATEID_ARFR6_AC_4SS; 948 } else { 949 if (tx_num == 1) 950 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 951 else if (tx_num == 2) 952 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 953 else if (tx_num == 3) 954 rate_id = RTW_RATEID_ARFR4_AC_3SS; 955 else if (tx_num == 4) 956 rate_id = RTW_RATEID_ARFR6_AC_4SS; 957 } 958 break; 959 default: 960 break; 961 } 962 963 return rate_id; 964 } 965 966 #define RA_MASK_CCK_RATES 0x0000f 967 #define RA_MASK_OFDM_RATES 0x00ff0 968 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 969 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 970 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 971 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 972 RA_MASK_HT_RATES_2SS | \ 973 RA_MASK_HT_RATES_3SS) 974 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 975 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 976 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 977 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 978 RA_MASK_VHT_RATES_2SS | \ 979 RA_MASK_VHT_RATES_3SS) 980 #define RA_MASK_CCK_IN_HT 0x00005 981 #define RA_MASK_CCK_IN_VHT 0x00005 982 #define RA_MASK_OFDM_IN_VHT 0x00010 983 #define RA_MASK_OFDM_IN_HT_2G 0x00010 984 #define RA_MASK_OFDM_IN_HT_5G 0x00030 985 986 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, 987 struct rtw_sta_info *si, 988 u64 ra_mask, bool is_vht_enable, 989 u8 wireless_set) 990 { 991 struct rtw_hal *hal = &rtwdev->hal; 992 const struct cfg80211_bitrate_mask *mask = si->mask; 993 u64 cfg_mask = GENMASK_ULL(63, 0); 994 u8 rssi_level, band; 995 996 if (wireless_set != WIRELESS_CCK) { 997 rssi_level = si->rssi_level; 998 if (rssi_level == 0) 999 ra_mask &= 0xffffffffffffffffULL; 1000 else if (rssi_level == 1) 1001 ra_mask &= 0xfffffffffffffff0ULL; 1002 else if (rssi_level == 2) 1003 ra_mask &= 0xffffffffffffefe0ULL; 1004 else if (rssi_level == 3) 1005 ra_mask &= 0xffffffffffffcfc0ULL; 1006 else if (rssi_level == 4) 1007 ra_mask &= 0xffffffffffff8f80ULL; 1008 else if (rssi_level >= 5) 1009 ra_mask &= 0xffffffffffff0f00ULL; 1010 } 1011 1012 if (!si->use_cfg_mask) 1013 return ra_mask; 1014 1015 band = hal->current_band_type; 1016 if (band == RTW_BAND_2G) { 1017 band = NL80211_BAND_2GHZ; 1018 cfg_mask = mask->control[band].legacy; 1019 } else if (band == RTW_BAND_5G) { 1020 band = NL80211_BAND_5GHZ; 1021 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1022 RA_MASK_OFDM_RATES); 1023 } 1024 1025 if (!is_vht_enable) { 1026 if (ra_mask & RA_MASK_HT_RATES_1SS) 1027 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1028 RA_MASK_HT_RATES_1SS); 1029 if (ra_mask & RA_MASK_HT_RATES_2SS) 1030 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1031 RA_MASK_HT_RATES_2SS); 1032 } else { 1033 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1034 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1035 RA_MASK_VHT_RATES_1SS); 1036 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1037 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1038 RA_MASK_VHT_RATES_2SS); 1039 } 1040 1041 ra_mask &= cfg_mask; 1042 1043 return ra_mask; 1044 } 1045 1046 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 1047 { 1048 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1049 struct ieee80211_sta *sta = si->sta; 1050 struct rtw_efuse *efuse = &rtwdev->efuse; 1051 struct rtw_hal *hal = &rtwdev->hal; 1052 u8 wireless_set; 1053 u8 bw_mode; 1054 u8 rate_id; 1055 u8 rf_type = RF_1T1R; 1056 u8 stbc_en = 0; 1057 u8 ldpc_en = 0; 1058 u8 tx_num = 1; 1059 u64 ra_mask = 0; 1060 bool is_vht_enable = false; 1061 bool is_support_sgi = false; 1062 1063 if (sta->vht_cap.vht_supported) { 1064 is_vht_enable = true; 1065 ra_mask |= get_vht_ra_mask(sta); 1066 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1067 stbc_en = VHT_STBC_EN; 1068 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1069 ldpc_en = VHT_LDPC_EN; 1070 } else if (sta->ht_cap.ht_supported) { 1071 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 1072 (sta->ht_cap.mcs.rx_mask[0] << 12); 1073 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1074 stbc_en = HT_STBC_EN; 1075 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1076 ldpc_en = HT_LDPC_EN; 1077 } 1078 1079 if (efuse->hw_cap.nss == 1) 1080 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1081 1082 if (hal->current_band_type == RTW_BAND_5G) { 1083 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 1084 if (sta->vht_cap.vht_supported) { 1085 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1086 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1087 } else if (sta->ht_cap.ht_supported) { 1088 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1089 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1090 } else { 1091 wireless_set = WIRELESS_OFDM; 1092 } 1093 dm_info->rrsr_val_init = RRSR_INIT_5G; 1094 } else if (hal->current_band_type == RTW_BAND_2G) { 1095 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 1096 if (sta->vht_cap.vht_supported) { 1097 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1098 RA_MASK_OFDM_IN_VHT; 1099 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1100 WIRELESS_HT | WIRELESS_VHT; 1101 } else if (sta->ht_cap.ht_supported) { 1102 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1103 RA_MASK_OFDM_IN_HT_2G; 1104 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1105 WIRELESS_HT; 1106 } else if (sta->supp_rates[0] <= 0xf) { 1107 wireless_set = WIRELESS_CCK; 1108 } else { 1109 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1110 } 1111 dm_info->rrsr_val_init = RRSR_INIT_2G; 1112 } else { 1113 rtw_err(rtwdev, "Unknown band type\n"); 1114 wireless_set = 0; 1115 } 1116 1117 switch (sta->bandwidth) { 1118 case IEEE80211_STA_RX_BW_80: 1119 bw_mode = RTW_CHANNEL_WIDTH_80; 1120 is_support_sgi = sta->vht_cap.vht_supported && 1121 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1122 break; 1123 case IEEE80211_STA_RX_BW_40: 1124 bw_mode = RTW_CHANNEL_WIDTH_40; 1125 is_support_sgi = sta->ht_cap.ht_supported && 1126 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1127 break; 1128 default: 1129 bw_mode = RTW_CHANNEL_WIDTH_20; 1130 is_support_sgi = sta->ht_cap.ht_supported && 1131 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1132 break; 1133 } 1134 1135 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 1136 tx_num = 2; 1137 rf_type = RF_2T2R; 1138 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 1139 tx_num = 2; 1140 rf_type = RF_2T2R; 1141 } 1142 1143 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1144 1145 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, 1146 wireless_set); 1147 1148 si->bw_mode = bw_mode; 1149 si->stbc_en = stbc_en; 1150 si->ldpc_en = ldpc_en; 1151 si->rf_type = rf_type; 1152 si->wireless_set = wireless_set; 1153 si->sgi_enable = is_support_sgi; 1154 si->vht_enable = is_vht_enable; 1155 si->ra_mask = ra_mask; 1156 si->rate_id = rate_id; 1157 1158 rtw_fw_send_ra_info(rtwdev, si); 1159 } 1160 1161 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1162 { 1163 struct rtw_chip_info *chip = rtwdev->chip; 1164 struct rtw_fw_state *fw; 1165 1166 fw = &rtwdev->fw; 1167 wait_for_completion(&fw->completion); 1168 if (!fw->firmware) 1169 return -EINVAL; 1170 1171 if (chip->wow_fw_name) { 1172 fw = &rtwdev->wow_fw; 1173 wait_for_completion(&fw->completion); 1174 if (!fw->firmware) 1175 return -EINVAL; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1182 struct rtw_fw_state *fw) 1183 { 1184 struct rtw_chip_info *chip = rtwdev->chip; 1185 1186 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1187 !fw->feature) 1188 return LPS_DEEP_MODE_NONE; 1189 1190 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1191 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1192 return LPS_DEEP_MODE_PG; 1193 1194 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1195 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1196 return LPS_DEEP_MODE_LCLK; 1197 1198 return LPS_DEEP_MODE_NONE; 1199 } 1200 1201 static int rtw_power_on(struct rtw_dev *rtwdev) 1202 { 1203 struct rtw_chip_info *chip = rtwdev->chip; 1204 struct rtw_fw_state *fw = &rtwdev->fw; 1205 bool wifi_only; 1206 int ret; 1207 1208 ret = rtw_hci_setup(rtwdev); 1209 if (ret) { 1210 rtw_err(rtwdev, "failed to setup hci\n"); 1211 goto err; 1212 } 1213 1214 /* power on MAC before firmware downloaded */ 1215 ret = rtw_mac_power_on(rtwdev); 1216 if (ret) { 1217 rtw_err(rtwdev, "failed to power on mac\n"); 1218 goto err; 1219 } 1220 1221 ret = rtw_wait_firmware_completion(rtwdev); 1222 if (ret) { 1223 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1224 goto err_off; 1225 } 1226 1227 ret = rtw_download_firmware(rtwdev, fw); 1228 if (ret) { 1229 rtw_err(rtwdev, "failed to download firmware\n"); 1230 goto err_off; 1231 } 1232 1233 /* config mac after firmware downloaded */ 1234 ret = rtw_mac_init(rtwdev); 1235 if (ret) { 1236 rtw_err(rtwdev, "failed to configure mac\n"); 1237 goto err_off; 1238 } 1239 1240 chip->ops->phy_set_param(rtwdev); 1241 1242 ret = rtw_hci_start(rtwdev); 1243 if (ret) { 1244 rtw_err(rtwdev, "failed to start hci\n"); 1245 goto err_off; 1246 } 1247 1248 /* send H2C after HCI has started */ 1249 rtw_fw_send_general_info(rtwdev); 1250 rtw_fw_send_phydm_info(rtwdev); 1251 1252 wifi_only = !rtwdev->efuse.btcoex; 1253 rtw_coex_power_on_setting(rtwdev); 1254 rtw_coex_init_hw_config(rtwdev, wifi_only); 1255 1256 return 0; 1257 1258 err_off: 1259 rtw_mac_power_off(rtwdev); 1260 1261 err: 1262 return ret; 1263 } 1264 1265 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1266 { 1267 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1268 return; 1269 1270 if (start) { 1271 rtw_fw_scan_notify(rtwdev, true); 1272 } else { 1273 reinit_completion(&rtwdev->fw_scan_density); 1274 rtw_fw_scan_notify(rtwdev, false); 1275 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1276 SCAN_NOTIFY_TIMEOUT)) 1277 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1278 } 1279 } 1280 1281 int rtw_core_start(struct rtw_dev *rtwdev) 1282 { 1283 int ret; 1284 1285 ret = rtw_power_on(rtwdev); 1286 if (ret) 1287 return ret; 1288 1289 rtw_sec_enable_sec_engine(rtwdev); 1290 1291 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1292 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1293 1294 /* rcr reset after powered on */ 1295 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1296 1297 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1298 RTW_WATCH_DOG_DELAY_TIME); 1299 1300 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1301 1302 return 0; 1303 } 1304 1305 static void rtw_power_off(struct rtw_dev *rtwdev) 1306 { 1307 rtw_hci_stop(rtwdev); 1308 rtw_coex_power_off_setting(rtwdev); 1309 rtw_mac_power_off(rtwdev); 1310 } 1311 1312 void rtw_core_stop(struct rtw_dev *rtwdev) 1313 { 1314 struct rtw_coex *coex = &rtwdev->coex; 1315 1316 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1317 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1318 1319 mutex_unlock(&rtwdev->mutex); 1320 1321 cancel_work_sync(&rtwdev->c2h_work); 1322 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1323 cancel_delayed_work_sync(&coex->bt_relink_work); 1324 cancel_delayed_work_sync(&coex->bt_reenable_work); 1325 cancel_delayed_work_sync(&coex->defreeze_work); 1326 cancel_delayed_work_sync(&coex->wl_remain_work); 1327 cancel_delayed_work_sync(&coex->bt_remain_work); 1328 cancel_delayed_work_sync(&coex->wl_connecting_work); 1329 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1330 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1331 1332 mutex_lock(&rtwdev->mutex); 1333 1334 rtw_power_off(rtwdev); 1335 } 1336 1337 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1338 struct ieee80211_sta_ht_cap *ht_cap) 1339 { 1340 struct rtw_efuse *efuse = &rtwdev->efuse; 1341 1342 ht_cap->ht_supported = true; 1343 ht_cap->cap = 0; 1344 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1345 IEEE80211_HT_CAP_MAX_AMSDU | 1346 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1347 1348 if (rtw_chip_has_rx_ldpc(rtwdev)) 1349 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1350 if (rtw_chip_has_tx_stbc(rtwdev)) 1351 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1352 1353 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1354 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1355 IEEE80211_HT_CAP_DSSSCCK40 | 1356 IEEE80211_HT_CAP_SGI_40; 1357 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1358 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 1359 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1360 if (efuse->hw_cap.nss > 1) { 1361 ht_cap->mcs.rx_mask[0] = 0xFF; 1362 ht_cap->mcs.rx_mask[1] = 0xFF; 1363 ht_cap->mcs.rx_mask[4] = 0x01; 1364 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1365 } else { 1366 ht_cap->mcs.rx_mask[0] = 0xFF; 1367 ht_cap->mcs.rx_mask[1] = 0x00; 1368 ht_cap->mcs.rx_mask[4] = 0x01; 1369 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1370 } 1371 } 1372 1373 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1374 struct ieee80211_sta_vht_cap *vht_cap) 1375 { 1376 struct rtw_efuse *efuse = &rtwdev->efuse; 1377 u16 mcs_map; 1378 __le16 highest; 1379 1380 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1381 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1382 return; 1383 1384 vht_cap->vht_supported = true; 1385 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1386 IEEE80211_VHT_CAP_SHORT_GI_80 | 1387 IEEE80211_VHT_CAP_RXSTBC_1 | 1388 IEEE80211_VHT_CAP_HTC_VHT | 1389 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1390 0; 1391 if (rtwdev->hal.rf_path_num > 1) 1392 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1393 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1394 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1395 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1396 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1397 1398 if (rtw_chip_has_rx_ldpc(rtwdev)) 1399 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1400 1401 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1402 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1403 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1404 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1405 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1406 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1407 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1408 if (efuse->hw_cap.nss > 1) { 1409 highest = cpu_to_le16(780); 1410 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1411 } else { 1412 highest = cpu_to_le16(390); 1413 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1414 } 1415 1416 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1417 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1418 vht_cap->vht_mcs.rx_highest = highest; 1419 vht_cap->vht_mcs.tx_highest = highest; 1420 } 1421 1422 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1423 struct rtw_chip_info *chip) 1424 { 1425 struct rtw_dev *rtwdev = hw->priv; 1426 struct ieee80211_supported_band *sband; 1427 1428 if (chip->band & RTW_BAND_2G) { 1429 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1430 if (!sband) 1431 goto err_out; 1432 if (chip->ht_supported) 1433 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1434 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1435 } 1436 1437 if (chip->band & RTW_BAND_5G) { 1438 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1439 if (!sband) 1440 goto err_out; 1441 if (chip->ht_supported) 1442 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1443 if (chip->vht_supported) 1444 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1445 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1446 } 1447 1448 return; 1449 1450 err_out: 1451 rtw_err(rtwdev, "failed to set supported band\n"); 1452 } 1453 1454 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1455 struct rtw_chip_info *chip) 1456 { 1457 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1458 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1459 } 1460 1461 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1462 struct rtw_fw_state *fw) 1463 { 1464 u32 feature; 1465 const struct rtw_fw_hdr *fw_hdr = 1466 (const struct rtw_fw_hdr *)fw->firmware->data; 1467 1468 feature = le32_to_cpu(fw_hdr->feature); 1469 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1470 } 1471 1472 static void __update_firmware_info(struct rtw_dev *rtwdev, 1473 struct rtw_fw_state *fw) 1474 { 1475 const struct rtw_fw_hdr *fw_hdr = 1476 (const struct rtw_fw_hdr *)fw->firmware->data; 1477 1478 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1479 fw->version = le16_to_cpu(fw_hdr->version); 1480 fw->sub_version = fw_hdr->subversion; 1481 fw->sub_index = fw_hdr->subindex; 1482 1483 __update_firmware_feature(rtwdev, fw); 1484 } 1485 1486 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1487 struct rtw_fw_state *fw) 1488 { 1489 struct rtw_fw_hdr_legacy *legacy = 1490 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1491 1492 fw->h2c_version = 0; 1493 fw->version = le16_to_cpu(legacy->version); 1494 fw->sub_version = legacy->subversion1; 1495 fw->sub_index = legacy->subversion2; 1496 } 1497 1498 static void update_firmware_info(struct rtw_dev *rtwdev, 1499 struct rtw_fw_state *fw) 1500 { 1501 if (rtw_chip_wcpu_11n(rtwdev)) 1502 __update_firmware_info_legacy(rtwdev, fw); 1503 else 1504 __update_firmware_info(rtwdev, fw); 1505 } 1506 1507 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1508 { 1509 struct rtw_fw_state *fw = context; 1510 struct rtw_dev *rtwdev = fw->rtwdev; 1511 1512 if (!firmware || !firmware->data) { 1513 rtw_err(rtwdev, "failed to request firmware\n"); 1514 complete_all(&fw->completion); 1515 return; 1516 } 1517 1518 fw->firmware = firmware; 1519 update_firmware_info(rtwdev, fw); 1520 complete_all(&fw->completion); 1521 1522 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1523 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1524 } 1525 1526 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1527 { 1528 const char *fw_name; 1529 struct rtw_fw_state *fw; 1530 int ret; 1531 1532 switch (type) { 1533 case RTW_WOWLAN_FW: 1534 fw = &rtwdev->wow_fw; 1535 fw_name = rtwdev->chip->wow_fw_name; 1536 break; 1537 1538 case RTW_NORMAL_FW: 1539 fw = &rtwdev->fw; 1540 fw_name = rtwdev->chip->fw_name; 1541 break; 1542 1543 default: 1544 rtw_warn(rtwdev, "unsupported firmware type\n"); 1545 return -ENOENT; 1546 } 1547 1548 fw->rtwdev = rtwdev; 1549 init_completion(&fw->completion); 1550 1551 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1552 GFP_KERNEL, fw, rtw_load_firmware_cb); 1553 if (ret) { 1554 rtw_err(rtwdev, "failed to async firmware request\n"); 1555 return ret; 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1562 { 1563 struct rtw_chip_info *chip = rtwdev->chip; 1564 struct rtw_hal *hal = &rtwdev->hal; 1565 struct rtw_efuse *efuse = &rtwdev->efuse; 1566 1567 switch (rtw_hci_type(rtwdev)) { 1568 case RTW_HCI_TYPE_PCIE: 1569 rtwdev->hci.rpwm_addr = 0x03d9; 1570 rtwdev->hci.cpwm_addr = 0x03da; 1571 break; 1572 default: 1573 rtw_err(rtwdev, "unsupported hci type\n"); 1574 return -EINVAL; 1575 } 1576 1577 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1578 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1579 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1580 if (hal->chip_version & BIT_RF_TYPE_ID) { 1581 hal->rf_type = RF_2T2R; 1582 hal->rf_path_num = 2; 1583 hal->antenna_tx = BB_PATH_AB; 1584 hal->antenna_rx = BB_PATH_AB; 1585 } else { 1586 hal->rf_type = RF_1T1R; 1587 hal->rf_path_num = 1; 1588 hal->antenna_tx = BB_PATH_A; 1589 hal->antenna_rx = BB_PATH_A; 1590 } 1591 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1592 hal->rf_path_num; 1593 1594 efuse->physical_size = chip->phy_efuse_size; 1595 efuse->logical_size = chip->log_efuse_size; 1596 efuse->protect_size = chip->ptct_efuse_size; 1597 1598 /* default use ack */ 1599 rtwdev->hal.rcr |= BIT_VHT_DACK; 1600 1601 hal->bfee_sts_cap = 3; 1602 1603 return 0; 1604 } 1605 1606 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1607 { 1608 struct rtw_fw_state *fw = &rtwdev->fw; 1609 int ret; 1610 1611 ret = rtw_hci_setup(rtwdev); 1612 if (ret) { 1613 rtw_err(rtwdev, "failed to setup hci\n"); 1614 goto err; 1615 } 1616 1617 ret = rtw_mac_power_on(rtwdev); 1618 if (ret) { 1619 rtw_err(rtwdev, "failed to power on mac\n"); 1620 goto err; 1621 } 1622 1623 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1624 1625 wait_for_completion(&fw->completion); 1626 if (!fw->firmware) { 1627 ret = -EINVAL; 1628 rtw_err(rtwdev, "failed to load firmware\n"); 1629 goto err; 1630 } 1631 1632 ret = rtw_download_firmware(rtwdev, fw); 1633 if (ret) { 1634 rtw_err(rtwdev, "failed to download firmware\n"); 1635 goto err_off; 1636 } 1637 1638 return 0; 1639 1640 err_off: 1641 rtw_mac_power_off(rtwdev); 1642 1643 err: 1644 return ret; 1645 } 1646 1647 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1648 { 1649 struct rtw_efuse *efuse = &rtwdev->efuse; 1650 u8 hw_feature[HW_FEATURE_LEN]; 1651 u8 id; 1652 u8 bw; 1653 int i; 1654 1655 id = rtw_read8(rtwdev, REG_C2HEVT); 1656 if (id != C2H_HW_FEATURE_REPORT) { 1657 rtw_err(rtwdev, "failed to read hw feature report\n"); 1658 return -EBUSY; 1659 } 1660 1661 for (i = 0; i < HW_FEATURE_LEN; i++) 1662 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1663 1664 rtw_write8(rtwdev, REG_C2HEVT, 0); 1665 1666 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1667 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1668 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1669 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1670 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1671 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1672 1673 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1674 1675 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1676 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1677 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1678 1679 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1680 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1681 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1682 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1683 1684 return 0; 1685 } 1686 1687 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1688 { 1689 rtw_hci_stop(rtwdev); 1690 rtw_mac_power_off(rtwdev); 1691 } 1692 1693 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1694 { 1695 struct rtw_efuse *efuse = &rtwdev->efuse; 1696 int ret; 1697 1698 mutex_lock(&rtwdev->mutex); 1699 1700 /* power on mac to read efuse */ 1701 ret = rtw_chip_efuse_enable(rtwdev); 1702 if (ret) 1703 goto out_unlock; 1704 1705 ret = rtw_parse_efuse_map(rtwdev); 1706 if (ret) 1707 goto out_disable; 1708 1709 ret = rtw_dump_hw_feature(rtwdev); 1710 if (ret) 1711 goto out_disable; 1712 1713 ret = rtw_check_supported_rfe(rtwdev); 1714 if (ret) 1715 goto out_disable; 1716 1717 if (efuse->crystal_cap == 0xff) 1718 efuse->crystal_cap = 0; 1719 if (efuse->pa_type_2g == 0xff) 1720 efuse->pa_type_2g = 0; 1721 if (efuse->pa_type_5g == 0xff) 1722 efuse->pa_type_5g = 0; 1723 if (efuse->lna_type_2g == 0xff) 1724 efuse->lna_type_2g = 0; 1725 if (efuse->lna_type_5g == 0xff) 1726 efuse->lna_type_5g = 0; 1727 if (efuse->channel_plan == 0xff) 1728 efuse->channel_plan = 0x7f; 1729 if (efuse->rf_board_option == 0xff) 1730 efuse->rf_board_option = 0; 1731 if (efuse->bt_setting & BIT(0)) 1732 efuse->share_ant = true; 1733 if (efuse->regd == 0xff) 1734 efuse->regd = 0; 1735 if (efuse->tx_bb_swing_setting_2g == 0xff) 1736 efuse->tx_bb_swing_setting_2g = 0; 1737 if (efuse->tx_bb_swing_setting_5g == 0xff) 1738 efuse->tx_bb_swing_setting_5g = 0; 1739 1740 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1741 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1742 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1743 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1744 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1745 1746 out_disable: 1747 rtw_chip_efuse_disable(rtwdev); 1748 1749 out_unlock: 1750 mutex_unlock(&rtwdev->mutex); 1751 return ret; 1752 } 1753 1754 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1755 { 1756 struct rtw_hal *hal = &rtwdev->hal; 1757 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1758 1759 if (!rfe_def) 1760 return -ENODEV; 1761 1762 rtw_phy_setup_phy_cond(rtwdev, 0); 1763 1764 rtw_phy_init_tx_power(rtwdev); 1765 if (rfe_def->agc_btg_tbl) 1766 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1767 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1768 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1769 rtw_phy_tx_power_by_rate_config(hal); 1770 rtw_phy_tx_power_limit_config(hal); 1771 1772 return 0; 1773 } 1774 1775 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1776 { 1777 int ret; 1778 1779 ret = rtw_chip_parameter_setup(rtwdev); 1780 if (ret) { 1781 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1782 goto err_out; 1783 } 1784 1785 ret = rtw_chip_efuse_info_setup(rtwdev); 1786 if (ret) { 1787 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1788 goto err_out; 1789 } 1790 1791 ret = rtw_chip_board_info_setup(rtwdev); 1792 if (ret) { 1793 rtw_err(rtwdev, "failed to setup chip board info\n"); 1794 goto err_out; 1795 } 1796 1797 return 0; 1798 1799 err_out: 1800 return ret; 1801 } 1802 EXPORT_SYMBOL(rtw_chip_info_setup); 1803 1804 static void rtw_stats_init(struct rtw_dev *rtwdev) 1805 { 1806 struct rtw_traffic_stats *stats = &rtwdev->stats; 1807 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1808 int i; 1809 1810 ewma_tp_init(&stats->tx_ewma_tp); 1811 ewma_tp_init(&stats->rx_ewma_tp); 1812 1813 for (i = 0; i < RTW_EVM_NUM; i++) 1814 ewma_evm_init(&dm_info->ewma_evm[i]); 1815 for (i = 0; i < RTW_SNR_NUM; i++) 1816 ewma_snr_init(&dm_info->ewma_snr[i]); 1817 } 1818 1819 int rtw_core_init(struct rtw_dev *rtwdev) 1820 { 1821 struct rtw_chip_info *chip = rtwdev->chip; 1822 struct rtw_coex *coex = &rtwdev->coex; 1823 int ret; 1824 1825 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1826 INIT_LIST_HEAD(&rtwdev->txqs); 1827 1828 timer_setup(&rtwdev->tx_report.purge_timer, 1829 rtw_tx_report_purge_timer, 0); 1830 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1831 1832 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1833 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1834 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1835 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1836 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1837 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1838 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1839 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1840 rtw_coex_bt_multi_link_remain_work); 1841 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 1842 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 1843 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1844 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 1845 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1846 skb_queue_head_init(&rtwdev->c2h_queue); 1847 skb_queue_head_init(&rtwdev->coex.queue); 1848 skb_queue_head_init(&rtwdev->tx_report.queue); 1849 1850 spin_lock_init(&rtwdev->rf_lock); 1851 spin_lock_init(&rtwdev->h2c.lock); 1852 spin_lock_init(&rtwdev->txq_lock); 1853 spin_lock_init(&rtwdev->tx_report.q_lock); 1854 1855 mutex_init(&rtwdev->mutex); 1856 mutex_init(&rtwdev->coex.mutex); 1857 mutex_init(&rtwdev->hal.tx_power_mutex); 1858 1859 init_waitqueue_head(&rtwdev->coex.wait); 1860 init_completion(&rtwdev->lps_leave_check); 1861 init_completion(&rtwdev->fw_scan_density); 1862 1863 rtwdev->sec.total_cam_num = 32; 1864 rtwdev->hal.current_channel = 1; 1865 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1866 1867 rtw_stats_init(rtwdev); 1868 1869 /* default rx filter setting */ 1870 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1871 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1872 BIT_AB | BIT_AM | BIT_APM; 1873 1874 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 1875 if (ret) { 1876 rtw_warn(rtwdev, "no firmware loaded\n"); 1877 return ret; 1878 } 1879 1880 if (chip->wow_fw_name) { 1881 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 1882 if (ret) { 1883 rtw_warn(rtwdev, "no wow firmware loaded\n"); 1884 wait_for_completion(&rtwdev->fw.completion); 1885 if (rtwdev->fw.firmware) 1886 release_firmware(rtwdev->fw.firmware); 1887 return ret; 1888 } 1889 } 1890 1891 return 0; 1892 } 1893 EXPORT_SYMBOL(rtw_core_init); 1894 1895 void rtw_core_deinit(struct rtw_dev *rtwdev) 1896 { 1897 struct rtw_fw_state *fw = &rtwdev->fw; 1898 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 1899 struct rtw_rsvd_page *rsvd_pkt, *tmp; 1900 unsigned long flags; 1901 1902 rtw_wait_firmware_completion(rtwdev); 1903 1904 if (fw->firmware) 1905 release_firmware(fw->firmware); 1906 1907 if (wow_fw->firmware) 1908 release_firmware(wow_fw->firmware); 1909 1910 destroy_workqueue(rtwdev->tx_wq); 1911 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 1912 skb_queue_purge(&rtwdev->tx_report.queue); 1913 skb_queue_purge(&rtwdev->coex.queue); 1914 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 1915 1916 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 1917 build_list) { 1918 list_del(&rsvd_pkt->build_list); 1919 kfree(rsvd_pkt); 1920 } 1921 1922 mutex_destroy(&rtwdev->mutex); 1923 mutex_destroy(&rtwdev->coex.mutex); 1924 mutex_destroy(&rtwdev->hal.tx_power_mutex); 1925 } 1926 EXPORT_SYMBOL(rtw_core_deinit); 1927 1928 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1929 { 1930 struct rtw_hal *hal = &rtwdev->hal; 1931 int max_tx_headroom = 0; 1932 int ret; 1933 1934 /* TODO: USB & SDIO may need extra room? */ 1935 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 1936 1937 hw->extra_tx_headroom = max_tx_headroom; 1938 hw->queues = IEEE80211_NUM_ACS; 1939 hw->txq_data_size = sizeof(struct rtw_txq); 1940 hw->sta_data_size = sizeof(struct rtw_sta_info); 1941 hw->vif_data_size = sizeof(struct rtw_vif); 1942 1943 ieee80211_hw_set(hw, SIGNAL_DBM); 1944 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 1945 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 1946 ieee80211_hw_set(hw, MFP_CAPABLE); 1947 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 1948 ieee80211_hw_set(hw, SUPPORTS_PS); 1949 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 1950 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 1951 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 1952 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 1953 ieee80211_hw_set(hw, TX_AMSDU); 1954 1955 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1956 BIT(NL80211_IFTYPE_AP) | 1957 BIT(NL80211_IFTYPE_ADHOC) | 1958 BIT(NL80211_IFTYPE_MESH_POINT); 1959 hw->wiphy->available_antennas_tx = hal->antenna_tx; 1960 hw->wiphy->available_antennas_rx = hal->antenna_rx; 1961 1962 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 1963 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 1964 1965 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 1966 1967 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 1968 1969 #ifdef CONFIG_PM 1970 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 1971 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 1972 #endif 1973 rtw_set_supported_band(hw, rtwdev->chip); 1974 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 1975 1976 ret = rtw_regd_init(rtwdev); 1977 if (ret) { 1978 rtw_err(rtwdev, "failed to init regd\n"); 1979 return ret; 1980 } 1981 1982 ret = ieee80211_register_hw(hw); 1983 if (ret) { 1984 rtw_err(rtwdev, "failed to register hw\n"); 1985 return ret; 1986 } 1987 1988 ret = rtw_regd_hint(rtwdev); 1989 if (ret) { 1990 rtw_err(rtwdev, "failed to hint regd\n"); 1991 return ret; 1992 } 1993 1994 rtw_debugfs_init(rtwdev); 1995 1996 rtwdev->bf_info.bfer_mu_cnt = 0; 1997 rtwdev->bf_info.bfer_su_cnt = 0; 1998 1999 return 0; 2000 } 2001 EXPORT_SYMBOL(rtw_register_hw); 2002 2003 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2004 { 2005 struct rtw_chip_info *chip = rtwdev->chip; 2006 2007 ieee80211_unregister_hw(hw); 2008 rtw_unset_supported_band(hw, chip); 2009 } 2010 EXPORT_SYMBOL(rtw_unregister_hw); 2011 2012 MODULE_AUTHOR("Realtek Corporation"); 2013 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2014 MODULE_LICENSE("Dual BSD/GPL"); 2015