1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 #include "sdio.h" 22 23 bool rtw_disable_lps_deep_mode; 24 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 25 bool rtw_bf_support = true; 26 unsigned int rtw_debug_mask; 27 EXPORT_SYMBOL(rtw_debug_mask); 28 /* EDCCA is enabled during normal behavior. For debugging purpose in 29 * a noisy environment, it can be disabled via edcca debugfs. Because 30 * all rtw88 devices will probably be affected if environment is noisy, 31 * rtw_edcca_enabled is just declared by driver instead of by device. 32 * So, turning it off will take effect for all rtw88 devices before 33 * there is a tough reason to maintain rtw_edcca_enabled by device. 34 */ 35 bool rtw_edcca_enabled = true; 36 37 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 38 module_param_named(support_bf, rtw_bf_support, bool, 0644); 39 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 40 41 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 42 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 43 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 44 45 static struct ieee80211_channel rtw_channeltable_2g[] = { 46 {.center_freq = 2412, .hw_value = 1,}, 47 {.center_freq = 2417, .hw_value = 2,}, 48 {.center_freq = 2422, .hw_value = 3,}, 49 {.center_freq = 2427, .hw_value = 4,}, 50 {.center_freq = 2432, .hw_value = 5,}, 51 {.center_freq = 2437, .hw_value = 6,}, 52 {.center_freq = 2442, .hw_value = 7,}, 53 {.center_freq = 2447, .hw_value = 8,}, 54 {.center_freq = 2452, .hw_value = 9,}, 55 {.center_freq = 2457, .hw_value = 10,}, 56 {.center_freq = 2462, .hw_value = 11,}, 57 {.center_freq = 2467, .hw_value = 12,}, 58 {.center_freq = 2472, .hw_value = 13,}, 59 {.center_freq = 2484, .hw_value = 14,}, 60 }; 61 62 static struct ieee80211_channel rtw_channeltable_5g[] = { 63 {.center_freq = 5180, .hw_value = 36,}, 64 {.center_freq = 5200, .hw_value = 40,}, 65 {.center_freq = 5220, .hw_value = 44,}, 66 {.center_freq = 5240, .hw_value = 48,}, 67 {.center_freq = 5260, .hw_value = 52,}, 68 {.center_freq = 5280, .hw_value = 56,}, 69 {.center_freq = 5300, .hw_value = 60,}, 70 {.center_freq = 5320, .hw_value = 64,}, 71 {.center_freq = 5500, .hw_value = 100,}, 72 {.center_freq = 5520, .hw_value = 104,}, 73 {.center_freq = 5540, .hw_value = 108,}, 74 {.center_freq = 5560, .hw_value = 112,}, 75 {.center_freq = 5580, .hw_value = 116,}, 76 {.center_freq = 5600, .hw_value = 120,}, 77 {.center_freq = 5620, .hw_value = 124,}, 78 {.center_freq = 5640, .hw_value = 128,}, 79 {.center_freq = 5660, .hw_value = 132,}, 80 {.center_freq = 5680, .hw_value = 136,}, 81 {.center_freq = 5700, .hw_value = 140,}, 82 {.center_freq = 5720, .hw_value = 144,}, 83 {.center_freq = 5745, .hw_value = 149,}, 84 {.center_freq = 5765, .hw_value = 153,}, 85 {.center_freq = 5785, .hw_value = 157,}, 86 {.center_freq = 5805, .hw_value = 161,}, 87 {.center_freq = 5825, .hw_value = 165, 88 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 89 }; 90 91 static struct ieee80211_rate rtw_ratetable[] = { 92 {.bitrate = 10, .hw_value = 0x00,}, 93 {.bitrate = 20, .hw_value = 0x01,}, 94 {.bitrate = 55, .hw_value = 0x02,}, 95 {.bitrate = 110, .hw_value = 0x03,}, 96 {.bitrate = 60, .hw_value = 0x04,}, 97 {.bitrate = 90, .hw_value = 0x05,}, 98 {.bitrate = 120, .hw_value = 0x06,}, 99 {.bitrate = 180, .hw_value = 0x07,}, 100 {.bitrate = 240, .hw_value = 0x08,}, 101 {.bitrate = 360, .hw_value = 0x09,}, 102 {.bitrate = 480, .hw_value = 0x0a,}, 103 {.bitrate = 540, .hw_value = 0x0b,}, 104 }; 105 106 static const struct ieee80211_iface_limit rtw_iface_limits[] = { 107 { 108 .max = 1, 109 .types = BIT(NL80211_IFTYPE_STATION), 110 }, 111 { 112 .max = 1, 113 .types = BIT(NL80211_IFTYPE_AP), 114 } 115 }; 116 117 static const struct ieee80211_iface_combination rtw_iface_combs[] = { 118 { 119 .limits = rtw_iface_limits, 120 .n_limits = ARRAY_SIZE(rtw_iface_limits), 121 .max_interfaces = 2, 122 .num_different_channels = 1, 123 } 124 }; 125 126 u16 rtw_desc_to_bitrate(u8 desc_rate) 127 { 128 struct ieee80211_rate rate; 129 130 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 131 return 0; 132 133 rate = rtw_ratetable[desc_rate]; 134 135 return rate.bitrate; 136 } 137 138 static struct ieee80211_supported_band rtw_band_2ghz = { 139 .band = NL80211_BAND_2GHZ, 140 141 .channels = rtw_channeltable_2g, 142 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 143 144 .bitrates = rtw_ratetable, 145 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 146 147 .ht_cap = {0}, 148 .vht_cap = {0}, 149 }; 150 151 static struct ieee80211_supported_band rtw_band_5ghz = { 152 .band = NL80211_BAND_5GHZ, 153 154 .channels = rtw_channeltable_5g, 155 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 156 157 /* 5G has no CCK rates */ 158 .bitrates = rtw_ratetable + 4, 159 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 160 161 .ht_cap = {0}, 162 .vht_cap = {0}, 163 }; 164 165 struct rtw_watch_dog_iter_data { 166 struct rtw_dev *rtwdev; 167 struct rtw_vif *rtwvif; 168 }; 169 170 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 171 { 172 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 173 u8 fix_rate_enable = 0; 174 u8 new_csi_rate_idx; 175 176 if (rtwvif->bfee.role != RTW_BFEE_SU && 177 rtwvif->bfee.role != RTW_BFEE_MU) 178 return; 179 180 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 181 bf_info->cur_csi_rpt_rate, 182 fix_rate_enable, &new_csi_rate_idx); 183 184 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 185 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 186 } 187 188 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 189 struct ieee80211_vif *vif) 190 { 191 struct rtw_watch_dog_iter_data *iter_data = data; 192 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 193 194 if (vif->type == NL80211_IFTYPE_STATION) 195 if (vif->cfg.assoc) 196 iter_data->rtwvif = rtwvif; 197 198 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 199 200 rtwvif->stats.tx_unicast = 0; 201 rtwvif->stats.rx_unicast = 0; 202 rtwvif->stats.tx_cnt = 0; 203 rtwvif->stats.rx_cnt = 0; 204 } 205 206 /* process TX/RX statistics periodically for hardware, 207 * the information helps hardware to enhance performance 208 */ 209 static void rtw_watch_dog_work(struct work_struct *work) 210 { 211 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 212 watch_dog_work.work); 213 struct rtw_traffic_stats *stats = &rtwdev->stats; 214 struct rtw_watch_dog_iter_data data = {}; 215 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 216 bool ps_active; 217 218 mutex_lock(&rtwdev->mutex); 219 220 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 221 goto unlock; 222 223 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 224 RTW_WATCH_DOG_DELAY_TIME); 225 226 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 227 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 228 else 229 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 230 231 rtw_coex_wl_status_check(rtwdev); 232 rtw_coex_query_bt_hid_list(rtwdev); 233 234 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 235 rtw_coex_wl_status_change_notify(rtwdev, 0); 236 237 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 238 stats->rx_cnt > RTW_LPS_THRESHOLD) 239 ps_active = true; 240 else 241 ps_active = false; 242 243 ewma_tp_add(&stats->tx_ewma_tp, 244 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 245 ewma_tp_add(&stats->rx_ewma_tp, 246 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 247 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 248 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 249 250 /* reset tx/rx statictics */ 251 stats->tx_unicast = 0; 252 stats->rx_unicast = 0; 253 stats->tx_cnt = 0; 254 stats->rx_cnt = 0; 255 256 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 257 goto unlock; 258 259 /* make sure BB/RF is working for dynamic mech */ 260 rtw_leave_lps(rtwdev); 261 262 rtw_phy_dynamic_mechanism(rtwdev); 263 264 data.rtwdev = rtwdev; 265 /* rtw_iterate_vifs internally uses an atomic iterator which is needed 266 * to avoid taking local->iflist_mtx mutex 267 */ 268 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); 269 270 /* fw supports only one station associated to enter lps, if there are 271 * more than two stations associated to the AP, then we can not enter 272 * lps, because fw does not handle the overlapped beacon interval 273 * 274 * rtw_recalc_lps() iterate vifs and determine if driver can enter 275 * ps by vif->type and vif->cfg.ps, all we need to do here is to 276 * get that vif and check if device is having traffic more than the 277 * threshold. 278 */ 279 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 280 !rtwdev->beacon_loss && !rtwdev->ap_active) 281 rtw_enter_lps(rtwdev, data.rtwvif->port); 282 283 rtwdev->watch_dog_cnt++; 284 285 unlock: 286 mutex_unlock(&rtwdev->mutex); 287 } 288 289 static void rtw_c2h_work(struct work_struct *work) 290 { 291 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 292 struct sk_buff *skb, *tmp; 293 294 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 295 skb_unlink(skb, &rtwdev->c2h_queue); 296 rtw_fw_c2h_cmd_handle(rtwdev, skb); 297 dev_kfree_skb_any(skb); 298 } 299 } 300 301 static void rtw_ips_work(struct work_struct *work) 302 { 303 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 304 305 mutex_lock(&rtwdev->mutex); 306 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 307 rtw_enter_ips(rtwdev); 308 mutex_unlock(&rtwdev->mutex); 309 } 310 311 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 312 { 313 unsigned long mac_id; 314 315 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 316 if (mac_id < RTW_MAX_MAC_ID_NUM) 317 set_bit(mac_id, rtwdev->mac_id_map); 318 319 return mac_id; 320 } 321 322 static void rtw_sta_rc_work(struct work_struct *work) 323 { 324 struct rtw_sta_info *si = container_of(work, struct rtw_sta_info, 325 rc_work); 326 struct rtw_dev *rtwdev = si->rtwdev; 327 328 mutex_lock(&rtwdev->mutex); 329 rtw_update_sta_info(rtwdev, si, true); 330 mutex_unlock(&rtwdev->mutex); 331 } 332 333 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 334 struct ieee80211_vif *vif) 335 { 336 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 337 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 338 int i; 339 340 si->mac_id = rtw_acquire_macid(rtwdev); 341 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 342 return -ENOSPC; 343 344 if (vif->type == NL80211_IFTYPE_STATION && vif->cfg.assoc == 0) 345 rtwvif->mac_id = si->mac_id; 346 si->rtwdev = rtwdev; 347 si->sta = sta; 348 si->vif = vif; 349 si->init_ra_lv = 1; 350 ewma_rssi_init(&si->avg_rssi); 351 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 352 rtw_txq_init(rtwdev, sta->txq[i]); 353 INIT_WORK(&si->rc_work, rtw_sta_rc_work); 354 355 rtw_update_sta_info(rtwdev, si, true); 356 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 357 358 rtwdev->sta_cnt++; 359 rtwdev->beacon_loss = false; 360 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 361 sta->addr, si->mac_id); 362 363 return 0; 364 } 365 366 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 367 bool fw_exist) 368 { 369 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 370 int i; 371 372 cancel_work_sync(&si->rc_work); 373 374 rtw_release_macid(rtwdev, si->mac_id); 375 if (fw_exist) 376 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 377 378 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 379 rtw_txq_cleanup(rtwdev, sta->txq[i]); 380 381 kfree(si->mask); 382 383 rtwdev->sta_cnt--; 384 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 385 sta->addr, si->mac_id); 386 } 387 388 struct rtw_fwcd_hdr { 389 u32 item; 390 u32 size; 391 u32 padding1; 392 u32 padding2; 393 } __packed; 394 395 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 396 { 397 const struct rtw_chip_info *chip = rtwdev->chip; 398 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 399 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 400 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 401 u8 i; 402 403 if (segs) { 404 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 405 406 for (i = 0; i < segs->num; i++) 407 prep_size += segs->segs[i]; 408 } 409 410 desc->data = vmalloc(prep_size); 411 if (!desc->data) 412 return -ENOMEM; 413 414 desc->size = prep_size; 415 desc->next = desc->data; 416 417 return 0; 418 } 419 420 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 421 { 422 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 423 struct rtw_fwcd_hdr *hdr; 424 u8 *next; 425 426 if (!desc->data) { 427 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 428 return NULL; 429 } 430 431 next = desc->next + sizeof(struct rtw_fwcd_hdr); 432 if (next - desc->data + size > desc->size) { 433 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 434 return NULL; 435 } 436 437 hdr = (struct rtw_fwcd_hdr *)(desc->next); 438 hdr->item = item; 439 hdr->size = size; 440 hdr->padding1 = 0x01234567; 441 hdr->padding2 = 0x89abcdef; 442 desc->next = next + size; 443 444 return next; 445 } 446 447 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 448 { 449 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 450 451 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 452 453 /* Data will be freed after lifetime of device coredump. After calling 454 * dev_coredump, data is supposed to be handled by the device coredump 455 * framework. Note that a new dump will be discarded if a previous one 456 * hasn't been released yet. 457 */ 458 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 459 } 460 461 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 462 { 463 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 464 465 if (free_self) { 466 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 467 vfree(desc->data); 468 } 469 470 desc->data = NULL; 471 desc->next = NULL; 472 } 473 474 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 475 { 476 u32 size = rtwdev->chip->fw_rxff_size; 477 u32 *buf; 478 u8 seq; 479 480 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 481 if (!buf) 482 return -ENOMEM; 483 484 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 485 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 486 return -EINVAL; 487 } 488 489 if (GET_FW_DUMP_LEN(buf) == 0) { 490 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 491 return -EINVAL; 492 } 493 494 seq = GET_FW_DUMP_SEQ(buf); 495 if (seq > 0) { 496 rtw_dbg(rtwdev, RTW_DBG_FW, 497 "fw crash dump's seq is wrong: %d\n", seq); 498 return -EINVAL; 499 } 500 501 return 0; 502 } 503 504 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 505 u32 fwcd_item) 506 { 507 u32 rxff = rtwdev->chip->fw_rxff_size; 508 u32 dump_size, done_size = 0; 509 u8 *buf; 510 int ret; 511 512 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 513 if (!buf) 514 return -ENOMEM; 515 516 while (size) { 517 dump_size = size > rxff ? rxff : size; 518 519 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 520 dump_size); 521 if (ret) { 522 rtw_err(rtwdev, 523 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 524 ocp_src, done_size); 525 return ret; 526 } 527 528 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 529 dump_size, (u32 *)(buf + done_size)); 530 if (ret) { 531 rtw_err(rtwdev, 532 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 533 ocp_src, done_size); 534 return ret; 535 } 536 537 size -= dump_size; 538 done_size += dump_size; 539 } 540 541 return 0; 542 } 543 EXPORT_SYMBOL(rtw_dump_fw); 544 545 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 546 { 547 u8 *buf; 548 u32 i; 549 550 if (addr & 0x3) { 551 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 552 return -EINVAL; 553 } 554 555 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 556 if (!buf) 557 return -ENOMEM; 558 559 for (i = 0; i < size; i += 4) 560 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 561 562 return 0; 563 } 564 EXPORT_SYMBOL(rtw_dump_reg); 565 566 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 567 struct ieee80211_bss_conf *conf) 568 { 569 struct ieee80211_vif *vif = NULL; 570 571 if (conf) 572 vif = container_of(conf, struct ieee80211_vif, bss_conf); 573 574 if (conf && vif->cfg.assoc) { 575 rtwvif->aid = vif->cfg.aid; 576 rtwvif->net_type = RTW_NET_MGD_LINKED; 577 } else { 578 rtwvif->aid = 0; 579 rtwvif->net_type = RTW_NET_NO_LINK; 580 } 581 } 582 583 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 584 struct ieee80211_vif *vif, 585 struct ieee80211_sta *sta, 586 struct ieee80211_key_conf *key, 587 void *data) 588 { 589 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 590 struct rtw_sec_desc *sec = &rtwdev->sec; 591 592 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 593 } 594 595 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 596 { 597 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 598 599 if (rtwdev->sta_cnt == 0) { 600 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 601 return; 602 } 603 rtw_sta_remove(rtwdev, sta, false); 604 } 605 606 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 607 { 608 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 609 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 610 611 rtw_bf_disassoc(rtwdev, vif, NULL); 612 rtw_vif_assoc_changed(rtwvif, NULL); 613 rtw_txq_cleanup(rtwdev, vif->txq); 614 } 615 616 void rtw_fw_recovery(struct rtw_dev *rtwdev) 617 { 618 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 619 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 620 } 621 622 static void __fw_recovery_work(struct rtw_dev *rtwdev) 623 { 624 int ret = 0; 625 626 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 627 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 628 629 ret = rtw_fwcd_prep(rtwdev); 630 if (ret) 631 goto free; 632 ret = rtw_fw_dump_crash_log(rtwdev); 633 if (ret) 634 goto free; 635 ret = rtw_chip_dump_fw_crash(rtwdev); 636 if (ret) 637 goto free; 638 639 rtw_fwcd_dump(rtwdev); 640 free: 641 rtw_fwcd_free(rtwdev, !!ret); 642 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 643 644 WARN(1, "firmware crash, start reset and recover\n"); 645 646 rcu_read_lock(); 647 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 648 rcu_read_unlock(); 649 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 650 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 651 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM); 652 rtw_enter_ips(rtwdev); 653 } 654 655 static void rtw_fw_recovery_work(struct work_struct *work) 656 { 657 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 658 fw_recovery_work); 659 660 mutex_lock(&rtwdev->mutex); 661 __fw_recovery_work(rtwdev); 662 mutex_unlock(&rtwdev->mutex); 663 664 ieee80211_restart_hw(rtwdev->hw); 665 } 666 667 struct rtw_txq_ba_iter_data { 668 }; 669 670 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 671 { 672 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 673 int ret; 674 u8 tid; 675 676 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 677 while (tid != IEEE80211_NUM_TIDS) { 678 clear_bit(tid, si->tid_ba); 679 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 680 if (ret == -EINVAL) { 681 struct ieee80211_txq *txq; 682 struct rtw_txq *rtwtxq; 683 684 txq = sta->txq[tid]; 685 rtwtxq = (struct rtw_txq *)txq->drv_priv; 686 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 687 } 688 689 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 690 } 691 } 692 693 static void rtw_txq_ba_work(struct work_struct *work) 694 { 695 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 696 struct rtw_txq_ba_iter_data data; 697 698 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 699 } 700 701 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 702 { 703 if (IS_CH_2G_BAND(channel)) 704 pkt_stat->band = NL80211_BAND_2GHZ; 705 else if (IS_CH_5G_BAND(channel)) 706 pkt_stat->band = NL80211_BAND_5GHZ; 707 else 708 return; 709 710 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 711 } 712 EXPORT_SYMBOL(rtw_set_rx_freq_band); 713 714 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 715 { 716 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 717 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 718 } 719 720 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 721 u8 primary_channel, enum rtw_supported_band band, 722 enum rtw_bandwidth bandwidth) 723 { 724 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); 725 struct rtw_hal *hal = &rtwdev->hal; 726 u8 *cch_by_bw = hal->cch_by_bw; 727 u32 center_freq, primary_freq; 728 enum rtw_sar_bands sar_band; 729 u8 primary_channel_idx; 730 731 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); 732 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); 733 734 /* assign the center channel used while 20M bw is selected */ 735 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; 736 737 /* assign the center channel used while current bw is selected */ 738 cch_by_bw[bandwidth] = center_channel; 739 740 switch (bandwidth) { 741 case RTW_CHANNEL_WIDTH_20: 742 default: 743 primary_channel_idx = RTW_SC_DONT_CARE; 744 break; 745 case RTW_CHANNEL_WIDTH_40: 746 if (primary_freq > center_freq) 747 primary_channel_idx = RTW_SC_20_UPPER; 748 else 749 primary_channel_idx = RTW_SC_20_LOWER; 750 break; 751 case RTW_CHANNEL_WIDTH_80: 752 if (primary_freq > center_freq) { 753 if (primary_freq - center_freq == 10) 754 primary_channel_idx = RTW_SC_20_UPPER; 755 else 756 primary_channel_idx = RTW_SC_20_UPMOST; 757 758 /* assign the center channel used 759 * while 40M bw is selected 760 */ 761 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; 762 } else { 763 if (center_freq - primary_freq == 10) 764 primary_channel_idx = RTW_SC_20_LOWER; 765 else 766 primary_channel_idx = RTW_SC_20_LOWEST; 767 768 /* assign the center channel used 769 * while 40M bw is selected 770 */ 771 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; 772 } 773 break; 774 } 775 776 switch (center_channel) { 777 case 1 ... 14: 778 sar_band = RTW_SAR_BAND_0; 779 break; 780 case 36 ... 64: 781 sar_band = RTW_SAR_BAND_1; 782 break; 783 case 100 ... 144: 784 sar_band = RTW_SAR_BAND_3; 785 break; 786 case 149 ... 177: 787 sar_band = RTW_SAR_BAND_4; 788 break; 789 default: 790 WARN(1, "unknown ch(%u) to SAR band\n", center_channel); 791 sar_band = RTW_SAR_BAND_0; 792 break; 793 } 794 795 hal->current_primary_channel_index = primary_channel_idx; 796 hal->current_band_width = bandwidth; 797 hal->primary_channel = primary_channel; 798 hal->current_channel = center_channel; 799 hal->current_band_type = band; 800 hal->sar_band = sar_band; 801 } 802 803 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 804 struct rtw_channel_params *chan_params) 805 { 806 struct ieee80211_channel *channel = chandef->chan; 807 enum nl80211_chan_width width = chandef->width; 808 u32 primary_freq, center_freq; 809 u8 center_chan; 810 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 811 812 center_chan = channel->hw_value; 813 primary_freq = channel->center_freq; 814 center_freq = chandef->center_freq1; 815 816 switch (width) { 817 case NL80211_CHAN_WIDTH_20_NOHT: 818 case NL80211_CHAN_WIDTH_20: 819 bandwidth = RTW_CHANNEL_WIDTH_20; 820 break; 821 case NL80211_CHAN_WIDTH_40: 822 bandwidth = RTW_CHANNEL_WIDTH_40; 823 if (primary_freq > center_freq) 824 center_chan -= 2; 825 else 826 center_chan += 2; 827 break; 828 case NL80211_CHAN_WIDTH_80: 829 bandwidth = RTW_CHANNEL_WIDTH_80; 830 if (primary_freq > center_freq) { 831 if (primary_freq - center_freq == 10) 832 center_chan -= 2; 833 else 834 center_chan -= 6; 835 } else { 836 if (center_freq - primary_freq == 10) 837 center_chan += 2; 838 else 839 center_chan += 6; 840 } 841 break; 842 default: 843 center_chan = 0; 844 break; 845 } 846 847 chan_params->center_chan = center_chan; 848 chan_params->bandwidth = bandwidth; 849 chan_params->primary_chan = channel->hw_value; 850 } 851 852 void rtw_set_channel(struct rtw_dev *rtwdev) 853 { 854 const struct rtw_chip_info *chip = rtwdev->chip; 855 struct ieee80211_hw *hw = rtwdev->hw; 856 struct rtw_hal *hal = &rtwdev->hal; 857 struct rtw_channel_params ch_param; 858 u8 center_chan, primary_chan, bandwidth, band; 859 860 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 861 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 862 return; 863 864 center_chan = ch_param.center_chan; 865 primary_chan = ch_param.primary_chan; 866 bandwidth = ch_param.bandwidth; 867 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 868 869 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); 870 871 if (rtwdev->scan_info.op_chan) 872 rtw_store_op_chan(rtwdev, true); 873 874 chip->ops->set_channel(rtwdev, center_chan, bandwidth, 875 hal->current_primary_channel_index); 876 877 if (hal->current_band_type == RTW_BAND_5G) { 878 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 879 } else { 880 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 881 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 882 else 883 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 884 } 885 886 rtw_phy_set_tx_power_level(rtwdev, center_chan); 887 888 /* if the channel isn't set for scanning, we will do RF calibration 889 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 890 * during scanning on each channel takes too long. 891 */ 892 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 893 rtwdev->need_rfk = true; 894 } 895 896 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 897 { 898 const struct rtw_chip_info *chip = rtwdev->chip; 899 900 if (rtwdev->need_rfk) { 901 rtwdev->need_rfk = false; 902 chip->ops->phy_calibration(rtwdev); 903 } 904 } 905 906 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 907 { 908 int i; 909 910 for (i = 0; i < ETH_ALEN; i++) 911 rtw_write8(rtwdev, start + i, addr[i]); 912 } 913 914 void rtw_vif_port_config(struct rtw_dev *rtwdev, 915 struct rtw_vif *rtwvif, 916 u32 config) 917 { 918 u32 addr, mask; 919 920 if (config & PORT_SET_MAC_ADDR) { 921 addr = rtwvif->conf->mac_addr.addr; 922 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 923 } 924 if (config & PORT_SET_BSSID) { 925 addr = rtwvif->conf->bssid.addr; 926 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 927 } 928 if (config & PORT_SET_NET_TYPE) { 929 addr = rtwvif->conf->net_type.addr; 930 mask = rtwvif->conf->net_type.mask; 931 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 932 } 933 if (config & PORT_SET_AID) { 934 addr = rtwvif->conf->aid.addr; 935 mask = rtwvif->conf->aid.mask; 936 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 937 } 938 if (config & PORT_SET_BCN_CTRL) { 939 addr = rtwvif->conf->bcn_ctrl.addr; 940 mask = rtwvif->conf->bcn_ctrl.mask; 941 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 942 } 943 } 944 945 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 946 { 947 u8 bw = 0; 948 949 switch (bw_cap) { 950 case EFUSE_HW_CAP_IGNORE: 951 case EFUSE_HW_CAP_SUPP_BW80: 952 bw |= BIT(RTW_CHANNEL_WIDTH_80); 953 fallthrough; 954 case EFUSE_HW_CAP_SUPP_BW40: 955 bw |= BIT(RTW_CHANNEL_WIDTH_40); 956 fallthrough; 957 default: 958 bw |= BIT(RTW_CHANNEL_WIDTH_20); 959 break; 960 } 961 962 return bw; 963 } 964 965 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 966 { 967 const struct rtw_chip_info *chip = rtwdev->chip; 968 struct rtw_hal *hal = &rtwdev->hal; 969 970 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 971 hw_ant_num >= hal->rf_path_num) 972 return; 973 974 switch (hw_ant_num) { 975 case 1: 976 hal->rf_type = RF_1T1R; 977 hal->rf_path_num = 1; 978 if (!chip->fix_rf_phy_num) 979 hal->rf_phy_num = hal->rf_path_num; 980 hal->antenna_tx = BB_PATH_A; 981 hal->antenna_rx = BB_PATH_A; 982 break; 983 default: 984 WARN(1, "invalid hw configuration from efuse\n"); 985 break; 986 } 987 } 988 989 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 990 { 991 u64 ra_mask = 0; 992 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 993 u8 vht_mcs_cap; 994 int i, nss; 995 996 /* 4SS, every two bits for MCS7/8/9 */ 997 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 998 vht_mcs_cap = mcs_map & 0x3; 999 switch (vht_mcs_cap) { 1000 case 2: /* MCS9 */ 1001 ra_mask |= 0x3ffULL << nss; 1002 break; 1003 case 1: /* MCS8 */ 1004 ra_mask |= 0x1ffULL << nss; 1005 break; 1006 case 0: /* MCS7 */ 1007 ra_mask |= 0x0ffULL << nss; 1008 break; 1009 default: 1010 break; 1011 } 1012 } 1013 1014 return ra_mask; 1015 } 1016 1017 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 1018 { 1019 u8 rate_id = 0; 1020 1021 switch (wireless_set) { 1022 case WIRELESS_CCK: 1023 rate_id = RTW_RATEID_B_20M; 1024 break; 1025 case WIRELESS_OFDM: 1026 rate_id = RTW_RATEID_G; 1027 break; 1028 case WIRELESS_CCK | WIRELESS_OFDM: 1029 rate_id = RTW_RATEID_BG; 1030 break; 1031 case WIRELESS_OFDM | WIRELESS_HT: 1032 if (tx_num == 1) 1033 rate_id = RTW_RATEID_GN_N1SS; 1034 else if (tx_num == 2) 1035 rate_id = RTW_RATEID_GN_N2SS; 1036 else if (tx_num == 3) 1037 rate_id = RTW_RATEID_ARFR5_N_3SS; 1038 break; 1039 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 1040 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 1041 if (tx_num == 1) 1042 rate_id = RTW_RATEID_BGN_40M_1SS; 1043 else if (tx_num == 2) 1044 rate_id = RTW_RATEID_BGN_40M_2SS; 1045 else if (tx_num == 3) 1046 rate_id = RTW_RATEID_ARFR5_N_3SS; 1047 else if (tx_num == 4) 1048 rate_id = RTW_RATEID_ARFR7_N_4SS; 1049 } else { 1050 if (tx_num == 1) 1051 rate_id = RTW_RATEID_BGN_20M_1SS; 1052 else if (tx_num == 2) 1053 rate_id = RTW_RATEID_BGN_20M_2SS; 1054 else if (tx_num == 3) 1055 rate_id = RTW_RATEID_ARFR5_N_3SS; 1056 else if (tx_num == 4) 1057 rate_id = RTW_RATEID_ARFR7_N_4SS; 1058 } 1059 break; 1060 case WIRELESS_OFDM | WIRELESS_VHT: 1061 if (tx_num == 1) 1062 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1063 else if (tx_num == 2) 1064 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1065 else if (tx_num == 3) 1066 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1067 else if (tx_num == 4) 1068 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1069 break; 1070 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1071 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1072 if (tx_num == 1) 1073 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1074 else if (tx_num == 2) 1075 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1076 else if (tx_num == 3) 1077 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1078 else if (tx_num == 4) 1079 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1080 } else { 1081 if (tx_num == 1) 1082 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1083 else if (tx_num == 2) 1084 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1085 else if (tx_num == 3) 1086 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1087 else if (tx_num == 4) 1088 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1089 } 1090 break; 1091 default: 1092 break; 1093 } 1094 1095 return rate_id; 1096 } 1097 1098 #define RA_MASK_CCK_RATES 0x0000f 1099 #define RA_MASK_OFDM_RATES 0x00ff0 1100 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1101 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1102 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1103 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1104 RA_MASK_HT_RATES_2SS | \ 1105 RA_MASK_HT_RATES_3SS) 1106 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1107 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1108 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1109 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1110 RA_MASK_VHT_RATES_2SS | \ 1111 RA_MASK_VHT_RATES_3SS) 1112 #define RA_MASK_CCK_IN_BG 0x00005 1113 #define RA_MASK_CCK_IN_HT 0x00005 1114 #define RA_MASK_CCK_IN_VHT 0x00005 1115 #define RA_MASK_OFDM_IN_VHT 0x00010 1116 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1117 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1118 1119 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1120 { 1121 u8 rssi_level = si->rssi_level; 1122 1123 if (wireless_set == WIRELESS_CCK) 1124 return 0xffffffffffffffffULL; 1125 1126 if (rssi_level == 0) 1127 return 0xffffffffffffffffULL; 1128 else if (rssi_level == 1) 1129 return 0xfffffffffffffff0ULL; 1130 else if (rssi_level == 2) 1131 return 0xffffffffffffefe0ULL; 1132 else if (rssi_level == 3) 1133 return 0xffffffffffffcfc0ULL; 1134 else if (rssi_level == 4) 1135 return 0xffffffffffff8f80ULL; 1136 else 1137 return 0xffffffffffff0f00ULL; 1138 } 1139 1140 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1141 { 1142 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1143 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1144 1145 if (ra_mask == 0) 1146 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1147 1148 return ra_mask; 1149 } 1150 1151 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1152 u64 ra_mask, bool is_vht_enable) 1153 { 1154 struct rtw_hal *hal = &rtwdev->hal; 1155 const struct cfg80211_bitrate_mask *mask = si->mask; 1156 u64 cfg_mask = GENMASK_ULL(63, 0); 1157 u8 band; 1158 1159 if (!si->use_cfg_mask) 1160 return ra_mask; 1161 1162 band = hal->current_band_type; 1163 if (band == RTW_BAND_2G) { 1164 band = NL80211_BAND_2GHZ; 1165 cfg_mask = mask->control[band].legacy; 1166 } else if (band == RTW_BAND_5G) { 1167 band = NL80211_BAND_5GHZ; 1168 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1169 RA_MASK_OFDM_RATES); 1170 } 1171 1172 if (!is_vht_enable) { 1173 if (ra_mask & RA_MASK_HT_RATES_1SS) 1174 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1175 RA_MASK_HT_RATES_1SS); 1176 if (ra_mask & RA_MASK_HT_RATES_2SS) 1177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1178 RA_MASK_HT_RATES_2SS); 1179 } else { 1180 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1181 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1182 RA_MASK_VHT_RATES_1SS); 1183 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1184 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1185 RA_MASK_VHT_RATES_2SS); 1186 } 1187 1188 ra_mask &= cfg_mask; 1189 1190 return ra_mask; 1191 } 1192 1193 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1194 bool reset_ra_mask) 1195 { 1196 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1197 struct ieee80211_sta *sta = si->sta; 1198 struct rtw_efuse *efuse = &rtwdev->efuse; 1199 struct rtw_hal *hal = &rtwdev->hal; 1200 u8 wireless_set; 1201 u8 bw_mode; 1202 u8 rate_id; 1203 u8 rf_type = RF_1T1R; 1204 u8 stbc_en = 0; 1205 u8 ldpc_en = 0; 1206 u8 tx_num = 1; 1207 u64 ra_mask = 0; 1208 u64 ra_mask_bak = 0; 1209 bool is_vht_enable = false; 1210 bool is_support_sgi = false; 1211 1212 if (sta->deflink.vht_cap.vht_supported) { 1213 is_vht_enable = true; 1214 ra_mask |= get_vht_ra_mask(sta); 1215 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1216 stbc_en = VHT_STBC_EN; 1217 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1218 ldpc_en = VHT_LDPC_EN; 1219 } else if (sta->deflink.ht_cap.ht_supported) { 1220 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1221 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1222 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1223 stbc_en = HT_STBC_EN; 1224 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1225 ldpc_en = HT_LDPC_EN; 1226 } 1227 1228 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1229 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1230 1231 if (hal->current_band_type == RTW_BAND_5G) { 1232 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1233 ra_mask_bak = ra_mask; 1234 if (sta->deflink.vht_cap.vht_supported) { 1235 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1236 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1237 } else if (sta->deflink.ht_cap.ht_supported) { 1238 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1239 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1240 } else { 1241 wireless_set = WIRELESS_OFDM; 1242 } 1243 dm_info->rrsr_val_init = RRSR_INIT_5G; 1244 } else if (hal->current_band_type == RTW_BAND_2G) { 1245 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1246 ra_mask_bak = ra_mask; 1247 if (sta->deflink.vht_cap.vht_supported) { 1248 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1249 RA_MASK_OFDM_IN_VHT; 1250 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1251 WIRELESS_HT | WIRELESS_VHT; 1252 } else if (sta->deflink.ht_cap.ht_supported) { 1253 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1254 RA_MASK_OFDM_IN_HT_2G; 1255 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1256 WIRELESS_HT; 1257 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1258 wireless_set = WIRELESS_CCK; 1259 } else { 1260 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1261 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1262 } 1263 dm_info->rrsr_val_init = RRSR_INIT_2G; 1264 } else { 1265 rtw_err(rtwdev, "Unknown band type\n"); 1266 ra_mask_bak = ra_mask; 1267 wireless_set = 0; 1268 } 1269 1270 switch (sta->deflink.bandwidth) { 1271 case IEEE80211_STA_RX_BW_80: 1272 bw_mode = RTW_CHANNEL_WIDTH_80; 1273 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1274 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1275 break; 1276 case IEEE80211_STA_RX_BW_40: 1277 bw_mode = RTW_CHANNEL_WIDTH_40; 1278 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1279 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1280 break; 1281 default: 1282 bw_mode = RTW_CHANNEL_WIDTH_20; 1283 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1284 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1285 break; 1286 } 1287 1288 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1289 tx_num = 2; 1290 rf_type = RF_2T2R; 1291 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1292 tx_num = 2; 1293 rf_type = RF_2T2R; 1294 } 1295 1296 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1297 1298 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1299 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1300 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1301 1302 si->bw_mode = bw_mode; 1303 si->stbc_en = stbc_en; 1304 si->ldpc_en = ldpc_en; 1305 si->rf_type = rf_type; 1306 si->wireless_set = wireless_set; 1307 si->sgi_enable = is_support_sgi; 1308 si->vht_enable = is_vht_enable; 1309 si->ra_mask = ra_mask; 1310 si->rate_id = rate_id; 1311 1312 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1313 } 1314 1315 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1316 { 1317 const struct rtw_chip_info *chip = rtwdev->chip; 1318 struct rtw_fw_state *fw; 1319 1320 fw = &rtwdev->fw; 1321 wait_for_completion(&fw->completion); 1322 if (!fw->firmware) 1323 return -EINVAL; 1324 1325 if (chip->wow_fw_name) { 1326 fw = &rtwdev->wow_fw; 1327 wait_for_completion(&fw->completion); 1328 if (!fw->firmware) 1329 return -EINVAL; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1336 struct rtw_fw_state *fw) 1337 { 1338 const struct rtw_chip_info *chip = rtwdev->chip; 1339 1340 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1341 !fw->feature) 1342 return LPS_DEEP_MODE_NONE; 1343 1344 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1345 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1346 return LPS_DEEP_MODE_PG; 1347 1348 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1349 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1350 return LPS_DEEP_MODE_LCLK; 1351 1352 return LPS_DEEP_MODE_NONE; 1353 } 1354 1355 static int rtw_power_on(struct rtw_dev *rtwdev) 1356 { 1357 const struct rtw_chip_info *chip = rtwdev->chip; 1358 struct rtw_fw_state *fw = &rtwdev->fw; 1359 bool wifi_only; 1360 int ret; 1361 1362 ret = rtw_hci_setup(rtwdev); 1363 if (ret) { 1364 rtw_err(rtwdev, "failed to setup hci\n"); 1365 goto err; 1366 } 1367 1368 /* power on MAC before firmware downloaded */ 1369 ret = rtw_mac_power_on(rtwdev); 1370 if (ret) { 1371 rtw_err(rtwdev, "failed to power on mac\n"); 1372 goto err; 1373 } 1374 1375 ret = rtw_wait_firmware_completion(rtwdev); 1376 if (ret) { 1377 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1378 goto err_off; 1379 } 1380 1381 ret = rtw_download_firmware(rtwdev, fw); 1382 if (ret) { 1383 rtw_err(rtwdev, "failed to download firmware\n"); 1384 goto err_off; 1385 } 1386 1387 /* config mac after firmware downloaded */ 1388 ret = rtw_mac_init(rtwdev); 1389 if (ret) { 1390 rtw_err(rtwdev, "failed to configure mac\n"); 1391 goto err_off; 1392 } 1393 1394 chip->ops->phy_set_param(rtwdev); 1395 1396 ret = rtw_hci_start(rtwdev); 1397 if (ret) { 1398 rtw_err(rtwdev, "failed to start hci\n"); 1399 goto err_off; 1400 } 1401 1402 /* send H2C after HCI has started */ 1403 rtw_fw_send_general_info(rtwdev); 1404 rtw_fw_send_phydm_info(rtwdev); 1405 1406 wifi_only = !rtwdev->efuse.btcoex; 1407 rtw_coex_power_on_setting(rtwdev); 1408 rtw_coex_init_hw_config(rtwdev, wifi_only); 1409 1410 return 0; 1411 1412 err_off: 1413 rtw_mac_power_off(rtwdev); 1414 1415 err: 1416 return ret; 1417 } 1418 1419 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1420 { 1421 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1422 return; 1423 1424 if (start) { 1425 rtw_fw_scan_notify(rtwdev, true); 1426 } else { 1427 reinit_completion(&rtwdev->fw_scan_density); 1428 rtw_fw_scan_notify(rtwdev, false); 1429 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1430 SCAN_NOTIFY_TIMEOUT)) 1431 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1432 } 1433 } 1434 1435 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1436 const u8 *mac_addr, bool hw_scan) 1437 { 1438 u32 config = 0; 1439 int ret = 0; 1440 1441 rtw_leave_lps(rtwdev); 1442 1443 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1444 ret = rtw_leave_ips(rtwdev); 1445 if (ret) { 1446 rtw_err(rtwdev, "failed to leave idle state\n"); 1447 return; 1448 } 1449 } 1450 1451 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1452 config |= PORT_SET_MAC_ADDR; 1453 rtw_vif_port_config(rtwdev, rtwvif, config); 1454 1455 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1456 rtw_core_fw_scan_notify(rtwdev, true); 1457 1458 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1459 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1460 } 1461 1462 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1463 bool hw_scan) 1464 { 1465 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1466 u32 config = 0; 1467 1468 if (!rtwvif) 1469 return; 1470 1471 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1472 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1473 1474 rtw_core_fw_scan_notify(rtwdev, false); 1475 1476 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1477 config |= PORT_SET_MAC_ADDR; 1478 rtw_vif_port_config(rtwdev, rtwvif, config); 1479 1480 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1481 1482 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1483 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1484 } 1485 1486 int rtw_core_start(struct rtw_dev *rtwdev) 1487 { 1488 int ret; 1489 1490 ret = rtw_power_on(rtwdev); 1491 if (ret) 1492 return ret; 1493 1494 rtw_sec_enable_sec_engine(rtwdev); 1495 1496 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1497 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1498 1499 /* rcr reset after powered on */ 1500 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1501 1502 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1503 RTW_WATCH_DOG_DELAY_TIME); 1504 1505 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1506 1507 return 0; 1508 } 1509 1510 static void rtw_power_off(struct rtw_dev *rtwdev) 1511 { 1512 rtw_hci_stop(rtwdev); 1513 rtw_coex_power_off_setting(rtwdev); 1514 rtw_mac_power_off(rtwdev); 1515 } 1516 1517 void rtw_core_stop(struct rtw_dev *rtwdev) 1518 { 1519 struct rtw_coex *coex = &rtwdev->coex; 1520 1521 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1522 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1523 1524 mutex_unlock(&rtwdev->mutex); 1525 1526 cancel_work_sync(&rtwdev->c2h_work); 1527 cancel_work_sync(&rtwdev->update_beacon_work); 1528 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1529 cancel_delayed_work_sync(&coex->bt_relink_work); 1530 cancel_delayed_work_sync(&coex->bt_reenable_work); 1531 cancel_delayed_work_sync(&coex->defreeze_work); 1532 cancel_delayed_work_sync(&coex->wl_remain_work); 1533 cancel_delayed_work_sync(&coex->bt_remain_work); 1534 cancel_delayed_work_sync(&coex->wl_connecting_work); 1535 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1536 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1537 1538 mutex_lock(&rtwdev->mutex); 1539 1540 rtw_power_off(rtwdev); 1541 } 1542 1543 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1544 struct ieee80211_sta_ht_cap *ht_cap) 1545 { 1546 const struct rtw_chip_info *chip = rtwdev->chip; 1547 struct rtw_efuse *efuse = &rtwdev->efuse; 1548 1549 ht_cap->ht_supported = true; 1550 ht_cap->cap = 0; 1551 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1552 IEEE80211_HT_CAP_MAX_AMSDU | 1553 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1554 1555 if (rtw_chip_has_rx_ldpc(rtwdev)) 1556 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1557 if (rtw_chip_has_tx_stbc(rtwdev)) 1558 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1559 1560 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1561 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1562 IEEE80211_HT_CAP_DSSSCCK40 | 1563 IEEE80211_HT_CAP_SGI_40; 1564 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1565 ht_cap->ampdu_density = chip->ampdu_density; 1566 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1567 if (efuse->hw_cap.nss > 1) { 1568 ht_cap->mcs.rx_mask[0] = 0xFF; 1569 ht_cap->mcs.rx_mask[1] = 0xFF; 1570 ht_cap->mcs.rx_mask[4] = 0x01; 1571 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1572 } else { 1573 ht_cap->mcs.rx_mask[0] = 0xFF; 1574 ht_cap->mcs.rx_mask[1] = 0x00; 1575 ht_cap->mcs.rx_mask[4] = 0x01; 1576 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1577 } 1578 } 1579 1580 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1581 struct ieee80211_sta_vht_cap *vht_cap) 1582 { 1583 struct rtw_efuse *efuse = &rtwdev->efuse; 1584 u16 mcs_map; 1585 __le16 highest; 1586 1587 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1588 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1589 return; 1590 1591 vht_cap->vht_supported = true; 1592 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1593 IEEE80211_VHT_CAP_SHORT_GI_80 | 1594 IEEE80211_VHT_CAP_RXSTBC_1 | 1595 IEEE80211_VHT_CAP_HTC_VHT | 1596 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1597 0; 1598 if (rtwdev->hal.rf_path_num > 1) 1599 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1600 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1601 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1602 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1603 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1604 1605 if (rtw_chip_has_rx_ldpc(rtwdev)) 1606 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1607 1608 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1609 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1610 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1611 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1612 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1613 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1614 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1615 if (efuse->hw_cap.nss > 1) { 1616 highest = cpu_to_le16(780); 1617 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1618 } else { 1619 highest = cpu_to_le16(390); 1620 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1621 } 1622 1623 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1624 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1625 vht_cap->vht_mcs.rx_highest = highest; 1626 vht_cap->vht_mcs.tx_highest = highest; 1627 } 1628 1629 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) 1630 { 1631 u16 len; 1632 1633 len = rtwdev->chip->max_scan_ie_len; 1634 1635 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && 1636 rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 1637 len = IEEE80211_MAX_DATA_LEN; 1638 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) 1639 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; 1640 1641 return len; 1642 } 1643 1644 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1645 const struct rtw_chip_info *chip) 1646 { 1647 struct rtw_dev *rtwdev = hw->priv; 1648 struct ieee80211_supported_band *sband; 1649 1650 if (chip->band & RTW_BAND_2G) { 1651 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1652 if (!sband) 1653 goto err_out; 1654 if (chip->ht_supported) 1655 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1656 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1657 } 1658 1659 if (chip->band & RTW_BAND_5G) { 1660 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1661 if (!sband) 1662 goto err_out; 1663 if (chip->ht_supported) 1664 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1665 if (chip->vht_supported) 1666 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1667 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1668 } 1669 1670 return; 1671 1672 err_out: 1673 rtw_err(rtwdev, "failed to set supported band\n"); 1674 } 1675 1676 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1677 const struct rtw_chip_info *chip) 1678 { 1679 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1680 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1681 } 1682 1683 static void rtw_vif_smps_iter(void *data, u8 *mac, 1684 struct ieee80211_vif *vif) 1685 { 1686 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1687 1688 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1689 return; 1690 1691 if (rtwdev->hal.txrx_1ss) 1692 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); 1693 else 1694 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); 1695 } 1696 1697 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1698 { 1699 const struct rtw_chip_info *chip = rtwdev->chip; 1700 struct rtw_hal *hal = &rtwdev->hal; 1701 1702 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1703 return; 1704 1705 rtwdev->hal.txrx_1ss = txrx_1ss; 1706 if (txrx_1ss) 1707 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1708 else 1709 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1710 hal->antenna_rx, false); 1711 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1712 } 1713 1714 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1715 struct rtw_fw_state *fw) 1716 { 1717 u32 feature; 1718 const struct rtw_fw_hdr *fw_hdr = 1719 (const struct rtw_fw_hdr *)fw->firmware->data; 1720 1721 feature = le32_to_cpu(fw_hdr->feature); 1722 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1723 1724 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && 1725 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) 1726 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; 1727 } 1728 1729 static void __update_firmware_info(struct rtw_dev *rtwdev, 1730 struct rtw_fw_state *fw) 1731 { 1732 const struct rtw_fw_hdr *fw_hdr = 1733 (const struct rtw_fw_hdr *)fw->firmware->data; 1734 1735 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1736 fw->version = le16_to_cpu(fw_hdr->version); 1737 fw->sub_version = fw_hdr->subversion; 1738 fw->sub_index = fw_hdr->subindex; 1739 1740 __update_firmware_feature(rtwdev, fw); 1741 } 1742 1743 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1744 struct rtw_fw_state *fw) 1745 { 1746 struct rtw_fw_hdr_legacy *legacy = 1747 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1748 1749 fw->h2c_version = 0; 1750 fw->version = le16_to_cpu(legacy->version); 1751 fw->sub_version = legacy->subversion1; 1752 fw->sub_index = legacy->subversion2; 1753 } 1754 1755 static void update_firmware_info(struct rtw_dev *rtwdev, 1756 struct rtw_fw_state *fw) 1757 { 1758 if (rtw_chip_wcpu_11n(rtwdev)) 1759 __update_firmware_info_legacy(rtwdev, fw); 1760 else 1761 __update_firmware_info(rtwdev, fw); 1762 } 1763 1764 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1765 { 1766 struct rtw_fw_state *fw = context; 1767 struct rtw_dev *rtwdev = fw->rtwdev; 1768 1769 if (!firmware || !firmware->data) { 1770 rtw_err(rtwdev, "failed to request firmware\n"); 1771 complete_all(&fw->completion); 1772 return; 1773 } 1774 1775 fw->firmware = firmware; 1776 update_firmware_info(rtwdev, fw); 1777 complete_all(&fw->completion); 1778 1779 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", 1780 fw->type == RTW_WOWLAN_FW ? "WOW " : "", 1781 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1782 } 1783 1784 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1785 { 1786 const char *fw_name; 1787 struct rtw_fw_state *fw; 1788 int ret; 1789 1790 switch (type) { 1791 case RTW_WOWLAN_FW: 1792 fw = &rtwdev->wow_fw; 1793 fw_name = rtwdev->chip->wow_fw_name; 1794 break; 1795 1796 case RTW_NORMAL_FW: 1797 fw = &rtwdev->fw; 1798 fw_name = rtwdev->chip->fw_name; 1799 break; 1800 1801 default: 1802 rtw_warn(rtwdev, "unsupported firmware type\n"); 1803 return -ENOENT; 1804 } 1805 1806 fw->type = type; 1807 fw->rtwdev = rtwdev; 1808 init_completion(&fw->completion); 1809 1810 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1811 GFP_KERNEL, fw, rtw_load_firmware_cb); 1812 if (ret) { 1813 rtw_err(rtwdev, "failed to async firmware request\n"); 1814 return ret; 1815 } 1816 1817 return 0; 1818 } 1819 1820 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1821 { 1822 const struct rtw_chip_info *chip = rtwdev->chip; 1823 struct rtw_hal *hal = &rtwdev->hal; 1824 struct rtw_efuse *efuse = &rtwdev->efuse; 1825 1826 switch (rtw_hci_type(rtwdev)) { 1827 case RTW_HCI_TYPE_PCIE: 1828 rtwdev->hci.rpwm_addr = 0x03d9; 1829 rtwdev->hci.cpwm_addr = 0x03da; 1830 break; 1831 case RTW_HCI_TYPE_SDIO: 1832 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1; 1833 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2; 1834 break; 1835 case RTW_HCI_TYPE_USB: 1836 rtwdev->hci.rpwm_addr = 0xfe58; 1837 rtwdev->hci.cpwm_addr = 0xfe57; 1838 break; 1839 default: 1840 rtw_err(rtwdev, "unsupported hci type\n"); 1841 return -EINVAL; 1842 } 1843 1844 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1845 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1846 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1847 if (hal->chip_version & BIT_RF_TYPE_ID) { 1848 hal->rf_type = RF_2T2R; 1849 hal->rf_path_num = 2; 1850 hal->antenna_tx = BB_PATH_AB; 1851 hal->antenna_rx = BB_PATH_AB; 1852 } else { 1853 hal->rf_type = RF_1T1R; 1854 hal->rf_path_num = 1; 1855 hal->antenna_tx = BB_PATH_A; 1856 hal->antenna_rx = BB_PATH_A; 1857 } 1858 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1859 hal->rf_path_num; 1860 1861 efuse->physical_size = chip->phy_efuse_size; 1862 efuse->logical_size = chip->log_efuse_size; 1863 efuse->protect_size = chip->ptct_efuse_size; 1864 1865 /* default use ack */ 1866 rtwdev->hal.rcr |= BIT_VHT_DACK; 1867 1868 hal->bfee_sts_cap = 3; 1869 1870 return 0; 1871 } 1872 1873 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1874 { 1875 struct rtw_fw_state *fw = &rtwdev->fw; 1876 int ret; 1877 1878 ret = rtw_hci_setup(rtwdev); 1879 if (ret) { 1880 rtw_err(rtwdev, "failed to setup hci\n"); 1881 goto err; 1882 } 1883 1884 ret = rtw_mac_power_on(rtwdev); 1885 if (ret) { 1886 rtw_err(rtwdev, "failed to power on mac\n"); 1887 goto err; 1888 } 1889 1890 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1891 1892 wait_for_completion(&fw->completion); 1893 if (!fw->firmware) { 1894 ret = -EINVAL; 1895 rtw_err(rtwdev, "failed to load firmware\n"); 1896 goto err; 1897 } 1898 1899 ret = rtw_download_firmware(rtwdev, fw); 1900 if (ret) { 1901 rtw_err(rtwdev, "failed to download firmware\n"); 1902 goto err_off; 1903 } 1904 1905 return 0; 1906 1907 err_off: 1908 rtw_mac_power_off(rtwdev); 1909 1910 err: 1911 return ret; 1912 } 1913 1914 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1915 { 1916 struct rtw_efuse *efuse = &rtwdev->efuse; 1917 u8 hw_feature[HW_FEATURE_LEN]; 1918 u8 id; 1919 u8 bw; 1920 int i; 1921 1922 id = rtw_read8(rtwdev, REG_C2HEVT); 1923 if (id != C2H_HW_FEATURE_REPORT) { 1924 rtw_err(rtwdev, "failed to read hw feature report\n"); 1925 return -EBUSY; 1926 } 1927 1928 for (i = 0; i < HW_FEATURE_LEN; i++) 1929 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1930 1931 rtw_write8(rtwdev, REG_C2HEVT, 0); 1932 1933 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1934 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1935 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1936 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1937 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1938 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1939 1940 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1941 1942 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1943 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1944 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1945 1946 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1947 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1948 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1949 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1950 1951 return 0; 1952 } 1953 1954 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1955 { 1956 rtw_hci_stop(rtwdev); 1957 rtw_mac_power_off(rtwdev); 1958 } 1959 1960 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1961 { 1962 struct rtw_efuse *efuse = &rtwdev->efuse; 1963 int ret; 1964 1965 mutex_lock(&rtwdev->mutex); 1966 1967 /* power on mac to read efuse */ 1968 ret = rtw_chip_efuse_enable(rtwdev); 1969 if (ret) 1970 goto out_unlock; 1971 1972 ret = rtw_parse_efuse_map(rtwdev); 1973 if (ret) 1974 goto out_disable; 1975 1976 ret = rtw_dump_hw_feature(rtwdev); 1977 if (ret) 1978 goto out_disable; 1979 1980 ret = rtw_check_supported_rfe(rtwdev); 1981 if (ret) 1982 goto out_disable; 1983 1984 if (efuse->crystal_cap == 0xff) 1985 efuse->crystal_cap = 0; 1986 if (efuse->pa_type_2g == 0xff) 1987 efuse->pa_type_2g = 0; 1988 if (efuse->pa_type_5g == 0xff) 1989 efuse->pa_type_5g = 0; 1990 if (efuse->lna_type_2g == 0xff) 1991 efuse->lna_type_2g = 0; 1992 if (efuse->lna_type_5g == 0xff) 1993 efuse->lna_type_5g = 0; 1994 if (efuse->channel_plan == 0xff) 1995 efuse->channel_plan = 0x7f; 1996 if (efuse->rf_board_option == 0xff) 1997 efuse->rf_board_option = 0; 1998 if (efuse->bt_setting & BIT(0)) 1999 efuse->share_ant = true; 2000 if (efuse->regd == 0xff) 2001 efuse->regd = 0; 2002 if (efuse->tx_bb_swing_setting_2g == 0xff) 2003 efuse->tx_bb_swing_setting_2g = 0; 2004 if (efuse->tx_bb_swing_setting_5g == 0xff) 2005 efuse->tx_bb_swing_setting_5g = 0; 2006 2007 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 2008 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 2009 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 2010 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 2011 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 2012 2013 out_disable: 2014 rtw_chip_efuse_disable(rtwdev); 2015 2016 out_unlock: 2017 mutex_unlock(&rtwdev->mutex); 2018 return ret; 2019 } 2020 2021 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 2022 { 2023 struct rtw_hal *hal = &rtwdev->hal; 2024 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 2025 2026 if (!rfe_def) 2027 return -ENODEV; 2028 2029 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); 2030 2031 rtw_phy_init_tx_power(rtwdev); 2032 if (rfe_def->agc_btg_tbl) 2033 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 2034 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 2035 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 2036 rtw_phy_tx_power_by_rate_config(hal); 2037 rtw_phy_tx_power_limit_config(hal); 2038 2039 return 0; 2040 } 2041 2042 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 2043 { 2044 int ret; 2045 2046 ret = rtw_chip_parameter_setup(rtwdev); 2047 if (ret) { 2048 rtw_err(rtwdev, "failed to setup chip parameters\n"); 2049 goto err_out; 2050 } 2051 2052 ret = rtw_chip_efuse_info_setup(rtwdev); 2053 if (ret) { 2054 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 2055 goto err_out; 2056 } 2057 2058 ret = rtw_chip_board_info_setup(rtwdev); 2059 if (ret) { 2060 rtw_err(rtwdev, "failed to setup chip board info\n"); 2061 goto err_out; 2062 } 2063 2064 return 0; 2065 2066 err_out: 2067 return ret; 2068 } 2069 EXPORT_SYMBOL(rtw_chip_info_setup); 2070 2071 static void rtw_stats_init(struct rtw_dev *rtwdev) 2072 { 2073 struct rtw_traffic_stats *stats = &rtwdev->stats; 2074 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2075 int i; 2076 2077 ewma_tp_init(&stats->tx_ewma_tp); 2078 ewma_tp_init(&stats->rx_ewma_tp); 2079 2080 for (i = 0; i < RTW_EVM_NUM; i++) 2081 ewma_evm_init(&dm_info->ewma_evm[i]); 2082 for (i = 0; i < RTW_SNR_NUM; i++) 2083 ewma_snr_init(&dm_info->ewma_snr[i]); 2084 } 2085 2086 int rtw_core_init(struct rtw_dev *rtwdev) 2087 { 2088 const struct rtw_chip_info *chip = rtwdev->chip; 2089 struct rtw_coex *coex = &rtwdev->coex; 2090 int ret; 2091 2092 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2093 INIT_LIST_HEAD(&rtwdev->txqs); 2094 2095 timer_setup(&rtwdev->tx_report.purge_timer, 2096 rtw_tx_report_purge_timer, 0); 2097 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2098 if (!rtwdev->tx_wq) { 2099 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); 2100 return -ENOMEM; 2101 } 2102 2103 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2104 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2105 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2106 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2107 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2108 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2109 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2110 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2111 rtw_coex_bt_multi_link_remain_work); 2112 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2113 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2114 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2115 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2116 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2117 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2118 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2119 skb_queue_head_init(&rtwdev->c2h_queue); 2120 skb_queue_head_init(&rtwdev->coex.queue); 2121 skb_queue_head_init(&rtwdev->tx_report.queue); 2122 2123 spin_lock_init(&rtwdev->txq_lock); 2124 spin_lock_init(&rtwdev->tx_report.q_lock); 2125 2126 mutex_init(&rtwdev->mutex); 2127 mutex_init(&rtwdev->hal.tx_power_mutex); 2128 2129 init_waitqueue_head(&rtwdev->coex.wait); 2130 init_completion(&rtwdev->lps_leave_check); 2131 init_completion(&rtwdev->fw_scan_density); 2132 2133 rtwdev->sec.total_cam_num = 32; 2134 rtwdev->hal.current_channel = 1; 2135 rtwdev->dm_info.fix_rate = U8_MAX; 2136 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2137 2138 rtw_stats_init(rtwdev); 2139 2140 /* default rx filter setting */ 2141 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2142 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2143 BIT_AB | BIT_AM | BIT_APM; 2144 2145 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2146 if (ret) { 2147 rtw_warn(rtwdev, "no firmware loaded\n"); 2148 goto out; 2149 } 2150 2151 if (chip->wow_fw_name) { 2152 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2153 if (ret) { 2154 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2155 wait_for_completion(&rtwdev->fw.completion); 2156 if (rtwdev->fw.firmware) 2157 release_firmware(rtwdev->fw.firmware); 2158 goto out; 2159 } 2160 } 2161 2162 return 0; 2163 2164 out: 2165 destroy_workqueue(rtwdev->tx_wq); 2166 return ret; 2167 } 2168 EXPORT_SYMBOL(rtw_core_init); 2169 2170 void rtw_core_deinit(struct rtw_dev *rtwdev) 2171 { 2172 struct rtw_fw_state *fw = &rtwdev->fw; 2173 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2174 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2175 unsigned long flags; 2176 2177 rtw_wait_firmware_completion(rtwdev); 2178 2179 if (fw->firmware) 2180 release_firmware(fw->firmware); 2181 2182 if (wow_fw->firmware) 2183 release_firmware(wow_fw->firmware); 2184 2185 destroy_workqueue(rtwdev->tx_wq); 2186 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2187 skb_queue_purge(&rtwdev->tx_report.queue); 2188 skb_queue_purge(&rtwdev->coex.queue); 2189 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2190 2191 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2192 build_list) { 2193 list_del(&rsvd_pkt->build_list); 2194 kfree(rsvd_pkt); 2195 } 2196 2197 mutex_destroy(&rtwdev->mutex); 2198 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2199 } 2200 EXPORT_SYMBOL(rtw_core_deinit); 2201 2202 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2203 { 2204 struct rtw_hal *hal = &rtwdev->hal; 2205 int max_tx_headroom = 0; 2206 int ret; 2207 2208 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2209 2210 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 2211 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN; 2212 2213 hw->extra_tx_headroom = max_tx_headroom; 2214 hw->queues = IEEE80211_NUM_ACS; 2215 hw->txq_data_size = sizeof(struct rtw_txq); 2216 hw->sta_data_size = sizeof(struct rtw_sta_info); 2217 hw->vif_data_size = sizeof(struct rtw_vif); 2218 2219 ieee80211_hw_set(hw, SIGNAL_DBM); 2220 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2221 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2222 ieee80211_hw_set(hw, MFP_CAPABLE); 2223 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2224 ieee80211_hw_set(hw, SUPPORTS_PS); 2225 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2226 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2227 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2228 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2229 ieee80211_hw_set(hw, TX_AMSDU); 2230 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2231 2232 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2233 BIT(NL80211_IFTYPE_AP) | 2234 BIT(NL80211_IFTYPE_ADHOC) | 2235 BIT(NL80211_IFTYPE_MESH_POINT); 2236 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2237 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2238 2239 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2240 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2241 2242 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2243 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2244 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); 2245 2246 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) { 2247 hw->wiphy->iface_combinations = rtw_iface_combs; 2248 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs); 2249 } 2250 2251 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2252 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2253 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2254 2255 #ifdef CONFIG_PM 2256 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2257 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2258 #endif 2259 rtw_set_supported_band(hw, rtwdev->chip); 2260 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2261 2262 hw->wiphy->sar_capa = &rtw_sar_capa; 2263 2264 ret = rtw_regd_init(rtwdev); 2265 if (ret) { 2266 rtw_err(rtwdev, "failed to init regd\n"); 2267 return ret; 2268 } 2269 2270 ret = ieee80211_register_hw(hw); 2271 if (ret) { 2272 rtw_err(rtwdev, "failed to register hw\n"); 2273 return ret; 2274 } 2275 2276 ret = rtw_regd_hint(rtwdev); 2277 if (ret) { 2278 rtw_err(rtwdev, "failed to hint regd\n"); 2279 return ret; 2280 } 2281 2282 rtw_debugfs_init(rtwdev); 2283 2284 rtwdev->bf_info.bfer_mu_cnt = 0; 2285 rtwdev->bf_info.bfer_su_cnt = 0; 2286 2287 return 0; 2288 } 2289 EXPORT_SYMBOL(rtw_register_hw); 2290 2291 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2292 { 2293 const struct rtw_chip_info *chip = rtwdev->chip; 2294 2295 ieee80211_unregister_hw(hw); 2296 rtw_unset_supported_band(hw, chip); 2297 } 2298 EXPORT_SYMBOL(rtw_unregister_hw); 2299 2300 static 2301 void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2302 const struct rtw_hw_reg *reg2, u8 nbytes) 2303 { 2304 u8 i; 2305 2306 for (i = 0; i < nbytes; i++) { 2307 u8 v1 = rtw_read8(rtwdev, reg1->addr + i); 2308 u8 v2 = rtw_read8(rtwdev, reg2->addr + i); 2309 2310 rtw_write8(rtwdev, reg1->addr + i, v2); 2311 rtw_write8(rtwdev, reg2->addr + i, v1); 2312 } 2313 } 2314 2315 static 2316 void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2317 const struct rtw_hw_reg *reg2) 2318 { 2319 u32 v1, v2; 2320 2321 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask); 2322 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask); 2323 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); 2324 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); 2325 } 2326 2327 struct rtw_iter_port_switch_data { 2328 struct rtw_dev *rtwdev; 2329 struct rtw_vif *rtwvif_ap; 2330 }; 2331 2332 static void rtw_port_switch_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 2333 { 2334 struct rtw_iter_port_switch_data *iter_data = data; 2335 struct rtw_dev *rtwdev = iter_data->rtwdev; 2336 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv; 2337 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap; 2338 const struct rtw_hw_reg *reg1, *reg2; 2339 2340 if (rtwvif_target->port != RTW_PORT_0) 2341 return; 2342 2343 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n", 2344 rtwvif_ap->port, rtwvif_target->port); 2345 2346 /* Leave LPS so the value swapped are not in PS mode */ 2347 rtw_leave_lps(rtwdev); 2348 2349 reg1 = &rtwvif_ap->conf->net_type; 2350 reg2 = &rtwvif_target->conf->net_type; 2351 rtw_swap_reg_mask(rtwdev, reg1, reg2); 2352 2353 reg1 = &rtwvif_ap->conf->mac_addr; 2354 reg2 = &rtwvif_target->conf->mac_addr; 2355 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2356 2357 reg1 = &rtwvif_ap->conf->bssid; 2358 reg2 = &rtwvif_target->conf->bssid; 2359 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2360 2361 reg1 = &rtwvif_ap->conf->bcn_ctrl; 2362 reg2 = &rtwvif_target->conf->bcn_ctrl; 2363 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1); 2364 2365 swap(rtwvif_target->port, rtwvif_ap->port); 2366 swap(rtwvif_target->conf, rtwvif_ap->conf); 2367 2368 rtw_fw_default_port(rtwdev, rtwvif_target); 2369 } 2370 2371 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 2372 { 2373 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2374 struct rtw_iter_port_switch_data iter_data; 2375 2376 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0) 2377 return; 2378 2379 iter_data.rtwdev = rtwdev; 2380 iter_data.rtwvif_ap = rtwvif; 2381 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data); 2382 } 2383 2384 static void rtw_check_sta_active_iter(void *data, u8 *mac, 2385 struct ieee80211_vif *vif) 2386 { 2387 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2388 bool *active = data; 2389 2390 if (*active) 2391 return; 2392 2393 if (vif->type != NL80211_IFTYPE_STATION) 2394 return; 2395 2396 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) 2397 *active = true; 2398 } 2399 2400 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev) 2401 { 2402 bool sta_active = false; 2403 2404 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active); 2405 2406 return rtwdev->ap_active || sta_active; 2407 } 2408 2409 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable) 2410 { 2411 if (!rtwdev->ap_active) 2412 return; 2413 2414 if (enable) { 2415 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2416 rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2417 } else { 2418 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2419 rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE); 2420 } 2421 } 2422 2423 MODULE_AUTHOR("Realtek Corporation"); 2424 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2425 MODULE_LICENSE("Dual BSD/GPL"); 2426