1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 #include "sdio.h" 22 23 bool rtw_disable_lps_deep_mode; 24 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 25 bool rtw_bf_support = true; 26 unsigned int rtw_debug_mask; 27 EXPORT_SYMBOL(rtw_debug_mask); 28 /* EDCCA is enabled during normal behavior. For debugging purpose in 29 * a noisy environment, it can be disabled via edcca debugfs. Because 30 * all rtw88 devices will probably be affected if environment is noisy, 31 * rtw_edcca_enabled is just declared by driver instead of by device. 32 * So, turning it off will take effect for all rtw88 devices before 33 * there is a tough reason to maintain rtw_edcca_enabled by device. 34 */ 35 bool rtw_edcca_enabled = true; 36 37 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 38 module_param_named(support_bf, rtw_bf_support, bool, 0644); 39 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 40 41 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 42 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 43 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 44 45 static struct ieee80211_channel rtw_channeltable_2g[] = { 46 {.center_freq = 2412, .hw_value = 1,}, 47 {.center_freq = 2417, .hw_value = 2,}, 48 {.center_freq = 2422, .hw_value = 3,}, 49 {.center_freq = 2427, .hw_value = 4,}, 50 {.center_freq = 2432, .hw_value = 5,}, 51 {.center_freq = 2437, .hw_value = 6,}, 52 {.center_freq = 2442, .hw_value = 7,}, 53 {.center_freq = 2447, .hw_value = 8,}, 54 {.center_freq = 2452, .hw_value = 9,}, 55 {.center_freq = 2457, .hw_value = 10,}, 56 {.center_freq = 2462, .hw_value = 11,}, 57 {.center_freq = 2467, .hw_value = 12,}, 58 {.center_freq = 2472, .hw_value = 13,}, 59 {.center_freq = 2484, .hw_value = 14,}, 60 }; 61 62 static struct ieee80211_channel rtw_channeltable_5g[] = { 63 {.center_freq = 5180, .hw_value = 36,}, 64 {.center_freq = 5200, .hw_value = 40,}, 65 {.center_freq = 5220, .hw_value = 44,}, 66 {.center_freq = 5240, .hw_value = 48,}, 67 {.center_freq = 5260, .hw_value = 52,}, 68 {.center_freq = 5280, .hw_value = 56,}, 69 {.center_freq = 5300, .hw_value = 60,}, 70 {.center_freq = 5320, .hw_value = 64,}, 71 {.center_freq = 5500, .hw_value = 100,}, 72 {.center_freq = 5520, .hw_value = 104,}, 73 {.center_freq = 5540, .hw_value = 108,}, 74 {.center_freq = 5560, .hw_value = 112,}, 75 {.center_freq = 5580, .hw_value = 116,}, 76 {.center_freq = 5600, .hw_value = 120,}, 77 {.center_freq = 5620, .hw_value = 124,}, 78 {.center_freq = 5640, .hw_value = 128,}, 79 {.center_freq = 5660, .hw_value = 132,}, 80 {.center_freq = 5680, .hw_value = 136,}, 81 {.center_freq = 5700, .hw_value = 140,}, 82 {.center_freq = 5720, .hw_value = 144,}, 83 {.center_freq = 5745, .hw_value = 149,}, 84 {.center_freq = 5765, .hw_value = 153,}, 85 {.center_freq = 5785, .hw_value = 157,}, 86 {.center_freq = 5805, .hw_value = 161,}, 87 {.center_freq = 5825, .hw_value = 165, 88 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 89 }; 90 91 static struct ieee80211_rate rtw_ratetable[] = { 92 {.bitrate = 10, .hw_value = 0x00,}, 93 {.bitrate = 20, .hw_value = 0x01,}, 94 {.bitrate = 55, .hw_value = 0x02,}, 95 {.bitrate = 110, .hw_value = 0x03,}, 96 {.bitrate = 60, .hw_value = 0x04,}, 97 {.bitrate = 90, .hw_value = 0x05,}, 98 {.bitrate = 120, .hw_value = 0x06,}, 99 {.bitrate = 180, .hw_value = 0x07,}, 100 {.bitrate = 240, .hw_value = 0x08,}, 101 {.bitrate = 360, .hw_value = 0x09,}, 102 {.bitrate = 480, .hw_value = 0x0a,}, 103 {.bitrate = 540, .hw_value = 0x0b,}, 104 }; 105 106 static const struct ieee80211_iface_limit rtw_iface_limits[] = { 107 { 108 .max = 1, 109 .types = BIT(NL80211_IFTYPE_STATION), 110 }, 111 { 112 .max = 1, 113 .types = BIT(NL80211_IFTYPE_AP), 114 } 115 }; 116 117 static const struct ieee80211_iface_combination rtw_iface_combs[] = { 118 { 119 .limits = rtw_iface_limits, 120 .n_limits = ARRAY_SIZE(rtw_iface_limits), 121 .max_interfaces = 2, 122 .num_different_channels = 1, 123 } 124 }; 125 126 u16 rtw_desc_to_bitrate(u8 desc_rate) 127 { 128 struct ieee80211_rate rate; 129 130 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 131 return 0; 132 133 rate = rtw_ratetable[desc_rate]; 134 135 return rate.bitrate; 136 } 137 138 static struct ieee80211_supported_band rtw_band_2ghz = { 139 .band = NL80211_BAND_2GHZ, 140 141 .channels = rtw_channeltable_2g, 142 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 143 144 .bitrates = rtw_ratetable, 145 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 146 147 .ht_cap = {0}, 148 .vht_cap = {0}, 149 }; 150 151 static struct ieee80211_supported_band rtw_band_5ghz = { 152 .band = NL80211_BAND_5GHZ, 153 154 .channels = rtw_channeltable_5g, 155 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 156 157 /* 5G has no CCK rates */ 158 .bitrates = rtw_ratetable + 4, 159 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 160 161 .ht_cap = {0}, 162 .vht_cap = {0}, 163 }; 164 165 struct rtw_watch_dog_iter_data { 166 struct rtw_dev *rtwdev; 167 struct rtw_vif *rtwvif; 168 }; 169 170 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 171 { 172 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 173 u8 fix_rate_enable = 0; 174 u8 new_csi_rate_idx; 175 176 if (rtwvif->bfee.role != RTW_BFEE_SU && 177 rtwvif->bfee.role != RTW_BFEE_MU) 178 return; 179 180 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 181 bf_info->cur_csi_rpt_rate, 182 fix_rate_enable, &new_csi_rate_idx); 183 184 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 185 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 186 } 187 188 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 189 struct ieee80211_vif *vif) 190 { 191 struct rtw_watch_dog_iter_data *iter_data = data; 192 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 193 194 if (vif->type == NL80211_IFTYPE_STATION) 195 if (vif->cfg.assoc) 196 iter_data->rtwvif = rtwvif; 197 198 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 199 200 rtwvif->stats.tx_unicast = 0; 201 rtwvif->stats.rx_unicast = 0; 202 rtwvif->stats.tx_cnt = 0; 203 rtwvif->stats.rx_cnt = 0; 204 } 205 206 /* process TX/RX statistics periodically for hardware, 207 * the information helps hardware to enhance performance 208 */ 209 static void rtw_watch_dog_work(struct work_struct *work) 210 { 211 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 212 watch_dog_work.work); 213 struct rtw_traffic_stats *stats = &rtwdev->stats; 214 struct rtw_watch_dog_iter_data data = {}; 215 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 216 bool ps_active; 217 218 mutex_lock(&rtwdev->mutex); 219 220 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 221 goto unlock; 222 223 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 224 RTW_WATCH_DOG_DELAY_TIME); 225 226 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 227 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 228 else 229 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 230 231 rtw_coex_wl_status_check(rtwdev); 232 rtw_coex_query_bt_hid_list(rtwdev); 233 234 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 235 rtw_coex_wl_status_change_notify(rtwdev, 0); 236 237 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 238 stats->rx_cnt > RTW_LPS_THRESHOLD) 239 ps_active = true; 240 else 241 ps_active = false; 242 243 ewma_tp_add(&stats->tx_ewma_tp, 244 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 245 ewma_tp_add(&stats->rx_ewma_tp, 246 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 247 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 248 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 249 250 /* reset tx/rx statictics */ 251 stats->tx_unicast = 0; 252 stats->rx_unicast = 0; 253 stats->tx_cnt = 0; 254 stats->rx_cnt = 0; 255 256 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 257 goto unlock; 258 259 /* make sure BB/RF is working for dynamic mech */ 260 rtw_leave_lps(rtwdev); 261 262 rtw_phy_dynamic_mechanism(rtwdev); 263 264 data.rtwdev = rtwdev; 265 /* rtw_iterate_vifs internally uses an atomic iterator which is needed 266 * to avoid taking local->iflist_mtx mutex 267 */ 268 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); 269 270 /* fw supports only one station associated to enter lps, if there are 271 * more than two stations associated to the AP, then we can not enter 272 * lps, because fw does not handle the overlapped beacon interval 273 * 274 * mac80211 should iterate vifs and determine if driver can enter 275 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 276 * get that vif and check if device is having traffic more than the 277 * threshold. 278 */ 279 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 280 !rtwdev->beacon_loss && !rtwdev->ap_active) 281 rtw_enter_lps(rtwdev, data.rtwvif->port); 282 283 rtwdev->watch_dog_cnt++; 284 285 unlock: 286 mutex_unlock(&rtwdev->mutex); 287 } 288 289 static void rtw_c2h_work(struct work_struct *work) 290 { 291 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 292 struct sk_buff *skb, *tmp; 293 294 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 295 skb_unlink(skb, &rtwdev->c2h_queue); 296 rtw_fw_c2h_cmd_handle(rtwdev, skb); 297 dev_kfree_skb_any(skb); 298 } 299 } 300 301 static void rtw_ips_work(struct work_struct *work) 302 { 303 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 304 305 mutex_lock(&rtwdev->mutex); 306 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 307 rtw_enter_ips(rtwdev); 308 mutex_unlock(&rtwdev->mutex); 309 } 310 311 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 312 { 313 unsigned long mac_id; 314 315 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 316 if (mac_id < RTW_MAX_MAC_ID_NUM) 317 set_bit(mac_id, rtwdev->mac_id_map); 318 319 return mac_id; 320 } 321 322 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 323 struct ieee80211_vif *vif) 324 { 325 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 326 int i; 327 328 si->mac_id = rtw_acquire_macid(rtwdev); 329 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 330 return -ENOSPC; 331 332 si->sta = sta; 333 si->vif = vif; 334 si->init_ra_lv = 1; 335 ewma_rssi_init(&si->avg_rssi); 336 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 337 rtw_txq_init(rtwdev, sta->txq[i]); 338 339 rtw_update_sta_info(rtwdev, si, true); 340 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 341 342 rtwdev->sta_cnt++; 343 rtwdev->beacon_loss = false; 344 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 345 sta->addr, si->mac_id); 346 347 return 0; 348 } 349 350 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 351 bool fw_exist) 352 { 353 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 354 int i; 355 356 rtw_release_macid(rtwdev, si->mac_id); 357 if (fw_exist) 358 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 359 360 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 361 rtw_txq_cleanup(rtwdev, sta->txq[i]); 362 363 kfree(si->mask); 364 365 rtwdev->sta_cnt--; 366 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 367 sta->addr, si->mac_id); 368 } 369 370 struct rtw_fwcd_hdr { 371 u32 item; 372 u32 size; 373 u32 padding1; 374 u32 padding2; 375 } __packed; 376 377 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 378 { 379 const struct rtw_chip_info *chip = rtwdev->chip; 380 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 381 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 382 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 383 u8 i; 384 385 if (segs) { 386 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 387 388 for (i = 0; i < segs->num; i++) 389 prep_size += segs->segs[i]; 390 } 391 392 desc->data = vmalloc(prep_size); 393 if (!desc->data) 394 return -ENOMEM; 395 396 desc->size = prep_size; 397 desc->next = desc->data; 398 399 return 0; 400 } 401 402 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 403 { 404 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 405 struct rtw_fwcd_hdr *hdr; 406 u8 *next; 407 408 if (!desc->data) { 409 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 410 return NULL; 411 } 412 413 next = desc->next + sizeof(struct rtw_fwcd_hdr); 414 if (next - desc->data + size > desc->size) { 415 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 416 return NULL; 417 } 418 419 hdr = (struct rtw_fwcd_hdr *)(desc->next); 420 hdr->item = item; 421 hdr->size = size; 422 hdr->padding1 = 0x01234567; 423 hdr->padding2 = 0x89abcdef; 424 desc->next = next + size; 425 426 return next; 427 } 428 429 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 430 { 431 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 432 433 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 434 435 /* Data will be freed after lifetime of device coredump. After calling 436 * dev_coredump, data is supposed to be handled by the device coredump 437 * framework. Note that a new dump will be discarded if a previous one 438 * hasn't been released yet. 439 */ 440 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 441 } 442 443 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 444 { 445 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 446 447 if (free_self) { 448 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 449 vfree(desc->data); 450 } 451 452 desc->data = NULL; 453 desc->next = NULL; 454 } 455 456 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 457 { 458 u32 size = rtwdev->chip->fw_rxff_size; 459 u32 *buf; 460 u8 seq; 461 462 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 463 if (!buf) 464 return -ENOMEM; 465 466 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 467 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 468 return -EINVAL; 469 } 470 471 if (GET_FW_DUMP_LEN(buf) == 0) { 472 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 473 return -EINVAL; 474 } 475 476 seq = GET_FW_DUMP_SEQ(buf); 477 if (seq > 0) { 478 rtw_dbg(rtwdev, RTW_DBG_FW, 479 "fw crash dump's seq is wrong: %d\n", seq); 480 return -EINVAL; 481 } 482 483 return 0; 484 } 485 486 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 487 u32 fwcd_item) 488 { 489 u32 rxff = rtwdev->chip->fw_rxff_size; 490 u32 dump_size, done_size = 0; 491 u8 *buf; 492 int ret; 493 494 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 495 if (!buf) 496 return -ENOMEM; 497 498 while (size) { 499 dump_size = size > rxff ? rxff : size; 500 501 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 502 dump_size); 503 if (ret) { 504 rtw_err(rtwdev, 505 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 506 ocp_src, done_size); 507 return ret; 508 } 509 510 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 511 dump_size, (u32 *)(buf + done_size)); 512 if (ret) { 513 rtw_err(rtwdev, 514 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 515 ocp_src, done_size); 516 return ret; 517 } 518 519 size -= dump_size; 520 done_size += dump_size; 521 } 522 523 return 0; 524 } 525 EXPORT_SYMBOL(rtw_dump_fw); 526 527 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 528 { 529 u8 *buf; 530 u32 i; 531 532 if (addr & 0x3) { 533 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 534 return -EINVAL; 535 } 536 537 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 538 if (!buf) 539 return -ENOMEM; 540 541 for (i = 0; i < size; i += 4) 542 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 543 544 return 0; 545 } 546 EXPORT_SYMBOL(rtw_dump_reg); 547 548 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 549 struct ieee80211_bss_conf *conf) 550 { 551 struct ieee80211_vif *vif = NULL; 552 553 if (conf) 554 vif = container_of(conf, struct ieee80211_vif, bss_conf); 555 556 if (conf && vif->cfg.assoc) { 557 rtwvif->aid = vif->cfg.aid; 558 rtwvif->net_type = RTW_NET_MGD_LINKED; 559 } else { 560 rtwvif->aid = 0; 561 rtwvif->net_type = RTW_NET_NO_LINK; 562 } 563 } 564 565 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 566 struct ieee80211_vif *vif, 567 struct ieee80211_sta *sta, 568 struct ieee80211_key_conf *key, 569 void *data) 570 { 571 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 572 struct rtw_sec_desc *sec = &rtwdev->sec; 573 574 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 575 } 576 577 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 578 { 579 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 580 581 if (rtwdev->sta_cnt == 0) { 582 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 583 return; 584 } 585 rtw_sta_remove(rtwdev, sta, false); 586 } 587 588 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 589 { 590 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 591 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 592 593 rtw_bf_disassoc(rtwdev, vif, NULL); 594 rtw_vif_assoc_changed(rtwvif, NULL); 595 rtw_txq_cleanup(rtwdev, vif->txq); 596 } 597 598 void rtw_fw_recovery(struct rtw_dev *rtwdev) 599 { 600 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 601 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 602 } 603 604 static void __fw_recovery_work(struct rtw_dev *rtwdev) 605 { 606 int ret = 0; 607 608 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 609 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 610 611 ret = rtw_fwcd_prep(rtwdev); 612 if (ret) 613 goto free; 614 ret = rtw_fw_dump_crash_log(rtwdev); 615 if (ret) 616 goto free; 617 ret = rtw_chip_dump_fw_crash(rtwdev); 618 if (ret) 619 goto free; 620 621 rtw_fwcd_dump(rtwdev); 622 free: 623 rtw_fwcd_free(rtwdev, !!ret); 624 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 625 626 WARN(1, "firmware crash, start reset and recover\n"); 627 628 rcu_read_lock(); 629 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 630 rcu_read_unlock(); 631 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 632 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 633 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM); 634 rtw_enter_ips(rtwdev); 635 } 636 637 static void rtw_fw_recovery_work(struct work_struct *work) 638 { 639 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 640 fw_recovery_work); 641 642 mutex_lock(&rtwdev->mutex); 643 __fw_recovery_work(rtwdev); 644 mutex_unlock(&rtwdev->mutex); 645 646 ieee80211_restart_hw(rtwdev->hw); 647 } 648 649 struct rtw_txq_ba_iter_data { 650 }; 651 652 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 653 { 654 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 655 int ret; 656 u8 tid; 657 658 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 659 while (tid != IEEE80211_NUM_TIDS) { 660 clear_bit(tid, si->tid_ba); 661 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 662 if (ret == -EINVAL) { 663 struct ieee80211_txq *txq; 664 struct rtw_txq *rtwtxq; 665 666 txq = sta->txq[tid]; 667 rtwtxq = (struct rtw_txq *)txq->drv_priv; 668 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 669 } 670 671 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 672 } 673 } 674 675 static void rtw_txq_ba_work(struct work_struct *work) 676 { 677 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 678 struct rtw_txq_ba_iter_data data; 679 680 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 681 } 682 683 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 684 { 685 if (IS_CH_2G_BAND(channel)) 686 pkt_stat->band = NL80211_BAND_2GHZ; 687 else if (IS_CH_5G_BAND(channel)) 688 pkt_stat->band = NL80211_BAND_5GHZ; 689 else 690 return; 691 692 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 693 } 694 EXPORT_SYMBOL(rtw_set_rx_freq_band); 695 696 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 697 { 698 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 699 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 700 } 701 702 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 703 u8 primary_channel, enum rtw_supported_band band, 704 enum rtw_bandwidth bandwidth) 705 { 706 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); 707 struct rtw_hal *hal = &rtwdev->hal; 708 u8 *cch_by_bw = hal->cch_by_bw; 709 u32 center_freq, primary_freq; 710 enum rtw_sar_bands sar_band; 711 u8 primary_channel_idx; 712 713 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); 714 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); 715 716 /* assign the center channel used while 20M bw is selected */ 717 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; 718 719 /* assign the center channel used while current bw is selected */ 720 cch_by_bw[bandwidth] = center_channel; 721 722 switch (bandwidth) { 723 case RTW_CHANNEL_WIDTH_20: 724 default: 725 primary_channel_idx = RTW_SC_DONT_CARE; 726 break; 727 case RTW_CHANNEL_WIDTH_40: 728 if (primary_freq > center_freq) 729 primary_channel_idx = RTW_SC_20_UPPER; 730 else 731 primary_channel_idx = RTW_SC_20_LOWER; 732 break; 733 case RTW_CHANNEL_WIDTH_80: 734 if (primary_freq > center_freq) { 735 if (primary_freq - center_freq == 10) 736 primary_channel_idx = RTW_SC_20_UPPER; 737 else 738 primary_channel_idx = RTW_SC_20_UPMOST; 739 740 /* assign the center channel used 741 * while 40M bw is selected 742 */ 743 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; 744 } else { 745 if (center_freq - primary_freq == 10) 746 primary_channel_idx = RTW_SC_20_LOWER; 747 else 748 primary_channel_idx = RTW_SC_20_LOWEST; 749 750 /* assign the center channel used 751 * while 40M bw is selected 752 */ 753 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; 754 } 755 break; 756 } 757 758 switch (center_channel) { 759 case 1 ... 14: 760 sar_band = RTW_SAR_BAND_0; 761 break; 762 case 36 ... 64: 763 sar_band = RTW_SAR_BAND_1; 764 break; 765 case 100 ... 144: 766 sar_band = RTW_SAR_BAND_3; 767 break; 768 case 149 ... 177: 769 sar_band = RTW_SAR_BAND_4; 770 break; 771 default: 772 WARN(1, "unknown ch(%u) to SAR band\n", center_channel); 773 sar_band = RTW_SAR_BAND_0; 774 break; 775 } 776 777 hal->current_primary_channel_index = primary_channel_idx; 778 hal->current_band_width = bandwidth; 779 hal->primary_channel = primary_channel; 780 hal->current_channel = center_channel; 781 hal->current_band_type = band; 782 hal->sar_band = sar_band; 783 } 784 785 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 786 struct rtw_channel_params *chan_params) 787 { 788 struct ieee80211_channel *channel = chandef->chan; 789 enum nl80211_chan_width width = chandef->width; 790 u32 primary_freq, center_freq; 791 u8 center_chan; 792 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 793 794 center_chan = channel->hw_value; 795 primary_freq = channel->center_freq; 796 center_freq = chandef->center_freq1; 797 798 switch (width) { 799 case NL80211_CHAN_WIDTH_20_NOHT: 800 case NL80211_CHAN_WIDTH_20: 801 bandwidth = RTW_CHANNEL_WIDTH_20; 802 break; 803 case NL80211_CHAN_WIDTH_40: 804 bandwidth = RTW_CHANNEL_WIDTH_40; 805 if (primary_freq > center_freq) 806 center_chan -= 2; 807 else 808 center_chan += 2; 809 break; 810 case NL80211_CHAN_WIDTH_80: 811 bandwidth = RTW_CHANNEL_WIDTH_80; 812 if (primary_freq > center_freq) { 813 if (primary_freq - center_freq == 10) 814 center_chan -= 2; 815 else 816 center_chan -= 6; 817 } else { 818 if (center_freq - primary_freq == 10) 819 center_chan += 2; 820 else 821 center_chan += 6; 822 } 823 break; 824 default: 825 center_chan = 0; 826 break; 827 } 828 829 chan_params->center_chan = center_chan; 830 chan_params->bandwidth = bandwidth; 831 chan_params->primary_chan = channel->hw_value; 832 } 833 834 void rtw_set_channel(struct rtw_dev *rtwdev) 835 { 836 const struct rtw_chip_info *chip = rtwdev->chip; 837 struct ieee80211_hw *hw = rtwdev->hw; 838 struct rtw_hal *hal = &rtwdev->hal; 839 struct rtw_channel_params ch_param; 840 u8 center_chan, primary_chan, bandwidth, band; 841 842 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 843 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 844 return; 845 846 center_chan = ch_param.center_chan; 847 primary_chan = ch_param.primary_chan; 848 bandwidth = ch_param.bandwidth; 849 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 850 851 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); 852 853 if (rtwdev->scan_info.op_chan) 854 rtw_store_op_chan(rtwdev, true); 855 856 chip->ops->set_channel(rtwdev, center_chan, bandwidth, 857 hal->current_primary_channel_index); 858 859 if (hal->current_band_type == RTW_BAND_5G) { 860 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 861 } else { 862 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 863 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 864 else 865 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 866 } 867 868 rtw_phy_set_tx_power_level(rtwdev, center_chan); 869 870 /* if the channel isn't set for scanning, we will do RF calibration 871 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 872 * during scanning on each channel takes too long. 873 */ 874 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 875 rtwdev->need_rfk = true; 876 } 877 878 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 879 { 880 const struct rtw_chip_info *chip = rtwdev->chip; 881 882 if (rtwdev->need_rfk) { 883 rtwdev->need_rfk = false; 884 chip->ops->phy_calibration(rtwdev); 885 } 886 } 887 888 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 889 { 890 int i; 891 892 for (i = 0; i < ETH_ALEN; i++) 893 rtw_write8(rtwdev, start + i, addr[i]); 894 } 895 896 void rtw_vif_port_config(struct rtw_dev *rtwdev, 897 struct rtw_vif *rtwvif, 898 u32 config) 899 { 900 u32 addr, mask; 901 902 if (config & PORT_SET_MAC_ADDR) { 903 addr = rtwvif->conf->mac_addr.addr; 904 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 905 } 906 if (config & PORT_SET_BSSID) { 907 addr = rtwvif->conf->bssid.addr; 908 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 909 } 910 if (config & PORT_SET_NET_TYPE) { 911 addr = rtwvif->conf->net_type.addr; 912 mask = rtwvif->conf->net_type.mask; 913 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 914 } 915 if (config & PORT_SET_AID) { 916 addr = rtwvif->conf->aid.addr; 917 mask = rtwvif->conf->aid.mask; 918 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 919 } 920 if (config & PORT_SET_BCN_CTRL) { 921 addr = rtwvif->conf->bcn_ctrl.addr; 922 mask = rtwvif->conf->bcn_ctrl.mask; 923 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 924 } 925 } 926 927 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 928 { 929 u8 bw = 0; 930 931 switch (bw_cap) { 932 case EFUSE_HW_CAP_IGNORE: 933 case EFUSE_HW_CAP_SUPP_BW80: 934 bw |= BIT(RTW_CHANNEL_WIDTH_80); 935 fallthrough; 936 case EFUSE_HW_CAP_SUPP_BW40: 937 bw |= BIT(RTW_CHANNEL_WIDTH_40); 938 fallthrough; 939 default: 940 bw |= BIT(RTW_CHANNEL_WIDTH_20); 941 break; 942 } 943 944 return bw; 945 } 946 947 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 948 { 949 const struct rtw_chip_info *chip = rtwdev->chip; 950 struct rtw_hal *hal = &rtwdev->hal; 951 952 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 953 hw_ant_num >= hal->rf_path_num) 954 return; 955 956 switch (hw_ant_num) { 957 case 1: 958 hal->rf_type = RF_1T1R; 959 hal->rf_path_num = 1; 960 if (!chip->fix_rf_phy_num) 961 hal->rf_phy_num = hal->rf_path_num; 962 hal->antenna_tx = BB_PATH_A; 963 hal->antenna_rx = BB_PATH_A; 964 break; 965 default: 966 WARN(1, "invalid hw configuration from efuse\n"); 967 break; 968 } 969 } 970 971 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 972 { 973 u64 ra_mask = 0; 974 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 975 u8 vht_mcs_cap; 976 int i, nss; 977 978 /* 4SS, every two bits for MCS7/8/9 */ 979 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 980 vht_mcs_cap = mcs_map & 0x3; 981 switch (vht_mcs_cap) { 982 case 2: /* MCS9 */ 983 ra_mask |= 0x3ffULL << nss; 984 break; 985 case 1: /* MCS8 */ 986 ra_mask |= 0x1ffULL << nss; 987 break; 988 case 0: /* MCS7 */ 989 ra_mask |= 0x0ffULL << nss; 990 break; 991 default: 992 break; 993 } 994 } 995 996 return ra_mask; 997 } 998 999 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 1000 { 1001 u8 rate_id = 0; 1002 1003 switch (wireless_set) { 1004 case WIRELESS_CCK: 1005 rate_id = RTW_RATEID_B_20M; 1006 break; 1007 case WIRELESS_OFDM: 1008 rate_id = RTW_RATEID_G; 1009 break; 1010 case WIRELESS_CCK | WIRELESS_OFDM: 1011 rate_id = RTW_RATEID_BG; 1012 break; 1013 case WIRELESS_OFDM | WIRELESS_HT: 1014 if (tx_num == 1) 1015 rate_id = RTW_RATEID_GN_N1SS; 1016 else if (tx_num == 2) 1017 rate_id = RTW_RATEID_GN_N2SS; 1018 else if (tx_num == 3) 1019 rate_id = RTW_RATEID_ARFR5_N_3SS; 1020 break; 1021 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 1022 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 1023 if (tx_num == 1) 1024 rate_id = RTW_RATEID_BGN_40M_1SS; 1025 else if (tx_num == 2) 1026 rate_id = RTW_RATEID_BGN_40M_2SS; 1027 else if (tx_num == 3) 1028 rate_id = RTW_RATEID_ARFR5_N_3SS; 1029 else if (tx_num == 4) 1030 rate_id = RTW_RATEID_ARFR7_N_4SS; 1031 } else { 1032 if (tx_num == 1) 1033 rate_id = RTW_RATEID_BGN_20M_1SS; 1034 else if (tx_num == 2) 1035 rate_id = RTW_RATEID_BGN_20M_2SS; 1036 else if (tx_num == 3) 1037 rate_id = RTW_RATEID_ARFR5_N_3SS; 1038 else if (tx_num == 4) 1039 rate_id = RTW_RATEID_ARFR7_N_4SS; 1040 } 1041 break; 1042 case WIRELESS_OFDM | WIRELESS_VHT: 1043 if (tx_num == 1) 1044 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1045 else if (tx_num == 2) 1046 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1047 else if (tx_num == 3) 1048 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1049 else if (tx_num == 4) 1050 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1051 break; 1052 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1053 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1054 if (tx_num == 1) 1055 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1056 else if (tx_num == 2) 1057 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1058 else if (tx_num == 3) 1059 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1060 else if (tx_num == 4) 1061 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1062 } else { 1063 if (tx_num == 1) 1064 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1065 else if (tx_num == 2) 1066 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1067 else if (tx_num == 3) 1068 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1069 else if (tx_num == 4) 1070 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1071 } 1072 break; 1073 default: 1074 break; 1075 } 1076 1077 return rate_id; 1078 } 1079 1080 #define RA_MASK_CCK_RATES 0x0000f 1081 #define RA_MASK_OFDM_RATES 0x00ff0 1082 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1083 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1084 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1085 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1086 RA_MASK_HT_RATES_2SS | \ 1087 RA_MASK_HT_RATES_3SS) 1088 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1089 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1090 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1091 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1092 RA_MASK_VHT_RATES_2SS | \ 1093 RA_MASK_VHT_RATES_3SS) 1094 #define RA_MASK_CCK_IN_BG 0x00005 1095 #define RA_MASK_CCK_IN_HT 0x00005 1096 #define RA_MASK_CCK_IN_VHT 0x00005 1097 #define RA_MASK_OFDM_IN_VHT 0x00010 1098 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1099 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1100 1101 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1102 { 1103 u8 rssi_level = si->rssi_level; 1104 1105 if (wireless_set == WIRELESS_CCK) 1106 return 0xffffffffffffffffULL; 1107 1108 if (rssi_level == 0) 1109 return 0xffffffffffffffffULL; 1110 else if (rssi_level == 1) 1111 return 0xfffffffffffffff0ULL; 1112 else if (rssi_level == 2) 1113 return 0xffffffffffffefe0ULL; 1114 else if (rssi_level == 3) 1115 return 0xffffffffffffcfc0ULL; 1116 else if (rssi_level == 4) 1117 return 0xffffffffffff8f80ULL; 1118 else 1119 return 0xffffffffffff0f00ULL; 1120 } 1121 1122 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1123 { 1124 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1125 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1126 1127 if (ra_mask == 0) 1128 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1129 1130 return ra_mask; 1131 } 1132 1133 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1134 u64 ra_mask, bool is_vht_enable) 1135 { 1136 struct rtw_hal *hal = &rtwdev->hal; 1137 const struct cfg80211_bitrate_mask *mask = si->mask; 1138 u64 cfg_mask = GENMASK_ULL(63, 0); 1139 u8 band; 1140 1141 if (!si->use_cfg_mask) 1142 return ra_mask; 1143 1144 band = hal->current_band_type; 1145 if (band == RTW_BAND_2G) { 1146 band = NL80211_BAND_2GHZ; 1147 cfg_mask = mask->control[band].legacy; 1148 } else if (band == RTW_BAND_5G) { 1149 band = NL80211_BAND_5GHZ; 1150 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1151 RA_MASK_OFDM_RATES); 1152 } 1153 1154 if (!is_vht_enable) { 1155 if (ra_mask & RA_MASK_HT_RATES_1SS) 1156 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1157 RA_MASK_HT_RATES_1SS); 1158 if (ra_mask & RA_MASK_HT_RATES_2SS) 1159 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1160 RA_MASK_HT_RATES_2SS); 1161 } else { 1162 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1163 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1164 RA_MASK_VHT_RATES_1SS); 1165 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1166 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1167 RA_MASK_VHT_RATES_2SS); 1168 } 1169 1170 ra_mask &= cfg_mask; 1171 1172 return ra_mask; 1173 } 1174 1175 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1176 bool reset_ra_mask) 1177 { 1178 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1179 struct ieee80211_sta *sta = si->sta; 1180 struct rtw_efuse *efuse = &rtwdev->efuse; 1181 struct rtw_hal *hal = &rtwdev->hal; 1182 u8 wireless_set; 1183 u8 bw_mode; 1184 u8 rate_id; 1185 u8 rf_type = RF_1T1R; 1186 u8 stbc_en = 0; 1187 u8 ldpc_en = 0; 1188 u8 tx_num = 1; 1189 u64 ra_mask = 0; 1190 u64 ra_mask_bak = 0; 1191 bool is_vht_enable = false; 1192 bool is_support_sgi = false; 1193 1194 if (sta->deflink.vht_cap.vht_supported) { 1195 is_vht_enable = true; 1196 ra_mask |= get_vht_ra_mask(sta); 1197 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1198 stbc_en = VHT_STBC_EN; 1199 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1200 ldpc_en = VHT_LDPC_EN; 1201 } else if (sta->deflink.ht_cap.ht_supported) { 1202 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1203 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1204 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1205 stbc_en = HT_STBC_EN; 1206 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1207 ldpc_en = HT_LDPC_EN; 1208 } 1209 1210 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1211 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1212 1213 if (hal->current_band_type == RTW_BAND_5G) { 1214 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1215 ra_mask_bak = ra_mask; 1216 if (sta->deflink.vht_cap.vht_supported) { 1217 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1218 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1219 } else if (sta->deflink.ht_cap.ht_supported) { 1220 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1221 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1222 } else { 1223 wireless_set = WIRELESS_OFDM; 1224 } 1225 dm_info->rrsr_val_init = RRSR_INIT_5G; 1226 } else if (hal->current_band_type == RTW_BAND_2G) { 1227 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1228 ra_mask_bak = ra_mask; 1229 if (sta->deflink.vht_cap.vht_supported) { 1230 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1231 RA_MASK_OFDM_IN_VHT; 1232 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1233 WIRELESS_HT | WIRELESS_VHT; 1234 } else if (sta->deflink.ht_cap.ht_supported) { 1235 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1236 RA_MASK_OFDM_IN_HT_2G; 1237 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1238 WIRELESS_HT; 1239 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1240 wireless_set = WIRELESS_CCK; 1241 } else { 1242 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1243 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1244 } 1245 dm_info->rrsr_val_init = RRSR_INIT_2G; 1246 } else { 1247 rtw_err(rtwdev, "Unknown band type\n"); 1248 ra_mask_bak = ra_mask; 1249 wireless_set = 0; 1250 } 1251 1252 switch (sta->deflink.bandwidth) { 1253 case IEEE80211_STA_RX_BW_80: 1254 bw_mode = RTW_CHANNEL_WIDTH_80; 1255 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1256 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1257 break; 1258 case IEEE80211_STA_RX_BW_40: 1259 bw_mode = RTW_CHANNEL_WIDTH_40; 1260 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1261 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1262 break; 1263 default: 1264 bw_mode = RTW_CHANNEL_WIDTH_20; 1265 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1266 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1267 break; 1268 } 1269 1270 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1271 tx_num = 2; 1272 rf_type = RF_2T2R; 1273 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1274 tx_num = 2; 1275 rf_type = RF_2T2R; 1276 } 1277 1278 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1279 1280 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1281 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1282 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1283 1284 si->bw_mode = bw_mode; 1285 si->stbc_en = stbc_en; 1286 si->ldpc_en = ldpc_en; 1287 si->rf_type = rf_type; 1288 si->wireless_set = wireless_set; 1289 si->sgi_enable = is_support_sgi; 1290 si->vht_enable = is_vht_enable; 1291 si->ra_mask = ra_mask; 1292 si->rate_id = rate_id; 1293 1294 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1295 } 1296 1297 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1298 { 1299 const struct rtw_chip_info *chip = rtwdev->chip; 1300 struct rtw_fw_state *fw; 1301 1302 fw = &rtwdev->fw; 1303 wait_for_completion(&fw->completion); 1304 if (!fw->firmware) 1305 return -EINVAL; 1306 1307 if (chip->wow_fw_name) { 1308 fw = &rtwdev->wow_fw; 1309 wait_for_completion(&fw->completion); 1310 if (!fw->firmware) 1311 return -EINVAL; 1312 } 1313 1314 return 0; 1315 } 1316 1317 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1318 struct rtw_fw_state *fw) 1319 { 1320 const struct rtw_chip_info *chip = rtwdev->chip; 1321 1322 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1323 !fw->feature) 1324 return LPS_DEEP_MODE_NONE; 1325 1326 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1327 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1328 return LPS_DEEP_MODE_PG; 1329 1330 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1331 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1332 return LPS_DEEP_MODE_LCLK; 1333 1334 return LPS_DEEP_MODE_NONE; 1335 } 1336 1337 static int rtw_power_on(struct rtw_dev *rtwdev) 1338 { 1339 const struct rtw_chip_info *chip = rtwdev->chip; 1340 struct rtw_fw_state *fw = &rtwdev->fw; 1341 bool wifi_only; 1342 int ret; 1343 1344 ret = rtw_hci_setup(rtwdev); 1345 if (ret) { 1346 rtw_err(rtwdev, "failed to setup hci\n"); 1347 goto err; 1348 } 1349 1350 /* power on MAC before firmware downloaded */ 1351 ret = rtw_mac_power_on(rtwdev); 1352 if (ret) { 1353 rtw_err(rtwdev, "failed to power on mac\n"); 1354 goto err; 1355 } 1356 1357 ret = rtw_wait_firmware_completion(rtwdev); 1358 if (ret) { 1359 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1360 goto err_off; 1361 } 1362 1363 ret = rtw_download_firmware(rtwdev, fw); 1364 if (ret) { 1365 rtw_err(rtwdev, "failed to download firmware\n"); 1366 goto err_off; 1367 } 1368 1369 /* config mac after firmware downloaded */ 1370 ret = rtw_mac_init(rtwdev); 1371 if (ret) { 1372 rtw_err(rtwdev, "failed to configure mac\n"); 1373 goto err_off; 1374 } 1375 1376 chip->ops->phy_set_param(rtwdev); 1377 1378 ret = rtw_hci_start(rtwdev); 1379 if (ret) { 1380 rtw_err(rtwdev, "failed to start hci\n"); 1381 goto err_off; 1382 } 1383 1384 /* send H2C after HCI has started */ 1385 rtw_fw_send_general_info(rtwdev); 1386 rtw_fw_send_phydm_info(rtwdev); 1387 1388 wifi_only = !rtwdev->efuse.btcoex; 1389 rtw_coex_power_on_setting(rtwdev); 1390 rtw_coex_init_hw_config(rtwdev, wifi_only); 1391 1392 return 0; 1393 1394 err_off: 1395 rtw_mac_power_off(rtwdev); 1396 1397 err: 1398 return ret; 1399 } 1400 1401 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1402 { 1403 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1404 return; 1405 1406 if (start) { 1407 rtw_fw_scan_notify(rtwdev, true); 1408 } else { 1409 reinit_completion(&rtwdev->fw_scan_density); 1410 rtw_fw_scan_notify(rtwdev, false); 1411 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1412 SCAN_NOTIFY_TIMEOUT)) 1413 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1414 } 1415 } 1416 1417 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1418 const u8 *mac_addr, bool hw_scan) 1419 { 1420 u32 config = 0; 1421 int ret = 0; 1422 1423 rtw_leave_lps(rtwdev); 1424 1425 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1426 ret = rtw_leave_ips(rtwdev); 1427 if (ret) { 1428 rtw_err(rtwdev, "failed to leave idle state\n"); 1429 return; 1430 } 1431 } 1432 1433 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1434 config |= PORT_SET_MAC_ADDR; 1435 rtw_vif_port_config(rtwdev, rtwvif, config); 1436 1437 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1438 rtw_core_fw_scan_notify(rtwdev, true); 1439 1440 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1441 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1442 } 1443 1444 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1445 bool hw_scan) 1446 { 1447 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1448 u32 config = 0; 1449 1450 if (!rtwvif) 1451 return; 1452 1453 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1454 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1455 1456 rtw_core_fw_scan_notify(rtwdev, false); 1457 1458 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1459 config |= PORT_SET_MAC_ADDR; 1460 rtw_vif_port_config(rtwdev, rtwvif, config); 1461 1462 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1463 1464 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1465 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1466 } 1467 1468 int rtw_core_start(struct rtw_dev *rtwdev) 1469 { 1470 int ret; 1471 1472 ret = rtw_power_on(rtwdev); 1473 if (ret) 1474 return ret; 1475 1476 rtw_sec_enable_sec_engine(rtwdev); 1477 1478 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1479 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1480 1481 /* rcr reset after powered on */ 1482 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1483 1484 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1485 RTW_WATCH_DOG_DELAY_TIME); 1486 1487 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1488 1489 return 0; 1490 } 1491 1492 static void rtw_power_off(struct rtw_dev *rtwdev) 1493 { 1494 rtw_hci_stop(rtwdev); 1495 rtw_coex_power_off_setting(rtwdev); 1496 rtw_mac_power_off(rtwdev); 1497 } 1498 1499 void rtw_core_stop(struct rtw_dev *rtwdev) 1500 { 1501 struct rtw_coex *coex = &rtwdev->coex; 1502 1503 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1504 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1505 1506 mutex_unlock(&rtwdev->mutex); 1507 1508 cancel_work_sync(&rtwdev->c2h_work); 1509 cancel_work_sync(&rtwdev->update_beacon_work); 1510 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1511 cancel_delayed_work_sync(&coex->bt_relink_work); 1512 cancel_delayed_work_sync(&coex->bt_reenable_work); 1513 cancel_delayed_work_sync(&coex->defreeze_work); 1514 cancel_delayed_work_sync(&coex->wl_remain_work); 1515 cancel_delayed_work_sync(&coex->bt_remain_work); 1516 cancel_delayed_work_sync(&coex->wl_connecting_work); 1517 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1518 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1519 1520 mutex_lock(&rtwdev->mutex); 1521 1522 rtw_power_off(rtwdev); 1523 } 1524 1525 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1526 struct ieee80211_sta_ht_cap *ht_cap) 1527 { 1528 const struct rtw_chip_info *chip = rtwdev->chip; 1529 struct rtw_efuse *efuse = &rtwdev->efuse; 1530 1531 ht_cap->ht_supported = true; 1532 ht_cap->cap = 0; 1533 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1534 IEEE80211_HT_CAP_MAX_AMSDU | 1535 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1536 1537 if (rtw_chip_has_rx_ldpc(rtwdev)) 1538 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1539 if (rtw_chip_has_tx_stbc(rtwdev)) 1540 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1541 1542 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1543 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1544 IEEE80211_HT_CAP_DSSSCCK40 | 1545 IEEE80211_HT_CAP_SGI_40; 1546 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1547 ht_cap->ampdu_density = chip->ampdu_density; 1548 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1549 if (efuse->hw_cap.nss > 1) { 1550 ht_cap->mcs.rx_mask[0] = 0xFF; 1551 ht_cap->mcs.rx_mask[1] = 0xFF; 1552 ht_cap->mcs.rx_mask[4] = 0x01; 1553 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1554 } else { 1555 ht_cap->mcs.rx_mask[0] = 0xFF; 1556 ht_cap->mcs.rx_mask[1] = 0x00; 1557 ht_cap->mcs.rx_mask[4] = 0x01; 1558 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1559 } 1560 } 1561 1562 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1563 struct ieee80211_sta_vht_cap *vht_cap) 1564 { 1565 struct rtw_efuse *efuse = &rtwdev->efuse; 1566 u16 mcs_map; 1567 __le16 highest; 1568 1569 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1570 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1571 return; 1572 1573 vht_cap->vht_supported = true; 1574 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1575 IEEE80211_VHT_CAP_SHORT_GI_80 | 1576 IEEE80211_VHT_CAP_RXSTBC_1 | 1577 IEEE80211_VHT_CAP_HTC_VHT | 1578 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1579 0; 1580 if (rtwdev->hal.rf_path_num > 1) 1581 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1582 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1583 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1584 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1585 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1586 1587 if (rtw_chip_has_rx_ldpc(rtwdev)) 1588 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1589 1590 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1591 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1592 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1593 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1594 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1595 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1596 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1597 if (efuse->hw_cap.nss > 1) { 1598 highest = cpu_to_le16(780); 1599 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1600 } else { 1601 highest = cpu_to_le16(390); 1602 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1603 } 1604 1605 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1606 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1607 vht_cap->vht_mcs.rx_highest = highest; 1608 vht_cap->vht_mcs.tx_highest = highest; 1609 } 1610 1611 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) 1612 { 1613 u16 len; 1614 1615 len = rtwdev->chip->max_scan_ie_len; 1616 1617 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && 1618 rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 1619 len = IEEE80211_MAX_DATA_LEN; 1620 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) 1621 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; 1622 1623 return len; 1624 } 1625 1626 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1627 const struct rtw_chip_info *chip) 1628 { 1629 struct rtw_dev *rtwdev = hw->priv; 1630 struct ieee80211_supported_band *sband; 1631 1632 if (chip->band & RTW_BAND_2G) { 1633 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1634 if (!sband) 1635 goto err_out; 1636 if (chip->ht_supported) 1637 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1638 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1639 } 1640 1641 if (chip->band & RTW_BAND_5G) { 1642 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1643 if (!sband) 1644 goto err_out; 1645 if (chip->ht_supported) 1646 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1647 if (chip->vht_supported) 1648 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1649 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1650 } 1651 1652 return; 1653 1654 err_out: 1655 rtw_err(rtwdev, "failed to set supported band\n"); 1656 } 1657 1658 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1659 const struct rtw_chip_info *chip) 1660 { 1661 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1662 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1663 } 1664 1665 static void rtw_vif_smps_iter(void *data, u8 *mac, 1666 struct ieee80211_vif *vif) 1667 { 1668 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1669 1670 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1671 return; 1672 1673 if (rtwdev->hal.txrx_1ss) 1674 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); 1675 else 1676 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); 1677 } 1678 1679 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1680 { 1681 const struct rtw_chip_info *chip = rtwdev->chip; 1682 struct rtw_hal *hal = &rtwdev->hal; 1683 1684 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1685 return; 1686 1687 rtwdev->hal.txrx_1ss = txrx_1ss; 1688 if (txrx_1ss) 1689 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1690 else 1691 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1692 hal->antenna_rx, false); 1693 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1694 } 1695 1696 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1697 struct rtw_fw_state *fw) 1698 { 1699 u32 feature; 1700 const struct rtw_fw_hdr *fw_hdr = 1701 (const struct rtw_fw_hdr *)fw->firmware->data; 1702 1703 feature = le32_to_cpu(fw_hdr->feature); 1704 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1705 1706 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && 1707 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) 1708 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; 1709 } 1710 1711 static void __update_firmware_info(struct rtw_dev *rtwdev, 1712 struct rtw_fw_state *fw) 1713 { 1714 const struct rtw_fw_hdr *fw_hdr = 1715 (const struct rtw_fw_hdr *)fw->firmware->data; 1716 1717 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1718 fw->version = le16_to_cpu(fw_hdr->version); 1719 fw->sub_version = fw_hdr->subversion; 1720 fw->sub_index = fw_hdr->subindex; 1721 1722 __update_firmware_feature(rtwdev, fw); 1723 } 1724 1725 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1726 struct rtw_fw_state *fw) 1727 { 1728 struct rtw_fw_hdr_legacy *legacy = 1729 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1730 1731 fw->h2c_version = 0; 1732 fw->version = le16_to_cpu(legacy->version); 1733 fw->sub_version = legacy->subversion1; 1734 fw->sub_index = legacy->subversion2; 1735 } 1736 1737 static void update_firmware_info(struct rtw_dev *rtwdev, 1738 struct rtw_fw_state *fw) 1739 { 1740 if (rtw_chip_wcpu_11n(rtwdev)) 1741 __update_firmware_info_legacy(rtwdev, fw); 1742 else 1743 __update_firmware_info(rtwdev, fw); 1744 } 1745 1746 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1747 { 1748 struct rtw_fw_state *fw = context; 1749 struct rtw_dev *rtwdev = fw->rtwdev; 1750 1751 if (!firmware || !firmware->data) { 1752 rtw_err(rtwdev, "failed to request firmware\n"); 1753 complete_all(&fw->completion); 1754 return; 1755 } 1756 1757 fw->firmware = firmware; 1758 update_firmware_info(rtwdev, fw); 1759 complete_all(&fw->completion); 1760 1761 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", 1762 fw->type == RTW_WOWLAN_FW ? "WOW " : "", 1763 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1764 } 1765 1766 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1767 { 1768 const char *fw_name; 1769 struct rtw_fw_state *fw; 1770 int ret; 1771 1772 switch (type) { 1773 case RTW_WOWLAN_FW: 1774 fw = &rtwdev->wow_fw; 1775 fw_name = rtwdev->chip->wow_fw_name; 1776 break; 1777 1778 case RTW_NORMAL_FW: 1779 fw = &rtwdev->fw; 1780 fw_name = rtwdev->chip->fw_name; 1781 break; 1782 1783 default: 1784 rtw_warn(rtwdev, "unsupported firmware type\n"); 1785 return -ENOENT; 1786 } 1787 1788 fw->type = type; 1789 fw->rtwdev = rtwdev; 1790 init_completion(&fw->completion); 1791 1792 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1793 GFP_KERNEL, fw, rtw_load_firmware_cb); 1794 if (ret) { 1795 rtw_err(rtwdev, "failed to async firmware request\n"); 1796 return ret; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1803 { 1804 const struct rtw_chip_info *chip = rtwdev->chip; 1805 struct rtw_hal *hal = &rtwdev->hal; 1806 struct rtw_efuse *efuse = &rtwdev->efuse; 1807 1808 switch (rtw_hci_type(rtwdev)) { 1809 case RTW_HCI_TYPE_PCIE: 1810 rtwdev->hci.rpwm_addr = 0x03d9; 1811 rtwdev->hci.cpwm_addr = 0x03da; 1812 break; 1813 case RTW_HCI_TYPE_SDIO: 1814 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1; 1815 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2; 1816 break; 1817 case RTW_HCI_TYPE_USB: 1818 rtwdev->hci.rpwm_addr = 0xfe58; 1819 rtwdev->hci.cpwm_addr = 0xfe57; 1820 break; 1821 default: 1822 rtw_err(rtwdev, "unsupported hci type\n"); 1823 return -EINVAL; 1824 } 1825 1826 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1827 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1828 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1829 if (hal->chip_version & BIT_RF_TYPE_ID) { 1830 hal->rf_type = RF_2T2R; 1831 hal->rf_path_num = 2; 1832 hal->antenna_tx = BB_PATH_AB; 1833 hal->antenna_rx = BB_PATH_AB; 1834 } else { 1835 hal->rf_type = RF_1T1R; 1836 hal->rf_path_num = 1; 1837 hal->antenna_tx = BB_PATH_A; 1838 hal->antenna_rx = BB_PATH_A; 1839 } 1840 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1841 hal->rf_path_num; 1842 1843 efuse->physical_size = chip->phy_efuse_size; 1844 efuse->logical_size = chip->log_efuse_size; 1845 efuse->protect_size = chip->ptct_efuse_size; 1846 1847 /* default use ack */ 1848 rtwdev->hal.rcr |= BIT_VHT_DACK; 1849 1850 hal->bfee_sts_cap = 3; 1851 1852 return 0; 1853 } 1854 1855 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1856 { 1857 struct rtw_fw_state *fw = &rtwdev->fw; 1858 int ret; 1859 1860 ret = rtw_hci_setup(rtwdev); 1861 if (ret) { 1862 rtw_err(rtwdev, "failed to setup hci\n"); 1863 goto err; 1864 } 1865 1866 ret = rtw_mac_power_on(rtwdev); 1867 if (ret) { 1868 rtw_err(rtwdev, "failed to power on mac\n"); 1869 goto err; 1870 } 1871 1872 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1873 1874 wait_for_completion(&fw->completion); 1875 if (!fw->firmware) { 1876 ret = -EINVAL; 1877 rtw_err(rtwdev, "failed to load firmware\n"); 1878 goto err; 1879 } 1880 1881 ret = rtw_download_firmware(rtwdev, fw); 1882 if (ret) { 1883 rtw_err(rtwdev, "failed to download firmware\n"); 1884 goto err_off; 1885 } 1886 1887 return 0; 1888 1889 err_off: 1890 rtw_mac_power_off(rtwdev); 1891 1892 err: 1893 return ret; 1894 } 1895 1896 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1897 { 1898 struct rtw_efuse *efuse = &rtwdev->efuse; 1899 u8 hw_feature[HW_FEATURE_LEN]; 1900 u8 id; 1901 u8 bw; 1902 int i; 1903 1904 id = rtw_read8(rtwdev, REG_C2HEVT); 1905 if (id != C2H_HW_FEATURE_REPORT) { 1906 rtw_err(rtwdev, "failed to read hw feature report\n"); 1907 return -EBUSY; 1908 } 1909 1910 for (i = 0; i < HW_FEATURE_LEN; i++) 1911 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1912 1913 rtw_write8(rtwdev, REG_C2HEVT, 0); 1914 1915 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1916 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1917 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1918 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1919 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1920 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1921 1922 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1923 1924 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1925 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1926 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1927 1928 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1929 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1930 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1931 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1932 1933 return 0; 1934 } 1935 1936 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1937 { 1938 rtw_hci_stop(rtwdev); 1939 rtw_mac_power_off(rtwdev); 1940 } 1941 1942 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1943 { 1944 struct rtw_efuse *efuse = &rtwdev->efuse; 1945 int ret; 1946 1947 mutex_lock(&rtwdev->mutex); 1948 1949 /* power on mac to read efuse */ 1950 ret = rtw_chip_efuse_enable(rtwdev); 1951 if (ret) 1952 goto out_unlock; 1953 1954 ret = rtw_parse_efuse_map(rtwdev); 1955 if (ret) 1956 goto out_disable; 1957 1958 ret = rtw_dump_hw_feature(rtwdev); 1959 if (ret) 1960 goto out_disable; 1961 1962 ret = rtw_check_supported_rfe(rtwdev); 1963 if (ret) 1964 goto out_disable; 1965 1966 if (efuse->crystal_cap == 0xff) 1967 efuse->crystal_cap = 0; 1968 if (efuse->pa_type_2g == 0xff) 1969 efuse->pa_type_2g = 0; 1970 if (efuse->pa_type_5g == 0xff) 1971 efuse->pa_type_5g = 0; 1972 if (efuse->lna_type_2g == 0xff) 1973 efuse->lna_type_2g = 0; 1974 if (efuse->lna_type_5g == 0xff) 1975 efuse->lna_type_5g = 0; 1976 if (efuse->channel_plan == 0xff) 1977 efuse->channel_plan = 0x7f; 1978 if (efuse->rf_board_option == 0xff) 1979 efuse->rf_board_option = 0; 1980 if (efuse->bt_setting & BIT(0)) 1981 efuse->share_ant = true; 1982 if (efuse->regd == 0xff) 1983 efuse->regd = 0; 1984 if (efuse->tx_bb_swing_setting_2g == 0xff) 1985 efuse->tx_bb_swing_setting_2g = 0; 1986 if (efuse->tx_bb_swing_setting_5g == 0xff) 1987 efuse->tx_bb_swing_setting_5g = 0; 1988 1989 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1990 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1991 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1992 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1993 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1994 1995 out_disable: 1996 rtw_chip_efuse_disable(rtwdev); 1997 1998 out_unlock: 1999 mutex_unlock(&rtwdev->mutex); 2000 return ret; 2001 } 2002 2003 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 2004 { 2005 struct rtw_hal *hal = &rtwdev->hal; 2006 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 2007 2008 if (!rfe_def) 2009 return -ENODEV; 2010 2011 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type); 2012 2013 rtw_phy_init_tx_power(rtwdev); 2014 if (rfe_def->agc_btg_tbl) 2015 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 2016 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 2017 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 2018 rtw_phy_tx_power_by_rate_config(hal); 2019 rtw_phy_tx_power_limit_config(hal); 2020 2021 return 0; 2022 } 2023 2024 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 2025 { 2026 int ret; 2027 2028 ret = rtw_chip_parameter_setup(rtwdev); 2029 if (ret) { 2030 rtw_err(rtwdev, "failed to setup chip parameters\n"); 2031 goto err_out; 2032 } 2033 2034 ret = rtw_chip_efuse_info_setup(rtwdev); 2035 if (ret) { 2036 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 2037 goto err_out; 2038 } 2039 2040 ret = rtw_chip_board_info_setup(rtwdev); 2041 if (ret) { 2042 rtw_err(rtwdev, "failed to setup chip board info\n"); 2043 goto err_out; 2044 } 2045 2046 return 0; 2047 2048 err_out: 2049 return ret; 2050 } 2051 EXPORT_SYMBOL(rtw_chip_info_setup); 2052 2053 static void rtw_stats_init(struct rtw_dev *rtwdev) 2054 { 2055 struct rtw_traffic_stats *stats = &rtwdev->stats; 2056 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2057 int i; 2058 2059 ewma_tp_init(&stats->tx_ewma_tp); 2060 ewma_tp_init(&stats->rx_ewma_tp); 2061 2062 for (i = 0; i < RTW_EVM_NUM; i++) 2063 ewma_evm_init(&dm_info->ewma_evm[i]); 2064 for (i = 0; i < RTW_SNR_NUM; i++) 2065 ewma_snr_init(&dm_info->ewma_snr[i]); 2066 } 2067 2068 int rtw_core_init(struct rtw_dev *rtwdev) 2069 { 2070 const struct rtw_chip_info *chip = rtwdev->chip; 2071 struct rtw_coex *coex = &rtwdev->coex; 2072 int ret; 2073 2074 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2075 INIT_LIST_HEAD(&rtwdev->txqs); 2076 2077 timer_setup(&rtwdev->tx_report.purge_timer, 2078 rtw_tx_report_purge_timer, 0); 2079 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2080 if (!rtwdev->tx_wq) { 2081 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); 2082 return -ENOMEM; 2083 } 2084 2085 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2086 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2087 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2088 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2089 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2090 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2091 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2092 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2093 rtw_coex_bt_multi_link_remain_work); 2094 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2095 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2096 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2097 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2098 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2099 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2100 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2101 skb_queue_head_init(&rtwdev->c2h_queue); 2102 skb_queue_head_init(&rtwdev->coex.queue); 2103 skb_queue_head_init(&rtwdev->tx_report.queue); 2104 2105 spin_lock_init(&rtwdev->txq_lock); 2106 spin_lock_init(&rtwdev->tx_report.q_lock); 2107 2108 mutex_init(&rtwdev->mutex); 2109 mutex_init(&rtwdev->hal.tx_power_mutex); 2110 2111 init_waitqueue_head(&rtwdev->coex.wait); 2112 init_completion(&rtwdev->lps_leave_check); 2113 init_completion(&rtwdev->fw_scan_density); 2114 2115 rtwdev->sec.total_cam_num = 32; 2116 rtwdev->hal.current_channel = 1; 2117 rtwdev->dm_info.fix_rate = U8_MAX; 2118 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2119 2120 rtw_stats_init(rtwdev); 2121 2122 /* default rx filter setting */ 2123 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2124 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2125 BIT_AB | BIT_AM | BIT_APM; 2126 2127 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2128 if (ret) { 2129 rtw_warn(rtwdev, "no firmware loaded\n"); 2130 goto out; 2131 } 2132 2133 if (chip->wow_fw_name) { 2134 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2135 if (ret) { 2136 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2137 wait_for_completion(&rtwdev->fw.completion); 2138 if (rtwdev->fw.firmware) 2139 release_firmware(rtwdev->fw.firmware); 2140 goto out; 2141 } 2142 } 2143 2144 return 0; 2145 2146 out: 2147 destroy_workqueue(rtwdev->tx_wq); 2148 return ret; 2149 } 2150 EXPORT_SYMBOL(rtw_core_init); 2151 2152 void rtw_core_deinit(struct rtw_dev *rtwdev) 2153 { 2154 struct rtw_fw_state *fw = &rtwdev->fw; 2155 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2156 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2157 unsigned long flags; 2158 2159 rtw_wait_firmware_completion(rtwdev); 2160 2161 if (fw->firmware) 2162 release_firmware(fw->firmware); 2163 2164 if (wow_fw->firmware) 2165 release_firmware(wow_fw->firmware); 2166 2167 destroy_workqueue(rtwdev->tx_wq); 2168 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2169 skb_queue_purge(&rtwdev->tx_report.queue); 2170 skb_queue_purge(&rtwdev->coex.queue); 2171 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2172 2173 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2174 build_list) { 2175 list_del(&rsvd_pkt->build_list); 2176 kfree(rsvd_pkt); 2177 } 2178 2179 mutex_destroy(&rtwdev->mutex); 2180 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2181 } 2182 EXPORT_SYMBOL(rtw_core_deinit); 2183 2184 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2185 { 2186 struct rtw_hal *hal = &rtwdev->hal; 2187 int max_tx_headroom = 0; 2188 int ret; 2189 2190 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2191 2192 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) 2193 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN; 2194 2195 hw->extra_tx_headroom = max_tx_headroom; 2196 hw->queues = IEEE80211_NUM_ACS; 2197 hw->txq_data_size = sizeof(struct rtw_txq); 2198 hw->sta_data_size = sizeof(struct rtw_sta_info); 2199 hw->vif_data_size = sizeof(struct rtw_vif); 2200 2201 ieee80211_hw_set(hw, SIGNAL_DBM); 2202 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2203 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2204 ieee80211_hw_set(hw, MFP_CAPABLE); 2205 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2206 ieee80211_hw_set(hw, SUPPORTS_PS); 2207 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2208 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2209 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2210 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2211 ieee80211_hw_set(hw, TX_AMSDU); 2212 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2213 2214 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2215 BIT(NL80211_IFTYPE_AP) | 2216 BIT(NL80211_IFTYPE_ADHOC) | 2217 BIT(NL80211_IFTYPE_MESH_POINT); 2218 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2219 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2220 2221 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2222 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2223 2224 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2225 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2226 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); 2227 2228 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) { 2229 hw->wiphy->iface_combinations = rtw_iface_combs; 2230 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs); 2231 } 2232 2233 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2234 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2235 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2236 2237 #ifdef CONFIG_PM 2238 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2239 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2240 #endif 2241 rtw_set_supported_band(hw, rtwdev->chip); 2242 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2243 2244 hw->wiphy->sar_capa = &rtw_sar_capa; 2245 2246 ret = rtw_regd_init(rtwdev); 2247 if (ret) { 2248 rtw_err(rtwdev, "failed to init regd\n"); 2249 return ret; 2250 } 2251 2252 ret = ieee80211_register_hw(hw); 2253 if (ret) { 2254 rtw_err(rtwdev, "failed to register hw\n"); 2255 return ret; 2256 } 2257 2258 ret = rtw_regd_hint(rtwdev); 2259 if (ret) { 2260 rtw_err(rtwdev, "failed to hint regd\n"); 2261 return ret; 2262 } 2263 2264 rtw_debugfs_init(rtwdev); 2265 2266 rtwdev->bf_info.bfer_mu_cnt = 0; 2267 rtwdev->bf_info.bfer_su_cnt = 0; 2268 2269 return 0; 2270 } 2271 EXPORT_SYMBOL(rtw_register_hw); 2272 2273 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2274 { 2275 const struct rtw_chip_info *chip = rtwdev->chip; 2276 2277 ieee80211_unregister_hw(hw); 2278 rtw_unset_supported_band(hw, chip); 2279 } 2280 EXPORT_SYMBOL(rtw_unregister_hw); 2281 2282 static 2283 void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2284 const struct rtw_hw_reg *reg2, u8 nbytes) 2285 { 2286 u8 i; 2287 2288 for (i = 0; i < nbytes; i++) { 2289 u8 v1 = rtw_read8(rtwdev, reg1->addr + i); 2290 u8 v2 = rtw_read8(rtwdev, reg2->addr + i); 2291 2292 rtw_write8(rtwdev, reg1->addr + i, v2); 2293 rtw_write8(rtwdev, reg2->addr + i, v1); 2294 } 2295 } 2296 2297 static 2298 void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1, 2299 const struct rtw_hw_reg *reg2) 2300 { 2301 u32 v1, v2; 2302 2303 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask); 2304 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask); 2305 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1); 2306 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2); 2307 } 2308 2309 struct rtw_iter_port_switch_data { 2310 struct rtw_dev *rtwdev; 2311 struct rtw_vif *rtwvif_ap; 2312 }; 2313 2314 static void rtw_port_switch_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 2315 { 2316 struct rtw_iter_port_switch_data *iter_data = data; 2317 struct rtw_dev *rtwdev = iter_data->rtwdev; 2318 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv; 2319 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap; 2320 const struct rtw_hw_reg *reg1, *reg2; 2321 2322 if (rtwvif_target->port != RTW_PORT_0) 2323 return; 2324 2325 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n", 2326 rtwvif_ap->port, rtwvif_target->port); 2327 2328 reg1 = &rtwvif_ap->conf->net_type; 2329 reg2 = &rtwvif_target->conf->net_type; 2330 rtw_swap_reg_mask(rtwdev, reg1, reg2); 2331 2332 reg1 = &rtwvif_ap->conf->mac_addr; 2333 reg2 = &rtwvif_target->conf->mac_addr; 2334 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2335 2336 reg1 = &rtwvif_ap->conf->bssid; 2337 reg2 = &rtwvif_target->conf->bssid; 2338 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN); 2339 2340 reg1 = &rtwvif_ap->conf->bcn_ctrl; 2341 reg2 = &rtwvif_target->conf->bcn_ctrl; 2342 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1); 2343 2344 swap(rtwvif_target->port, rtwvif_ap->port); 2345 swap(rtwvif_target->conf, rtwvif_ap->conf); 2346 } 2347 2348 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 2349 { 2350 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2351 struct rtw_iter_port_switch_data iter_data; 2352 2353 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0) 2354 return; 2355 2356 iter_data.rtwdev = rtwdev; 2357 iter_data.rtwvif_ap = rtwvif; 2358 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data); 2359 } 2360 2361 static void rtw_check_sta_active_iter(void *data, u8 *mac, 2362 struct ieee80211_vif *vif) 2363 { 2364 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 2365 bool *active = data; 2366 2367 if (*active) 2368 return; 2369 2370 if (vif->type != NL80211_IFTYPE_STATION) 2371 return; 2372 2373 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid)) 2374 *active = true; 2375 } 2376 2377 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev) 2378 { 2379 bool sta_active = false; 2380 2381 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active); 2382 2383 return rtwdev->ap_active || sta_active; 2384 } 2385 2386 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable) 2387 { 2388 if (!rtwdev->ap_active) 2389 return; 2390 2391 if (enable) 2392 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2393 else 2394 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2395 } 2396 2397 MODULE_AUTHOR("Realtek Corporation"); 2398 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2399 MODULE_LICENSE("Dual BSD/GPL"); 2400