1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/devcoredump.h> 6 7 #include "main.h" 8 #include "regd.h" 9 #include "fw.h" 10 #include "ps.h" 11 #include "sec.h" 12 #include "mac.h" 13 #include "coex.h" 14 #include "phy.h" 15 #include "reg.h" 16 #include "efuse.h" 17 #include "tx.h" 18 #include "debug.h" 19 #include "bf.h" 20 #include "sar.h" 21 22 bool rtw_disable_lps_deep_mode; 23 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 24 bool rtw_bf_support = true; 25 unsigned int rtw_debug_mask; 26 EXPORT_SYMBOL(rtw_debug_mask); 27 /* EDCCA is enabled during normal behavior. For debugging purpose in 28 * a noisy environment, it can be disabled via edcca debugfs. Because 29 * all rtw88 devices will probably be affected if environment is noisy, 30 * rtw_edcca_enabled is just declared by driver instead of by device. 31 * So, turning it off will take effect for all rtw88 devices before 32 * there is a tough reason to maintain rtw_edcca_enabled by device. 33 */ 34 bool rtw_edcca_enabled = true; 35 36 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 37 module_param_named(support_bf, rtw_bf_support, bool, 0644); 38 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 39 40 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 41 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 42 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 43 44 static struct ieee80211_channel rtw_channeltable_2g[] = { 45 {.center_freq = 2412, .hw_value = 1,}, 46 {.center_freq = 2417, .hw_value = 2,}, 47 {.center_freq = 2422, .hw_value = 3,}, 48 {.center_freq = 2427, .hw_value = 4,}, 49 {.center_freq = 2432, .hw_value = 5,}, 50 {.center_freq = 2437, .hw_value = 6,}, 51 {.center_freq = 2442, .hw_value = 7,}, 52 {.center_freq = 2447, .hw_value = 8,}, 53 {.center_freq = 2452, .hw_value = 9,}, 54 {.center_freq = 2457, .hw_value = 10,}, 55 {.center_freq = 2462, .hw_value = 11,}, 56 {.center_freq = 2467, .hw_value = 12,}, 57 {.center_freq = 2472, .hw_value = 13,}, 58 {.center_freq = 2484, .hw_value = 14,}, 59 }; 60 61 static struct ieee80211_channel rtw_channeltable_5g[] = { 62 {.center_freq = 5180, .hw_value = 36,}, 63 {.center_freq = 5200, .hw_value = 40,}, 64 {.center_freq = 5220, .hw_value = 44,}, 65 {.center_freq = 5240, .hw_value = 48,}, 66 {.center_freq = 5260, .hw_value = 52,}, 67 {.center_freq = 5280, .hw_value = 56,}, 68 {.center_freq = 5300, .hw_value = 60,}, 69 {.center_freq = 5320, .hw_value = 64,}, 70 {.center_freq = 5500, .hw_value = 100,}, 71 {.center_freq = 5520, .hw_value = 104,}, 72 {.center_freq = 5540, .hw_value = 108,}, 73 {.center_freq = 5560, .hw_value = 112,}, 74 {.center_freq = 5580, .hw_value = 116,}, 75 {.center_freq = 5600, .hw_value = 120,}, 76 {.center_freq = 5620, .hw_value = 124,}, 77 {.center_freq = 5640, .hw_value = 128,}, 78 {.center_freq = 5660, .hw_value = 132,}, 79 {.center_freq = 5680, .hw_value = 136,}, 80 {.center_freq = 5700, .hw_value = 140,}, 81 {.center_freq = 5720, .hw_value = 144,}, 82 {.center_freq = 5745, .hw_value = 149,}, 83 {.center_freq = 5765, .hw_value = 153,}, 84 {.center_freq = 5785, .hw_value = 157,}, 85 {.center_freq = 5805, .hw_value = 161,}, 86 {.center_freq = 5825, .hw_value = 165, 87 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 88 }; 89 90 static struct ieee80211_rate rtw_ratetable[] = { 91 {.bitrate = 10, .hw_value = 0x00,}, 92 {.bitrate = 20, .hw_value = 0x01,}, 93 {.bitrate = 55, .hw_value = 0x02,}, 94 {.bitrate = 110, .hw_value = 0x03,}, 95 {.bitrate = 60, .hw_value = 0x04,}, 96 {.bitrate = 90, .hw_value = 0x05,}, 97 {.bitrate = 120, .hw_value = 0x06,}, 98 {.bitrate = 180, .hw_value = 0x07,}, 99 {.bitrate = 240, .hw_value = 0x08,}, 100 {.bitrate = 360, .hw_value = 0x09,}, 101 {.bitrate = 480, .hw_value = 0x0a,}, 102 {.bitrate = 540, .hw_value = 0x0b,}, 103 }; 104 105 u16 rtw_desc_to_bitrate(u8 desc_rate) 106 { 107 struct ieee80211_rate rate; 108 109 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 110 return 0; 111 112 rate = rtw_ratetable[desc_rate]; 113 114 return rate.bitrate; 115 } 116 117 static struct ieee80211_supported_band rtw_band_2ghz = { 118 .band = NL80211_BAND_2GHZ, 119 120 .channels = rtw_channeltable_2g, 121 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 122 123 .bitrates = rtw_ratetable, 124 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 125 126 .ht_cap = {0}, 127 .vht_cap = {0}, 128 }; 129 130 static struct ieee80211_supported_band rtw_band_5ghz = { 131 .band = NL80211_BAND_5GHZ, 132 133 .channels = rtw_channeltable_5g, 134 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 135 136 /* 5G has no CCK rates */ 137 .bitrates = rtw_ratetable + 4, 138 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 139 140 .ht_cap = {0}, 141 .vht_cap = {0}, 142 }; 143 144 struct rtw_watch_dog_iter_data { 145 struct rtw_dev *rtwdev; 146 struct rtw_vif *rtwvif; 147 }; 148 149 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 150 { 151 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 152 u8 fix_rate_enable = 0; 153 u8 new_csi_rate_idx; 154 155 if (rtwvif->bfee.role != RTW_BFEE_SU && 156 rtwvif->bfee.role != RTW_BFEE_MU) 157 return; 158 159 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 160 bf_info->cur_csi_rpt_rate, 161 fix_rate_enable, &new_csi_rate_idx); 162 163 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 164 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 165 } 166 167 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 168 struct ieee80211_vif *vif) 169 { 170 struct rtw_watch_dog_iter_data *iter_data = data; 171 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 172 173 if (vif->type == NL80211_IFTYPE_STATION) 174 if (vif->cfg.assoc) 175 iter_data->rtwvif = rtwvif; 176 177 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 178 179 rtwvif->stats.tx_unicast = 0; 180 rtwvif->stats.rx_unicast = 0; 181 rtwvif->stats.tx_cnt = 0; 182 rtwvif->stats.rx_cnt = 0; 183 } 184 185 /* process TX/RX statistics periodically for hardware, 186 * the information helps hardware to enhance performance 187 */ 188 static void rtw_watch_dog_work(struct work_struct *work) 189 { 190 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 191 watch_dog_work.work); 192 struct rtw_traffic_stats *stats = &rtwdev->stats; 193 struct rtw_watch_dog_iter_data data = {}; 194 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 195 bool ps_active; 196 197 mutex_lock(&rtwdev->mutex); 198 199 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 200 goto unlock; 201 202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 203 RTW_WATCH_DOG_DELAY_TIME); 204 205 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 206 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 207 else 208 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 209 210 rtw_coex_wl_status_check(rtwdev); 211 rtw_coex_query_bt_hid_list(rtwdev); 212 213 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 214 rtw_coex_wl_status_change_notify(rtwdev, 0); 215 216 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 217 stats->rx_cnt > RTW_LPS_THRESHOLD) 218 ps_active = true; 219 else 220 ps_active = false; 221 222 ewma_tp_add(&stats->tx_ewma_tp, 223 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 224 ewma_tp_add(&stats->rx_ewma_tp, 225 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 226 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 227 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 228 229 /* reset tx/rx statictics */ 230 stats->tx_unicast = 0; 231 stats->rx_unicast = 0; 232 stats->tx_cnt = 0; 233 stats->rx_cnt = 0; 234 235 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 236 goto unlock; 237 238 /* make sure BB/RF is working for dynamic mech */ 239 rtw_leave_lps(rtwdev); 240 241 rtw_phy_dynamic_mechanism(rtwdev); 242 243 data.rtwdev = rtwdev; 244 /* rtw_iterate_vifs internally uses an atomic iterator which is needed 245 * to avoid taking local->iflist_mtx mutex 246 */ 247 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data); 248 249 /* fw supports only one station associated to enter lps, if there are 250 * more than two stations associated to the AP, then we can not enter 251 * lps, because fw does not handle the overlapped beacon interval 252 * 253 * mac80211 should iterate vifs and determine if driver can enter 254 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 255 * get that vif and check if device is having traffic more than the 256 * threshold. 257 */ 258 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 259 !rtwdev->beacon_loss) 260 rtw_enter_lps(rtwdev, data.rtwvif->port); 261 262 rtwdev->watch_dog_cnt++; 263 264 unlock: 265 mutex_unlock(&rtwdev->mutex); 266 } 267 268 static void rtw_c2h_work(struct work_struct *work) 269 { 270 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 271 struct sk_buff *skb, *tmp; 272 273 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 274 skb_unlink(skb, &rtwdev->c2h_queue); 275 rtw_fw_c2h_cmd_handle(rtwdev, skb); 276 dev_kfree_skb_any(skb); 277 } 278 } 279 280 static void rtw_ips_work(struct work_struct *work) 281 { 282 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 283 284 mutex_lock(&rtwdev->mutex); 285 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 286 rtw_enter_ips(rtwdev); 287 mutex_unlock(&rtwdev->mutex); 288 } 289 290 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 291 { 292 unsigned long mac_id; 293 294 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 295 if (mac_id < RTW_MAX_MAC_ID_NUM) 296 set_bit(mac_id, rtwdev->mac_id_map); 297 298 return mac_id; 299 } 300 301 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 302 struct ieee80211_vif *vif) 303 { 304 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 305 int i; 306 307 si->mac_id = rtw_acquire_macid(rtwdev); 308 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 309 return -ENOSPC; 310 311 si->sta = sta; 312 si->vif = vif; 313 si->init_ra_lv = 1; 314 ewma_rssi_init(&si->avg_rssi); 315 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 316 rtw_txq_init(rtwdev, sta->txq[i]); 317 318 rtw_update_sta_info(rtwdev, si, true); 319 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 320 321 rtwdev->sta_cnt++; 322 rtwdev->beacon_loss = false; 323 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 324 sta->addr, si->mac_id); 325 326 return 0; 327 } 328 329 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 330 bool fw_exist) 331 { 332 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 333 int i; 334 335 rtw_release_macid(rtwdev, si->mac_id); 336 if (fw_exist) 337 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 338 339 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 340 rtw_txq_cleanup(rtwdev, sta->txq[i]); 341 342 kfree(si->mask); 343 344 rtwdev->sta_cnt--; 345 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 346 sta->addr, si->mac_id); 347 } 348 349 struct rtw_fwcd_hdr { 350 u32 item; 351 u32 size; 352 u32 padding1; 353 u32 padding2; 354 } __packed; 355 356 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 357 { 358 const struct rtw_chip_info *chip = rtwdev->chip; 359 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 360 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 361 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 362 u8 i; 363 364 if (segs) { 365 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 366 367 for (i = 0; i < segs->num; i++) 368 prep_size += segs->segs[i]; 369 } 370 371 desc->data = vmalloc(prep_size); 372 if (!desc->data) 373 return -ENOMEM; 374 375 desc->size = prep_size; 376 desc->next = desc->data; 377 378 return 0; 379 } 380 381 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 382 { 383 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 384 struct rtw_fwcd_hdr *hdr; 385 u8 *next; 386 387 if (!desc->data) { 388 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 389 return NULL; 390 } 391 392 next = desc->next + sizeof(struct rtw_fwcd_hdr); 393 if (next - desc->data + size > desc->size) { 394 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 395 return NULL; 396 } 397 398 hdr = (struct rtw_fwcd_hdr *)(desc->next); 399 hdr->item = item; 400 hdr->size = size; 401 hdr->padding1 = 0x01234567; 402 hdr->padding2 = 0x89abcdef; 403 desc->next = next + size; 404 405 return next; 406 } 407 408 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 409 { 410 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 411 412 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 413 414 /* Data will be freed after lifetime of device coredump. After calling 415 * dev_coredump, data is supposed to be handled by the device coredump 416 * framework. Note that a new dump will be discarded if a previous one 417 * hasn't been released yet. 418 */ 419 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 420 } 421 422 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 423 { 424 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 425 426 if (free_self) { 427 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 428 vfree(desc->data); 429 } 430 431 desc->data = NULL; 432 desc->next = NULL; 433 } 434 435 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 436 { 437 u32 size = rtwdev->chip->fw_rxff_size; 438 u32 *buf; 439 u8 seq; 440 441 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 442 if (!buf) 443 return -ENOMEM; 444 445 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 446 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 447 return -EINVAL; 448 } 449 450 if (GET_FW_DUMP_LEN(buf) == 0) { 451 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 452 return -EINVAL; 453 } 454 455 seq = GET_FW_DUMP_SEQ(buf); 456 if (seq > 0) { 457 rtw_dbg(rtwdev, RTW_DBG_FW, 458 "fw crash dump's seq is wrong: %d\n", seq); 459 return -EINVAL; 460 } 461 462 return 0; 463 } 464 465 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 466 u32 fwcd_item) 467 { 468 u32 rxff = rtwdev->chip->fw_rxff_size; 469 u32 dump_size, done_size = 0; 470 u8 *buf; 471 int ret; 472 473 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 474 if (!buf) 475 return -ENOMEM; 476 477 while (size) { 478 dump_size = size > rxff ? rxff : size; 479 480 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 481 dump_size); 482 if (ret) { 483 rtw_err(rtwdev, 484 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 485 ocp_src, done_size); 486 return ret; 487 } 488 489 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 490 dump_size, (u32 *)(buf + done_size)); 491 if (ret) { 492 rtw_err(rtwdev, 493 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 494 ocp_src, done_size); 495 return ret; 496 } 497 498 size -= dump_size; 499 done_size += dump_size; 500 } 501 502 return 0; 503 } 504 EXPORT_SYMBOL(rtw_dump_fw); 505 506 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 507 { 508 u8 *buf; 509 u32 i; 510 511 if (addr & 0x3) { 512 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 513 return -EINVAL; 514 } 515 516 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 517 if (!buf) 518 return -ENOMEM; 519 520 for (i = 0; i < size; i += 4) 521 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 522 523 return 0; 524 } 525 EXPORT_SYMBOL(rtw_dump_reg); 526 527 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 528 struct ieee80211_bss_conf *conf) 529 { 530 struct ieee80211_vif *vif = NULL; 531 532 if (conf) 533 vif = container_of(conf, struct ieee80211_vif, bss_conf); 534 535 if (conf && vif->cfg.assoc) { 536 rtwvif->aid = vif->cfg.aid; 537 rtwvif->net_type = RTW_NET_MGD_LINKED; 538 } else { 539 rtwvif->aid = 0; 540 rtwvif->net_type = RTW_NET_NO_LINK; 541 } 542 } 543 544 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 545 struct ieee80211_vif *vif, 546 struct ieee80211_sta *sta, 547 struct ieee80211_key_conf *key, 548 void *data) 549 { 550 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 551 struct rtw_sec_desc *sec = &rtwdev->sec; 552 553 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 554 } 555 556 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 557 { 558 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 559 560 if (rtwdev->sta_cnt == 0) { 561 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 562 return; 563 } 564 rtw_sta_remove(rtwdev, sta, false); 565 } 566 567 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 568 { 569 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 570 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 571 572 rtw_bf_disassoc(rtwdev, vif, NULL); 573 rtw_vif_assoc_changed(rtwvif, NULL); 574 rtw_txq_cleanup(rtwdev, vif->txq); 575 } 576 577 void rtw_fw_recovery(struct rtw_dev *rtwdev) 578 { 579 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 580 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 581 } 582 583 static void __fw_recovery_work(struct rtw_dev *rtwdev) 584 { 585 int ret = 0; 586 587 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 588 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 589 590 ret = rtw_fwcd_prep(rtwdev); 591 if (ret) 592 goto free; 593 ret = rtw_fw_dump_crash_log(rtwdev); 594 if (ret) 595 goto free; 596 ret = rtw_chip_dump_fw_crash(rtwdev); 597 if (ret) 598 goto free; 599 600 rtw_fwcd_dump(rtwdev); 601 free: 602 rtw_fwcd_free(rtwdev, !!ret); 603 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 604 605 WARN(1, "firmware crash, start reset and recover\n"); 606 607 rcu_read_lock(); 608 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 609 rcu_read_unlock(); 610 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 611 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 612 rtw_enter_ips(rtwdev); 613 } 614 615 static void rtw_fw_recovery_work(struct work_struct *work) 616 { 617 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 618 fw_recovery_work); 619 620 mutex_lock(&rtwdev->mutex); 621 __fw_recovery_work(rtwdev); 622 mutex_unlock(&rtwdev->mutex); 623 624 ieee80211_restart_hw(rtwdev->hw); 625 } 626 627 struct rtw_txq_ba_iter_data { 628 }; 629 630 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 631 { 632 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 633 int ret; 634 u8 tid; 635 636 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 637 while (tid != IEEE80211_NUM_TIDS) { 638 clear_bit(tid, si->tid_ba); 639 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 640 if (ret == -EINVAL) { 641 struct ieee80211_txq *txq; 642 struct rtw_txq *rtwtxq; 643 644 txq = sta->txq[tid]; 645 rtwtxq = (struct rtw_txq *)txq->drv_priv; 646 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 647 } 648 649 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 650 } 651 } 652 653 static void rtw_txq_ba_work(struct work_struct *work) 654 { 655 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 656 struct rtw_txq_ba_iter_data data; 657 658 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 659 } 660 661 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 662 { 663 if (IS_CH_2G_BAND(channel)) 664 pkt_stat->band = NL80211_BAND_2GHZ; 665 else if (IS_CH_5G_BAND(channel)) 666 pkt_stat->band = NL80211_BAND_5GHZ; 667 else 668 return; 669 670 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 671 } 672 EXPORT_SYMBOL(rtw_set_rx_freq_band); 673 674 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 675 { 676 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 677 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 678 } 679 680 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel, 681 u8 primary_channel, enum rtw_supported_band band, 682 enum rtw_bandwidth bandwidth) 683 { 684 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band); 685 struct rtw_hal *hal = &rtwdev->hal; 686 u8 *cch_by_bw = hal->cch_by_bw; 687 u32 center_freq, primary_freq; 688 enum rtw_sar_bands sar_band; 689 u8 primary_channel_idx; 690 691 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band); 692 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band); 693 694 /* assign the center channel used while 20M bw is selected */ 695 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel; 696 697 /* assign the center channel used while current bw is selected */ 698 cch_by_bw[bandwidth] = center_channel; 699 700 switch (bandwidth) { 701 case RTW_CHANNEL_WIDTH_20: 702 default: 703 primary_channel_idx = RTW_SC_DONT_CARE; 704 break; 705 case RTW_CHANNEL_WIDTH_40: 706 if (primary_freq > center_freq) 707 primary_channel_idx = RTW_SC_20_UPPER; 708 else 709 primary_channel_idx = RTW_SC_20_LOWER; 710 break; 711 case RTW_CHANNEL_WIDTH_80: 712 if (primary_freq > center_freq) { 713 if (primary_freq - center_freq == 10) 714 primary_channel_idx = RTW_SC_20_UPPER; 715 else 716 primary_channel_idx = RTW_SC_20_UPMOST; 717 718 /* assign the center channel used 719 * while 40M bw is selected 720 */ 721 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4; 722 } else { 723 if (center_freq - primary_freq == 10) 724 primary_channel_idx = RTW_SC_20_LOWER; 725 else 726 primary_channel_idx = RTW_SC_20_LOWEST; 727 728 /* assign the center channel used 729 * while 40M bw is selected 730 */ 731 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4; 732 } 733 break; 734 } 735 736 switch (center_channel) { 737 case 1 ... 14: 738 sar_band = RTW_SAR_BAND_0; 739 break; 740 case 36 ... 64: 741 sar_band = RTW_SAR_BAND_1; 742 break; 743 case 100 ... 144: 744 sar_band = RTW_SAR_BAND_3; 745 break; 746 case 149 ... 177: 747 sar_band = RTW_SAR_BAND_4; 748 break; 749 default: 750 WARN(1, "unknown ch(%u) to SAR band\n", center_channel); 751 sar_band = RTW_SAR_BAND_0; 752 break; 753 } 754 755 hal->current_primary_channel_index = primary_channel_idx; 756 hal->current_band_width = bandwidth; 757 hal->primary_channel = primary_channel; 758 hal->current_channel = center_channel; 759 hal->current_band_type = band; 760 hal->sar_band = sar_band; 761 } 762 763 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 764 struct rtw_channel_params *chan_params) 765 { 766 struct ieee80211_channel *channel = chandef->chan; 767 enum nl80211_chan_width width = chandef->width; 768 u32 primary_freq, center_freq; 769 u8 center_chan; 770 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 771 772 center_chan = channel->hw_value; 773 primary_freq = channel->center_freq; 774 center_freq = chandef->center_freq1; 775 776 switch (width) { 777 case NL80211_CHAN_WIDTH_20_NOHT: 778 case NL80211_CHAN_WIDTH_20: 779 bandwidth = RTW_CHANNEL_WIDTH_20; 780 break; 781 case NL80211_CHAN_WIDTH_40: 782 bandwidth = RTW_CHANNEL_WIDTH_40; 783 if (primary_freq > center_freq) 784 center_chan -= 2; 785 else 786 center_chan += 2; 787 break; 788 case NL80211_CHAN_WIDTH_80: 789 bandwidth = RTW_CHANNEL_WIDTH_80; 790 if (primary_freq > center_freq) { 791 if (primary_freq - center_freq == 10) 792 center_chan -= 2; 793 else 794 center_chan -= 6; 795 } else { 796 if (center_freq - primary_freq == 10) 797 center_chan += 2; 798 else 799 center_chan += 6; 800 } 801 break; 802 default: 803 center_chan = 0; 804 break; 805 } 806 807 chan_params->center_chan = center_chan; 808 chan_params->bandwidth = bandwidth; 809 chan_params->primary_chan = channel->hw_value; 810 } 811 812 void rtw_set_channel(struct rtw_dev *rtwdev) 813 { 814 const struct rtw_chip_info *chip = rtwdev->chip; 815 struct ieee80211_hw *hw = rtwdev->hw; 816 struct rtw_hal *hal = &rtwdev->hal; 817 struct rtw_channel_params ch_param; 818 u8 center_chan, primary_chan, bandwidth, band; 819 820 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 821 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 822 return; 823 824 center_chan = ch_param.center_chan; 825 primary_chan = ch_param.primary_chan; 826 bandwidth = ch_param.bandwidth; 827 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 828 829 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth); 830 831 chip->ops->set_channel(rtwdev, center_chan, bandwidth, 832 hal->current_primary_channel_index); 833 834 if (hal->current_band_type == RTW_BAND_5G) { 835 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 836 } else { 837 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 838 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 839 else 840 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 841 } 842 843 rtw_phy_set_tx_power_level(rtwdev, center_chan); 844 845 /* if the channel isn't set for scanning, we will do RF calibration 846 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 847 * during scanning on each channel takes too long. 848 */ 849 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 850 rtwdev->need_rfk = true; 851 } 852 853 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 854 { 855 const struct rtw_chip_info *chip = rtwdev->chip; 856 857 if (rtwdev->need_rfk) { 858 rtwdev->need_rfk = false; 859 chip->ops->phy_calibration(rtwdev); 860 } 861 } 862 863 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 864 { 865 int i; 866 867 for (i = 0; i < ETH_ALEN; i++) 868 rtw_write8(rtwdev, start + i, addr[i]); 869 } 870 871 void rtw_vif_port_config(struct rtw_dev *rtwdev, 872 struct rtw_vif *rtwvif, 873 u32 config) 874 { 875 u32 addr, mask; 876 877 if (config & PORT_SET_MAC_ADDR) { 878 addr = rtwvif->conf->mac_addr.addr; 879 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 880 } 881 if (config & PORT_SET_BSSID) { 882 addr = rtwvif->conf->bssid.addr; 883 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 884 } 885 if (config & PORT_SET_NET_TYPE) { 886 addr = rtwvif->conf->net_type.addr; 887 mask = rtwvif->conf->net_type.mask; 888 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 889 } 890 if (config & PORT_SET_AID) { 891 addr = rtwvif->conf->aid.addr; 892 mask = rtwvif->conf->aid.mask; 893 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 894 } 895 if (config & PORT_SET_BCN_CTRL) { 896 addr = rtwvif->conf->bcn_ctrl.addr; 897 mask = rtwvif->conf->bcn_ctrl.mask; 898 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 899 } 900 } 901 902 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 903 { 904 u8 bw = 0; 905 906 switch (bw_cap) { 907 case EFUSE_HW_CAP_IGNORE: 908 case EFUSE_HW_CAP_SUPP_BW80: 909 bw |= BIT(RTW_CHANNEL_WIDTH_80); 910 fallthrough; 911 case EFUSE_HW_CAP_SUPP_BW40: 912 bw |= BIT(RTW_CHANNEL_WIDTH_40); 913 fallthrough; 914 default: 915 bw |= BIT(RTW_CHANNEL_WIDTH_20); 916 break; 917 } 918 919 return bw; 920 } 921 922 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 923 { 924 const struct rtw_chip_info *chip = rtwdev->chip; 925 struct rtw_hal *hal = &rtwdev->hal; 926 927 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 928 hw_ant_num >= hal->rf_path_num) 929 return; 930 931 switch (hw_ant_num) { 932 case 1: 933 hal->rf_type = RF_1T1R; 934 hal->rf_path_num = 1; 935 if (!chip->fix_rf_phy_num) 936 hal->rf_phy_num = hal->rf_path_num; 937 hal->antenna_tx = BB_PATH_A; 938 hal->antenna_rx = BB_PATH_A; 939 break; 940 default: 941 WARN(1, "invalid hw configuration from efuse\n"); 942 break; 943 } 944 } 945 946 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 947 { 948 u64 ra_mask = 0; 949 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 950 u8 vht_mcs_cap; 951 int i, nss; 952 953 /* 4SS, every two bits for MCS7/8/9 */ 954 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 955 vht_mcs_cap = mcs_map & 0x3; 956 switch (vht_mcs_cap) { 957 case 2: /* MCS9 */ 958 ra_mask |= 0x3ffULL << nss; 959 break; 960 case 1: /* MCS8 */ 961 ra_mask |= 0x1ffULL << nss; 962 break; 963 case 0: /* MCS7 */ 964 ra_mask |= 0x0ffULL << nss; 965 break; 966 default: 967 break; 968 } 969 } 970 971 return ra_mask; 972 } 973 974 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 975 { 976 u8 rate_id = 0; 977 978 switch (wireless_set) { 979 case WIRELESS_CCK: 980 rate_id = RTW_RATEID_B_20M; 981 break; 982 case WIRELESS_OFDM: 983 rate_id = RTW_RATEID_G; 984 break; 985 case WIRELESS_CCK | WIRELESS_OFDM: 986 rate_id = RTW_RATEID_BG; 987 break; 988 case WIRELESS_OFDM | WIRELESS_HT: 989 if (tx_num == 1) 990 rate_id = RTW_RATEID_GN_N1SS; 991 else if (tx_num == 2) 992 rate_id = RTW_RATEID_GN_N2SS; 993 else if (tx_num == 3) 994 rate_id = RTW_RATEID_ARFR5_N_3SS; 995 break; 996 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 997 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 998 if (tx_num == 1) 999 rate_id = RTW_RATEID_BGN_40M_1SS; 1000 else if (tx_num == 2) 1001 rate_id = RTW_RATEID_BGN_40M_2SS; 1002 else if (tx_num == 3) 1003 rate_id = RTW_RATEID_ARFR5_N_3SS; 1004 else if (tx_num == 4) 1005 rate_id = RTW_RATEID_ARFR7_N_4SS; 1006 } else { 1007 if (tx_num == 1) 1008 rate_id = RTW_RATEID_BGN_20M_1SS; 1009 else if (tx_num == 2) 1010 rate_id = RTW_RATEID_BGN_20M_2SS; 1011 else if (tx_num == 3) 1012 rate_id = RTW_RATEID_ARFR5_N_3SS; 1013 else if (tx_num == 4) 1014 rate_id = RTW_RATEID_ARFR7_N_4SS; 1015 } 1016 break; 1017 case WIRELESS_OFDM | WIRELESS_VHT: 1018 if (tx_num == 1) 1019 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1020 else if (tx_num == 2) 1021 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1022 else if (tx_num == 3) 1023 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1024 else if (tx_num == 4) 1025 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1026 break; 1027 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1028 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1029 if (tx_num == 1) 1030 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1031 else if (tx_num == 2) 1032 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1033 else if (tx_num == 3) 1034 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1035 else if (tx_num == 4) 1036 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1037 } else { 1038 if (tx_num == 1) 1039 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1040 else if (tx_num == 2) 1041 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1042 else if (tx_num == 3) 1043 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1044 else if (tx_num == 4) 1045 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1046 } 1047 break; 1048 default: 1049 break; 1050 } 1051 1052 return rate_id; 1053 } 1054 1055 #define RA_MASK_CCK_RATES 0x0000f 1056 #define RA_MASK_OFDM_RATES 0x00ff0 1057 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1058 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1059 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1060 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1061 RA_MASK_HT_RATES_2SS | \ 1062 RA_MASK_HT_RATES_3SS) 1063 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1064 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1065 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1066 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1067 RA_MASK_VHT_RATES_2SS | \ 1068 RA_MASK_VHT_RATES_3SS) 1069 #define RA_MASK_CCK_IN_BG 0x00005 1070 #define RA_MASK_CCK_IN_HT 0x00005 1071 #define RA_MASK_CCK_IN_VHT 0x00005 1072 #define RA_MASK_OFDM_IN_VHT 0x00010 1073 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1074 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1075 1076 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1077 { 1078 u8 rssi_level = si->rssi_level; 1079 1080 if (wireless_set == WIRELESS_CCK) 1081 return 0xffffffffffffffffULL; 1082 1083 if (rssi_level == 0) 1084 return 0xffffffffffffffffULL; 1085 else if (rssi_level == 1) 1086 return 0xfffffffffffffff0ULL; 1087 else if (rssi_level == 2) 1088 return 0xffffffffffffefe0ULL; 1089 else if (rssi_level == 3) 1090 return 0xffffffffffffcfc0ULL; 1091 else if (rssi_level == 4) 1092 return 0xffffffffffff8f80ULL; 1093 else 1094 return 0xffffffffffff0f00ULL; 1095 } 1096 1097 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1098 { 1099 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1100 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1101 1102 if (ra_mask == 0) 1103 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1104 1105 return ra_mask; 1106 } 1107 1108 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1109 u64 ra_mask, bool is_vht_enable) 1110 { 1111 struct rtw_hal *hal = &rtwdev->hal; 1112 const struct cfg80211_bitrate_mask *mask = si->mask; 1113 u64 cfg_mask = GENMASK_ULL(63, 0); 1114 u8 band; 1115 1116 if (!si->use_cfg_mask) 1117 return ra_mask; 1118 1119 band = hal->current_band_type; 1120 if (band == RTW_BAND_2G) { 1121 band = NL80211_BAND_2GHZ; 1122 cfg_mask = mask->control[band].legacy; 1123 } else if (band == RTW_BAND_5G) { 1124 band = NL80211_BAND_5GHZ; 1125 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1126 RA_MASK_OFDM_RATES); 1127 } 1128 1129 if (!is_vht_enable) { 1130 if (ra_mask & RA_MASK_HT_RATES_1SS) 1131 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1132 RA_MASK_HT_RATES_1SS); 1133 if (ra_mask & RA_MASK_HT_RATES_2SS) 1134 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1135 RA_MASK_HT_RATES_2SS); 1136 } else { 1137 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1138 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1139 RA_MASK_VHT_RATES_1SS); 1140 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1141 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1142 RA_MASK_VHT_RATES_2SS); 1143 } 1144 1145 ra_mask &= cfg_mask; 1146 1147 return ra_mask; 1148 } 1149 1150 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1151 bool reset_ra_mask) 1152 { 1153 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1154 struct ieee80211_sta *sta = si->sta; 1155 struct rtw_efuse *efuse = &rtwdev->efuse; 1156 struct rtw_hal *hal = &rtwdev->hal; 1157 u8 wireless_set; 1158 u8 bw_mode; 1159 u8 rate_id; 1160 u8 rf_type = RF_1T1R; 1161 u8 stbc_en = 0; 1162 u8 ldpc_en = 0; 1163 u8 tx_num = 1; 1164 u64 ra_mask = 0; 1165 u64 ra_mask_bak = 0; 1166 bool is_vht_enable = false; 1167 bool is_support_sgi = false; 1168 1169 if (sta->deflink.vht_cap.vht_supported) { 1170 is_vht_enable = true; 1171 ra_mask |= get_vht_ra_mask(sta); 1172 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1173 stbc_en = VHT_STBC_EN; 1174 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1175 ldpc_en = VHT_LDPC_EN; 1176 } else if (sta->deflink.ht_cap.ht_supported) { 1177 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1178 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1179 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1180 stbc_en = HT_STBC_EN; 1181 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1182 ldpc_en = HT_LDPC_EN; 1183 } 1184 1185 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1186 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1187 1188 if (hal->current_band_type == RTW_BAND_5G) { 1189 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1190 ra_mask_bak = ra_mask; 1191 if (sta->deflink.vht_cap.vht_supported) { 1192 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1193 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1194 } else if (sta->deflink.ht_cap.ht_supported) { 1195 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1196 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1197 } else { 1198 wireless_set = WIRELESS_OFDM; 1199 } 1200 dm_info->rrsr_val_init = RRSR_INIT_5G; 1201 } else if (hal->current_band_type == RTW_BAND_2G) { 1202 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1203 ra_mask_bak = ra_mask; 1204 if (sta->deflink.vht_cap.vht_supported) { 1205 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1206 RA_MASK_OFDM_IN_VHT; 1207 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1208 WIRELESS_HT | WIRELESS_VHT; 1209 } else if (sta->deflink.ht_cap.ht_supported) { 1210 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1211 RA_MASK_OFDM_IN_HT_2G; 1212 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1213 WIRELESS_HT; 1214 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1215 wireless_set = WIRELESS_CCK; 1216 } else { 1217 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1218 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1219 } 1220 dm_info->rrsr_val_init = RRSR_INIT_2G; 1221 } else { 1222 rtw_err(rtwdev, "Unknown band type\n"); 1223 ra_mask_bak = ra_mask; 1224 wireless_set = 0; 1225 } 1226 1227 switch (sta->deflink.bandwidth) { 1228 case IEEE80211_STA_RX_BW_80: 1229 bw_mode = RTW_CHANNEL_WIDTH_80; 1230 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1231 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1232 break; 1233 case IEEE80211_STA_RX_BW_40: 1234 bw_mode = RTW_CHANNEL_WIDTH_40; 1235 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1236 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1237 break; 1238 default: 1239 bw_mode = RTW_CHANNEL_WIDTH_20; 1240 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1241 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1242 break; 1243 } 1244 1245 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1246 tx_num = 2; 1247 rf_type = RF_2T2R; 1248 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1249 tx_num = 2; 1250 rf_type = RF_2T2R; 1251 } 1252 1253 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1254 1255 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1256 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1257 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1258 1259 si->bw_mode = bw_mode; 1260 si->stbc_en = stbc_en; 1261 si->ldpc_en = ldpc_en; 1262 si->rf_type = rf_type; 1263 si->wireless_set = wireless_set; 1264 si->sgi_enable = is_support_sgi; 1265 si->vht_enable = is_vht_enable; 1266 si->ra_mask = ra_mask; 1267 si->rate_id = rate_id; 1268 1269 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1270 } 1271 1272 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1273 { 1274 const struct rtw_chip_info *chip = rtwdev->chip; 1275 struct rtw_fw_state *fw; 1276 1277 fw = &rtwdev->fw; 1278 wait_for_completion(&fw->completion); 1279 if (!fw->firmware) 1280 return -EINVAL; 1281 1282 if (chip->wow_fw_name) { 1283 fw = &rtwdev->wow_fw; 1284 wait_for_completion(&fw->completion); 1285 if (!fw->firmware) 1286 return -EINVAL; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1293 struct rtw_fw_state *fw) 1294 { 1295 const struct rtw_chip_info *chip = rtwdev->chip; 1296 1297 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1298 !fw->feature) 1299 return LPS_DEEP_MODE_NONE; 1300 1301 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1302 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1303 return LPS_DEEP_MODE_PG; 1304 1305 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1306 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1307 return LPS_DEEP_MODE_LCLK; 1308 1309 return LPS_DEEP_MODE_NONE; 1310 } 1311 1312 static int rtw_power_on(struct rtw_dev *rtwdev) 1313 { 1314 const struct rtw_chip_info *chip = rtwdev->chip; 1315 struct rtw_fw_state *fw = &rtwdev->fw; 1316 bool wifi_only; 1317 int ret; 1318 1319 ret = rtw_hci_setup(rtwdev); 1320 if (ret) { 1321 rtw_err(rtwdev, "failed to setup hci\n"); 1322 goto err; 1323 } 1324 1325 /* power on MAC before firmware downloaded */ 1326 ret = rtw_mac_power_on(rtwdev); 1327 if (ret) { 1328 rtw_err(rtwdev, "failed to power on mac\n"); 1329 goto err; 1330 } 1331 1332 ret = rtw_wait_firmware_completion(rtwdev); 1333 if (ret) { 1334 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1335 goto err_off; 1336 } 1337 1338 ret = rtw_download_firmware(rtwdev, fw); 1339 if (ret) { 1340 rtw_err(rtwdev, "failed to download firmware\n"); 1341 goto err_off; 1342 } 1343 1344 /* config mac after firmware downloaded */ 1345 ret = rtw_mac_init(rtwdev); 1346 if (ret) { 1347 rtw_err(rtwdev, "failed to configure mac\n"); 1348 goto err_off; 1349 } 1350 1351 chip->ops->phy_set_param(rtwdev); 1352 1353 ret = rtw_hci_start(rtwdev); 1354 if (ret) { 1355 rtw_err(rtwdev, "failed to start hci\n"); 1356 goto err_off; 1357 } 1358 1359 /* send H2C after HCI has started */ 1360 rtw_fw_send_general_info(rtwdev); 1361 rtw_fw_send_phydm_info(rtwdev); 1362 1363 wifi_only = !rtwdev->efuse.btcoex; 1364 rtw_coex_power_on_setting(rtwdev); 1365 rtw_coex_init_hw_config(rtwdev, wifi_only); 1366 1367 return 0; 1368 1369 err_off: 1370 rtw_mac_power_off(rtwdev); 1371 1372 err: 1373 return ret; 1374 } 1375 1376 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1377 { 1378 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1379 return; 1380 1381 if (start) { 1382 rtw_fw_scan_notify(rtwdev, true); 1383 } else { 1384 reinit_completion(&rtwdev->fw_scan_density); 1385 rtw_fw_scan_notify(rtwdev, false); 1386 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1387 SCAN_NOTIFY_TIMEOUT)) 1388 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1389 } 1390 } 1391 1392 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1393 const u8 *mac_addr, bool hw_scan) 1394 { 1395 u32 config = 0; 1396 int ret = 0; 1397 1398 rtw_leave_lps(rtwdev); 1399 1400 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1401 ret = rtw_leave_ips(rtwdev); 1402 if (ret) { 1403 rtw_err(rtwdev, "failed to leave idle state\n"); 1404 return; 1405 } 1406 } 1407 1408 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1409 config |= PORT_SET_MAC_ADDR; 1410 rtw_vif_port_config(rtwdev, rtwvif, config); 1411 1412 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1413 rtw_core_fw_scan_notify(rtwdev, true); 1414 1415 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1416 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1417 } 1418 1419 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1420 bool hw_scan) 1421 { 1422 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1423 u32 config = 0; 1424 1425 if (!rtwvif) 1426 return; 1427 1428 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1429 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1430 1431 rtw_core_fw_scan_notify(rtwdev, false); 1432 1433 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1434 config |= PORT_SET_MAC_ADDR; 1435 rtw_vif_port_config(rtwdev, rtwvif, config); 1436 1437 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1438 1439 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1440 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1441 } 1442 1443 int rtw_core_start(struct rtw_dev *rtwdev) 1444 { 1445 int ret; 1446 1447 ret = rtw_power_on(rtwdev); 1448 if (ret) 1449 return ret; 1450 1451 rtw_sec_enable_sec_engine(rtwdev); 1452 1453 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1454 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1455 1456 /* rcr reset after powered on */ 1457 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1458 1459 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1460 RTW_WATCH_DOG_DELAY_TIME); 1461 1462 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1463 1464 return 0; 1465 } 1466 1467 static void rtw_power_off(struct rtw_dev *rtwdev) 1468 { 1469 rtw_hci_stop(rtwdev); 1470 rtw_coex_power_off_setting(rtwdev); 1471 rtw_mac_power_off(rtwdev); 1472 } 1473 1474 void rtw_core_stop(struct rtw_dev *rtwdev) 1475 { 1476 struct rtw_coex *coex = &rtwdev->coex; 1477 1478 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1479 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1480 1481 mutex_unlock(&rtwdev->mutex); 1482 1483 cancel_work_sync(&rtwdev->c2h_work); 1484 cancel_work_sync(&rtwdev->update_beacon_work); 1485 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1486 cancel_delayed_work_sync(&coex->bt_relink_work); 1487 cancel_delayed_work_sync(&coex->bt_reenable_work); 1488 cancel_delayed_work_sync(&coex->defreeze_work); 1489 cancel_delayed_work_sync(&coex->wl_remain_work); 1490 cancel_delayed_work_sync(&coex->bt_remain_work); 1491 cancel_delayed_work_sync(&coex->wl_connecting_work); 1492 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1493 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1494 1495 mutex_lock(&rtwdev->mutex); 1496 1497 rtw_power_off(rtwdev); 1498 } 1499 1500 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1501 struct ieee80211_sta_ht_cap *ht_cap) 1502 { 1503 const struct rtw_chip_info *chip = rtwdev->chip; 1504 struct rtw_efuse *efuse = &rtwdev->efuse; 1505 1506 ht_cap->ht_supported = true; 1507 ht_cap->cap = 0; 1508 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1509 IEEE80211_HT_CAP_MAX_AMSDU | 1510 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1511 1512 if (rtw_chip_has_rx_ldpc(rtwdev)) 1513 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1514 if (rtw_chip_has_tx_stbc(rtwdev)) 1515 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1516 1517 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1518 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1519 IEEE80211_HT_CAP_DSSSCCK40 | 1520 IEEE80211_HT_CAP_SGI_40; 1521 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1522 ht_cap->ampdu_density = chip->ampdu_density; 1523 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1524 if (efuse->hw_cap.nss > 1) { 1525 ht_cap->mcs.rx_mask[0] = 0xFF; 1526 ht_cap->mcs.rx_mask[1] = 0xFF; 1527 ht_cap->mcs.rx_mask[4] = 0x01; 1528 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1529 } else { 1530 ht_cap->mcs.rx_mask[0] = 0xFF; 1531 ht_cap->mcs.rx_mask[1] = 0x00; 1532 ht_cap->mcs.rx_mask[4] = 0x01; 1533 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1534 } 1535 } 1536 1537 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1538 struct ieee80211_sta_vht_cap *vht_cap) 1539 { 1540 struct rtw_efuse *efuse = &rtwdev->efuse; 1541 u16 mcs_map; 1542 __le16 highest; 1543 1544 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1545 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1546 return; 1547 1548 vht_cap->vht_supported = true; 1549 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1550 IEEE80211_VHT_CAP_SHORT_GI_80 | 1551 IEEE80211_VHT_CAP_RXSTBC_1 | 1552 IEEE80211_VHT_CAP_HTC_VHT | 1553 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1554 0; 1555 if (rtwdev->hal.rf_path_num > 1) 1556 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1557 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1558 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1559 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1560 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1561 1562 if (rtw_chip_has_rx_ldpc(rtwdev)) 1563 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1564 1565 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1566 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1567 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1568 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1569 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1570 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1571 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1572 if (efuse->hw_cap.nss > 1) { 1573 highest = cpu_to_le16(780); 1574 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1575 } else { 1576 highest = cpu_to_le16(390); 1577 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1578 } 1579 1580 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1581 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1582 vht_cap->vht_mcs.rx_highest = highest; 1583 vht_cap->vht_mcs.tx_highest = highest; 1584 } 1585 1586 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev) 1587 { 1588 u16 len; 1589 1590 len = rtwdev->chip->max_scan_ie_len; 1591 1592 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) && 1593 rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 1594 len = IEEE80211_MAX_DATA_LEN; 1595 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM)) 1596 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE; 1597 1598 return len; 1599 } 1600 1601 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1602 const struct rtw_chip_info *chip) 1603 { 1604 struct rtw_dev *rtwdev = hw->priv; 1605 struct ieee80211_supported_band *sband; 1606 1607 if (chip->band & RTW_BAND_2G) { 1608 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1609 if (!sband) 1610 goto err_out; 1611 if (chip->ht_supported) 1612 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1613 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1614 } 1615 1616 if (chip->band & RTW_BAND_5G) { 1617 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1618 if (!sband) 1619 goto err_out; 1620 if (chip->ht_supported) 1621 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1622 if (chip->vht_supported) 1623 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1624 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1625 } 1626 1627 return; 1628 1629 err_out: 1630 rtw_err(rtwdev, "failed to set supported band\n"); 1631 } 1632 1633 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1634 const struct rtw_chip_info *chip) 1635 { 1636 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1637 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1638 } 1639 1640 static void rtw_vif_smps_iter(void *data, u8 *mac, 1641 struct ieee80211_vif *vif) 1642 { 1643 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1644 1645 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 1646 return; 1647 1648 if (rtwdev->hal.txrx_1ss) 1649 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC); 1650 else 1651 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF); 1652 } 1653 1654 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1655 { 1656 const struct rtw_chip_info *chip = rtwdev->chip; 1657 struct rtw_hal *hal = &rtwdev->hal; 1658 1659 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1660 return; 1661 1662 rtwdev->hal.txrx_1ss = txrx_1ss; 1663 if (txrx_1ss) 1664 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1665 else 1666 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1667 hal->antenna_rx, false); 1668 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1669 } 1670 1671 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1672 struct rtw_fw_state *fw) 1673 { 1674 u32 feature; 1675 const struct rtw_fw_hdr *fw_hdr = 1676 (const struct rtw_fw_hdr *)fw->firmware->data; 1677 1678 feature = le32_to_cpu(fw_hdr->feature); 1679 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1680 1681 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C && 1682 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13)) 1683 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM; 1684 } 1685 1686 static void __update_firmware_info(struct rtw_dev *rtwdev, 1687 struct rtw_fw_state *fw) 1688 { 1689 const struct rtw_fw_hdr *fw_hdr = 1690 (const struct rtw_fw_hdr *)fw->firmware->data; 1691 1692 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1693 fw->version = le16_to_cpu(fw_hdr->version); 1694 fw->sub_version = fw_hdr->subversion; 1695 fw->sub_index = fw_hdr->subindex; 1696 1697 __update_firmware_feature(rtwdev, fw); 1698 } 1699 1700 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1701 struct rtw_fw_state *fw) 1702 { 1703 struct rtw_fw_hdr_legacy *legacy = 1704 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1705 1706 fw->h2c_version = 0; 1707 fw->version = le16_to_cpu(legacy->version); 1708 fw->sub_version = legacy->subversion1; 1709 fw->sub_index = legacy->subversion2; 1710 } 1711 1712 static void update_firmware_info(struct rtw_dev *rtwdev, 1713 struct rtw_fw_state *fw) 1714 { 1715 if (rtw_chip_wcpu_11n(rtwdev)) 1716 __update_firmware_info_legacy(rtwdev, fw); 1717 else 1718 __update_firmware_info(rtwdev, fw); 1719 } 1720 1721 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1722 { 1723 struct rtw_fw_state *fw = context; 1724 struct rtw_dev *rtwdev = fw->rtwdev; 1725 1726 if (!firmware || !firmware->data) { 1727 rtw_err(rtwdev, "failed to request firmware\n"); 1728 complete_all(&fw->completion); 1729 return; 1730 } 1731 1732 fw->firmware = firmware; 1733 update_firmware_info(rtwdev, fw); 1734 complete_all(&fw->completion); 1735 1736 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n", 1737 fw->type == RTW_WOWLAN_FW ? "WOW " : "", 1738 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1739 } 1740 1741 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1742 { 1743 const char *fw_name; 1744 struct rtw_fw_state *fw; 1745 int ret; 1746 1747 switch (type) { 1748 case RTW_WOWLAN_FW: 1749 fw = &rtwdev->wow_fw; 1750 fw_name = rtwdev->chip->wow_fw_name; 1751 break; 1752 1753 case RTW_NORMAL_FW: 1754 fw = &rtwdev->fw; 1755 fw_name = rtwdev->chip->fw_name; 1756 break; 1757 1758 default: 1759 rtw_warn(rtwdev, "unsupported firmware type\n"); 1760 return -ENOENT; 1761 } 1762 1763 fw->type = type; 1764 fw->rtwdev = rtwdev; 1765 init_completion(&fw->completion); 1766 1767 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1768 GFP_KERNEL, fw, rtw_load_firmware_cb); 1769 if (ret) { 1770 rtw_err(rtwdev, "failed to async firmware request\n"); 1771 return ret; 1772 } 1773 1774 return 0; 1775 } 1776 1777 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1778 { 1779 const struct rtw_chip_info *chip = rtwdev->chip; 1780 struct rtw_hal *hal = &rtwdev->hal; 1781 struct rtw_efuse *efuse = &rtwdev->efuse; 1782 1783 switch (rtw_hci_type(rtwdev)) { 1784 case RTW_HCI_TYPE_PCIE: 1785 rtwdev->hci.rpwm_addr = 0x03d9; 1786 rtwdev->hci.cpwm_addr = 0x03da; 1787 break; 1788 case RTW_HCI_TYPE_USB: 1789 rtwdev->hci.rpwm_addr = 0xfe58; 1790 rtwdev->hci.cpwm_addr = 0xfe57; 1791 break; 1792 default: 1793 rtw_err(rtwdev, "unsupported hci type\n"); 1794 return -EINVAL; 1795 } 1796 1797 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1798 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1799 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1800 if (hal->chip_version & BIT_RF_TYPE_ID) { 1801 hal->rf_type = RF_2T2R; 1802 hal->rf_path_num = 2; 1803 hal->antenna_tx = BB_PATH_AB; 1804 hal->antenna_rx = BB_PATH_AB; 1805 } else { 1806 hal->rf_type = RF_1T1R; 1807 hal->rf_path_num = 1; 1808 hal->antenna_tx = BB_PATH_A; 1809 hal->antenna_rx = BB_PATH_A; 1810 } 1811 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1812 hal->rf_path_num; 1813 1814 efuse->physical_size = chip->phy_efuse_size; 1815 efuse->logical_size = chip->log_efuse_size; 1816 efuse->protect_size = chip->ptct_efuse_size; 1817 1818 /* default use ack */ 1819 rtwdev->hal.rcr |= BIT_VHT_DACK; 1820 1821 hal->bfee_sts_cap = 3; 1822 1823 return 0; 1824 } 1825 1826 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1827 { 1828 struct rtw_fw_state *fw = &rtwdev->fw; 1829 int ret; 1830 1831 ret = rtw_hci_setup(rtwdev); 1832 if (ret) { 1833 rtw_err(rtwdev, "failed to setup hci\n"); 1834 goto err; 1835 } 1836 1837 ret = rtw_mac_power_on(rtwdev); 1838 if (ret) { 1839 rtw_err(rtwdev, "failed to power on mac\n"); 1840 goto err; 1841 } 1842 1843 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1844 1845 wait_for_completion(&fw->completion); 1846 if (!fw->firmware) { 1847 ret = -EINVAL; 1848 rtw_err(rtwdev, "failed to load firmware\n"); 1849 goto err; 1850 } 1851 1852 ret = rtw_download_firmware(rtwdev, fw); 1853 if (ret) { 1854 rtw_err(rtwdev, "failed to download firmware\n"); 1855 goto err_off; 1856 } 1857 1858 return 0; 1859 1860 err_off: 1861 rtw_mac_power_off(rtwdev); 1862 1863 err: 1864 return ret; 1865 } 1866 1867 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1868 { 1869 struct rtw_efuse *efuse = &rtwdev->efuse; 1870 u8 hw_feature[HW_FEATURE_LEN]; 1871 u8 id; 1872 u8 bw; 1873 int i; 1874 1875 id = rtw_read8(rtwdev, REG_C2HEVT); 1876 if (id != C2H_HW_FEATURE_REPORT) { 1877 rtw_err(rtwdev, "failed to read hw feature report\n"); 1878 return -EBUSY; 1879 } 1880 1881 for (i = 0; i < HW_FEATURE_LEN; i++) 1882 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1883 1884 rtw_write8(rtwdev, REG_C2HEVT, 0); 1885 1886 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1887 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1888 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1889 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1890 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1891 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1892 1893 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1894 1895 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1896 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1897 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1898 1899 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1900 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1901 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1902 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1903 1904 return 0; 1905 } 1906 1907 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1908 { 1909 rtw_hci_stop(rtwdev); 1910 rtw_mac_power_off(rtwdev); 1911 } 1912 1913 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1914 { 1915 struct rtw_efuse *efuse = &rtwdev->efuse; 1916 int ret; 1917 1918 mutex_lock(&rtwdev->mutex); 1919 1920 /* power on mac to read efuse */ 1921 ret = rtw_chip_efuse_enable(rtwdev); 1922 if (ret) 1923 goto out_unlock; 1924 1925 ret = rtw_parse_efuse_map(rtwdev); 1926 if (ret) 1927 goto out_disable; 1928 1929 ret = rtw_dump_hw_feature(rtwdev); 1930 if (ret) 1931 goto out_disable; 1932 1933 ret = rtw_check_supported_rfe(rtwdev); 1934 if (ret) 1935 goto out_disable; 1936 1937 if (efuse->crystal_cap == 0xff) 1938 efuse->crystal_cap = 0; 1939 if (efuse->pa_type_2g == 0xff) 1940 efuse->pa_type_2g = 0; 1941 if (efuse->pa_type_5g == 0xff) 1942 efuse->pa_type_5g = 0; 1943 if (efuse->lna_type_2g == 0xff) 1944 efuse->lna_type_2g = 0; 1945 if (efuse->lna_type_5g == 0xff) 1946 efuse->lna_type_5g = 0; 1947 if (efuse->channel_plan == 0xff) 1948 efuse->channel_plan = 0x7f; 1949 if (efuse->rf_board_option == 0xff) 1950 efuse->rf_board_option = 0; 1951 if (efuse->bt_setting & BIT(0)) 1952 efuse->share_ant = true; 1953 if (efuse->regd == 0xff) 1954 efuse->regd = 0; 1955 if (efuse->tx_bb_swing_setting_2g == 0xff) 1956 efuse->tx_bb_swing_setting_2g = 0; 1957 if (efuse->tx_bb_swing_setting_5g == 0xff) 1958 efuse->tx_bb_swing_setting_5g = 0; 1959 1960 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1961 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1962 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1963 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1964 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1965 1966 out_disable: 1967 rtw_chip_efuse_disable(rtwdev); 1968 1969 out_unlock: 1970 mutex_unlock(&rtwdev->mutex); 1971 return ret; 1972 } 1973 1974 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1975 { 1976 struct rtw_hal *hal = &rtwdev->hal; 1977 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1978 1979 if (!rfe_def) 1980 return -ENODEV; 1981 1982 rtw_phy_setup_phy_cond(rtwdev, 0); 1983 1984 rtw_phy_init_tx_power(rtwdev); 1985 if (rfe_def->agc_btg_tbl) 1986 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1987 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1988 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1989 rtw_phy_tx_power_by_rate_config(hal); 1990 rtw_phy_tx_power_limit_config(hal); 1991 1992 return 0; 1993 } 1994 1995 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1996 { 1997 int ret; 1998 1999 ret = rtw_chip_parameter_setup(rtwdev); 2000 if (ret) { 2001 rtw_err(rtwdev, "failed to setup chip parameters\n"); 2002 goto err_out; 2003 } 2004 2005 ret = rtw_chip_efuse_info_setup(rtwdev); 2006 if (ret) { 2007 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 2008 goto err_out; 2009 } 2010 2011 ret = rtw_chip_board_info_setup(rtwdev); 2012 if (ret) { 2013 rtw_err(rtwdev, "failed to setup chip board info\n"); 2014 goto err_out; 2015 } 2016 2017 return 0; 2018 2019 err_out: 2020 return ret; 2021 } 2022 EXPORT_SYMBOL(rtw_chip_info_setup); 2023 2024 static void rtw_stats_init(struct rtw_dev *rtwdev) 2025 { 2026 struct rtw_traffic_stats *stats = &rtwdev->stats; 2027 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2028 int i; 2029 2030 ewma_tp_init(&stats->tx_ewma_tp); 2031 ewma_tp_init(&stats->rx_ewma_tp); 2032 2033 for (i = 0; i < RTW_EVM_NUM; i++) 2034 ewma_evm_init(&dm_info->ewma_evm[i]); 2035 for (i = 0; i < RTW_SNR_NUM; i++) 2036 ewma_snr_init(&dm_info->ewma_snr[i]); 2037 } 2038 2039 int rtw_core_init(struct rtw_dev *rtwdev) 2040 { 2041 const struct rtw_chip_info *chip = rtwdev->chip; 2042 struct rtw_coex *coex = &rtwdev->coex; 2043 int ret; 2044 2045 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2046 INIT_LIST_HEAD(&rtwdev->txqs); 2047 2048 timer_setup(&rtwdev->tx_report.purge_timer, 2049 rtw_tx_report_purge_timer, 0); 2050 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2051 if (!rtwdev->tx_wq) { 2052 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n"); 2053 return -ENOMEM; 2054 } 2055 2056 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2057 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2058 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2059 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2060 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2061 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2062 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2063 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2064 rtw_coex_bt_multi_link_remain_work); 2065 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2066 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2067 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2068 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2069 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2070 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2071 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2072 skb_queue_head_init(&rtwdev->c2h_queue); 2073 skb_queue_head_init(&rtwdev->coex.queue); 2074 skb_queue_head_init(&rtwdev->tx_report.queue); 2075 2076 spin_lock_init(&rtwdev->txq_lock); 2077 spin_lock_init(&rtwdev->tx_report.q_lock); 2078 2079 mutex_init(&rtwdev->mutex); 2080 mutex_init(&rtwdev->hal.tx_power_mutex); 2081 2082 init_waitqueue_head(&rtwdev->coex.wait); 2083 init_completion(&rtwdev->lps_leave_check); 2084 init_completion(&rtwdev->fw_scan_density); 2085 2086 rtwdev->sec.total_cam_num = 32; 2087 rtwdev->hal.current_channel = 1; 2088 rtwdev->dm_info.fix_rate = U8_MAX; 2089 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2090 2091 rtw_stats_init(rtwdev); 2092 2093 /* default rx filter setting */ 2094 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2095 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2096 BIT_AB | BIT_AM | BIT_APM; 2097 2098 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2099 if (ret) { 2100 rtw_warn(rtwdev, "no firmware loaded\n"); 2101 goto out; 2102 } 2103 2104 if (chip->wow_fw_name) { 2105 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2106 if (ret) { 2107 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2108 wait_for_completion(&rtwdev->fw.completion); 2109 if (rtwdev->fw.firmware) 2110 release_firmware(rtwdev->fw.firmware); 2111 goto out; 2112 } 2113 } 2114 2115 return 0; 2116 2117 out: 2118 destroy_workqueue(rtwdev->tx_wq); 2119 return ret; 2120 } 2121 EXPORT_SYMBOL(rtw_core_init); 2122 2123 void rtw_core_deinit(struct rtw_dev *rtwdev) 2124 { 2125 struct rtw_fw_state *fw = &rtwdev->fw; 2126 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2127 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2128 unsigned long flags; 2129 2130 rtw_wait_firmware_completion(rtwdev); 2131 2132 if (fw->firmware) 2133 release_firmware(fw->firmware); 2134 2135 if (wow_fw->firmware) 2136 release_firmware(wow_fw->firmware); 2137 2138 destroy_workqueue(rtwdev->tx_wq); 2139 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2140 skb_queue_purge(&rtwdev->tx_report.queue); 2141 skb_queue_purge(&rtwdev->coex.queue); 2142 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2143 2144 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2145 build_list) { 2146 list_del(&rsvd_pkt->build_list); 2147 kfree(rsvd_pkt); 2148 } 2149 2150 mutex_destroy(&rtwdev->mutex); 2151 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2152 } 2153 EXPORT_SYMBOL(rtw_core_deinit); 2154 2155 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2156 { 2157 struct rtw_hal *hal = &rtwdev->hal; 2158 int max_tx_headroom = 0; 2159 int ret; 2160 2161 /* TODO: USB & SDIO may need extra room? */ 2162 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2163 2164 hw->extra_tx_headroom = max_tx_headroom; 2165 hw->queues = IEEE80211_NUM_ACS; 2166 hw->txq_data_size = sizeof(struct rtw_txq); 2167 hw->sta_data_size = sizeof(struct rtw_sta_info); 2168 hw->vif_data_size = sizeof(struct rtw_vif); 2169 2170 ieee80211_hw_set(hw, SIGNAL_DBM); 2171 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2172 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2173 ieee80211_hw_set(hw, MFP_CAPABLE); 2174 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2175 ieee80211_hw_set(hw, SUPPORTS_PS); 2176 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2177 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2178 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2179 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2180 ieee80211_hw_set(hw, TX_AMSDU); 2181 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2182 2183 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2184 BIT(NL80211_IFTYPE_AP) | 2185 BIT(NL80211_IFTYPE_ADHOC) | 2186 BIT(NL80211_IFTYPE_MESH_POINT); 2187 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2188 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2189 2190 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2191 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2192 2193 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2194 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2195 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev); 2196 2197 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2198 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2199 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2200 2201 #ifdef CONFIG_PM 2202 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2203 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2204 #endif 2205 rtw_set_supported_band(hw, rtwdev->chip); 2206 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2207 2208 hw->wiphy->sar_capa = &rtw_sar_capa; 2209 2210 ret = rtw_regd_init(rtwdev); 2211 if (ret) { 2212 rtw_err(rtwdev, "failed to init regd\n"); 2213 return ret; 2214 } 2215 2216 ret = ieee80211_register_hw(hw); 2217 if (ret) { 2218 rtw_err(rtwdev, "failed to register hw\n"); 2219 return ret; 2220 } 2221 2222 ret = rtw_regd_hint(rtwdev); 2223 if (ret) { 2224 rtw_err(rtwdev, "failed to hint regd\n"); 2225 return ret; 2226 } 2227 2228 rtw_debugfs_init(rtwdev); 2229 2230 rtwdev->bf_info.bfer_mu_cnt = 0; 2231 rtwdev->bf_info.bfer_su_cnt = 0; 2232 2233 return 0; 2234 } 2235 EXPORT_SYMBOL(rtw_register_hw); 2236 2237 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2238 { 2239 const struct rtw_chip_info *chip = rtwdev->chip; 2240 2241 ieee80211_unregister_hw(hw); 2242 rtw_unset_supported_band(hw, chip); 2243 } 2244 EXPORT_SYMBOL(rtw_unregister_hw); 2245 2246 MODULE_AUTHOR("Realtek Corporation"); 2247 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2248 MODULE_LICENSE("Dual BSD/GPL"); 2249