1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "regd.h" 7 #include "fw.h" 8 #include "ps.h" 9 #include "sec.h" 10 #include "mac.h" 11 #include "coex.h" 12 #include "phy.h" 13 #include "reg.h" 14 #include "efuse.h" 15 #include "tx.h" 16 #include "debug.h" 17 #include "bf.h" 18 19 unsigned int rtw_fw_lps_deep_mode; 20 EXPORT_SYMBOL(rtw_fw_lps_deep_mode); 21 bool rtw_bf_support = true; 22 unsigned int rtw_debug_mask; 23 EXPORT_SYMBOL(rtw_debug_mask); 24 25 module_param_named(lps_deep_mode, rtw_fw_lps_deep_mode, uint, 0644); 26 module_param_named(support_bf, rtw_bf_support, bool, 0644); 27 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 28 29 MODULE_PARM_DESC(lps_deep_mode, "Deeper PS mode. If 0, deep PS is disabled"); 30 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 31 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 32 33 static struct ieee80211_channel rtw_channeltable_2g[] = { 34 {.center_freq = 2412, .hw_value = 1,}, 35 {.center_freq = 2417, .hw_value = 2,}, 36 {.center_freq = 2422, .hw_value = 3,}, 37 {.center_freq = 2427, .hw_value = 4,}, 38 {.center_freq = 2432, .hw_value = 5,}, 39 {.center_freq = 2437, .hw_value = 6,}, 40 {.center_freq = 2442, .hw_value = 7,}, 41 {.center_freq = 2447, .hw_value = 8,}, 42 {.center_freq = 2452, .hw_value = 9,}, 43 {.center_freq = 2457, .hw_value = 10,}, 44 {.center_freq = 2462, .hw_value = 11,}, 45 {.center_freq = 2467, .hw_value = 12,}, 46 {.center_freq = 2472, .hw_value = 13,}, 47 {.center_freq = 2484, .hw_value = 14,}, 48 }; 49 50 static struct ieee80211_channel rtw_channeltable_5g[] = { 51 {.center_freq = 5180, .hw_value = 36,}, 52 {.center_freq = 5200, .hw_value = 40,}, 53 {.center_freq = 5220, .hw_value = 44,}, 54 {.center_freq = 5240, .hw_value = 48,}, 55 {.center_freq = 5260, .hw_value = 52,}, 56 {.center_freq = 5280, .hw_value = 56,}, 57 {.center_freq = 5300, .hw_value = 60,}, 58 {.center_freq = 5320, .hw_value = 64,}, 59 {.center_freq = 5500, .hw_value = 100,}, 60 {.center_freq = 5520, .hw_value = 104,}, 61 {.center_freq = 5540, .hw_value = 108,}, 62 {.center_freq = 5560, .hw_value = 112,}, 63 {.center_freq = 5580, .hw_value = 116,}, 64 {.center_freq = 5600, .hw_value = 120,}, 65 {.center_freq = 5620, .hw_value = 124,}, 66 {.center_freq = 5640, .hw_value = 128,}, 67 {.center_freq = 5660, .hw_value = 132,}, 68 {.center_freq = 5680, .hw_value = 136,}, 69 {.center_freq = 5700, .hw_value = 140,}, 70 {.center_freq = 5745, .hw_value = 149,}, 71 {.center_freq = 5765, .hw_value = 153,}, 72 {.center_freq = 5785, .hw_value = 157,}, 73 {.center_freq = 5805, .hw_value = 161,}, 74 {.center_freq = 5825, .hw_value = 165, 75 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 76 }; 77 78 static struct ieee80211_rate rtw_ratetable[] = { 79 {.bitrate = 10, .hw_value = 0x00,}, 80 {.bitrate = 20, .hw_value = 0x01,}, 81 {.bitrate = 55, .hw_value = 0x02,}, 82 {.bitrate = 110, .hw_value = 0x03,}, 83 {.bitrate = 60, .hw_value = 0x04,}, 84 {.bitrate = 90, .hw_value = 0x05,}, 85 {.bitrate = 120, .hw_value = 0x06,}, 86 {.bitrate = 180, .hw_value = 0x07,}, 87 {.bitrate = 240, .hw_value = 0x08,}, 88 {.bitrate = 360, .hw_value = 0x09,}, 89 {.bitrate = 480, .hw_value = 0x0a,}, 90 {.bitrate = 540, .hw_value = 0x0b,}, 91 }; 92 93 u16 rtw_desc_to_bitrate(u8 desc_rate) 94 { 95 struct ieee80211_rate rate; 96 97 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 98 return 0; 99 100 rate = rtw_ratetable[desc_rate]; 101 102 return rate.bitrate; 103 } 104 105 static struct ieee80211_supported_band rtw_band_2ghz = { 106 .band = NL80211_BAND_2GHZ, 107 108 .channels = rtw_channeltable_2g, 109 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 110 111 .bitrates = rtw_ratetable, 112 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 113 114 .ht_cap = {0}, 115 .vht_cap = {0}, 116 }; 117 118 static struct ieee80211_supported_band rtw_band_5ghz = { 119 .band = NL80211_BAND_5GHZ, 120 121 .channels = rtw_channeltable_5g, 122 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 123 124 /* 5G has no CCK rates */ 125 .bitrates = rtw_ratetable + 4, 126 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 127 128 .ht_cap = {0}, 129 .vht_cap = {0}, 130 }; 131 132 struct rtw_watch_dog_iter_data { 133 struct rtw_dev *rtwdev; 134 struct rtw_vif *rtwvif; 135 }; 136 137 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 138 { 139 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 140 u8 fix_rate_enable = 0; 141 u8 new_csi_rate_idx; 142 143 if (rtwvif->bfee.role != RTW_BFEE_SU && 144 rtwvif->bfee.role != RTW_BFEE_MU) 145 return; 146 147 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 148 bf_info->cur_csi_rpt_rate, 149 fix_rate_enable, &new_csi_rate_idx); 150 151 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 152 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 153 } 154 155 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 156 struct ieee80211_vif *vif) 157 { 158 struct rtw_watch_dog_iter_data *iter_data = data; 159 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 160 161 if (vif->type == NL80211_IFTYPE_STATION) 162 if (vif->bss_conf.assoc) 163 iter_data->rtwvif = rtwvif; 164 165 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 166 167 rtwvif->stats.tx_unicast = 0; 168 rtwvif->stats.rx_unicast = 0; 169 rtwvif->stats.tx_cnt = 0; 170 rtwvif->stats.rx_cnt = 0; 171 } 172 173 /* process TX/RX statistics periodically for hardware, 174 * the information helps hardware to enhance performance 175 */ 176 static void rtw_watch_dog_work(struct work_struct *work) 177 { 178 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 179 watch_dog_work.work); 180 struct rtw_traffic_stats *stats = &rtwdev->stats; 181 struct rtw_watch_dog_iter_data data = {}; 182 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 183 bool ps_active; 184 185 mutex_lock(&rtwdev->mutex); 186 187 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 188 goto unlock; 189 190 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 191 RTW_WATCH_DOG_DELAY_TIME); 192 193 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 194 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 195 else 196 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 197 198 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 199 rtw_coex_wl_status_change_notify(rtwdev); 200 201 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 202 stats->rx_cnt > RTW_LPS_THRESHOLD) 203 ps_active = true; 204 else 205 ps_active = false; 206 207 ewma_tp_add(&stats->tx_ewma_tp, 208 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 209 ewma_tp_add(&stats->rx_ewma_tp, 210 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 211 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 212 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 213 214 /* reset tx/rx statictics */ 215 stats->tx_unicast = 0; 216 stats->rx_unicast = 0; 217 stats->tx_cnt = 0; 218 stats->rx_cnt = 0; 219 220 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 221 goto unlock; 222 223 /* make sure BB/RF is working for dynamic mech */ 224 rtw_leave_lps(rtwdev); 225 226 rtw_phy_dynamic_mechanism(rtwdev); 227 228 data.rtwdev = rtwdev; 229 /* use atomic version to avoid taking local->iflist_mtx mutex */ 230 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 231 232 /* fw supports only one station associated to enter lps, if there are 233 * more than two stations associated to the AP, then we can not enter 234 * lps, because fw does not handle the overlapped beacon interval 235 * 236 * mac80211 should iterate vifs and determine if driver can enter 237 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 238 * get that vif and check if device is having traffic more than the 239 * threshold. 240 */ 241 if (rtwdev->ps_enabled && data.rtwvif && !ps_active) 242 rtw_enter_lps(rtwdev, data.rtwvif->port); 243 244 rtwdev->watch_dog_cnt++; 245 246 unlock: 247 mutex_unlock(&rtwdev->mutex); 248 } 249 250 static void rtw_c2h_work(struct work_struct *work) 251 { 252 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 253 struct sk_buff *skb, *tmp; 254 255 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 256 skb_unlink(skb, &rtwdev->c2h_queue); 257 rtw_fw_c2h_cmd_handle(rtwdev, skb); 258 dev_kfree_skb_any(skb); 259 } 260 } 261 262 struct rtw_txq_ba_iter_data { 263 }; 264 265 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 266 { 267 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 268 int ret; 269 u8 tid; 270 271 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 272 while (tid != IEEE80211_NUM_TIDS) { 273 clear_bit(tid, si->tid_ba); 274 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 275 if (ret == -EINVAL) { 276 struct ieee80211_txq *txq; 277 struct rtw_txq *rtwtxq; 278 279 txq = sta->txq[tid]; 280 rtwtxq = (struct rtw_txq *)txq->drv_priv; 281 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 282 } 283 284 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 285 } 286 } 287 288 static void rtw_txq_ba_work(struct work_struct *work) 289 { 290 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 291 struct rtw_txq_ba_iter_data data; 292 293 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 294 } 295 296 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 297 struct rtw_channel_params *chan_params) 298 { 299 struct ieee80211_channel *channel = chandef->chan; 300 enum nl80211_chan_width width = chandef->width; 301 u8 *cch_by_bw = chan_params->cch_by_bw; 302 u32 primary_freq, center_freq; 303 u8 center_chan; 304 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 305 u8 primary_chan_idx = 0; 306 u8 i; 307 308 center_chan = channel->hw_value; 309 primary_freq = channel->center_freq; 310 center_freq = chandef->center_freq1; 311 312 /* assign the center channel used while 20M bw is selected */ 313 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 314 315 switch (width) { 316 case NL80211_CHAN_WIDTH_20_NOHT: 317 case NL80211_CHAN_WIDTH_20: 318 bandwidth = RTW_CHANNEL_WIDTH_20; 319 primary_chan_idx = RTW_SC_DONT_CARE; 320 break; 321 case NL80211_CHAN_WIDTH_40: 322 bandwidth = RTW_CHANNEL_WIDTH_40; 323 if (primary_freq > center_freq) { 324 primary_chan_idx = RTW_SC_20_UPPER; 325 center_chan -= 2; 326 } else { 327 primary_chan_idx = RTW_SC_20_LOWER; 328 center_chan += 2; 329 } 330 break; 331 case NL80211_CHAN_WIDTH_80: 332 bandwidth = RTW_CHANNEL_WIDTH_80; 333 if (primary_freq > center_freq) { 334 if (primary_freq - center_freq == 10) { 335 primary_chan_idx = RTW_SC_20_UPPER; 336 center_chan -= 2; 337 } else { 338 primary_chan_idx = RTW_SC_20_UPMOST; 339 center_chan -= 6; 340 } 341 /* assign the center channel used 342 * while 40M bw is selected 343 */ 344 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 345 } else { 346 if (center_freq - primary_freq == 10) { 347 primary_chan_idx = RTW_SC_20_LOWER; 348 center_chan += 2; 349 } else { 350 primary_chan_idx = RTW_SC_20_LOWEST; 351 center_chan += 6; 352 } 353 /* assign the center channel used 354 * while 40M bw is selected 355 */ 356 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 357 } 358 break; 359 default: 360 center_chan = 0; 361 break; 362 } 363 364 chan_params->center_chan = center_chan; 365 chan_params->bandwidth = bandwidth; 366 chan_params->primary_chan_idx = primary_chan_idx; 367 368 /* assign the center channel used while current bw is selected */ 369 cch_by_bw[bandwidth] = center_chan; 370 371 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 372 cch_by_bw[i] = 0; 373 } 374 375 void rtw_set_channel(struct rtw_dev *rtwdev) 376 { 377 struct ieee80211_hw *hw = rtwdev->hw; 378 struct rtw_hal *hal = &rtwdev->hal; 379 struct rtw_chip_info *chip = rtwdev->chip; 380 struct rtw_channel_params ch_param; 381 u8 center_chan, bandwidth, primary_chan_idx; 382 u8 i; 383 384 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 385 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 386 return; 387 388 center_chan = ch_param.center_chan; 389 bandwidth = ch_param.bandwidth; 390 primary_chan_idx = ch_param.primary_chan_idx; 391 392 hal->current_band_width = bandwidth; 393 hal->current_channel = center_chan; 394 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 395 396 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 397 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 398 399 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 400 401 if (hal->current_band_type == RTW_BAND_5G) { 402 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 403 } else { 404 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 405 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 406 else 407 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 408 } 409 410 rtw_phy_set_tx_power_level(rtwdev, center_chan); 411 412 /* if the channel isn't set for scanning, we will do RF calibration 413 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 414 * during scanning on each channel takes too long. 415 */ 416 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 417 rtwdev->need_rfk = true; 418 } 419 420 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 421 { 422 struct rtw_chip_info *chip = rtwdev->chip; 423 424 if (rtwdev->need_rfk) { 425 rtwdev->need_rfk = false; 426 chip->ops->phy_calibration(rtwdev); 427 } 428 } 429 430 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 431 { 432 int i; 433 434 for (i = 0; i < ETH_ALEN; i++) 435 rtw_write8(rtwdev, start + i, addr[i]); 436 } 437 438 void rtw_vif_port_config(struct rtw_dev *rtwdev, 439 struct rtw_vif *rtwvif, 440 u32 config) 441 { 442 u32 addr, mask; 443 444 if (config & PORT_SET_MAC_ADDR) { 445 addr = rtwvif->conf->mac_addr.addr; 446 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 447 } 448 if (config & PORT_SET_BSSID) { 449 addr = rtwvif->conf->bssid.addr; 450 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 451 } 452 if (config & PORT_SET_NET_TYPE) { 453 addr = rtwvif->conf->net_type.addr; 454 mask = rtwvif->conf->net_type.mask; 455 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 456 } 457 if (config & PORT_SET_AID) { 458 addr = rtwvif->conf->aid.addr; 459 mask = rtwvif->conf->aid.mask; 460 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 461 } 462 if (config & PORT_SET_BCN_CTRL) { 463 addr = rtwvif->conf->bcn_ctrl.addr; 464 mask = rtwvif->conf->bcn_ctrl.mask; 465 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 466 } 467 } 468 469 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 470 { 471 u8 bw = 0; 472 473 switch (bw_cap) { 474 case EFUSE_HW_CAP_IGNORE: 475 case EFUSE_HW_CAP_SUPP_BW80: 476 bw |= BIT(RTW_CHANNEL_WIDTH_80); 477 /* fall through */ 478 case EFUSE_HW_CAP_SUPP_BW40: 479 bw |= BIT(RTW_CHANNEL_WIDTH_40); 480 /* fall through */ 481 default: 482 bw |= BIT(RTW_CHANNEL_WIDTH_20); 483 break; 484 } 485 486 return bw; 487 } 488 489 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 490 { 491 struct rtw_hal *hal = &rtwdev->hal; 492 struct rtw_chip_info *chip = rtwdev->chip; 493 494 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 495 hw_ant_num >= hal->rf_path_num) 496 return; 497 498 switch (hw_ant_num) { 499 case 1: 500 hal->rf_type = RF_1T1R; 501 hal->rf_path_num = 1; 502 if (!chip->fix_rf_phy_num) 503 hal->rf_phy_num = hal->rf_path_num; 504 hal->antenna_tx = BB_PATH_A; 505 hal->antenna_rx = BB_PATH_A; 506 break; 507 default: 508 WARN(1, "invalid hw configuration from efuse\n"); 509 break; 510 } 511 } 512 513 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 514 { 515 u64 ra_mask = 0; 516 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 517 u8 vht_mcs_cap; 518 int i, nss; 519 520 /* 4SS, every two bits for MCS7/8/9 */ 521 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 522 vht_mcs_cap = mcs_map & 0x3; 523 switch (vht_mcs_cap) { 524 case 2: /* MCS9 */ 525 ra_mask |= 0x3ffULL << nss; 526 break; 527 case 1: /* MCS8 */ 528 ra_mask |= 0x1ffULL << nss; 529 break; 530 case 0: /* MCS7 */ 531 ra_mask |= 0x0ffULL << nss; 532 break; 533 default: 534 break; 535 } 536 } 537 538 return ra_mask; 539 } 540 541 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 542 { 543 u8 rate_id = 0; 544 545 switch (wireless_set) { 546 case WIRELESS_CCK: 547 rate_id = RTW_RATEID_B_20M; 548 break; 549 case WIRELESS_OFDM: 550 rate_id = RTW_RATEID_G; 551 break; 552 case WIRELESS_CCK | WIRELESS_OFDM: 553 rate_id = RTW_RATEID_BG; 554 break; 555 case WIRELESS_OFDM | WIRELESS_HT: 556 if (tx_num == 1) 557 rate_id = RTW_RATEID_GN_N1SS; 558 else if (tx_num == 2) 559 rate_id = RTW_RATEID_GN_N2SS; 560 else if (tx_num == 3) 561 rate_id = RTW_RATEID_ARFR5_N_3SS; 562 break; 563 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 564 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 565 if (tx_num == 1) 566 rate_id = RTW_RATEID_BGN_40M_1SS; 567 else if (tx_num == 2) 568 rate_id = RTW_RATEID_BGN_40M_2SS; 569 else if (tx_num == 3) 570 rate_id = RTW_RATEID_ARFR5_N_3SS; 571 else if (tx_num == 4) 572 rate_id = RTW_RATEID_ARFR7_N_4SS; 573 } else { 574 if (tx_num == 1) 575 rate_id = RTW_RATEID_BGN_20M_1SS; 576 else if (tx_num == 2) 577 rate_id = RTW_RATEID_BGN_20M_2SS; 578 else if (tx_num == 3) 579 rate_id = RTW_RATEID_ARFR5_N_3SS; 580 else if (tx_num == 4) 581 rate_id = RTW_RATEID_ARFR7_N_4SS; 582 } 583 break; 584 case WIRELESS_OFDM | WIRELESS_VHT: 585 if (tx_num == 1) 586 rate_id = RTW_RATEID_ARFR1_AC_1SS; 587 else if (tx_num == 2) 588 rate_id = RTW_RATEID_ARFR0_AC_2SS; 589 else if (tx_num == 3) 590 rate_id = RTW_RATEID_ARFR4_AC_3SS; 591 else if (tx_num == 4) 592 rate_id = RTW_RATEID_ARFR6_AC_4SS; 593 break; 594 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 595 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 596 if (tx_num == 1) 597 rate_id = RTW_RATEID_ARFR1_AC_1SS; 598 else if (tx_num == 2) 599 rate_id = RTW_RATEID_ARFR0_AC_2SS; 600 else if (tx_num == 3) 601 rate_id = RTW_RATEID_ARFR4_AC_3SS; 602 else if (tx_num == 4) 603 rate_id = RTW_RATEID_ARFR6_AC_4SS; 604 } else { 605 if (tx_num == 1) 606 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 607 else if (tx_num == 2) 608 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 609 else if (tx_num == 3) 610 rate_id = RTW_RATEID_ARFR4_AC_3SS; 611 else if (tx_num == 4) 612 rate_id = RTW_RATEID_ARFR6_AC_4SS; 613 } 614 break; 615 default: 616 break; 617 } 618 619 return rate_id; 620 } 621 622 #define RA_MASK_CCK_RATES 0x0000f 623 #define RA_MASK_OFDM_RATES 0x00ff0 624 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 625 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 626 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 627 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 628 RA_MASK_HT_RATES_2SS | \ 629 RA_MASK_HT_RATES_3SS) 630 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 631 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 632 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 633 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 634 RA_MASK_VHT_RATES_2SS | \ 635 RA_MASK_VHT_RATES_3SS) 636 #define RA_MASK_CCK_IN_HT 0x00005 637 #define RA_MASK_CCK_IN_VHT 0x00005 638 #define RA_MASK_OFDM_IN_VHT 0x00010 639 #define RA_MASK_OFDM_IN_HT_2G 0x00010 640 #define RA_MASK_OFDM_IN_HT_5G 0x00030 641 642 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, 643 struct rtw_sta_info *si, 644 u64 ra_mask, bool is_vht_enable, 645 u8 wireless_set) 646 { 647 struct rtw_hal *hal = &rtwdev->hal; 648 const struct cfg80211_bitrate_mask *mask = si->mask; 649 u64 cfg_mask = GENMASK_ULL(63, 0); 650 u8 rssi_level, band; 651 652 if (wireless_set != WIRELESS_CCK) { 653 rssi_level = si->rssi_level; 654 if (rssi_level == 0) 655 ra_mask &= 0xffffffffffffffffULL; 656 else if (rssi_level == 1) 657 ra_mask &= 0xfffffffffffffff0ULL; 658 else if (rssi_level == 2) 659 ra_mask &= 0xffffffffffffefe0ULL; 660 else if (rssi_level == 3) 661 ra_mask &= 0xffffffffffffcfc0ULL; 662 else if (rssi_level == 4) 663 ra_mask &= 0xffffffffffff8f80ULL; 664 else if (rssi_level >= 5) 665 ra_mask &= 0xffffffffffff0f00ULL; 666 } 667 668 if (!si->use_cfg_mask) 669 return ra_mask; 670 671 band = hal->current_band_type; 672 if (band == RTW_BAND_2G) { 673 band = NL80211_BAND_2GHZ; 674 cfg_mask = mask->control[band].legacy; 675 } else if (band == RTW_BAND_5G) { 676 band = NL80211_BAND_5GHZ; 677 cfg_mask = u64_encode_bits(mask->control[band].legacy, 678 RA_MASK_OFDM_RATES); 679 } 680 681 if (!is_vht_enable) { 682 if (ra_mask & RA_MASK_HT_RATES_1SS) 683 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 684 RA_MASK_HT_RATES_1SS); 685 if (ra_mask & RA_MASK_HT_RATES_2SS) 686 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 687 RA_MASK_HT_RATES_2SS); 688 } else { 689 if (ra_mask & RA_MASK_VHT_RATES_1SS) 690 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 691 RA_MASK_VHT_RATES_1SS); 692 if (ra_mask & RA_MASK_VHT_RATES_2SS) 693 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 694 RA_MASK_VHT_RATES_2SS); 695 } 696 697 ra_mask &= cfg_mask; 698 699 return ra_mask; 700 } 701 702 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 703 { 704 struct ieee80211_sta *sta = si->sta; 705 struct rtw_efuse *efuse = &rtwdev->efuse; 706 struct rtw_hal *hal = &rtwdev->hal; 707 u8 wireless_set; 708 u8 bw_mode; 709 u8 rate_id; 710 u8 rf_type = RF_1T1R; 711 u8 stbc_en = 0; 712 u8 ldpc_en = 0; 713 u8 tx_num = 1; 714 u64 ra_mask = 0; 715 bool is_vht_enable = false; 716 bool is_support_sgi = false; 717 718 if (sta->vht_cap.vht_supported) { 719 is_vht_enable = true; 720 ra_mask |= get_vht_ra_mask(sta); 721 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 722 stbc_en = VHT_STBC_EN; 723 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 724 ldpc_en = VHT_LDPC_EN; 725 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80) 726 is_support_sgi = true; 727 } else if (sta->ht_cap.ht_supported) { 728 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 729 (sta->ht_cap.mcs.rx_mask[0] << 12); 730 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 731 stbc_en = HT_STBC_EN; 732 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 733 ldpc_en = HT_LDPC_EN; 734 if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20 || 735 sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) 736 is_support_sgi = true; 737 } 738 739 if (efuse->hw_cap.nss == 1) 740 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 741 742 if (hal->current_band_type == RTW_BAND_5G) { 743 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 744 if (sta->vht_cap.vht_supported) { 745 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 746 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 747 } else if (sta->ht_cap.ht_supported) { 748 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 749 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 750 } else { 751 wireless_set = WIRELESS_OFDM; 752 } 753 } else if (hal->current_band_type == RTW_BAND_2G) { 754 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 755 if (sta->vht_cap.vht_supported) { 756 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 757 RA_MASK_OFDM_IN_VHT; 758 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 759 WIRELESS_HT | WIRELESS_VHT; 760 } else if (sta->ht_cap.ht_supported) { 761 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 762 RA_MASK_OFDM_IN_HT_2G; 763 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 764 WIRELESS_HT; 765 } else if (sta->supp_rates[0] <= 0xf) { 766 wireless_set = WIRELESS_CCK; 767 } else { 768 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 769 } 770 } else { 771 rtw_err(rtwdev, "Unknown band type\n"); 772 wireless_set = 0; 773 } 774 775 switch (sta->bandwidth) { 776 case IEEE80211_STA_RX_BW_80: 777 bw_mode = RTW_CHANNEL_WIDTH_80; 778 break; 779 case IEEE80211_STA_RX_BW_40: 780 bw_mode = RTW_CHANNEL_WIDTH_40; 781 break; 782 default: 783 bw_mode = RTW_CHANNEL_WIDTH_20; 784 break; 785 } 786 787 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 788 tx_num = 2; 789 rf_type = RF_2T2R; 790 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 791 tx_num = 2; 792 rf_type = RF_2T2R; 793 } 794 795 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 796 797 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, 798 wireless_set); 799 800 si->bw_mode = bw_mode; 801 si->stbc_en = stbc_en; 802 si->ldpc_en = ldpc_en; 803 si->rf_type = rf_type; 804 si->wireless_set = wireless_set; 805 si->sgi_enable = is_support_sgi; 806 si->vht_enable = is_vht_enable; 807 si->ra_mask = ra_mask; 808 si->rate_id = rate_id; 809 810 rtw_fw_send_ra_info(rtwdev, si); 811 } 812 813 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 814 { 815 struct rtw_chip_info *chip = rtwdev->chip; 816 struct rtw_fw_state *fw; 817 818 fw = &rtwdev->fw; 819 wait_for_completion(&fw->completion); 820 if (!fw->firmware) 821 return -EINVAL; 822 823 if (chip->wow_fw_name) { 824 fw = &rtwdev->wow_fw; 825 wait_for_completion(&fw->completion); 826 if (!fw->firmware) 827 return -EINVAL; 828 } 829 830 return 0; 831 } 832 833 static int rtw_power_on(struct rtw_dev *rtwdev) 834 { 835 struct rtw_chip_info *chip = rtwdev->chip; 836 struct rtw_fw_state *fw = &rtwdev->fw; 837 bool wifi_only; 838 int ret; 839 840 ret = rtw_hci_setup(rtwdev); 841 if (ret) { 842 rtw_err(rtwdev, "failed to setup hci\n"); 843 goto err; 844 } 845 846 /* power on MAC before firmware downloaded */ 847 ret = rtw_mac_power_on(rtwdev); 848 if (ret) { 849 rtw_err(rtwdev, "failed to power on mac\n"); 850 goto err; 851 } 852 853 ret = rtw_wait_firmware_completion(rtwdev); 854 if (ret) { 855 rtw_err(rtwdev, "failed to wait firmware completion\n"); 856 goto err_off; 857 } 858 859 ret = rtw_download_firmware(rtwdev, fw); 860 if (ret) { 861 rtw_err(rtwdev, "failed to download firmware\n"); 862 goto err_off; 863 } 864 865 /* config mac after firmware downloaded */ 866 ret = rtw_mac_init(rtwdev); 867 if (ret) { 868 rtw_err(rtwdev, "failed to configure mac\n"); 869 goto err_off; 870 } 871 872 chip->ops->phy_set_param(rtwdev); 873 874 ret = rtw_hci_start(rtwdev); 875 if (ret) { 876 rtw_err(rtwdev, "failed to start hci\n"); 877 goto err_off; 878 } 879 880 /* send H2C after HCI has started */ 881 rtw_fw_send_general_info(rtwdev); 882 rtw_fw_send_phydm_info(rtwdev); 883 884 wifi_only = !rtwdev->efuse.btcoex; 885 rtw_coex_power_on_setting(rtwdev); 886 rtw_coex_init_hw_config(rtwdev, wifi_only); 887 888 return 0; 889 890 err_off: 891 rtw_mac_power_off(rtwdev); 892 893 err: 894 return ret; 895 } 896 897 int rtw_core_start(struct rtw_dev *rtwdev) 898 { 899 int ret; 900 901 ret = rtw_power_on(rtwdev); 902 if (ret) 903 return ret; 904 905 rtw_sec_enable_sec_engine(rtwdev); 906 907 /* rcr reset after powered on */ 908 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 909 910 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 911 RTW_WATCH_DOG_DELAY_TIME); 912 913 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 914 915 return 0; 916 } 917 918 static void rtw_power_off(struct rtw_dev *rtwdev) 919 { 920 rtw_hci_stop(rtwdev); 921 rtw_mac_power_off(rtwdev); 922 } 923 924 void rtw_core_stop(struct rtw_dev *rtwdev) 925 { 926 struct rtw_coex *coex = &rtwdev->coex; 927 928 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 929 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 930 931 mutex_unlock(&rtwdev->mutex); 932 933 cancel_work_sync(&rtwdev->c2h_work); 934 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 935 cancel_delayed_work_sync(&coex->bt_relink_work); 936 cancel_delayed_work_sync(&coex->bt_reenable_work); 937 cancel_delayed_work_sync(&coex->defreeze_work); 938 939 mutex_lock(&rtwdev->mutex); 940 941 rtw_power_off(rtwdev); 942 } 943 944 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 945 struct ieee80211_sta_ht_cap *ht_cap) 946 { 947 struct rtw_efuse *efuse = &rtwdev->efuse; 948 949 ht_cap->ht_supported = true; 950 ht_cap->cap = 0; 951 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 952 IEEE80211_HT_CAP_MAX_AMSDU | 953 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 954 955 if (rtw_chip_has_rx_ldpc(rtwdev)) 956 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 957 958 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 959 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 960 IEEE80211_HT_CAP_DSSSCCK40 | 961 IEEE80211_HT_CAP_SGI_40; 962 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 963 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 964 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 965 if (efuse->hw_cap.nss > 1) { 966 ht_cap->mcs.rx_mask[0] = 0xFF; 967 ht_cap->mcs.rx_mask[1] = 0xFF; 968 ht_cap->mcs.rx_mask[4] = 0x01; 969 ht_cap->mcs.rx_highest = cpu_to_le16(300); 970 } else { 971 ht_cap->mcs.rx_mask[0] = 0xFF; 972 ht_cap->mcs.rx_mask[1] = 0x00; 973 ht_cap->mcs.rx_mask[4] = 0x01; 974 ht_cap->mcs.rx_highest = cpu_to_le16(150); 975 } 976 } 977 978 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 979 struct ieee80211_sta_vht_cap *vht_cap) 980 { 981 struct rtw_efuse *efuse = &rtwdev->efuse; 982 u16 mcs_map; 983 __le16 highest; 984 985 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 986 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 987 return; 988 989 vht_cap->vht_supported = true; 990 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 991 IEEE80211_VHT_CAP_SHORT_GI_80 | 992 IEEE80211_VHT_CAP_TXSTBC | 993 IEEE80211_VHT_CAP_RXSTBC_1 | 994 IEEE80211_VHT_CAP_HTC_VHT | 995 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 996 0; 997 998 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 999 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1000 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1001 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1002 1003 if (rtw_chip_has_rx_ldpc(rtwdev)) 1004 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1005 1006 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1007 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1008 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1009 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1010 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1011 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1012 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1013 if (efuse->hw_cap.nss > 1) { 1014 highest = cpu_to_le16(780); 1015 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1016 } else { 1017 highest = cpu_to_le16(390); 1018 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1019 } 1020 1021 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1022 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1023 vht_cap->vht_mcs.rx_highest = highest; 1024 vht_cap->vht_mcs.tx_highest = highest; 1025 } 1026 1027 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1028 struct rtw_chip_info *chip) 1029 { 1030 struct rtw_dev *rtwdev = hw->priv; 1031 struct ieee80211_supported_band *sband; 1032 1033 if (chip->band & RTW_BAND_2G) { 1034 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1035 if (!sband) 1036 goto err_out; 1037 if (chip->ht_supported) 1038 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1039 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1040 } 1041 1042 if (chip->band & RTW_BAND_5G) { 1043 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1044 if (!sband) 1045 goto err_out; 1046 if (chip->ht_supported) 1047 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1048 if (chip->vht_supported) 1049 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1050 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1051 } 1052 1053 return; 1054 1055 err_out: 1056 rtw_err(rtwdev, "failed to set supported band\n"); 1057 kfree(sband); 1058 } 1059 1060 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1061 struct rtw_chip_info *chip) 1062 { 1063 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1064 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1065 } 1066 1067 static void __update_firmware_info(struct rtw_dev *rtwdev, 1068 struct rtw_fw_state *fw) 1069 { 1070 const struct rtw_fw_hdr *fw_hdr = 1071 (const struct rtw_fw_hdr *)fw->firmware->data; 1072 1073 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1074 fw->version = le16_to_cpu(fw_hdr->version); 1075 fw->sub_version = fw_hdr->subversion; 1076 fw->sub_index = fw_hdr->subindex; 1077 } 1078 1079 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1080 struct rtw_fw_state *fw) 1081 { 1082 struct rtw_fw_hdr_legacy *legacy = 1083 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1084 1085 fw->h2c_version = 0; 1086 fw->version = le16_to_cpu(legacy->version); 1087 fw->sub_version = legacy->subversion1; 1088 fw->sub_index = legacy->subversion2; 1089 } 1090 1091 static void update_firmware_info(struct rtw_dev *rtwdev, 1092 struct rtw_fw_state *fw) 1093 { 1094 if (rtw_chip_wcpu_11n(rtwdev)) 1095 __update_firmware_info_legacy(rtwdev, fw); 1096 else 1097 __update_firmware_info(rtwdev, fw); 1098 } 1099 1100 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1101 { 1102 struct rtw_fw_state *fw = context; 1103 struct rtw_dev *rtwdev = fw->rtwdev; 1104 1105 if (!firmware || !firmware->data) { 1106 rtw_err(rtwdev, "failed to request firmware\n"); 1107 complete_all(&fw->completion); 1108 return; 1109 } 1110 1111 fw->firmware = firmware; 1112 update_firmware_info(rtwdev, fw); 1113 complete_all(&fw->completion); 1114 1115 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1116 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1117 } 1118 1119 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1120 { 1121 const char *fw_name; 1122 struct rtw_fw_state *fw; 1123 int ret; 1124 1125 switch (type) { 1126 case RTW_WOWLAN_FW: 1127 fw = &rtwdev->wow_fw; 1128 fw_name = rtwdev->chip->wow_fw_name; 1129 break; 1130 1131 case RTW_NORMAL_FW: 1132 fw = &rtwdev->fw; 1133 fw_name = rtwdev->chip->fw_name; 1134 break; 1135 1136 default: 1137 rtw_warn(rtwdev, "unsupported firmware type\n"); 1138 return -ENOENT; 1139 } 1140 1141 fw->rtwdev = rtwdev; 1142 init_completion(&fw->completion); 1143 1144 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1145 GFP_KERNEL, fw, rtw_load_firmware_cb); 1146 if (ret) { 1147 rtw_err(rtwdev, "failed to async firmware request\n"); 1148 return ret; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1155 { 1156 struct rtw_chip_info *chip = rtwdev->chip; 1157 struct rtw_hal *hal = &rtwdev->hal; 1158 struct rtw_efuse *efuse = &rtwdev->efuse; 1159 int ret = 0; 1160 1161 switch (rtw_hci_type(rtwdev)) { 1162 case RTW_HCI_TYPE_PCIE: 1163 rtwdev->hci.rpwm_addr = 0x03d9; 1164 rtwdev->hci.cpwm_addr = 0x03da; 1165 break; 1166 default: 1167 rtw_err(rtwdev, "unsupported hci type\n"); 1168 return -EINVAL; 1169 } 1170 1171 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1172 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1173 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1174 if (hal->chip_version & BIT_RF_TYPE_ID) { 1175 hal->rf_type = RF_2T2R; 1176 hal->rf_path_num = 2; 1177 hal->antenna_tx = BB_PATH_AB; 1178 hal->antenna_rx = BB_PATH_AB; 1179 } else { 1180 hal->rf_type = RF_1T1R; 1181 hal->rf_path_num = 1; 1182 hal->antenna_tx = BB_PATH_A; 1183 hal->antenna_rx = BB_PATH_A; 1184 } 1185 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1186 hal->rf_path_num; 1187 1188 efuse->physical_size = chip->phy_efuse_size; 1189 efuse->logical_size = chip->log_efuse_size; 1190 efuse->protect_size = chip->ptct_efuse_size; 1191 1192 /* default use ack */ 1193 rtwdev->hal.rcr |= BIT_VHT_DACK; 1194 1195 hal->bfee_sts_cap = 3; 1196 1197 return ret; 1198 } 1199 1200 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1201 { 1202 struct rtw_fw_state *fw = &rtwdev->fw; 1203 int ret; 1204 1205 ret = rtw_hci_setup(rtwdev); 1206 if (ret) { 1207 rtw_err(rtwdev, "failed to setup hci\n"); 1208 goto err; 1209 } 1210 1211 ret = rtw_mac_power_on(rtwdev); 1212 if (ret) { 1213 rtw_err(rtwdev, "failed to power on mac\n"); 1214 goto err; 1215 } 1216 1217 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1218 1219 wait_for_completion(&fw->completion); 1220 if (!fw->firmware) { 1221 ret = -EINVAL; 1222 rtw_err(rtwdev, "failed to load firmware\n"); 1223 goto err; 1224 } 1225 1226 ret = rtw_download_firmware(rtwdev, fw); 1227 if (ret) { 1228 rtw_err(rtwdev, "failed to download firmware\n"); 1229 goto err_off; 1230 } 1231 1232 return 0; 1233 1234 err_off: 1235 rtw_mac_power_off(rtwdev); 1236 1237 err: 1238 return ret; 1239 } 1240 1241 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1242 { 1243 struct rtw_efuse *efuse = &rtwdev->efuse; 1244 u8 hw_feature[HW_FEATURE_LEN]; 1245 u8 id; 1246 u8 bw; 1247 int i; 1248 1249 id = rtw_read8(rtwdev, REG_C2HEVT); 1250 if (id != C2H_HW_FEATURE_REPORT) { 1251 rtw_err(rtwdev, "failed to read hw feature report\n"); 1252 return -EBUSY; 1253 } 1254 1255 for (i = 0; i < HW_FEATURE_LEN; i++) 1256 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1257 1258 rtw_write8(rtwdev, REG_C2HEVT, 0); 1259 1260 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1261 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1262 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1263 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1264 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1265 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1266 1267 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1268 1269 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1270 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1271 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1272 1273 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1274 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1275 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1276 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1277 1278 return 0; 1279 } 1280 1281 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1282 { 1283 rtw_hci_stop(rtwdev); 1284 rtw_mac_power_off(rtwdev); 1285 } 1286 1287 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1288 { 1289 struct rtw_efuse *efuse = &rtwdev->efuse; 1290 int ret; 1291 1292 mutex_lock(&rtwdev->mutex); 1293 1294 /* power on mac to read efuse */ 1295 ret = rtw_chip_efuse_enable(rtwdev); 1296 if (ret) 1297 goto out_unlock; 1298 1299 ret = rtw_parse_efuse_map(rtwdev); 1300 if (ret) 1301 goto out_disable; 1302 1303 ret = rtw_dump_hw_feature(rtwdev); 1304 if (ret) 1305 goto out_disable; 1306 1307 ret = rtw_check_supported_rfe(rtwdev); 1308 if (ret) 1309 goto out_disable; 1310 1311 if (efuse->crystal_cap == 0xff) 1312 efuse->crystal_cap = 0; 1313 if (efuse->pa_type_2g == 0xff) 1314 efuse->pa_type_2g = 0; 1315 if (efuse->pa_type_5g == 0xff) 1316 efuse->pa_type_5g = 0; 1317 if (efuse->lna_type_2g == 0xff) 1318 efuse->lna_type_2g = 0; 1319 if (efuse->lna_type_5g == 0xff) 1320 efuse->lna_type_5g = 0; 1321 if (efuse->channel_plan == 0xff) 1322 efuse->channel_plan = 0x7f; 1323 if (efuse->rf_board_option == 0xff) 1324 efuse->rf_board_option = 0; 1325 if (efuse->bt_setting & BIT(0)) 1326 efuse->share_ant = true; 1327 if (efuse->regd == 0xff) 1328 efuse->regd = 0; 1329 1330 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1331 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1332 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1333 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1334 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1335 1336 out_disable: 1337 rtw_chip_efuse_disable(rtwdev); 1338 1339 out_unlock: 1340 mutex_unlock(&rtwdev->mutex); 1341 return ret; 1342 } 1343 1344 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1345 { 1346 struct rtw_hal *hal = &rtwdev->hal; 1347 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1348 1349 if (!rfe_def) 1350 return -ENODEV; 1351 1352 rtw_phy_setup_phy_cond(rtwdev, 0); 1353 1354 rtw_phy_init_tx_power(rtwdev); 1355 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1356 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1357 rtw_phy_tx_power_by_rate_config(hal); 1358 rtw_phy_tx_power_limit_config(hal); 1359 1360 return 0; 1361 } 1362 1363 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1364 { 1365 int ret; 1366 1367 ret = rtw_chip_parameter_setup(rtwdev); 1368 if (ret) { 1369 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1370 goto err_out; 1371 } 1372 1373 ret = rtw_chip_efuse_info_setup(rtwdev); 1374 if (ret) { 1375 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1376 goto err_out; 1377 } 1378 1379 ret = rtw_chip_board_info_setup(rtwdev); 1380 if (ret) { 1381 rtw_err(rtwdev, "failed to setup chip board info\n"); 1382 goto err_out; 1383 } 1384 1385 return 0; 1386 1387 err_out: 1388 return ret; 1389 } 1390 EXPORT_SYMBOL(rtw_chip_info_setup); 1391 1392 static void rtw_stats_init(struct rtw_dev *rtwdev) 1393 { 1394 struct rtw_traffic_stats *stats = &rtwdev->stats; 1395 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1396 int i; 1397 1398 ewma_tp_init(&stats->tx_ewma_tp); 1399 ewma_tp_init(&stats->rx_ewma_tp); 1400 1401 for (i = 0; i < RTW_EVM_NUM; i++) 1402 ewma_evm_init(&dm_info->ewma_evm[i]); 1403 for (i = 0; i < RTW_SNR_NUM; i++) 1404 ewma_snr_init(&dm_info->ewma_snr[i]); 1405 } 1406 1407 int rtw_core_init(struct rtw_dev *rtwdev) 1408 { 1409 struct rtw_chip_info *chip = rtwdev->chip; 1410 struct rtw_coex *coex = &rtwdev->coex; 1411 int ret; 1412 1413 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1414 INIT_LIST_HEAD(&rtwdev->txqs); 1415 1416 timer_setup(&rtwdev->tx_report.purge_timer, 1417 rtw_tx_report_purge_timer, 0); 1418 tasklet_init(&rtwdev->tx_tasklet, rtw_tx_tasklet, 1419 (unsigned long)rtwdev); 1420 1421 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1422 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1423 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1424 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1425 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1426 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1427 skb_queue_head_init(&rtwdev->c2h_queue); 1428 skb_queue_head_init(&rtwdev->coex.queue); 1429 skb_queue_head_init(&rtwdev->tx_report.queue); 1430 1431 spin_lock_init(&rtwdev->rf_lock); 1432 spin_lock_init(&rtwdev->h2c.lock); 1433 spin_lock_init(&rtwdev->txq_lock); 1434 spin_lock_init(&rtwdev->tx_report.q_lock); 1435 1436 mutex_init(&rtwdev->mutex); 1437 mutex_init(&rtwdev->coex.mutex); 1438 mutex_init(&rtwdev->hal.tx_power_mutex); 1439 1440 init_waitqueue_head(&rtwdev->coex.wait); 1441 1442 rtwdev->sec.total_cam_num = 32; 1443 rtwdev->hal.current_channel = 1; 1444 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1445 if (!(BIT(rtw_fw_lps_deep_mode) & chip->lps_deep_mode_supported)) 1446 rtwdev->lps_conf.deep_mode = LPS_DEEP_MODE_NONE; 1447 else 1448 rtwdev->lps_conf.deep_mode = rtw_fw_lps_deep_mode; 1449 1450 rtw_stats_init(rtwdev); 1451 1452 /* default rx filter setting */ 1453 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1454 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1455 BIT_AB | BIT_AM | BIT_APM; 1456 1457 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 1458 if (ret) { 1459 rtw_warn(rtwdev, "no firmware loaded\n"); 1460 return ret; 1461 } 1462 1463 if (chip->wow_fw_name) { 1464 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 1465 if (ret) { 1466 rtw_warn(rtwdev, "no wow firmware loaded\n"); 1467 return ret; 1468 } 1469 } 1470 return 0; 1471 } 1472 EXPORT_SYMBOL(rtw_core_init); 1473 1474 void rtw_core_deinit(struct rtw_dev *rtwdev) 1475 { 1476 struct rtw_fw_state *fw = &rtwdev->fw; 1477 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 1478 struct rtw_rsvd_page *rsvd_pkt, *tmp; 1479 unsigned long flags; 1480 1481 if (fw->firmware) 1482 release_firmware(fw->firmware); 1483 1484 if (wow_fw->firmware) 1485 release_firmware(wow_fw->firmware); 1486 1487 tasklet_kill(&rtwdev->tx_tasklet); 1488 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 1489 skb_queue_purge(&rtwdev->tx_report.queue); 1490 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 1491 1492 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 1493 build_list) { 1494 list_del(&rsvd_pkt->build_list); 1495 kfree(rsvd_pkt); 1496 } 1497 1498 mutex_destroy(&rtwdev->mutex); 1499 mutex_destroy(&rtwdev->coex.mutex); 1500 mutex_destroy(&rtwdev->hal.tx_power_mutex); 1501 } 1502 EXPORT_SYMBOL(rtw_core_deinit); 1503 1504 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1505 { 1506 struct rtw_hal *hal = &rtwdev->hal; 1507 int max_tx_headroom = 0; 1508 int ret; 1509 1510 /* TODO: USB & SDIO may need extra room? */ 1511 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 1512 1513 hw->extra_tx_headroom = max_tx_headroom; 1514 hw->queues = IEEE80211_NUM_ACS; 1515 hw->txq_data_size = sizeof(struct rtw_txq); 1516 hw->sta_data_size = sizeof(struct rtw_sta_info); 1517 hw->vif_data_size = sizeof(struct rtw_vif); 1518 1519 ieee80211_hw_set(hw, SIGNAL_DBM); 1520 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 1521 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 1522 ieee80211_hw_set(hw, MFP_CAPABLE); 1523 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 1524 ieee80211_hw_set(hw, SUPPORTS_PS); 1525 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 1526 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 1527 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 1528 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 1529 ieee80211_hw_set(hw, TX_AMSDU); 1530 1531 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1532 BIT(NL80211_IFTYPE_AP) | 1533 BIT(NL80211_IFTYPE_ADHOC) | 1534 BIT(NL80211_IFTYPE_MESH_POINT); 1535 hw->wiphy->available_antennas_tx = hal->antenna_tx; 1536 hw->wiphy->available_antennas_rx = hal->antenna_rx; 1537 1538 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 1539 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 1540 1541 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 1542 1543 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 1544 1545 #ifdef CONFIG_PM 1546 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 1547 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 1548 #endif 1549 rtw_set_supported_band(hw, rtwdev->chip); 1550 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 1551 1552 rtw_regd_init(rtwdev, rtw_regd_notifier); 1553 1554 ret = ieee80211_register_hw(hw); 1555 if (ret) { 1556 rtw_err(rtwdev, "failed to register hw\n"); 1557 return ret; 1558 } 1559 1560 if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2)) 1561 rtw_err(rtwdev, "regulatory_hint fail\n"); 1562 1563 rtw_debugfs_init(rtwdev); 1564 1565 rtwdev->bf_info.bfer_mu_cnt = 0; 1566 rtwdev->bf_info.bfer_su_cnt = 0; 1567 1568 return 0; 1569 } 1570 EXPORT_SYMBOL(rtw_register_hw); 1571 1572 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1573 { 1574 struct rtw_chip_info *chip = rtwdev->chip; 1575 1576 ieee80211_unregister_hw(hw); 1577 rtw_unset_supported_band(hw, chip); 1578 } 1579 EXPORT_SYMBOL(rtw_unregister_hw); 1580 1581 MODULE_AUTHOR("Realtek Corporation"); 1582 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 1583 MODULE_LICENSE("Dual BSD/GPL"); 1584