1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "regd.h" 7 #include "fw.h" 8 #include "ps.h" 9 #include "sec.h" 10 #include "mac.h" 11 #include "coex.h" 12 #include "phy.h" 13 #include "reg.h" 14 #include "efuse.h" 15 #include "tx.h" 16 #include "debug.h" 17 #include "bf.h" 18 19 bool rtw_disable_lps_deep_mode; 20 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 21 bool rtw_bf_support = true; 22 unsigned int rtw_debug_mask; 23 EXPORT_SYMBOL(rtw_debug_mask); 24 25 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 26 module_param_named(support_bf, rtw_bf_support, bool, 0644); 27 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 28 29 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 30 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 31 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 32 33 static struct ieee80211_channel rtw_channeltable_2g[] = { 34 {.center_freq = 2412, .hw_value = 1,}, 35 {.center_freq = 2417, .hw_value = 2,}, 36 {.center_freq = 2422, .hw_value = 3,}, 37 {.center_freq = 2427, .hw_value = 4,}, 38 {.center_freq = 2432, .hw_value = 5,}, 39 {.center_freq = 2437, .hw_value = 6,}, 40 {.center_freq = 2442, .hw_value = 7,}, 41 {.center_freq = 2447, .hw_value = 8,}, 42 {.center_freq = 2452, .hw_value = 9,}, 43 {.center_freq = 2457, .hw_value = 10,}, 44 {.center_freq = 2462, .hw_value = 11,}, 45 {.center_freq = 2467, .hw_value = 12,}, 46 {.center_freq = 2472, .hw_value = 13,}, 47 {.center_freq = 2484, .hw_value = 14,}, 48 }; 49 50 static struct ieee80211_channel rtw_channeltable_5g[] = { 51 {.center_freq = 5180, .hw_value = 36,}, 52 {.center_freq = 5200, .hw_value = 40,}, 53 {.center_freq = 5220, .hw_value = 44,}, 54 {.center_freq = 5240, .hw_value = 48,}, 55 {.center_freq = 5260, .hw_value = 52,}, 56 {.center_freq = 5280, .hw_value = 56,}, 57 {.center_freq = 5300, .hw_value = 60,}, 58 {.center_freq = 5320, .hw_value = 64,}, 59 {.center_freq = 5500, .hw_value = 100,}, 60 {.center_freq = 5520, .hw_value = 104,}, 61 {.center_freq = 5540, .hw_value = 108,}, 62 {.center_freq = 5560, .hw_value = 112,}, 63 {.center_freq = 5580, .hw_value = 116,}, 64 {.center_freq = 5600, .hw_value = 120,}, 65 {.center_freq = 5620, .hw_value = 124,}, 66 {.center_freq = 5640, .hw_value = 128,}, 67 {.center_freq = 5660, .hw_value = 132,}, 68 {.center_freq = 5680, .hw_value = 136,}, 69 {.center_freq = 5700, .hw_value = 140,}, 70 {.center_freq = 5720, .hw_value = 144,}, 71 {.center_freq = 5745, .hw_value = 149,}, 72 {.center_freq = 5765, .hw_value = 153,}, 73 {.center_freq = 5785, .hw_value = 157,}, 74 {.center_freq = 5805, .hw_value = 161,}, 75 {.center_freq = 5825, .hw_value = 165, 76 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 77 }; 78 79 static struct ieee80211_rate rtw_ratetable[] = { 80 {.bitrate = 10, .hw_value = 0x00,}, 81 {.bitrate = 20, .hw_value = 0x01,}, 82 {.bitrate = 55, .hw_value = 0x02,}, 83 {.bitrate = 110, .hw_value = 0x03,}, 84 {.bitrate = 60, .hw_value = 0x04,}, 85 {.bitrate = 90, .hw_value = 0x05,}, 86 {.bitrate = 120, .hw_value = 0x06,}, 87 {.bitrate = 180, .hw_value = 0x07,}, 88 {.bitrate = 240, .hw_value = 0x08,}, 89 {.bitrate = 360, .hw_value = 0x09,}, 90 {.bitrate = 480, .hw_value = 0x0a,}, 91 {.bitrate = 540, .hw_value = 0x0b,}, 92 }; 93 94 u16 rtw_desc_to_bitrate(u8 desc_rate) 95 { 96 struct ieee80211_rate rate; 97 98 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 99 return 0; 100 101 rate = rtw_ratetable[desc_rate]; 102 103 return rate.bitrate; 104 } 105 106 static struct ieee80211_supported_band rtw_band_2ghz = { 107 .band = NL80211_BAND_2GHZ, 108 109 .channels = rtw_channeltable_2g, 110 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 111 112 .bitrates = rtw_ratetable, 113 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 114 115 .ht_cap = {0}, 116 .vht_cap = {0}, 117 }; 118 119 static struct ieee80211_supported_band rtw_band_5ghz = { 120 .band = NL80211_BAND_5GHZ, 121 122 .channels = rtw_channeltable_5g, 123 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 124 125 /* 5G has no CCK rates */ 126 .bitrates = rtw_ratetable + 4, 127 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 128 129 .ht_cap = {0}, 130 .vht_cap = {0}, 131 }; 132 133 struct rtw_watch_dog_iter_data { 134 struct rtw_dev *rtwdev; 135 struct rtw_vif *rtwvif; 136 }; 137 138 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 139 { 140 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 141 u8 fix_rate_enable = 0; 142 u8 new_csi_rate_idx; 143 144 if (rtwvif->bfee.role != RTW_BFEE_SU && 145 rtwvif->bfee.role != RTW_BFEE_MU) 146 return; 147 148 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 149 bf_info->cur_csi_rpt_rate, 150 fix_rate_enable, &new_csi_rate_idx); 151 152 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 153 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 154 } 155 156 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 157 struct ieee80211_vif *vif) 158 { 159 struct rtw_watch_dog_iter_data *iter_data = data; 160 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 161 162 if (vif->type == NL80211_IFTYPE_STATION) 163 if (vif->bss_conf.assoc) 164 iter_data->rtwvif = rtwvif; 165 166 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 167 168 rtwvif->stats.tx_unicast = 0; 169 rtwvif->stats.rx_unicast = 0; 170 rtwvif->stats.tx_cnt = 0; 171 rtwvif->stats.rx_cnt = 0; 172 } 173 174 /* process TX/RX statistics periodically for hardware, 175 * the information helps hardware to enhance performance 176 */ 177 static void rtw_watch_dog_work(struct work_struct *work) 178 { 179 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 180 watch_dog_work.work); 181 struct rtw_traffic_stats *stats = &rtwdev->stats; 182 struct rtw_watch_dog_iter_data data = {}; 183 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 184 bool ps_active; 185 186 mutex_lock(&rtwdev->mutex); 187 188 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 189 goto unlock; 190 191 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 192 RTW_WATCH_DOG_DELAY_TIME); 193 194 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 195 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 196 else 197 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 198 199 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 200 rtw_coex_wl_status_change_notify(rtwdev, 0); 201 202 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 203 stats->rx_cnt > RTW_LPS_THRESHOLD) 204 ps_active = true; 205 else 206 ps_active = false; 207 208 ewma_tp_add(&stats->tx_ewma_tp, 209 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 210 ewma_tp_add(&stats->rx_ewma_tp, 211 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 212 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 213 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 214 215 /* reset tx/rx statictics */ 216 stats->tx_unicast = 0; 217 stats->rx_unicast = 0; 218 stats->tx_cnt = 0; 219 stats->rx_cnt = 0; 220 221 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 222 goto unlock; 223 224 /* make sure BB/RF is working for dynamic mech */ 225 rtw_leave_lps(rtwdev); 226 227 rtw_phy_dynamic_mechanism(rtwdev); 228 229 data.rtwdev = rtwdev; 230 /* use atomic version to avoid taking local->iflist_mtx mutex */ 231 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 232 233 /* fw supports only one station associated to enter lps, if there are 234 * more than two stations associated to the AP, then we can not enter 235 * lps, because fw does not handle the overlapped beacon interval 236 * 237 * mac80211 should iterate vifs and determine if driver can enter 238 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 239 * get that vif and check if device is having traffic more than the 240 * threshold. 241 */ 242 if (rtwdev->ps_enabled && data.rtwvif && !ps_active) 243 rtw_enter_lps(rtwdev, data.rtwvif->port); 244 245 rtwdev->watch_dog_cnt++; 246 247 unlock: 248 mutex_unlock(&rtwdev->mutex); 249 } 250 251 static void rtw_c2h_work(struct work_struct *work) 252 { 253 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 254 struct sk_buff *skb, *tmp; 255 256 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 257 skb_unlink(skb, &rtwdev->c2h_queue); 258 rtw_fw_c2h_cmd_handle(rtwdev, skb); 259 dev_kfree_skb_any(skb); 260 } 261 } 262 263 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 264 { 265 unsigned long mac_id; 266 267 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 268 if (mac_id < RTW_MAX_MAC_ID_NUM) 269 set_bit(mac_id, rtwdev->mac_id_map); 270 271 return mac_id; 272 } 273 274 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 275 struct ieee80211_vif *vif) 276 { 277 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 278 int i; 279 280 si->mac_id = rtw_acquire_macid(rtwdev); 281 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 282 return -ENOSPC; 283 284 si->sta = sta; 285 si->vif = vif; 286 si->init_ra_lv = 1; 287 ewma_rssi_init(&si->avg_rssi); 288 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 289 rtw_txq_init(rtwdev, sta->txq[i]); 290 291 rtw_update_sta_info(rtwdev, si); 292 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 293 294 rtwdev->sta_cnt++; 295 rtw_info(rtwdev, "sta %pM joined with macid %d\n", 296 sta->addr, si->mac_id); 297 298 return 0; 299 } 300 301 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 302 bool fw_exist) 303 { 304 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 305 int i; 306 307 rtw_release_macid(rtwdev, si->mac_id); 308 if (fw_exist) 309 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 310 311 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 312 rtw_txq_cleanup(rtwdev, sta->txq[i]); 313 314 kfree(si->mask); 315 316 rtwdev->sta_cnt--; 317 rtw_info(rtwdev, "sta %pM with macid %d left\n", 318 sta->addr, si->mac_id); 319 } 320 321 static bool rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 322 { 323 u32 size = rtwdev->chip->fw_rxff_size; 324 u32 *buf; 325 u8 seq; 326 bool ret = true; 327 328 buf = vmalloc(size); 329 if (!buf) 330 goto exit; 331 332 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 333 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 334 goto free_buf; 335 } 336 337 if (GET_FW_DUMP_LEN(buf) == 0) { 338 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 339 goto free_buf; 340 } 341 342 seq = GET_FW_DUMP_SEQ(buf); 343 if (seq > 0 && seq != (rtwdev->fw.prev_dump_seq + 1)) { 344 rtw_dbg(rtwdev, RTW_DBG_FW, 345 "fw crash dump's seq is wrong: %d\n", seq); 346 goto free_buf; 347 } 348 349 print_hex_dump(KERN_ERR, "rtw88 fw dump: ", DUMP_PREFIX_OFFSET, 16, 1, 350 buf, size, true); 351 352 if (GET_FW_DUMP_MORE(buf) == 1) { 353 rtwdev->fw.prev_dump_seq = seq; 354 ret = false; 355 } 356 357 free_buf: 358 vfree(buf); 359 exit: 360 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 361 362 return ret; 363 } 364 365 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 366 const char *prefix_str) 367 { 368 u32 rxff = rtwdev->chip->fw_rxff_size; 369 u32 dump_size, done_size = 0; 370 u8 *buf; 371 int ret; 372 373 buf = vzalloc(size); 374 if (!buf) 375 return -ENOMEM; 376 377 while (size) { 378 dump_size = size > rxff ? rxff : size; 379 380 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 381 dump_size); 382 if (ret) { 383 rtw_err(rtwdev, 384 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 385 ocp_src, done_size); 386 goto exit; 387 } 388 389 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 390 dump_size, (u32 *)(buf + done_size)); 391 if (ret) { 392 rtw_err(rtwdev, 393 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 394 ocp_src, done_size); 395 goto exit; 396 } 397 398 size -= dump_size; 399 done_size += dump_size; 400 } 401 402 print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 1, 403 buf, done_size, true); 404 405 exit: 406 vfree(buf); 407 return ret; 408 } 409 EXPORT_SYMBOL(rtw_dump_fw); 410 411 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size, 412 const char *prefix_str) 413 { 414 u8 *buf; 415 u32 i; 416 417 if (addr & 0x3) { 418 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 419 return -EINVAL; 420 } 421 422 buf = vzalloc(size); 423 if (!buf) 424 return -ENOMEM; 425 426 for (i = 0; i < size; i += 4) 427 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 428 429 print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, 430 size, true); 431 432 vfree(buf); 433 return 0; 434 } 435 EXPORT_SYMBOL(rtw_dump_reg); 436 437 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 438 struct ieee80211_bss_conf *conf) 439 { 440 if (conf && conf->assoc) { 441 rtwvif->aid = conf->aid; 442 rtwvif->net_type = RTW_NET_MGD_LINKED; 443 } else { 444 rtwvif->aid = 0; 445 rtwvif->net_type = RTW_NET_NO_LINK; 446 } 447 } 448 449 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 450 struct ieee80211_vif *vif, 451 struct ieee80211_sta *sta, 452 struct ieee80211_key_conf *key, 453 void *data) 454 { 455 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 456 struct rtw_sec_desc *sec = &rtwdev->sec; 457 458 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 459 } 460 461 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 462 { 463 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 464 465 if (rtwdev->sta_cnt == 0) { 466 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 467 return; 468 } 469 rtw_sta_remove(rtwdev, sta, false); 470 } 471 472 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 473 { 474 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 475 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 476 477 rtw_bf_disassoc(rtwdev, vif, NULL); 478 rtw_vif_assoc_changed(rtwvif, NULL); 479 rtw_txq_cleanup(rtwdev, vif->txq); 480 } 481 482 void rtw_fw_recovery(struct rtw_dev *rtwdev) 483 { 484 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 485 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 486 } 487 488 static void __fw_recovery_work(struct rtw_dev *rtwdev) 489 { 490 491 /* rtw_fw_dump_crash_log() returns false indicates that there are 492 * still more log to dump. Driver set 0x1cf[7:0] = 0x1 to tell firmware 493 * to dump the remaining part of the log, and firmware will trigger an 494 * IMR_C2HCMD interrupt to inform driver the log is ready. 495 */ 496 if (!rtw_fw_dump_crash_log(rtwdev)) { 497 rtw_write8(rtwdev, REG_HRCV_MSG, 1); 498 return; 499 } 500 rtwdev->fw.prev_dump_seq = 0; 501 502 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 503 rtw_chip_dump_fw_crash(rtwdev); 504 505 WARN(1, "firmware crash, start reset and recover\n"); 506 507 rcu_read_lock(); 508 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 509 rcu_read_unlock(); 510 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 511 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 512 rtw_enter_ips(rtwdev); 513 } 514 515 static void rtw_fw_recovery_work(struct work_struct *work) 516 { 517 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 518 fw_recovery_work); 519 520 mutex_lock(&rtwdev->mutex); 521 __fw_recovery_work(rtwdev); 522 mutex_unlock(&rtwdev->mutex); 523 524 ieee80211_restart_hw(rtwdev->hw); 525 } 526 527 struct rtw_txq_ba_iter_data { 528 }; 529 530 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 531 { 532 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 533 int ret; 534 u8 tid; 535 536 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 537 while (tid != IEEE80211_NUM_TIDS) { 538 clear_bit(tid, si->tid_ba); 539 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 540 if (ret == -EINVAL) { 541 struct ieee80211_txq *txq; 542 struct rtw_txq *rtwtxq; 543 544 txq = sta->txq[tid]; 545 rtwtxq = (struct rtw_txq *)txq->drv_priv; 546 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 547 } 548 549 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 550 } 551 } 552 553 static void rtw_txq_ba_work(struct work_struct *work) 554 { 555 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 556 struct rtw_txq_ba_iter_data data; 557 558 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 559 } 560 561 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 562 struct rtw_channel_params *chan_params) 563 { 564 struct ieee80211_channel *channel = chandef->chan; 565 enum nl80211_chan_width width = chandef->width; 566 u8 *cch_by_bw = chan_params->cch_by_bw; 567 u32 primary_freq, center_freq; 568 u8 center_chan; 569 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 570 u8 primary_chan_idx = 0; 571 u8 i; 572 573 center_chan = channel->hw_value; 574 primary_freq = channel->center_freq; 575 center_freq = chandef->center_freq1; 576 577 /* assign the center channel used while 20M bw is selected */ 578 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 579 580 switch (width) { 581 case NL80211_CHAN_WIDTH_20_NOHT: 582 case NL80211_CHAN_WIDTH_20: 583 bandwidth = RTW_CHANNEL_WIDTH_20; 584 primary_chan_idx = RTW_SC_DONT_CARE; 585 break; 586 case NL80211_CHAN_WIDTH_40: 587 bandwidth = RTW_CHANNEL_WIDTH_40; 588 if (primary_freq > center_freq) { 589 primary_chan_idx = RTW_SC_20_UPPER; 590 center_chan -= 2; 591 } else { 592 primary_chan_idx = RTW_SC_20_LOWER; 593 center_chan += 2; 594 } 595 break; 596 case NL80211_CHAN_WIDTH_80: 597 bandwidth = RTW_CHANNEL_WIDTH_80; 598 if (primary_freq > center_freq) { 599 if (primary_freq - center_freq == 10) { 600 primary_chan_idx = RTW_SC_20_UPPER; 601 center_chan -= 2; 602 } else { 603 primary_chan_idx = RTW_SC_20_UPMOST; 604 center_chan -= 6; 605 } 606 /* assign the center channel used 607 * while 40M bw is selected 608 */ 609 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 610 } else { 611 if (center_freq - primary_freq == 10) { 612 primary_chan_idx = RTW_SC_20_LOWER; 613 center_chan += 2; 614 } else { 615 primary_chan_idx = RTW_SC_20_LOWEST; 616 center_chan += 6; 617 } 618 /* assign the center channel used 619 * while 40M bw is selected 620 */ 621 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 622 } 623 break; 624 default: 625 center_chan = 0; 626 break; 627 } 628 629 chan_params->center_chan = center_chan; 630 chan_params->bandwidth = bandwidth; 631 chan_params->primary_chan_idx = primary_chan_idx; 632 633 /* assign the center channel used while current bw is selected */ 634 cch_by_bw[bandwidth] = center_chan; 635 636 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 637 cch_by_bw[i] = 0; 638 } 639 640 void rtw_set_channel(struct rtw_dev *rtwdev) 641 { 642 struct ieee80211_hw *hw = rtwdev->hw; 643 struct rtw_hal *hal = &rtwdev->hal; 644 struct rtw_chip_info *chip = rtwdev->chip; 645 struct rtw_channel_params ch_param; 646 u8 center_chan, bandwidth, primary_chan_idx; 647 u8 i; 648 649 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 650 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 651 return; 652 653 center_chan = ch_param.center_chan; 654 bandwidth = ch_param.bandwidth; 655 primary_chan_idx = ch_param.primary_chan_idx; 656 657 hal->current_band_width = bandwidth; 658 hal->current_channel = center_chan; 659 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 660 661 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 662 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 663 664 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 665 666 if (hal->current_band_type == RTW_BAND_5G) { 667 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 668 } else { 669 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 670 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 671 else 672 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 673 } 674 675 rtw_phy_set_tx_power_level(rtwdev, center_chan); 676 677 /* if the channel isn't set for scanning, we will do RF calibration 678 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 679 * during scanning on each channel takes too long. 680 */ 681 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 682 rtwdev->need_rfk = true; 683 } 684 685 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 686 { 687 struct rtw_chip_info *chip = rtwdev->chip; 688 689 if (rtwdev->need_rfk) { 690 rtwdev->need_rfk = false; 691 chip->ops->phy_calibration(rtwdev); 692 } 693 } 694 695 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 696 { 697 int i; 698 699 for (i = 0; i < ETH_ALEN; i++) 700 rtw_write8(rtwdev, start + i, addr[i]); 701 } 702 703 void rtw_vif_port_config(struct rtw_dev *rtwdev, 704 struct rtw_vif *rtwvif, 705 u32 config) 706 { 707 u32 addr, mask; 708 709 if (config & PORT_SET_MAC_ADDR) { 710 addr = rtwvif->conf->mac_addr.addr; 711 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 712 } 713 if (config & PORT_SET_BSSID) { 714 addr = rtwvif->conf->bssid.addr; 715 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 716 } 717 if (config & PORT_SET_NET_TYPE) { 718 addr = rtwvif->conf->net_type.addr; 719 mask = rtwvif->conf->net_type.mask; 720 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 721 } 722 if (config & PORT_SET_AID) { 723 addr = rtwvif->conf->aid.addr; 724 mask = rtwvif->conf->aid.mask; 725 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 726 } 727 if (config & PORT_SET_BCN_CTRL) { 728 addr = rtwvif->conf->bcn_ctrl.addr; 729 mask = rtwvif->conf->bcn_ctrl.mask; 730 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 731 } 732 } 733 734 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 735 { 736 u8 bw = 0; 737 738 switch (bw_cap) { 739 case EFUSE_HW_CAP_IGNORE: 740 case EFUSE_HW_CAP_SUPP_BW80: 741 bw |= BIT(RTW_CHANNEL_WIDTH_80); 742 fallthrough; 743 case EFUSE_HW_CAP_SUPP_BW40: 744 bw |= BIT(RTW_CHANNEL_WIDTH_40); 745 fallthrough; 746 default: 747 bw |= BIT(RTW_CHANNEL_WIDTH_20); 748 break; 749 } 750 751 return bw; 752 } 753 754 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 755 { 756 struct rtw_hal *hal = &rtwdev->hal; 757 struct rtw_chip_info *chip = rtwdev->chip; 758 759 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 760 hw_ant_num >= hal->rf_path_num) 761 return; 762 763 switch (hw_ant_num) { 764 case 1: 765 hal->rf_type = RF_1T1R; 766 hal->rf_path_num = 1; 767 if (!chip->fix_rf_phy_num) 768 hal->rf_phy_num = hal->rf_path_num; 769 hal->antenna_tx = BB_PATH_A; 770 hal->antenna_rx = BB_PATH_A; 771 break; 772 default: 773 WARN(1, "invalid hw configuration from efuse\n"); 774 break; 775 } 776 } 777 778 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 779 { 780 u64 ra_mask = 0; 781 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 782 u8 vht_mcs_cap; 783 int i, nss; 784 785 /* 4SS, every two bits for MCS7/8/9 */ 786 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 787 vht_mcs_cap = mcs_map & 0x3; 788 switch (vht_mcs_cap) { 789 case 2: /* MCS9 */ 790 ra_mask |= 0x3ffULL << nss; 791 break; 792 case 1: /* MCS8 */ 793 ra_mask |= 0x1ffULL << nss; 794 break; 795 case 0: /* MCS7 */ 796 ra_mask |= 0x0ffULL << nss; 797 break; 798 default: 799 break; 800 } 801 } 802 803 return ra_mask; 804 } 805 806 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 807 { 808 u8 rate_id = 0; 809 810 switch (wireless_set) { 811 case WIRELESS_CCK: 812 rate_id = RTW_RATEID_B_20M; 813 break; 814 case WIRELESS_OFDM: 815 rate_id = RTW_RATEID_G; 816 break; 817 case WIRELESS_CCK | WIRELESS_OFDM: 818 rate_id = RTW_RATEID_BG; 819 break; 820 case WIRELESS_OFDM | WIRELESS_HT: 821 if (tx_num == 1) 822 rate_id = RTW_RATEID_GN_N1SS; 823 else if (tx_num == 2) 824 rate_id = RTW_RATEID_GN_N2SS; 825 else if (tx_num == 3) 826 rate_id = RTW_RATEID_ARFR5_N_3SS; 827 break; 828 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 829 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 830 if (tx_num == 1) 831 rate_id = RTW_RATEID_BGN_40M_1SS; 832 else if (tx_num == 2) 833 rate_id = RTW_RATEID_BGN_40M_2SS; 834 else if (tx_num == 3) 835 rate_id = RTW_RATEID_ARFR5_N_3SS; 836 else if (tx_num == 4) 837 rate_id = RTW_RATEID_ARFR7_N_4SS; 838 } else { 839 if (tx_num == 1) 840 rate_id = RTW_RATEID_BGN_20M_1SS; 841 else if (tx_num == 2) 842 rate_id = RTW_RATEID_BGN_20M_2SS; 843 else if (tx_num == 3) 844 rate_id = RTW_RATEID_ARFR5_N_3SS; 845 else if (tx_num == 4) 846 rate_id = RTW_RATEID_ARFR7_N_4SS; 847 } 848 break; 849 case WIRELESS_OFDM | WIRELESS_VHT: 850 if (tx_num == 1) 851 rate_id = RTW_RATEID_ARFR1_AC_1SS; 852 else if (tx_num == 2) 853 rate_id = RTW_RATEID_ARFR0_AC_2SS; 854 else if (tx_num == 3) 855 rate_id = RTW_RATEID_ARFR4_AC_3SS; 856 else if (tx_num == 4) 857 rate_id = RTW_RATEID_ARFR6_AC_4SS; 858 break; 859 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 860 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 861 if (tx_num == 1) 862 rate_id = RTW_RATEID_ARFR1_AC_1SS; 863 else if (tx_num == 2) 864 rate_id = RTW_RATEID_ARFR0_AC_2SS; 865 else if (tx_num == 3) 866 rate_id = RTW_RATEID_ARFR4_AC_3SS; 867 else if (tx_num == 4) 868 rate_id = RTW_RATEID_ARFR6_AC_4SS; 869 } else { 870 if (tx_num == 1) 871 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 872 else if (tx_num == 2) 873 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 874 else if (tx_num == 3) 875 rate_id = RTW_RATEID_ARFR4_AC_3SS; 876 else if (tx_num == 4) 877 rate_id = RTW_RATEID_ARFR6_AC_4SS; 878 } 879 break; 880 default: 881 break; 882 } 883 884 return rate_id; 885 } 886 887 #define RA_MASK_CCK_RATES 0x0000f 888 #define RA_MASK_OFDM_RATES 0x00ff0 889 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 890 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 891 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 892 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 893 RA_MASK_HT_RATES_2SS | \ 894 RA_MASK_HT_RATES_3SS) 895 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 896 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 897 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 898 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 899 RA_MASK_VHT_RATES_2SS | \ 900 RA_MASK_VHT_RATES_3SS) 901 #define RA_MASK_CCK_IN_HT 0x00005 902 #define RA_MASK_CCK_IN_VHT 0x00005 903 #define RA_MASK_OFDM_IN_VHT 0x00010 904 #define RA_MASK_OFDM_IN_HT_2G 0x00010 905 #define RA_MASK_OFDM_IN_HT_5G 0x00030 906 907 static u64 rtw_update_rate_mask(struct rtw_dev *rtwdev, 908 struct rtw_sta_info *si, 909 u64 ra_mask, bool is_vht_enable, 910 u8 wireless_set) 911 { 912 struct rtw_hal *hal = &rtwdev->hal; 913 const struct cfg80211_bitrate_mask *mask = si->mask; 914 u64 cfg_mask = GENMASK_ULL(63, 0); 915 u8 rssi_level, band; 916 917 if (wireless_set != WIRELESS_CCK) { 918 rssi_level = si->rssi_level; 919 if (rssi_level == 0) 920 ra_mask &= 0xffffffffffffffffULL; 921 else if (rssi_level == 1) 922 ra_mask &= 0xfffffffffffffff0ULL; 923 else if (rssi_level == 2) 924 ra_mask &= 0xffffffffffffefe0ULL; 925 else if (rssi_level == 3) 926 ra_mask &= 0xffffffffffffcfc0ULL; 927 else if (rssi_level == 4) 928 ra_mask &= 0xffffffffffff8f80ULL; 929 else if (rssi_level >= 5) 930 ra_mask &= 0xffffffffffff0f00ULL; 931 } 932 933 if (!si->use_cfg_mask) 934 return ra_mask; 935 936 band = hal->current_band_type; 937 if (band == RTW_BAND_2G) { 938 band = NL80211_BAND_2GHZ; 939 cfg_mask = mask->control[band].legacy; 940 } else if (band == RTW_BAND_5G) { 941 band = NL80211_BAND_5GHZ; 942 cfg_mask = u64_encode_bits(mask->control[band].legacy, 943 RA_MASK_OFDM_RATES); 944 } 945 946 if (!is_vht_enable) { 947 if (ra_mask & RA_MASK_HT_RATES_1SS) 948 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 949 RA_MASK_HT_RATES_1SS); 950 if (ra_mask & RA_MASK_HT_RATES_2SS) 951 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 952 RA_MASK_HT_RATES_2SS); 953 } else { 954 if (ra_mask & RA_MASK_VHT_RATES_1SS) 955 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 956 RA_MASK_VHT_RATES_1SS); 957 if (ra_mask & RA_MASK_VHT_RATES_2SS) 958 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 959 RA_MASK_VHT_RATES_2SS); 960 } 961 962 ra_mask &= cfg_mask; 963 964 return ra_mask; 965 } 966 967 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 968 { 969 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 970 struct ieee80211_sta *sta = si->sta; 971 struct rtw_efuse *efuse = &rtwdev->efuse; 972 struct rtw_hal *hal = &rtwdev->hal; 973 u8 wireless_set; 974 u8 bw_mode; 975 u8 rate_id; 976 u8 rf_type = RF_1T1R; 977 u8 stbc_en = 0; 978 u8 ldpc_en = 0; 979 u8 tx_num = 1; 980 u64 ra_mask = 0; 981 bool is_vht_enable = false; 982 bool is_support_sgi = false; 983 984 if (sta->vht_cap.vht_supported) { 985 is_vht_enable = true; 986 ra_mask |= get_vht_ra_mask(sta); 987 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 988 stbc_en = VHT_STBC_EN; 989 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 990 ldpc_en = VHT_LDPC_EN; 991 } else if (sta->ht_cap.ht_supported) { 992 ra_mask |= (sta->ht_cap.mcs.rx_mask[1] << 20) | 993 (sta->ht_cap.mcs.rx_mask[0] << 12); 994 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 995 stbc_en = HT_STBC_EN; 996 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 997 ldpc_en = HT_LDPC_EN; 998 } 999 1000 if (efuse->hw_cap.nss == 1) 1001 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1002 1003 if (hal->current_band_type == RTW_BAND_5G) { 1004 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 1005 if (sta->vht_cap.vht_supported) { 1006 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1007 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1008 } else if (sta->ht_cap.ht_supported) { 1009 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1010 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1011 } else { 1012 wireless_set = WIRELESS_OFDM; 1013 } 1014 dm_info->rrsr_val_init = RRSR_INIT_5G; 1015 } else if (hal->current_band_type == RTW_BAND_2G) { 1016 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 1017 if (sta->vht_cap.vht_supported) { 1018 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1019 RA_MASK_OFDM_IN_VHT; 1020 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1021 WIRELESS_HT | WIRELESS_VHT; 1022 } else if (sta->ht_cap.ht_supported) { 1023 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1024 RA_MASK_OFDM_IN_HT_2G; 1025 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1026 WIRELESS_HT; 1027 } else if (sta->supp_rates[0] <= 0xf) { 1028 wireless_set = WIRELESS_CCK; 1029 } else { 1030 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1031 } 1032 dm_info->rrsr_val_init = RRSR_INIT_2G; 1033 } else { 1034 rtw_err(rtwdev, "Unknown band type\n"); 1035 wireless_set = 0; 1036 } 1037 1038 switch (sta->bandwidth) { 1039 case IEEE80211_STA_RX_BW_80: 1040 bw_mode = RTW_CHANNEL_WIDTH_80; 1041 is_support_sgi = sta->vht_cap.vht_supported && 1042 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1043 break; 1044 case IEEE80211_STA_RX_BW_40: 1045 bw_mode = RTW_CHANNEL_WIDTH_40; 1046 is_support_sgi = sta->ht_cap.ht_supported && 1047 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1048 break; 1049 default: 1050 bw_mode = RTW_CHANNEL_WIDTH_20; 1051 is_support_sgi = sta->ht_cap.ht_supported && 1052 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1053 break; 1054 } 1055 1056 if (sta->vht_cap.vht_supported && ra_mask & 0xffc00000) { 1057 tx_num = 2; 1058 rf_type = RF_2T2R; 1059 } else if (sta->ht_cap.ht_supported && ra_mask & 0xfff00000) { 1060 tx_num = 2; 1061 rf_type = RF_2T2R; 1062 } 1063 1064 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1065 1066 ra_mask = rtw_update_rate_mask(rtwdev, si, ra_mask, is_vht_enable, 1067 wireless_set); 1068 1069 si->bw_mode = bw_mode; 1070 si->stbc_en = stbc_en; 1071 si->ldpc_en = ldpc_en; 1072 si->rf_type = rf_type; 1073 si->wireless_set = wireless_set; 1074 si->sgi_enable = is_support_sgi; 1075 si->vht_enable = is_vht_enable; 1076 si->ra_mask = ra_mask; 1077 si->rate_id = rate_id; 1078 1079 rtw_fw_send_ra_info(rtwdev, si); 1080 } 1081 1082 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1083 { 1084 struct rtw_chip_info *chip = rtwdev->chip; 1085 struct rtw_fw_state *fw; 1086 1087 fw = &rtwdev->fw; 1088 wait_for_completion(&fw->completion); 1089 if (!fw->firmware) 1090 return -EINVAL; 1091 1092 if (chip->wow_fw_name) { 1093 fw = &rtwdev->wow_fw; 1094 wait_for_completion(&fw->completion); 1095 if (!fw->firmware) 1096 return -EINVAL; 1097 } 1098 1099 return 0; 1100 } 1101 1102 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1103 struct rtw_fw_state *fw) 1104 { 1105 struct rtw_chip_info *chip = rtwdev->chip; 1106 1107 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1108 !fw->feature) 1109 return LPS_DEEP_MODE_NONE; 1110 1111 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1112 (fw->feature & FW_FEATURE_PG)) 1113 return LPS_DEEP_MODE_PG; 1114 1115 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1116 (fw->feature & FW_FEATURE_LCLK)) 1117 return LPS_DEEP_MODE_LCLK; 1118 1119 return LPS_DEEP_MODE_NONE; 1120 } 1121 1122 static int rtw_power_on(struct rtw_dev *rtwdev) 1123 { 1124 struct rtw_chip_info *chip = rtwdev->chip; 1125 struct rtw_fw_state *fw = &rtwdev->fw; 1126 bool wifi_only; 1127 int ret; 1128 1129 ret = rtw_hci_setup(rtwdev); 1130 if (ret) { 1131 rtw_err(rtwdev, "failed to setup hci\n"); 1132 goto err; 1133 } 1134 1135 /* power on MAC before firmware downloaded */ 1136 ret = rtw_mac_power_on(rtwdev); 1137 if (ret) { 1138 rtw_err(rtwdev, "failed to power on mac\n"); 1139 goto err; 1140 } 1141 1142 ret = rtw_wait_firmware_completion(rtwdev); 1143 if (ret) { 1144 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1145 goto err_off; 1146 } 1147 1148 ret = rtw_download_firmware(rtwdev, fw); 1149 if (ret) { 1150 rtw_err(rtwdev, "failed to download firmware\n"); 1151 goto err_off; 1152 } 1153 1154 /* config mac after firmware downloaded */ 1155 ret = rtw_mac_init(rtwdev); 1156 if (ret) { 1157 rtw_err(rtwdev, "failed to configure mac\n"); 1158 goto err_off; 1159 } 1160 1161 chip->ops->phy_set_param(rtwdev); 1162 1163 ret = rtw_hci_start(rtwdev); 1164 if (ret) { 1165 rtw_err(rtwdev, "failed to start hci\n"); 1166 goto err_off; 1167 } 1168 1169 /* send H2C after HCI has started */ 1170 rtw_fw_send_general_info(rtwdev); 1171 rtw_fw_send_phydm_info(rtwdev); 1172 1173 wifi_only = !rtwdev->efuse.btcoex; 1174 rtw_coex_power_on_setting(rtwdev); 1175 rtw_coex_init_hw_config(rtwdev, wifi_only); 1176 1177 return 0; 1178 1179 err_off: 1180 rtw_mac_power_off(rtwdev); 1181 1182 err: 1183 return ret; 1184 } 1185 1186 int rtw_core_start(struct rtw_dev *rtwdev) 1187 { 1188 int ret; 1189 1190 ret = rtw_power_on(rtwdev); 1191 if (ret) 1192 return ret; 1193 1194 rtw_sec_enable_sec_engine(rtwdev); 1195 1196 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1197 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1198 1199 /* rcr reset after powered on */ 1200 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1201 1202 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1203 RTW_WATCH_DOG_DELAY_TIME); 1204 1205 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1206 1207 return 0; 1208 } 1209 1210 static void rtw_power_off(struct rtw_dev *rtwdev) 1211 { 1212 rtw_hci_stop(rtwdev); 1213 rtw_coex_power_off_setting(rtwdev); 1214 rtw_mac_power_off(rtwdev); 1215 } 1216 1217 void rtw_core_stop(struct rtw_dev *rtwdev) 1218 { 1219 struct rtw_coex *coex = &rtwdev->coex; 1220 1221 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1222 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1223 1224 mutex_unlock(&rtwdev->mutex); 1225 1226 cancel_work_sync(&rtwdev->c2h_work); 1227 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1228 cancel_delayed_work_sync(&coex->bt_relink_work); 1229 cancel_delayed_work_sync(&coex->bt_reenable_work); 1230 cancel_delayed_work_sync(&coex->defreeze_work); 1231 cancel_delayed_work_sync(&coex->wl_remain_work); 1232 cancel_delayed_work_sync(&coex->bt_remain_work); 1233 cancel_delayed_work_sync(&coex->wl_connecting_work); 1234 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1235 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1236 1237 mutex_lock(&rtwdev->mutex); 1238 1239 rtw_power_off(rtwdev); 1240 } 1241 1242 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1243 struct ieee80211_sta_ht_cap *ht_cap) 1244 { 1245 struct rtw_efuse *efuse = &rtwdev->efuse; 1246 1247 ht_cap->ht_supported = true; 1248 ht_cap->cap = 0; 1249 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1250 IEEE80211_HT_CAP_MAX_AMSDU | 1251 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1252 1253 if (rtw_chip_has_rx_ldpc(rtwdev)) 1254 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1255 1256 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1257 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1258 IEEE80211_HT_CAP_DSSSCCK40 | 1259 IEEE80211_HT_CAP_SGI_40; 1260 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1261 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; 1262 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1263 if (efuse->hw_cap.nss > 1) { 1264 ht_cap->mcs.rx_mask[0] = 0xFF; 1265 ht_cap->mcs.rx_mask[1] = 0xFF; 1266 ht_cap->mcs.rx_mask[4] = 0x01; 1267 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1268 } else { 1269 ht_cap->mcs.rx_mask[0] = 0xFF; 1270 ht_cap->mcs.rx_mask[1] = 0x00; 1271 ht_cap->mcs.rx_mask[4] = 0x01; 1272 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1273 } 1274 } 1275 1276 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1277 struct ieee80211_sta_vht_cap *vht_cap) 1278 { 1279 struct rtw_efuse *efuse = &rtwdev->efuse; 1280 u16 mcs_map; 1281 __le16 highest; 1282 1283 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1284 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1285 return; 1286 1287 vht_cap->vht_supported = true; 1288 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1289 IEEE80211_VHT_CAP_SHORT_GI_80 | 1290 IEEE80211_VHT_CAP_RXSTBC_1 | 1291 IEEE80211_VHT_CAP_HTC_VHT | 1292 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1293 0; 1294 if (rtwdev->hal.rf_path_num > 1) 1295 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1296 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1297 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1298 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1299 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1300 1301 if (rtw_chip_has_rx_ldpc(rtwdev)) 1302 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1303 1304 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1305 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1306 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1307 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1308 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1309 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1310 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1311 if (efuse->hw_cap.nss > 1) { 1312 highest = cpu_to_le16(780); 1313 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1314 } else { 1315 highest = cpu_to_le16(390); 1316 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1317 } 1318 1319 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1320 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1321 vht_cap->vht_mcs.rx_highest = highest; 1322 vht_cap->vht_mcs.tx_highest = highest; 1323 } 1324 1325 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1326 struct rtw_chip_info *chip) 1327 { 1328 struct rtw_dev *rtwdev = hw->priv; 1329 struct ieee80211_supported_band *sband; 1330 1331 if (chip->band & RTW_BAND_2G) { 1332 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1333 if (!sband) 1334 goto err_out; 1335 if (chip->ht_supported) 1336 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1337 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1338 } 1339 1340 if (chip->band & RTW_BAND_5G) { 1341 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1342 if (!sband) 1343 goto err_out; 1344 if (chip->ht_supported) 1345 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1346 if (chip->vht_supported) 1347 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1348 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1349 } 1350 1351 return; 1352 1353 err_out: 1354 rtw_err(rtwdev, "failed to set supported band\n"); 1355 } 1356 1357 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1358 struct rtw_chip_info *chip) 1359 { 1360 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1361 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1362 } 1363 1364 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1365 struct rtw_fw_state *fw) 1366 { 1367 u32 feature; 1368 const struct rtw_fw_hdr *fw_hdr = 1369 (const struct rtw_fw_hdr *)fw->firmware->data; 1370 1371 feature = le32_to_cpu(fw_hdr->feature); 1372 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1373 } 1374 1375 static void __update_firmware_info(struct rtw_dev *rtwdev, 1376 struct rtw_fw_state *fw) 1377 { 1378 const struct rtw_fw_hdr *fw_hdr = 1379 (const struct rtw_fw_hdr *)fw->firmware->data; 1380 1381 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1382 fw->version = le16_to_cpu(fw_hdr->version); 1383 fw->sub_version = fw_hdr->subversion; 1384 fw->sub_index = fw_hdr->subindex; 1385 1386 __update_firmware_feature(rtwdev, fw); 1387 } 1388 1389 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1390 struct rtw_fw_state *fw) 1391 { 1392 struct rtw_fw_hdr_legacy *legacy = 1393 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1394 1395 fw->h2c_version = 0; 1396 fw->version = le16_to_cpu(legacy->version); 1397 fw->sub_version = legacy->subversion1; 1398 fw->sub_index = legacy->subversion2; 1399 } 1400 1401 static void update_firmware_info(struct rtw_dev *rtwdev, 1402 struct rtw_fw_state *fw) 1403 { 1404 if (rtw_chip_wcpu_11n(rtwdev)) 1405 __update_firmware_info_legacy(rtwdev, fw); 1406 else 1407 __update_firmware_info(rtwdev, fw); 1408 } 1409 1410 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1411 { 1412 struct rtw_fw_state *fw = context; 1413 struct rtw_dev *rtwdev = fw->rtwdev; 1414 1415 if (!firmware || !firmware->data) { 1416 rtw_err(rtwdev, "failed to request firmware\n"); 1417 complete_all(&fw->completion); 1418 return; 1419 } 1420 1421 fw->firmware = firmware; 1422 update_firmware_info(rtwdev, fw); 1423 complete_all(&fw->completion); 1424 1425 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1426 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1427 } 1428 1429 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1430 { 1431 const char *fw_name; 1432 struct rtw_fw_state *fw; 1433 int ret; 1434 1435 switch (type) { 1436 case RTW_WOWLAN_FW: 1437 fw = &rtwdev->wow_fw; 1438 fw_name = rtwdev->chip->wow_fw_name; 1439 break; 1440 1441 case RTW_NORMAL_FW: 1442 fw = &rtwdev->fw; 1443 fw_name = rtwdev->chip->fw_name; 1444 break; 1445 1446 default: 1447 rtw_warn(rtwdev, "unsupported firmware type\n"); 1448 return -ENOENT; 1449 } 1450 1451 fw->rtwdev = rtwdev; 1452 init_completion(&fw->completion); 1453 1454 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1455 GFP_KERNEL, fw, rtw_load_firmware_cb); 1456 if (ret) { 1457 rtw_err(rtwdev, "failed to async firmware request\n"); 1458 return ret; 1459 } 1460 1461 return 0; 1462 } 1463 1464 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1465 { 1466 struct rtw_chip_info *chip = rtwdev->chip; 1467 struct rtw_hal *hal = &rtwdev->hal; 1468 struct rtw_efuse *efuse = &rtwdev->efuse; 1469 1470 switch (rtw_hci_type(rtwdev)) { 1471 case RTW_HCI_TYPE_PCIE: 1472 rtwdev->hci.rpwm_addr = 0x03d9; 1473 rtwdev->hci.cpwm_addr = 0x03da; 1474 break; 1475 default: 1476 rtw_err(rtwdev, "unsupported hci type\n"); 1477 return -EINVAL; 1478 } 1479 1480 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1481 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1482 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1483 if (hal->chip_version & BIT_RF_TYPE_ID) { 1484 hal->rf_type = RF_2T2R; 1485 hal->rf_path_num = 2; 1486 hal->antenna_tx = BB_PATH_AB; 1487 hal->antenna_rx = BB_PATH_AB; 1488 } else { 1489 hal->rf_type = RF_1T1R; 1490 hal->rf_path_num = 1; 1491 hal->antenna_tx = BB_PATH_A; 1492 hal->antenna_rx = BB_PATH_A; 1493 } 1494 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1495 hal->rf_path_num; 1496 1497 efuse->physical_size = chip->phy_efuse_size; 1498 efuse->logical_size = chip->log_efuse_size; 1499 efuse->protect_size = chip->ptct_efuse_size; 1500 1501 /* default use ack */ 1502 rtwdev->hal.rcr |= BIT_VHT_DACK; 1503 1504 hal->bfee_sts_cap = 3; 1505 1506 return 0; 1507 } 1508 1509 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1510 { 1511 struct rtw_fw_state *fw = &rtwdev->fw; 1512 int ret; 1513 1514 ret = rtw_hci_setup(rtwdev); 1515 if (ret) { 1516 rtw_err(rtwdev, "failed to setup hci\n"); 1517 goto err; 1518 } 1519 1520 ret = rtw_mac_power_on(rtwdev); 1521 if (ret) { 1522 rtw_err(rtwdev, "failed to power on mac\n"); 1523 goto err; 1524 } 1525 1526 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1527 1528 wait_for_completion(&fw->completion); 1529 if (!fw->firmware) { 1530 ret = -EINVAL; 1531 rtw_err(rtwdev, "failed to load firmware\n"); 1532 goto err; 1533 } 1534 1535 ret = rtw_download_firmware(rtwdev, fw); 1536 if (ret) { 1537 rtw_err(rtwdev, "failed to download firmware\n"); 1538 goto err_off; 1539 } 1540 1541 return 0; 1542 1543 err_off: 1544 rtw_mac_power_off(rtwdev); 1545 1546 err: 1547 return ret; 1548 } 1549 1550 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1551 { 1552 struct rtw_efuse *efuse = &rtwdev->efuse; 1553 u8 hw_feature[HW_FEATURE_LEN]; 1554 u8 id; 1555 u8 bw; 1556 int i; 1557 1558 id = rtw_read8(rtwdev, REG_C2HEVT); 1559 if (id != C2H_HW_FEATURE_REPORT) { 1560 rtw_err(rtwdev, "failed to read hw feature report\n"); 1561 return -EBUSY; 1562 } 1563 1564 for (i = 0; i < HW_FEATURE_LEN; i++) 1565 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1566 1567 rtw_write8(rtwdev, REG_C2HEVT, 0); 1568 1569 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1570 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1571 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1572 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1573 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1574 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1575 1576 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1577 1578 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1579 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1580 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1581 1582 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1583 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1584 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1585 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1586 1587 return 0; 1588 } 1589 1590 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1591 { 1592 rtw_hci_stop(rtwdev); 1593 rtw_mac_power_off(rtwdev); 1594 } 1595 1596 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1597 { 1598 struct rtw_efuse *efuse = &rtwdev->efuse; 1599 int ret; 1600 1601 mutex_lock(&rtwdev->mutex); 1602 1603 /* power on mac to read efuse */ 1604 ret = rtw_chip_efuse_enable(rtwdev); 1605 if (ret) 1606 goto out_unlock; 1607 1608 ret = rtw_parse_efuse_map(rtwdev); 1609 if (ret) 1610 goto out_disable; 1611 1612 ret = rtw_dump_hw_feature(rtwdev); 1613 if (ret) 1614 goto out_disable; 1615 1616 ret = rtw_check_supported_rfe(rtwdev); 1617 if (ret) 1618 goto out_disable; 1619 1620 if (efuse->crystal_cap == 0xff) 1621 efuse->crystal_cap = 0; 1622 if (efuse->pa_type_2g == 0xff) 1623 efuse->pa_type_2g = 0; 1624 if (efuse->pa_type_5g == 0xff) 1625 efuse->pa_type_5g = 0; 1626 if (efuse->lna_type_2g == 0xff) 1627 efuse->lna_type_2g = 0; 1628 if (efuse->lna_type_5g == 0xff) 1629 efuse->lna_type_5g = 0; 1630 if (efuse->channel_plan == 0xff) 1631 efuse->channel_plan = 0x7f; 1632 if (efuse->rf_board_option == 0xff) 1633 efuse->rf_board_option = 0; 1634 if (efuse->bt_setting & BIT(0)) 1635 efuse->share_ant = true; 1636 if (efuse->regd == 0xff) 1637 efuse->regd = 0; 1638 if (efuse->tx_bb_swing_setting_2g == 0xff) 1639 efuse->tx_bb_swing_setting_2g = 0; 1640 if (efuse->tx_bb_swing_setting_5g == 0xff) 1641 efuse->tx_bb_swing_setting_5g = 0; 1642 1643 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1644 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1645 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1646 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1647 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1648 1649 out_disable: 1650 rtw_chip_efuse_disable(rtwdev); 1651 1652 out_unlock: 1653 mutex_unlock(&rtwdev->mutex); 1654 return ret; 1655 } 1656 1657 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1658 { 1659 struct rtw_hal *hal = &rtwdev->hal; 1660 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1661 1662 if (!rfe_def) 1663 return -ENODEV; 1664 1665 rtw_phy_setup_phy_cond(rtwdev, 0); 1666 1667 rtw_phy_init_tx_power(rtwdev); 1668 if (rfe_def->agc_btg_tbl) 1669 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1670 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1671 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1672 rtw_phy_tx_power_by_rate_config(hal); 1673 rtw_phy_tx_power_limit_config(hal); 1674 1675 return 0; 1676 } 1677 1678 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1679 { 1680 int ret; 1681 1682 ret = rtw_chip_parameter_setup(rtwdev); 1683 if (ret) { 1684 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1685 goto err_out; 1686 } 1687 1688 ret = rtw_chip_efuse_info_setup(rtwdev); 1689 if (ret) { 1690 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1691 goto err_out; 1692 } 1693 1694 ret = rtw_chip_board_info_setup(rtwdev); 1695 if (ret) { 1696 rtw_err(rtwdev, "failed to setup chip board info\n"); 1697 goto err_out; 1698 } 1699 1700 return 0; 1701 1702 err_out: 1703 return ret; 1704 } 1705 EXPORT_SYMBOL(rtw_chip_info_setup); 1706 1707 static void rtw_stats_init(struct rtw_dev *rtwdev) 1708 { 1709 struct rtw_traffic_stats *stats = &rtwdev->stats; 1710 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1711 int i; 1712 1713 ewma_tp_init(&stats->tx_ewma_tp); 1714 ewma_tp_init(&stats->rx_ewma_tp); 1715 1716 for (i = 0; i < RTW_EVM_NUM; i++) 1717 ewma_evm_init(&dm_info->ewma_evm[i]); 1718 for (i = 0; i < RTW_SNR_NUM; i++) 1719 ewma_snr_init(&dm_info->ewma_snr[i]); 1720 } 1721 1722 int rtw_core_init(struct rtw_dev *rtwdev) 1723 { 1724 struct rtw_chip_info *chip = rtwdev->chip; 1725 struct rtw_coex *coex = &rtwdev->coex; 1726 int ret; 1727 1728 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 1729 INIT_LIST_HEAD(&rtwdev->txqs); 1730 1731 timer_setup(&rtwdev->tx_report.purge_timer, 1732 rtw_tx_report_purge_timer, 0); 1733 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 1734 1735 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 1736 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 1737 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 1738 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 1739 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 1740 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 1741 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 1742 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 1743 rtw_coex_bt_multi_link_remain_work); 1744 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 1745 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 1746 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 1747 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 1748 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 1749 skb_queue_head_init(&rtwdev->c2h_queue); 1750 skb_queue_head_init(&rtwdev->coex.queue); 1751 skb_queue_head_init(&rtwdev->tx_report.queue); 1752 1753 spin_lock_init(&rtwdev->rf_lock); 1754 spin_lock_init(&rtwdev->h2c.lock); 1755 spin_lock_init(&rtwdev->txq_lock); 1756 spin_lock_init(&rtwdev->tx_report.q_lock); 1757 1758 mutex_init(&rtwdev->mutex); 1759 mutex_init(&rtwdev->coex.mutex); 1760 mutex_init(&rtwdev->hal.tx_power_mutex); 1761 1762 init_waitqueue_head(&rtwdev->coex.wait); 1763 init_completion(&rtwdev->lps_leave_check); 1764 1765 rtwdev->sec.total_cam_num = 32; 1766 rtwdev->hal.current_channel = 1; 1767 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 1768 1769 rtw_stats_init(rtwdev); 1770 1771 /* default rx filter setting */ 1772 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 1773 BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 1774 BIT_AB | BIT_AM | BIT_APM; 1775 1776 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 1777 if (ret) { 1778 rtw_warn(rtwdev, "no firmware loaded\n"); 1779 return ret; 1780 } 1781 1782 if (chip->wow_fw_name) { 1783 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 1784 if (ret) { 1785 rtw_warn(rtwdev, "no wow firmware loaded\n"); 1786 wait_for_completion(&rtwdev->fw.completion); 1787 if (rtwdev->fw.firmware) 1788 release_firmware(rtwdev->fw.firmware); 1789 return ret; 1790 } 1791 } 1792 1793 return 0; 1794 } 1795 EXPORT_SYMBOL(rtw_core_init); 1796 1797 void rtw_core_deinit(struct rtw_dev *rtwdev) 1798 { 1799 struct rtw_fw_state *fw = &rtwdev->fw; 1800 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 1801 struct rtw_rsvd_page *rsvd_pkt, *tmp; 1802 unsigned long flags; 1803 1804 rtw_wait_firmware_completion(rtwdev); 1805 1806 if (fw->firmware) 1807 release_firmware(fw->firmware); 1808 1809 if (wow_fw->firmware) 1810 release_firmware(wow_fw->firmware); 1811 1812 destroy_workqueue(rtwdev->tx_wq); 1813 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 1814 skb_queue_purge(&rtwdev->tx_report.queue); 1815 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 1816 1817 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 1818 build_list) { 1819 list_del(&rsvd_pkt->build_list); 1820 kfree(rsvd_pkt); 1821 } 1822 1823 mutex_destroy(&rtwdev->mutex); 1824 mutex_destroy(&rtwdev->coex.mutex); 1825 mutex_destroy(&rtwdev->hal.tx_power_mutex); 1826 } 1827 EXPORT_SYMBOL(rtw_core_deinit); 1828 1829 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1830 { 1831 struct rtw_hal *hal = &rtwdev->hal; 1832 int max_tx_headroom = 0; 1833 int ret; 1834 1835 /* TODO: USB & SDIO may need extra room? */ 1836 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 1837 1838 hw->extra_tx_headroom = max_tx_headroom; 1839 hw->queues = IEEE80211_NUM_ACS; 1840 hw->txq_data_size = sizeof(struct rtw_txq); 1841 hw->sta_data_size = sizeof(struct rtw_sta_info); 1842 hw->vif_data_size = sizeof(struct rtw_vif); 1843 1844 ieee80211_hw_set(hw, SIGNAL_DBM); 1845 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 1846 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 1847 ieee80211_hw_set(hw, MFP_CAPABLE); 1848 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 1849 ieee80211_hw_set(hw, SUPPORTS_PS); 1850 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 1851 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 1852 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 1853 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 1854 ieee80211_hw_set(hw, TX_AMSDU); 1855 1856 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 1857 BIT(NL80211_IFTYPE_AP) | 1858 BIT(NL80211_IFTYPE_ADHOC) | 1859 BIT(NL80211_IFTYPE_MESH_POINT); 1860 hw->wiphy->available_antennas_tx = hal->antenna_tx; 1861 hw->wiphy->available_antennas_rx = hal->antenna_rx; 1862 1863 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 1864 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 1865 1866 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 1867 1868 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 1869 1870 #ifdef CONFIG_PM 1871 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 1872 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 1873 #endif 1874 rtw_set_supported_band(hw, rtwdev->chip); 1875 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 1876 1877 rtw_regd_init(rtwdev, rtw_regd_notifier); 1878 1879 ret = ieee80211_register_hw(hw); 1880 if (ret) { 1881 rtw_err(rtwdev, "failed to register hw\n"); 1882 return ret; 1883 } 1884 1885 if (regulatory_hint(hw->wiphy, rtwdev->regd.alpha2)) 1886 rtw_err(rtwdev, "regulatory_hint fail\n"); 1887 1888 rtw_debugfs_init(rtwdev); 1889 1890 rtwdev->bf_info.bfer_mu_cnt = 0; 1891 rtwdev->bf_info.bfer_su_cnt = 0; 1892 1893 return 0; 1894 } 1895 EXPORT_SYMBOL(rtw_register_hw); 1896 1897 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 1898 { 1899 struct rtw_chip_info *chip = rtwdev->chip; 1900 1901 ieee80211_unregister_hw(hw); 1902 rtw_unset_supported_band(hw, chip); 1903 } 1904 EXPORT_SYMBOL(rtw_unregister_hw); 1905 1906 MODULE_AUTHOR("Realtek Corporation"); 1907 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 1908 MODULE_LICENSE("Dual BSD/GPL"); 1909