1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "mac.h" 7 #include "reg.h" 8 #include "fw.h" 9 #include "debug.h" 10 11 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 12 u8 primary_ch_idx) 13 { 14 u8 txsc40 = 0, txsc20 = 0; 15 u32 value32; 16 u8 value8; 17 18 txsc20 = primary_ch_idx; 19 if (txsc20 == 1 || txsc20 == 3) 20 txsc40 = 9; 21 else 22 txsc40 = 10; 23 rtw_write8(rtwdev, REG_DATA_SC, 24 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 25 26 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 27 value32 &= ~BIT_RFMOD; 28 switch (bw) { 29 case RTW_CHANNEL_WIDTH_80: 30 value32 |= BIT_RFMOD_80M; 31 break; 32 case RTW_CHANNEL_WIDTH_40: 33 value32 |= BIT_RFMOD_40M; 34 break; 35 case RTW_CHANNEL_WIDTH_20: 36 default: 37 break; 38 } 39 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 40 41 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 42 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 43 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 44 45 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 46 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 47 48 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 49 value8 = value8 & ~BIT_CHECK_CCK_EN; 50 if (channel > 35) 51 value8 |= BIT_CHECK_CCK_EN; 52 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 53 } 54 55 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 56 { 57 u32 value32; 58 u8 value8; 59 60 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 61 62 switch (rtw_hci_type(rtwdev)) { 63 case RTW_HCI_TYPE_PCIE: 64 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN); 65 break; 66 case RTW_HCI_TYPE_USB: 67 break; 68 default: 69 return -EINVAL; 70 } 71 72 /* config PIN Mux */ 73 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 74 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 75 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 76 77 value32 = rtw_read32(rtwdev, REG_LED_CFG); 78 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 79 rtw_write32(rtwdev, REG_LED_CFG, value32); 80 81 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 82 value32 |= BIT_WLRFE_4_5_EN; 83 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 84 85 /* disable BB/RF */ 86 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 87 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 88 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 89 90 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 91 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 92 rtw_write8(rtwdev, REG_RF_CTRL, value8); 93 94 value32 = rtw_read32(rtwdev, REG_WLRF1); 95 value32 &= ~BIT_WLRF1_BBRF_EN; 96 rtw_write32(rtwdev, REG_WLRF1, value32); 97 98 return 0; 99 } 100 101 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 102 struct rtw_pwr_seq_cmd *cmd) 103 { 104 u8 value; 105 u8 flag = 0; 106 u32 offset; 107 u32 cnt = RTW_PWR_POLLING_CNT; 108 109 if (cmd->base == RTW_PWR_ADDR_SDIO) 110 offset = cmd->offset | SDIO_LOCAL_OFFSET; 111 else 112 offset = cmd->offset; 113 114 do { 115 cnt--; 116 value = rtw_read8(rtwdev, offset); 117 value &= cmd->mask; 118 if (value == (cmd->value & cmd->mask)) 119 return 0; 120 if (cnt == 0) { 121 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE && 122 flag == 0) { 123 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 124 value |= BIT(3); 125 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value); 126 value &= ~BIT(3); 127 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value); 128 cnt = RTW_PWR_POLLING_CNT; 129 flag = 1; 130 } else { 131 return -EBUSY; 132 } 133 } else { 134 udelay(50); 135 } 136 } while (1); 137 } 138 139 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 140 u8 cut_mask, struct rtw_pwr_seq_cmd *cmd) 141 { 142 struct rtw_pwr_seq_cmd *cur_cmd; 143 u32 offset; 144 u8 value; 145 146 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 147 if (!(cur_cmd->intf_mask & intf_mask) || 148 !(cur_cmd->cut_mask & cut_mask)) 149 continue; 150 151 switch (cur_cmd->cmd) { 152 case RTW_PWR_CMD_WRITE: 153 offset = cur_cmd->offset; 154 155 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 156 offset |= SDIO_LOCAL_OFFSET; 157 158 value = rtw_read8(rtwdev, offset); 159 value &= ~cur_cmd->mask; 160 value |= (cur_cmd->value & cur_cmd->mask); 161 rtw_write8(rtwdev, offset, value); 162 break; 163 case RTW_PWR_CMD_POLLING: 164 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 165 return -EBUSY; 166 break; 167 case RTW_PWR_CMD_DELAY: 168 if (cur_cmd->value == RTW_PWR_DELAY_US) 169 udelay(cur_cmd->offset); 170 else 171 mdelay(cur_cmd->offset); 172 break; 173 case RTW_PWR_CMD_READ: 174 break; 175 default: 176 return -EINVAL; 177 } 178 } 179 180 return 0; 181 } 182 183 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 184 struct rtw_pwr_seq_cmd **cmd_seq) 185 { 186 u8 cut_mask; 187 u8 intf_mask; 188 u8 cut; 189 u32 idx = 0; 190 struct rtw_pwr_seq_cmd *cmd; 191 int ret; 192 193 cut = rtwdev->hal.cut_version; 194 cut_mask = cut_version_to_mask(cut); 195 switch (rtw_hci_type(rtwdev)) { 196 case RTW_HCI_TYPE_PCIE: 197 intf_mask = BIT(2); 198 break; 199 case RTW_HCI_TYPE_USB: 200 intf_mask = BIT(1); 201 break; 202 default: 203 return -EINVAL; 204 } 205 206 do { 207 cmd = cmd_seq[idx]; 208 if (!cmd) 209 break; 210 211 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 212 if (ret) 213 return -EBUSY; 214 215 idx++; 216 } while (1); 217 218 return 0; 219 } 220 221 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 222 { 223 struct rtw_chip_info *chip = rtwdev->chip; 224 struct rtw_pwr_seq_cmd **pwr_seq; 225 u8 rpwm; 226 bool cur_pwr; 227 228 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 229 230 /* Check FW still exist or not */ 231 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 232 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 233 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 234 } 235 236 if (rtw_read8(rtwdev, REG_CR) == 0xea) 237 cur_pwr = false; 238 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 239 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 240 cur_pwr = false; 241 else 242 cur_pwr = true; 243 244 if (pwr_on && cur_pwr) 245 return -EALREADY; 246 247 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 248 if (rtw_pwr_seq_parser(rtwdev, pwr_seq)) 249 return -EINVAL; 250 251 return 0; 252 } 253 254 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 255 { 256 u8 sys_func_en = rtwdev->chip->sys_func_en; 257 u8 value8; 258 u32 value, tmp; 259 260 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 261 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 262 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 263 264 rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 265 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 266 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 267 268 /* disable boot-from-flash for driver's DL FW */ 269 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 270 if (tmp & BIT_BOOT_FSPI_EN) { 271 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 272 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 273 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 274 } 275 276 return 0; 277 } 278 279 int rtw_mac_power_on(struct rtw_dev *rtwdev) 280 { 281 int ret = 0; 282 283 ret = rtw_mac_pre_system_cfg(rtwdev); 284 if (ret) 285 goto err; 286 287 ret = rtw_mac_power_switch(rtwdev, true); 288 if (ret) 289 goto err; 290 291 ret = rtw_mac_init_system_cfg(rtwdev); 292 if (ret) 293 goto err; 294 295 return 0; 296 297 err: 298 rtw_err(rtwdev, "mac power on failed"); 299 return ret; 300 } 301 302 void rtw_mac_power_off(struct rtw_dev *rtwdev) 303 { 304 rtw_mac_power_switch(rtwdev, false); 305 } 306 307 static bool check_firmware_size(const u8 *data, u32 size) 308 { 309 u32 dmem_size; 310 u32 imem_size; 311 u32 emem_size; 312 u32 real_size; 313 314 dmem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_DMEM_SIZE))); 315 imem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_IMEM_SIZE))); 316 emem_size = ((*(data + FW_HDR_MEM_USAGE)) & BIT(4)) ? 317 le32_to_cpu(*((__le32 *)(data + FW_HDR_EMEM_SIZE))) : 0; 318 319 dmem_size += FW_HDR_CHKSUM_SIZE; 320 imem_size += FW_HDR_CHKSUM_SIZE; 321 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 322 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 323 if (real_size != size) 324 return false; 325 326 return true; 327 } 328 329 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 330 { 331 if (enable) { 332 /* cpu io interface enable */ 333 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 334 335 /* cpu enable */ 336 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 337 } else { 338 /* cpu io interface disable */ 339 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 340 341 /* cpu disable */ 342 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 343 } 344 } 345 346 #define DLFW_RESTORE_REG_NUM 6 347 348 static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 349 struct rtw_backup_info *bckp) 350 { 351 u8 tmp; 352 u8 bckp_idx = 0; 353 354 /* set HIQ to hi priority */ 355 bckp[bckp_idx].len = 1; 356 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 357 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 358 bckp_idx++; 359 tmp = RTW_DMA_MAPPING_HIGH << 6; 360 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 361 362 /* DLFW only use HIQ, map HIQ to hi priority */ 363 bckp[bckp_idx].len = 1; 364 bckp[bckp_idx].reg = REG_CR; 365 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 366 bckp_idx++; 367 bckp[bckp_idx].len = 4; 368 bckp[bckp_idx].reg = REG_H2CQ_CSR; 369 bckp[bckp_idx].val = BIT_H2CQ_FULL; 370 bckp_idx++; 371 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 372 rtw_write8(rtwdev, REG_CR, tmp); 373 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 374 375 /* Config hi priority queue and public priority queue page number */ 376 bckp[bckp_idx].len = 2; 377 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 378 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 379 bckp_idx++; 380 bckp[bckp_idx].len = 4; 381 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 382 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 383 bckp_idx++; 384 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 385 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 386 387 /* Disable beacon related functions */ 388 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 389 bckp[bckp_idx].len = 1; 390 bckp[bckp_idx].reg = REG_BCN_CTRL; 391 bckp[bckp_idx].val = tmp; 392 bckp_idx++; 393 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 394 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 395 396 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 397 } 398 399 static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 400 { 401 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 402 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 403 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 404 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 405 } 406 407 static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 408 struct rtw_backup_info *bckp, 409 u8 bckp_num) 410 { 411 rtw_restore_reg(rtwdev, bckp, bckp_num); 412 } 413 414 #define TX_DESC_SIZE 48 415 416 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 417 const u8 *data, u32 size) 418 { 419 u8 *buf; 420 int ret; 421 422 buf = kmemdup(data, size, GFP_KERNEL); 423 if (!buf) 424 return -ENOMEM; 425 426 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 427 kfree(buf); 428 return ret; 429 } 430 431 static int 432 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 433 { 434 int ret; 435 436 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 437 !((size + TX_DESC_SIZE) & (512 - 1))) 438 size += 1; 439 440 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 441 if (ret) 442 rtw_err(rtwdev, "failed to download rsvd page\n"); 443 444 return ret; 445 } 446 447 static int 448 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 449 { 450 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 451 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 452 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 453 454 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 455 return -EBUSY; 456 457 return 0; 458 } 459 460 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 461 u32 len, u8 first) 462 { 463 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 464 465 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 466 return -EBUSY; 467 468 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 469 if (!first) 470 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 471 472 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 473 return -EBUSY; 474 475 return 0; 476 } 477 478 static bool 479 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 480 { 481 u8 fw_ctrl; 482 483 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 484 485 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 486 if (addr < OCPBASE_DMEM_88XX) { 487 fw_ctrl |= BIT_IMEM_DW_OK; 488 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 489 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 490 } else { 491 fw_ctrl |= BIT_DMEM_DW_OK; 492 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 493 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 494 } 495 496 rtw_err(rtwdev, "invalid fw checksum\n"); 497 498 return false; 499 } 500 501 if (addr < OCPBASE_DMEM_88XX) { 502 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 503 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 504 } else { 505 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 506 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 507 } 508 509 return true; 510 } 511 512 static int 513 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 514 u32 src, u32 dst, u32 size) 515 { 516 struct rtw_chip_info *chip = rtwdev->chip; 517 u32 desc_size = chip->tx_pkt_desc_sz; 518 u8 first_part; 519 u32 mem_offset; 520 u32 residue_size; 521 u32 pkt_size; 522 u32 max_size = 0x1000; 523 u32 val; 524 int ret; 525 526 mem_offset = 0; 527 first_part = 1; 528 residue_size = size; 529 530 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 531 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 532 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 533 534 while (residue_size) { 535 if (residue_size >= max_size) 536 pkt_size = max_size; 537 else 538 pkt_size = residue_size; 539 540 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 541 data + mem_offset, pkt_size); 542 if (ret) 543 return ret; 544 545 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 546 src + desc_size, 547 dst + mem_offset, pkt_size, 548 first_part); 549 if (ret) 550 return ret; 551 552 first_part = 0; 553 mem_offset += pkt_size; 554 residue_size -= pkt_size; 555 } 556 557 if (!check_fw_checksum(rtwdev, dst)) 558 return -EINVAL; 559 560 return 0; 561 } 562 563 static void update_firmware_info(struct rtw_dev *rtwdev, 564 struct rtw_fw_state *fw) 565 { 566 const u8 *data = fw->firmware->data; 567 568 fw->h2c_version = 569 le16_to_cpu(*((__le16 *)(data + FW_HDR_H2C_FMT_VER))); 570 fw->version = 571 le16_to_cpu(*((__le16 *)(data + FW_HDR_VERSION))); 572 fw->sub_version = *(data + FW_HDR_SUBVERSION); 573 fw->sub_index = *(data + FW_HDR_SUBINDEX); 574 575 rtw_dbg(rtwdev, RTW_DBG_FW, "fw h2c version: %x\n", fw->h2c_version); 576 rtw_dbg(rtwdev, RTW_DBG_FW, "fw version: %x\n", fw->version); 577 rtw_dbg(rtwdev, RTW_DBG_FW, "fw sub version: %x\n", fw->sub_version); 578 rtw_dbg(rtwdev, RTW_DBG_FW, "fw sub index: %x\n", fw->sub_index); 579 } 580 581 static int 582 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 583 { 584 const u8 *cur_fw; 585 u16 val; 586 u32 imem_size; 587 u32 dmem_size; 588 u32 emem_size; 589 u32 addr; 590 int ret; 591 592 dmem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_DMEM_SIZE))); 593 imem_size = le32_to_cpu(*((__le32 *)(data + FW_HDR_IMEM_SIZE))); 594 emem_size = ((*(data + FW_HDR_MEM_USAGE)) & BIT(4)) ? 595 le32_to_cpu(*((__le32 *)(data + FW_HDR_EMEM_SIZE))) : 0; 596 dmem_size += FW_HDR_CHKSUM_SIZE; 597 imem_size += FW_HDR_CHKSUM_SIZE; 598 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 599 600 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 601 val |= BIT_MCUFWDL_EN; 602 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 603 604 cur_fw = data + FW_HDR_SIZE; 605 addr = le32_to_cpu(*((__le32 *)(data + FW_HDR_DMEM_ADDR))); 606 addr &= ~BIT(31); 607 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 608 if (ret) 609 return ret; 610 611 cur_fw = data + FW_HDR_SIZE + dmem_size; 612 addr = le32_to_cpu(*((__le32 *)(data + FW_HDR_IMEM_ADDR))); 613 addr &= ~BIT(31); 614 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 615 if (ret) 616 return ret; 617 618 if (emem_size) { 619 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 620 addr = le32_to_cpu(*((__le32 *)(data + FW_HDR_EMEM_ADDR))); 621 addr &= ~BIT(31); 622 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 623 emem_size); 624 if (ret) 625 return ret; 626 } 627 628 return 0; 629 } 630 631 static int download_firmware_validate(struct rtw_dev *rtwdev) 632 { 633 u32 fw_key; 634 635 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 636 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 637 if (fw_key == ILLEGAL_KEY_GROUP) 638 rtw_err(rtwdev, "invalid fw key\n"); 639 return -EINVAL; 640 } 641 642 return 0; 643 } 644 645 static void download_firmware_end_flow(struct rtw_dev *rtwdev) 646 { 647 u16 fw_ctrl; 648 649 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 650 651 /* Check IMEM & DMEM checksum is OK or not */ 652 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 653 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 654 return; 655 656 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 657 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 658 } 659 660 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 661 { 662 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 663 const u8 *data = fw->firmware->data; 664 u32 size = fw->firmware->size; 665 u32 ltecoex_bckp; 666 int ret; 667 668 if (!check_firmware_size(data, size)) 669 return -EINVAL; 670 671 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 672 return -EBUSY; 673 674 wlan_cpu_enable(rtwdev, false); 675 676 download_firmware_reg_backup(rtwdev, bckp); 677 download_firmware_reset_platform(rtwdev); 678 679 ret = start_download_firmware(rtwdev, data, size); 680 if (ret) 681 goto dlfw_fail; 682 683 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 684 685 download_firmware_end_flow(rtwdev); 686 687 wlan_cpu_enable(rtwdev, true); 688 689 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) 690 return -EBUSY; 691 692 ret = download_firmware_validate(rtwdev); 693 if (ret) 694 goto dlfw_fail; 695 696 update_firmware_info(rtwdev, fw); 697 698 /* reset desc and index */ 699 rtw_hci_setup(rtwdev); 700 701 rtwdev->h2c.last_box_num = 0; 702 rtwdev->h2c.seq = 0; 703 704 rtw_fw_send_general_info(rtwdev); 705 rtw_fw_send_phydm_info(rtwdev); 706 707 rtw_flag_set(rtwdev, RTW_FLAG_FW_RUNNING); 708 709 return 0; 710 711 dlfw_fail: 712 /* Disable FWDL_EN */ 713 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 714 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 715 716 return ret; 717 } 718 719 static int txdma_queue_mapping(struct rtw_dev *rtwdev) 720 { 721 struct rtw_chip_info *chip = rtwdev->chip; 722 struct rtw_rqpn *rqpn = NULL; 723 u16 txdma_pq_map = 0; 724 725 switch (rtw_hci_type(rtwdev)) { 726 case RTW_HCI_TYPE_PCIE: 727 rqpn = &chip->rqpn_table[1]; 728 break; 729 case RTW_HCI_TYPE_USB: 730 if (rtwdev->hci.bulkout_num == 2) 731 rqpn = &chip->rqpn_table[2]; 732 else if (rtwdev->hci.bulkout_num == 3) 733 rqpn = &chip->rqpn_table[3]; 734 else if (rtwdev->hci.bulkout_num == 4) 735 rqpn = &chip->rqpn_table[4]; 736 else 737 return -EINVAL; 738 break; 739 default: 740 return -EINVAL; 741 } 742 743 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 744 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 745 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 746 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 747 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 748 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 749 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 750 751 rtw_write8(rtwdev, REG_CR, 0); 752 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 753 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 754 755 return 0; 756 } 757 758 static int set_trx_fifo_info(struct rtw_dev *rtwdev) 759 { 760 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 761 struct rtw_chip_info *chip = rtwdev->chip; 762 u16 cur_pg_addr; 763 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 764 765 /* config rsvd page num */ 766 fifo->rsvd_drv_pg_num = 8; 767 fifo->txff_pg_num = chip->txff_size >> 7; 768 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 769 RSVD_PG_H2C_EXTRAINFO_NUM + 770 RSVD_PG_H2C_STATICINFO_NUM + 771 RSVD_PG_H2CQ_NUM + 772 RSVD_PG_CPU_INSTRUCTION_NUM + 773 RSVD_PG_FW_TXBUF_NUM + 774 csi_buf_pg_num; 775 776 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 777 return -ENOMEM; 778 779 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 780 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 781 782 cur_pg_addr = fifo->txff_pg_num; 783 cur_pg_addr -= csi_buf_pg_num; 784 fifo->rsvd_csibuf_addr = cur_pg_addr; 785 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 786 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 787 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 788 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 789 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 790 fifo->rsvd_h2cq_addr = cur_pg_addr; 791 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 792 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 793 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 794 fifo->rsvd_h2c_info_addr = cur_pg_addr; 795 cur_pg_addr -= fifo->rsvd_drv_pg_num; 796 fifo->rsvd_drv_addr = cur_pg_addr; 797 798 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 799 rtw_err(rtwdev, "wrong rsvd driver address\n"); 800 return -EINVAL; 801 } 802 803 return 0; 804 } 805 806 static int priority_queue_cfg(struct rtw_dev *rtwdev) 807 { 808 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 809 struct rtw_chip_info *chip = rtwdev->chip; 810 struct rtw_page_table *pg_tbl = NULL; 811 u16 pubq_num; 812 int ret; 813 814 ret = set_trx_fifo_info(rtwdev); 815 if (ret) 816 return ret; 817 818 switch (rtw_hci_type(rtwdev)) { 819 case RTW_HCI_TYPE_PCIE: 820 pg_tbl = &chip->page_table[1]; 821 break; 822 case RTW_HCI_TYPE_USB: 823 if (rtwdev->hci.bulkout_num == 2) 824 pg_tbl = &chip->page_table[2]; 825 else if (rtwdev->hci.bulkout_num == 3) 826 pg_tbl = &chip->page_table[3]; 827 else if (rtwdev->hci.bulkout_num == 4) 828 pg_tbl = &chip->page_table[4]; 829 else 830 return -EINVAL; 831 break; 832 default: 833 return -EINVAL; 834 } 835 836 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 837 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 838 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 839 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 840 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 841 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 842 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 843 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 844 845 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 846 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 847 848 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 849 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 850 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 851 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 852 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 853 854 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 855 return -EBUSY; 856 857 rtw_write8(rtwdev, REG_CR + 3, 0); 858 859 return 0; 860 } 861 862 static int init_h2c(struct rtw_dev *rtwdev) 863 { 864 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 865 u8 value8; 866 u32 value32; 867 u32 h2cq_addr; 868 u32 h2cq_size; 869 u32 h2cq_free; 870 u32 wp, rp; 871 872 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 873 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 874 875 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 876 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 877 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 878 879 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 880 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 881 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 882 883 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 884 value32 &= 0xFFFC0000; 885 value32 |= (h2cq_addr + h2cq_size); 886 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 887 888 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 889 value8 = (u8)((value8 & 0xFC) | 0x01); 890 rtw_write8(rtwdev, REG_H2C_INFO, value8); 891 892 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 893 value8 = (u8)((value8 & 0xFB) | 0x04); 894 rtw_write8(rtwdev, REG_H2C_INFO, value8); 895 896 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 897 value8 = (u8)((value8 & 0x7f) | 0x80); 898 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 899 900 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 901 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 902 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 903 904 if (h2cq_size != h2cq_free) { 905 rtw_err(rtwdev, "H2C queue mismatch\n"); 906 return -EINVAL; 907 } 908 909 return 0; 910 } 911 912 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 913 { 914 int ret; 915 916 ret = txdma_queue_mapping(rtwdev); 917 if (ret) 918 return ret; 919 920 ret = priority_queue_cfg(rtwdev); 921 if (ret) 922 return ret; 923 924 ret = init_h2c(rtwdev); 925 if (ret) 926 return ret; 927 928 return 0; 929 } 930 931 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 932 { 933 u8 value8; 934 935 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 936 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 937 value8 &= 0xF0; 938 /* For rxdesc len = 0 issue */ 939 value8 |= 0xF; 940 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 941 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 942 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 943 944 return 0; 945 } 946 947 int rtw_mac_init(struct rtw_dev *rtwdev) 948 { 949 struct rtw_chip_info *chip = rtwdev->chip; 950 int ret; 951 952 ret = rtw_init_trx_cfg(rtwdev); 953 if (ret) 954 return ret; 955 956 ret = chip->ops->mac_init(rtwdev); 957 if (ret) 958 return ret; 959 960 ret = rtw_drv_info_cfg(rtwdev); 961 if (ret) 962 return ret; 963 964 return 0; 965 } 966