1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "mac.h" 7 #include "reg.h" 8 #include "fw.h" 9 #include "debug.h" 10 11 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 12 u8 primary_ch_idx) 13 { 14 u8 txsc40 = 0, txsc20 = 0; 15 u32 value32; 16 u8 value8; 17 18 txsc20 = primary_ch_idx; 19 if (bw == RTW_CHANNEL_WIDTH_80) { 20 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 21 txsc40 = RTW_SC_40_UPPER; 22 else 23 txsc40 = RTW_SC_40_LOWER; 24 } 25 rtw_write8(rtwdev, REG_DATA_SC, 26 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 27 28 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 29 value32 &= ~BIT_RFMOD; 30 switch (bw) { 31 case RTW_CHANNEL_WIDTH_80: 32 value32 |= BIT_RFMOD_80M; 33 break; 34 case RTW_CHANNEL_WIDTH_40: 35 value32 |= BIT_RFMOD_40M; 36 break; 37 case RTW_CHANNEL_WIDTH_20: 38 default: 39 break; 40 } 41 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 42 43 if (rtw_chip_wcpu_11n(rtwdev)) 44 return; 45 46 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 47 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 48 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 49 50 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 51 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 52 53 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 54 value8 = value8 & ~BIT_CHECK_CCK_EN; 55 if (IS_CH_5G_BAND(channel)) 56 value8 |= BIT_CHECK_CCK_EN; 57 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 58 } 59 EXPORT_SYMBOL(rtw_set_channel_mac); 60 61 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 62 { 63 u32 value32; 64 u8 value8; 65 66 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 67 68 if (rtw_chip_wcpu_11n(rtwdev)) { 69 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO) 70 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL); 71 else 72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL); 73 return 0; 74 } 75 76 switch (rtw_hci_type(rtwdev)) { 77 case RTW_HCI_TYPE_PCIE: 78 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 79 break; 80 case RTW_HCI_TYPE_USB: 81 break; 82 default: 83 return -EINVAL; 84 } 85 86 /* config PIN Mux */ 87 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 88 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 89 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 90 91 value32 = rtw_read32(rtwdev, REG_LED_CFG); 92 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 93 rtw_write32(rtwdev, REG_LED_CFG, value32); 94 95 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 96 value32 |= BIT_WLRFE_4_5_EN; 97 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 98 99 /* disable BB/RF */ 100 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 101 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 102 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 103 104 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 105 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 106 rtw_write8(rtwdev, REG_RF_CTRL, value8); 107 108 value32 = rtw_read32(rtwdev, REG_WLRF1); 109 value32 &= ~BIT_WLRF1_BBRF_EN; 110 rtw_write32(rtwdev, REG_WLRF1, value32); 111 112 return 0; 113 } 114 115 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) 116 { 117 u32 val; 118 119 target &= mask; 120 121 return read_poll_timeout_atomic(rtw_read8, val, (val & mask) == target, 122 50, 50 * RTW_PWR_POLLING_CNT, false, 123 rtwdev, addr) == 0; 124 } 125 126 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 127 const struct rtw_pwr_seq_cmd *cmd) 128 { 129 u8 value; 130 u32 offset; 131 132 if (cmd->base == RTW_PWR_ADDR_SDIO) 133 offset = cmd->offset | SDIO_LOCAL_OFFSET; 134 else 135 offset = cmd->offset; 136 137 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 138 return 0; 139 140 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE) 141 goto err; 142 143 /* if PCIE, toggle BIT_PFM_WOWL and try again */ 144 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 145 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 146 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 147 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 148 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 149 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 150 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 151 152 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 153 return 0; 154 155 err: 156 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n", 157 offset, cmd->mask, cmd->value); 158 return -EBUSY; 159 } 160 161 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 162 u8 cut_mask, 163 const struct rtw_pwr_seq_cmd *cmd) 164 { 165 const struct rtw_pwr_seq_cmd *cur_cmd; 166 u32 offset; 167 u8 value; 168 169 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 170 if (!(cur_cmd->intf_mask & intf_mask) || 171 !(cur_cmd->cut_mask & cut_mask)) 172 continue; 173 174 switch (cur_cmd->cmd) { 175 case RTW_PWR_CMD_WRITE: 176 offset = cur_cmd->offset; 177 178 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 179 offset |= SDIO_LOCAL_OFFSET; 180 181 value = rtw_read8(rtwdev, offset); 182 value &= ~cur_cmd->mask; 183 value |= (cur_cmd->value & cur_cmd->mask); 184 rtw_write8(rtwdev, offset, value); 185 break; 186 case RTW_PWR_CMD_POLLING: 187 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 188 return -EBUSY; 189 break; 190 case RTW_PWR_CMD_DELAY: 191 if (cur_cmd->value == RTW_PWR_DELAY_US) 192 udelay(cur_cmd->offset); 193 else 194 mdelay(cur_cmd->offset); 195 break; 196 case RTW_PWR_CMD_READ: 197 break; 198 default: 199 return -EINVAL; 200 } 201 } 202 203 return 0; 204 } 205 206 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 207 const struct rtw_pwr_seq_cmd **cmd_seq) 208 { 209 u8 cut_mask; 210 u8 intf_mask; 211 u8 cut; 212 u32 idx = 0; 213 const struct rtw_pwr_seq_cmd *cmd; 214 int ret; 215 216 cut = rtwdev->hal.cut_version; 217 cut_mask = cut_version_to_mask(cut); 218 switch (rtw_hci_type(rtwdev)) { 219 case RTW_HCI_TYPE_PCIE: 220 intf_mask = RTW_PWR_INTF_PCI_MSK; 221 break; 222 case RTW_HCI_TYPE_USB: 223 intf_mask = RTW_PWR_INTF_USB_MSK; 224 break; 225 case RTW_HCI_TYPE_SDIO: 226 intf_mask = RTW_PWR_INTF_SDIO_MSK; 227 break; 228 default: 229 return -EINVAL; 230 } 231 232 do { 233 cmd = cmd_seq[idx]; 234 if (!cmd) 235 break; 236 237 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 238 if (ret) 239 return ret; 240 241 idx++; 242 } while (1); 243 244 return 0; 245 } 246 247 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 248 { 249 const struct rtw_chip_info *chip = rtwdev->chip; 250 const struct rtw_pwr_seq_cmd **pwr_seq; 251 u8 rpwm; 252 bool cur_pwr; 253 int ret; 254 255 if (rtw_chip_wcpu_11ac(rtwdev)) { 256 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 257 258 /* Check FW still exist or not */ 259 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 260 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 261 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 262 } 263 } 264 265 if (rtw_read8(rtwdev, REG_CR) == 0xea) 266 cur_pwr = false; 267 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 268 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 269 cur_pwr = false; 270 else 271 cur_pwr = true; 272 273 if (pwr_on == cur_pwr) 274 return -EALREADY; 275 276 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 277 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq); 278 if (ret) 279 return ret; 280 281 if (pwr_on) 282 set_bit(RTW_FLAG_POWERON, rtwdev->flags); 283 else 284 clear_bit(RTW_FLAG_POWERON, rtwdev->flags); 285 286 return 0; 287 } 288 289 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 290 { 291 u8 sys_func_en = rtwdev->chip->sys_func_en; 292 u8 value8; 293 u32 value, tmp; 294 295 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 296 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 297 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 298 299 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 300 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 301 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 302 303 /* disable boot-from-flash for driver's DL FW */ 304 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 305 if (tmp & BIT_BOOT_FSPI_EN) { 306 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 307 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 308 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 309 } 310 311 return 0; 312 } 313 314 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev) 315 { 316 rtw_write8(rtwdev, REG_CR, 0xff); 317 mdelay(2); 318 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f); 319 mdelay(2); 320 321 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN); 322 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC); 323 324 rtw_write16(rtwdev, REG_CR, 0x2ff); 325 326 return 0; 327 } 328 329 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 330 { 331 if (rtw_chip_wcpu_11n(rtwdev)) 332 return __rtw_mac_init_system_cfg_legacy(rtwdev); 333 334 return __rtw_mac_init_system_cfg(rtwdev); 335 } 336 337 int rtw_mac_power_on(struct rtw_dev *rtwdev) 338 { 339 int ret = 0; 340 341 ret = rtw_mac_pre_system_cfg(rtwdev); 342 if (ret) 343 goto err; 344 345 ret = rtw_mac_power_switch(rtwdev, true); 346 if (ret == -EALREADY) { 347 rtw_mac_power_switch(rtwdev, false); 348 349 ret = rtw_mac_pre_system_cfg(rtwdev); 350 if (ret) 351 goto err; 352 353 ret = rtw_mac_power_switch(rtwdev, true); 354 if (ret) 355 goto err; 356 } else if (ret) { 357 goto err; 358 } 359 360 ret = rtw_mac_init_system_cfg(rtwdev); 361 if (ret) 362 goto err; 363 364 return 0; 365 366 err: 367 rtw_err(rtwdev, "mac power on failed"); 368 return ret; 369 } 370 371 void rtw_mac_power_off(struct rtw_dev *rtwdev) 372 { 373 rtw_mac_power_switch(rtwdev, false); 374 } 375 376 static bool check_firmware_size(const u8 *data, u32 size) 377 { 378 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 379 u32 dmem_size; 380 u32 imem_size; 381 u32 emem_size; 382 u32 real_size; 383 384 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 385 imem_size = le32_to_cpu(fw_hdr->imem_size); 386 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 387 le32_to_cpu(fw_hdr->emem_size) : 0; 388 389 dmem_size += FW_HDR_CHKSUM_SIZE; 390 imem_size += FW_HDR_CHKSUM_SIZE; 391 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 392 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 393 if (real_size != size) 394 return false; 395 396 return true; 397 } 398 399 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 400 { 401 if (enable) { 402 /* cpu io interface enable */ 403 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 404 405 /* cpu enable */ 406 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 407 } else { 408 /* cpu io interface disable */ 409 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 410 411 /* cpu disable */ 412 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 413 } 414 } 415 416 #define DLFW_RESTORE_REG_NUM 6 417 418 static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 419 struct rtw_backup_info *bckp) 420 { 421 u8 tmp; 422 u8 bckp_idx = 0; 423 424 /* set HIQ to hi priority */ 425 bckp[bckp_idx].len = 1; 426 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 427 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 428 bckp_idx++; 429 tmp = RTW_DMA_MAPPING_HIGH << 6; 430 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 431 432 /* DLFW only use HIQ, map HIQ to hi priority */ 433 bckp[bckp_idx].len = 1; 434 bckp[bckp_idx].reg = REG_CR; 435 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 436 bckp_idx++; 437 bckp[bckp_idx].len = 4; 438 bckp[bckp_idx].reg = REG_H2CQ_CSR; 439 bckp[bckp_idx].val = BIT_H2CQ_FULL; 440 bckp_idx++; 441 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 442 rtw_write8(rtwdev, REG_CR, tmp); 443 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 444 445 /* Config hi priority queue and public priority queue page number */ 446 bckp[bckp_idx].len = 2; 447 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 448 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 449 bckp_idx++; 450 bckp[bckp_idx].len = 4; 451 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 452 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 453 bckp_idx++; 454 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 455 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 456 457 /* Disable beacon related functions */ 458 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 459 bckp[bckp_idx].len = 1; 460 bckp[bckp_idx].reg = REG_BCN_CTRL; 461 bckp[bckp_idx].val = tmp; 462 bckp_idx++; 463 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 464 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 465 466 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 467 } 468 469 static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 470 { 471 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 472 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 473 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 474 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 475 } 476 477 static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 478 struct rtw_backup_info *bckp, 479 u8 bckp_num) 480 { 481 rtw_restore_reg(rtwdev, bckp, bckp_num); 482 } 483 484 #define TX_DESC_SIZE 48 485 486 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 487 const u8 *data, u32 size) 488 { 489 u8 *buf; 490 int ret; 491 492 buf = kmemdup(data, size, GFP_KERNEL); 493 if (!buf) 494 return -ENOMEM; 495 496 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 497 kfree(buf); 498 return ret; 499 } 500 501 static int 502 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 503 { 504 int ret; 505 506 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 507 !((size + TX_DESC_SIZE) & (512 - 1))) 508 size += 1; 509 510 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 511 if (ret) 512 rtw_err(rtwdev, "failed to download rsvd page\n"); 513 514 return ret; 515 } 516 517 static int 518 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 519 { 520 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 521 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 522 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 523 524 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 525 return -EBUSY; 526 527 return 0; 528 } 529 530 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 531 u32 len, u8 first) 532 { 533 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 534 535 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 536 return -EBUSY; 537 538 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 539 if (!first) 540 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 541 542 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 543 return -EBUSY; 544 545 return 0; 546 } 547 548 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size) 549 { 550 u32 ch0_ctrl = BIT_DDMACH0_OWN | BIT_DDMACH0_DDMA_MODE; 551 552 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) { 553 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n"); 554 return -EBUSY; 555 } 556 557 ch0_ctrl |= size & BIT_MASK_DDMACH0_DLEN; 558 559 if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) { 560 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n"); 561 return -EBUSY; 562 } 563 564 return 0; 565 } 566 567 static bool 568 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 569 { 570 u8 fw_ctrl; 571 572 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 573 574 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 575 if (addr < OCPBASE_DMEM_88XX) { 576 fw_ctrl |= BIT_IMEM_DW_OK; 577 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 578 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 579 } else { 580 fw_ctrl |= BIT_DMEM_DW_OK; 581 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 582 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 583 } 584 585 rtw_err(rtwdev, "invalid fw checksum\n"); 586 587 return false; 588 } 589 590 if (addr < OCPBASE_DMEM_88XX) { 591 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 592 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 593 } else { 594 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 595 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 596 } 597 598 return true; 599 } 600 601 static int 602 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 603 u32 src, u32 dst, u32 size) 604 { 605 const struct rtw_chip_info *chip = rtwdev->chip; 606 u32 desc_size = chip->tx_pkt_desc_sz; 607 u8 first_part; 608 u32 mem_offset; 609 u32 residue_size; 610 u32 pkt_size; 611 u32 max_size = 0x1000; 612 u32 val; 613 int ret; 614 615 mem_offset = 0; 616 first_part = 1; 617 residue_size = size; 618 619 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 620 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 621 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 622 623 while (residue_size) { 624 if (residue_size >= max_size) 625 pkt_size = max_size; 626 else 627 pkt_size = residue_size; 628 629 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 630 data + mem_offset, pkt_size); 631 if (ret) 632 return ret; 633 634 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 635 src + desc_size, 636 dst + mem_offset, pkt_size, 637 first_part); 638 if (ret) 639 return ret; 640 641 first_part = 0; 642 mem_offset += pkt_size; 643 residue_size -= pkt_size; 644 } 645 646 if (!check_fw_checksum(rtwdev, dst)) 647 return -EINVAL; 648 649 return 0; 650 } 651 652 static int 653 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 654 { 655 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 656 const u8 *cur_fw; 657 u16 val; 658 u32 imem_size; 659 u32 dmem_size; 660 u32 emem_size; 661 u32 addr; 662 int ret; 663 664 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 665 imem_size = le32_to_cpu(fw_hdr->imem_size); 666 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 667 le32_to_cpu(fw_hdr->emem_size) : 0; 668 dmem_size += FW_HDR_CHKSUM_SIZE; 669 imem_size += FW_HDR_CHKSUM_SIZE; 670 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 671 672 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 673 val |= BIT_MCUFWDL_EN; 674 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 675 676 cur_fw = data + FW_HDR_SIZE; 677 addr = le32_to_cpu(fw_hdr->dmem_addr); 678 addr &= ~BIT(31); 679 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 680 if (ret) 681 return ret; 682 683 cur_fw = data + FW_HDR_SIZE + dmem_size; 684 addr = le32_to_cpu(fw_hdr->imem_addr); 685 addr &= ~BIT(31); 686 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 687 if (ret) 688 return ret; 689 690 if (emem_size) { 691 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 692 addr = le32_to_cpu(fw_hdr->emem_addr); 693 addr &= ~BIT(31); 694 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 695 emem_size); 696 if (ret) 697 return ret; 698 } 699 700 return 0; 701 } 702 703 static int download_firmware_validate(struct rtw_dev *rtwdev) 704 { 705 u32 fw_key; 706 707 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 708 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 709 if (fw_key == ILLEGAL_KEY_GROUP) 710 rtw_err(rtwdev, "invalid fw key\n"); 711 return -EINVAL; 712 } 713 714 return 0; 715 } 716 717 static void download_firmware_end_flow(struct rtw_dev *rtwdev) 718 { 719 u16 fw_ctrl; 720 721 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 722 723 /* Check IMEM & DMEM checksum is OK or not */ 724 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 725 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 726 return; 727 728 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 729 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 730 } 731 732 static int __rtw_download_firmware(struct rtw_dev *rtwdev, 733 struct rtw_fw_state *fw) 734 { 735 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 736 const u8 *data = fw->firmware->data; 737 u32 size = fw->firmware->size; 738 u32 ltecoex_bckp; 739 int ret; 740 741 if (!check_firmware_size(data, size)) 742 return -EINVAL; 743 744 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 745 return -EBUSY; 746 747 wlan_cpu_enable(rtwdev, false); 748 749 download_firmware_reg_backup(rtwdev, bckp); 750 download_firmware_reset_platform(rtwdev); 751 752 ret = start_download_firmware(rtwdev, data, size); 753 if (ret) 754 goto dlfw_fail; 755 756 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 757 758 download_firmware_end_flow(rtwdev); 759 760 wlan_cpu_enable(rtwdev, true); 761 762 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) 763 return -EBUSY; 764 765 ret = download_firmware_validate(rtwdev); 766 if (ret) 767 goto dlfw_fail; 768 769 /* reset desc and index */ 770 rtw_hci_setup(rtwdev); 771 772 rtwdev->h2c.last_box_num = 0; 773 rtwdev->h2c.seq = 0; 774 775 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 776 777 return 0; 778 779 dlfw_fail: 780 /* Disable FWDL_EN */ 781 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 782 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 783 784 return ret; 785 } 786 787 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en) 788 { 789 int try; 790 791 if (en) { 792 wlan_cpu_enable(rtwdev, false); 793 wlan_cpu_enable(rtwdev, true); 794 795 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 796 797 for (try = 0; try < 10; try++) { 798 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN) 799 goto fwdl_ready; 800 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 801 msleep(20); 802 } 803 rtw_err(rtwdev, "failed to check fw download ready\n"); 804 fwdl_ready: 805 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN); 806 } else { 807 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 808 } 809 } 810 811 static void 812 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size) 813 { 814 u32 val32; 815 u32 block_nr; 816 u32 remain_size; 817 u32 write_addr = FW_START_ADDR_LEGACY; 818 const __le32 *ptr = (const __le32 *)data; 819 u32 block; 820 __le32 remain_data = 0; 821 822 block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY; 823 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1); 824 825 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 826 val32 &= ~BIT_ROM_PGE; 827 val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE; 828 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 829 830 for (block = 0; block < block_nr; block++) { 831 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr)); 832 833 write_addr += DLFW_BLK_SIZE_LEGACY; 834 ptr++; 835 } 836 837 if (remain_size) { 838 memcpy(&remain_data, ptr, remain_size); 839 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data)); 840 } 841 } 842 843 static int 844 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size) 845 { 846 u32 page; 847 u32 total_page; 848 u32 last_page_size; 849 850 data += sizeof(struct rtw_fw_hdr_legacy); 851 size -= sizeof(struct rtw_fw_hdr_legacy); 852 853 total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY; 854 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1); 855 856 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT); 857 858 for (page = 0; page < total_page; page++) { 859 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY); 860 data += DLFW_PAGE_SIZE_LEGACY; 861 } 862 if (last_page_size) 863 write_firmware_page(rtwdev, page, data, last_page_size); 864 865 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) { 866 rtw_err(rtwdev, "failed to check download firmware report\n"); 867 return -EINVAL; 868 } 869 870 return 0; 871 } 872 873 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev) 874 { 875 u32 val32; 876 int try; 877 878 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 879 val32 |= BIT_MCUFWDL_RDY; 880 val32 &= ~BIT_WINTINI_RDY; 881 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 882 883 wlan_cpu_enable(rtwdev, false); 884 wlan_cpu_enable(rtwdev, true); 885 886 for (try = 0; try < 10; try++) { 887 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 888 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY) 889 return 0; 890 msleep(20); 891 } 892 893 rtw_err(rtwdev, "failed to validate firmware\n"); 894 return -EINVAL; 895 } 896 897 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, 898 struct rtw_fw_state *fw) 899 { 900 int ret = 0; 901 902 en_download_firmware_legacy(rtwdev, true); 903 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); 904 en_download_firmware_legacy(rtwdev, false); 905 if (ret) 906 goto out; 907 908 ret = download_firmware_validate_legacy(rtwdev); 909 if (ret) 910 goto out; 911 912 /* reset desc and index */ 913 rtw_hci_setup(rtwdev); 914 915 rtwdev->h2c.last_box_num = 0; 916 rtwdev->h2c.seq = 0; 917 918 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 919 920 out: 921 return ret; 922 } 923 924 static 925 int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 926 { 927 if (rtw_chip_wcpu_11n(rtwdev)) 928 return __rtw_download_firmware_legacy(rtwdev, fw); 929 930 return __rtw_download_firmware(rtwdev, fw); 931 } 932 933 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 934 { 935 int ret; 936 937 ret = _rtw_download_firmware(rtwdev, fw); 938 if (ret) 939 return ret; 940 941 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE && 942 rtwdev->chip->id == RTW_CHIP_TYPE_8821C) 943 rtw_fw_set_recover_bt_device(rtwdev); 944 945 return 0; 946 } 947 948 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues) 949 { 950 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn; 951 u32 prio_queues = 0; 952 953 if (queues & BIT(IEEE80211_AC_VO)) 954 prio_queues |= BIT(rqpn->dma_map_vo); 955 if (queues & BIT(IEEE80211_AC_VI)) 956 prio_queues |= BIT(rqpn->dma_map_vi); 957 if (queues & BIT(IEEE80211_AC_BE)) 958 prio_queues |= BIT(rqpn->dma_map_be); 959 if (queues & BIT(IEEE80211_AC_BK)) 960 prio_queues |= BIT(rqpn->dma_map_bk); 961 962 return prio_queues; 963 } 964 965 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev, 966 u32 prio_queue, bool drop) 967 { 968 const struct rtw_chip_info *chip = rtwdev->chip; 969 const struct rtw_prioq_addr *addr; 970 bool wsize; 971 u16 avail_page, rsvd_page; 972 int i; 973 974 if (prio_queue >= RTW_DMA_MAPPING_MAX) 975 return; 976 977 addr = &chip->prioq_addrs->prio[prio_queue]; 978 wsize = chip->prioq_addrs->wsize; 979 980 /* check if all of the reserved pages are available for 100 msecs */ 981 for (i = 0; i < 5; i++) { 982 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) : 983 rtw_read8(rtwdev, addr->rsvd); 984 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) : 985 rtw_read8(rtwdev, addr->avail); 986 if (rsvd_page == avail_page) 987 return; 988 989 msleep(20); 990 } 991 992 /* priority queue is still not empty, throw a warning, 993 * 994 * Note that if we want to flush the tx queue when having a lot of 995 * traffic (ex, 100Mbps up), some of the packets could be dropped. 996 * And it requires like ~2secs to flush the full priority queue. 997 */ 998 if (!drop) 999 rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue); 1000 } 1001 1002 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev, 1003 u32 prio_queues, bool drop) 1004 { 1005 u32 q; 1006 1007 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++) 1008 if (prio_queues & BIT(q)) 1009 __rtw_mac_flush_prio_queue(rtwdev, q, drop); 1010 } 1011 1012 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 1013 { 1014 u32 prio_queues = 0; 1015 1016 /* If all of the hardware queues are requested to flush, 1017 * or the priority queues are not mapped yet, 1018 * flush all of the priority queues 1019 */ 1020 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn) 1021 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1; 1022 else 1023 prio_queues = get_priority_queues(rtwdev, queues); 1024 1025 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop); 1026 } 1027 1028 static int txdma_queue_mapping(struct rtw_dev *rtwdev) 1029 { 1030 const struct rtw_chip_info *chip = rtwdev->chip; 1031 const struct rtw_rqpn *rqpn = NULL; 1032 u16 txdma_pq_map = 0; 1033 1034 switch (rtw_hci_type(rtwdev)) { 1035 case RTW_HCI_TYPE_PCIE: 1036 rqpn = &chip->rqpn_table[1]; 1037 break; 1038 case RTW_HCI_TYPE_USB: 1039 if (rtwdev->hci.bulkout_num == 2) 1040 rqpn = &chip->rqpn_table[2]; 1041 else if (rtwdev->hci.bulkout_num == 3) 1042 rqpn = &chip->rqpn_table[3]; 1043 else if (rtwdev->hci.bulkout_num == 4) 1044 rqpn = &chip->rqpn_table[4]; 1045 else 1046 return -EINVAL; 1047 break; 1048 case RTW_HCI_TYPE_SDIO: 1049 rqpn = &chip->rqpn_table[0]; 1050 break; 1051 default: 1052 return -EINVAL; 1053 } 1054 1055 rtwdev->fifo.rqpn = rqpn; 1056 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 1057 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 1058 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 1059 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 1060 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 1061 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 1062 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 1063 1064 rtw_write8(rtwdev, REG_CR, 0); 1065 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 1066 if (rtw_chip_wcpu_11ac(rtwdev)) 1067 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 1068 1069 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 1070 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN); 1071 1072 return 0; 1073 } 1074 1075 static int set_trx_fifo_info(struct rtw_dev *rtwdev) 1076 { 1077 const struct rtw_chip_info *chip = rtwdev->chip; 1078 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1079 u16 cur_pg_addr; 1080 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 1081 1082 /* config rsvd page num */ 1083 fifo->rsvd_drv_pg_num = 8; 1084 fifo->txff_pg_num = chip->txff_size >> 7; 1085 if (rtw_chip_wcpu_11n(rtwdev)) 1086 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num; 1087 else 1088 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 1089 RSVD_PG_H2C_EXTRAINFO_NUM + 1090 RSVD_PG_H2C_STATICINFO_NUM + 1091 RSVD_PG_H2CQ_NUM + 1092 RSVD_PG_CPU_INSTRUCTION_NUM + 1093 RSVD_PG_FW_TXBUF_NUM + 1094 csi_buf_pg_num; 1095 1096 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 1097 return -ENOMEM; 1098 1099 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 1100 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 1101 1102 cur_pg_addr = fifo->txff_pg_num; 1103 if (rtw_chip_wcpu_11ac(rtwdev)) { 1104 cur_pg_addr -= csi_buf_pg_num; 1105 fifo->rsvd_csibuf_addr = cur_pg_addr; 1106 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 1107 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 1108 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 1109 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 1110 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 1111 fifo->rsvd_h2cq_addr = cur_pg_addr; 1112 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 1113 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 1114 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 1115 fifo->rsvd_h2c_info_addr = cur_pg_addr; 1116 } 1117 cur_pg_addr -= fifo->rsvd_drv_pg_num; 1118 fifo->rsvd_drv_addr = cur_pg_addr; 1119 1120 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 1121 rtw_err(rtwdev, "wrong rsvd driver address\n"); 1122 return -EINVAL; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int __priority_queue_cfg(struct rtw_dev *rtwdev, 1129 const struct rtw_page_table *pg_tbl, 1130 u16 pubq_num) 1131 { 1132 const struct rtw_chip_info *chip = rtwdev->chip; 1133 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1134 1135 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 1136 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 1137 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 1138 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 1139 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 1140 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 1141 1142 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 1143 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 1144 1145 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 1146 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 1147 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 1148 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 1149 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 1150 1151 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 1152 return -EBUSY; 1153 1154 rtw_write8(rtwdev, REG_CR + 3, 0); 1155 1156 return 0; 1157 } 1158 1159 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev, 1160 const struct rtw_page_table *pg_tbl, 1161 u16 pubq_num) 1162 { 1163 const struct rtw_chip_info *chip = rtwdev->chip; 1164 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1165 u32 val32; 1166 1167 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num); 1168 rtw_write32(rtwdev, REG_RQPN_NPQ, val32); 1169 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num); 1170 rtw_write32(rtwdev, REG_RQPN, val32); 1171 1172 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary); 1173 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1); 1174 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary); 1175 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary); 1176 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary); 1177 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary); 1178 1179 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); 1180 1181 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0)) 1182 return -EBUSY; 1183 1184 return 0; 1185 } 1186 1187 static int priority_queue_cfg(struct rtw_dev *rtwdev) 1188 { 1189 const struct rtw_chip_info *chip = rtwdev->chip; 1190 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1191 const struct rtw_page_table *pg_tbl = NULL; 1192 u16 pubq_num; 1193 int ret; 1194 1195 ret = set_trx_fifo_info(rtwdev); 1196 if (ret) 1197 return ret; 1198 1199 switch (rtw_hci_type(rtwdev)) { 1200 case RTW_HCI_TYPE_PCIE: 1201 pg_tbl = &chip->page_table[1]; 1202 break; 1203 case RTW_HCI_TYPE_USB: 1204 if (rtwdev->hci.bulkout_num == 2) 1205 pg_tbl = &chip->page_table[2]; 1206 else if (rtwdev->hci.bulkout_num == 3) 1207 pg_tbl = &chip->page_table[3]; 1208 else if (rtwdev->hci.bulkout_num == 4) 1209 pg_tbl = &chip->page_table[4]; 1210 else 1211 return -EINVAL; 1212 break; 1213 case RTW_HCI_TYPE_SDIO: 1214 pg_tbl = &chip->page_table[0]; 1215 break; 1216 default: 1217 return -EINVAL; 1218 } 1219 1220 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 1221 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 1222 if (rtw_chip_wcpu_11n(rtwdev)) 1223 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num); 1224 else 1225 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num); 1226 } 1227 1228 static int init_h2c(struct rtw_dev *rtwdev) 1229 { 1230 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1231 u8 value8; 1232 u32 value32; 1233 u32 h2cq_addr; 1234 u32 h2cq_size; 1235 u32 h2cq_free; 1236 u32 wp, rp; 1237 1238 if (rtw_chip_wcpu_11n(rtwdev)) 1239 return 0; 1240 1241 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 1242 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 1243 1244 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 1245 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1246 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 1247 1248 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 1249 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1250 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 1251 1252 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 1253 value32 &= 0xFFFC0000; 1254 value32 |= (h2cq_addr + h2cq_size); 1255 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 1256 1257 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1258 value8 = (u8)((value8 & 0xFC) | 0x01); 1259 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1260 1261 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1262 value8 = (u8)((value8 & 0xFB) | 0x04); 1263 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1264 1265 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 1266 value8 = (u8)((value8 & 0x7f) | 0x80); 1267 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 1268 1269 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 1270 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 1271 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 1272 1273 if (h2cq_size != h2cq_free) { 1274 rtw_err(rtwdev, "H2C queue mismatch\n"); 1275 return -EINVAL; 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 1282 { 1283 int ret; 1284 1285 ret = txdma_queue_mapping(rtwdev); 1286 if (ret) 1287 return ret; 1288 1289 ret = priority_queue_cfg(rtwdev); 1290 if (ret) 1291 return ret; 1292 1293 ret = init_h2c(rtwdev); 1294 if (ret) 1295 return ret; 1296 1297 return 0; 1298 } 1299 1300 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 1301 { 1302 u8 value8; 1303 1304 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 1305 if (rtw_chip_wcpu_11ac(rtwdev)) { 1306 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 1307 value8 &= 0xF0; 1308 /* For rxdesc len = 0 issue */ 1309 value8 |= 0xF; 1310 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 1311 } 1312 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 1313 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 1314 1315 return 0; 1316 } 1317 1318 int rtw_mac_init(struct rtw_dev *rtwdev) 1319 { 1320 const struct rtw_chip_info *chip = rtwdev->chip; 1321 int ret; 1322 1323 ret = rtw_init_trx_cfg(rtwdev); 1324 if (ret) 1325 return ret; 1326 1327 ret = chip->ops->mac_init(rtwdev); 1328 if (ret) 1329 return ret; 1330 1331 ret = rtw_drv_info_cfg(rtwdev); 1332 if (ret) 1333 return ret; 1334 1335 rtw_hci_interface_cfg(rtwdev); 1336 1337 return 0; 1338 } 1339