1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "mac.h" 7 #include "reg.h" 8 #include "fw.h" 9 #include "debug.h" 10 11 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw, 12 u8 primary_ch_idx) 13 { 14 u8 txsc40 = 0, txsc20 = 0; 15 u32 value32; 16 u8 value8; 17 18 txsc20 = primary_ch_idx; 19 if (bw == RTW_CHANNEL_WIDTH_80) { 20 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 21 txsc40 = RTW_SC_40_UPPER; 22 else 23 txsc40 = RTW_SC_40_LOWER; 24 } 25 rtw_write8(rtwdev, REG_DATA_SC, 26 BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); 27 28 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL); 29 value32 &= ~BIT_RFMOD; 30 switch (bw) { 31 case RTW_CHANNEL_WIDTH_80: 32 value32 |= BIT_RFMOD_80M; 33 break; 34 case RTW_CHANNEL_WIDTH_40: 35 value32 |= BIT_RFMOD_40M; 36 break; 37 case RTW_CHANNEL_WIDTH_20: 38 default: 39 break; 40 } 41 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32); 42 43 if (rtw_chip_wcpu_11n(rtwdev)) 44 return; 45 46 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL); 47 value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); 48 rtw_write32(rtwdev, REG_AFE_CTRL1, value32); 49 50 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 51 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 52 53 value8 = rtw_read8(rtwdev, REG_CCK_CHECK); 54 value8 = value8 & ~BIT_CHECK_CCK_EN; 55 if (IS_CH_5G_BAND(channel)) 56 value8 |= BIT_CHECK_CCK_EN; 57 rtw_write8(rtwdev, REG_CCK_CHECK, value8); 58 } 59 EXPORT_SYMBOL(rtw_set_channel_mac); 60 61 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev) 62 { 63 u32 value32; 64 u8 value8; 65 66 rtw_write8(rtwdev, REG_RSV_CTRL, 0); 67 68 if (rtw_chip_wcpu_11n(rtwdev)) { 69 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO) 70 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL); 71 else 72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL); 73 return 0; 74 } 75 76 switch (rtw_hci_type(rtwdev)) { 77 case RTW_HCI_TYPE_PCIE: 78 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_BT_DIG_CLK_EN); 79 break; 80 case RTW_HCI_TYPE_USB: 81 break; 82 default: 83 return -EINVAL; 84 } 85 86 /* config PIN Mux */ 87 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1); 88 value32 |= BIT_PAPE_WLBT_SEL | BIT_LNAON_WLBT_SEL; 89 rtw_write32(rtwdev, REG_PAD_CTRL1, value32); 90 91 value32 = rtw_read32(rtwdev, REG_LED_CFG); 92 value32 &= ~(BIT_PAPE_SEL_EN | BIT_LNAON_SEL_EN); 93 rtw_write32(rtwdev, REG_LED_CFG, value32); 94 95 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG); 96 value32 |= BIT_WLRFE_4_5_EN; 97 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32); 98 99 /* disable BB/RF */ 100 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN); 101 value8 &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 102 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8); 103 104 value8 = rtw_read8(rtwdev, REG_RF_CTRL); 105 value8 &= ~(BIT_RF_SDM_RSTB | BIT_RF_RSTB | BIT_RF_EN); 106 rtw_write8(rtwdev, REG_RF_CTRL, value8); 107 108 value32 = rtw_read32(rtwdev, REG_WLRF1); 109 value32 &= ~BIT_WLRF1_BBRF_EN; 110 rtw_write32(rtwdev, REG_WLRF1, value32); 111 112 return 0; 113 } 114 115 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) 116 { 117 u32 cnt; 118 119 target &= mask; 120 121 for (cnt = 0; cnt < RTW_PWR_POLLING_CNT; cnt++) { 122 if ((rtw_read8(rtwdev, addr) & mask) == target) 123 return true; 124 125 udelay(50); 126 } 127 128 return false; 129 } 130 131 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev, 132 const struct rtw_pwr_seq_cmd *cmd) 133 { 134 u8 value; 135 u32 offset; 136 137 if (cmd->base == RTW_PWR_ADDR_SDIO) 138 offset = cmd->offset | SDIO_LOCAL_OFFSET; 139 else 140 offset = cmd->offset; 141 142 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 143 return 0; 144 145 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE) 146 goto err; 147 148 /* if PCIE, toggle BIT_PFM_WOWL and try again */ 149 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL); 150 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 151 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 152 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 153 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL); 154 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) 155 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL); 156 157 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value)) 158 return 0; 159 160 err: 161 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n", 162 offset, cmd->mask, cmd->value); 163 return -EBUSY; 164 } 165 166 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask, 167 u8 cut_mask, 168 const struct rtw_pwr_seq_cmd *cmd) 169 { 170 const struct rtw_pwr_seq_cmd *cur_cmd; 171 u32 offset; 172 u8 value; 173 174 for (cur_cmd = cmd; cur_cmd->cmd != RTW_PWR_CMD_END; cur_cmd++) { 175 if (!(cur_cmd->intf_mask & intf_mask) || 176 !(cur_cmd->cut_mask & cut_mask)) 177 continue; 178 179 switch (cur_cmd->cmd) { 180 case RTW_PWR_CMD_WRITE: 181 offset = cur_cmd->offset; 182 183 if (cur_cmd->base == RTW_PWR_ADDR_SDIO) 184 offset |= SDIO_LOCAL_OFFSET; 185 186 value = rtw_read8(rtwdev, offset); 187 value &= ~cur_cmd->mask; 188 value |= (cur_cmd->value & cur_cmd->mask); 189 rtw_write8(rtwdev, offset, value); 190 break; 191 case RTW_PWR_CMD_POLLING: 192 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd)) 193 return -EBUSY; 194 break; 195 case RTW_PWR_CMD_DELAY: 196 if (cur_cmd->value == RTW_PWR_DELAY_US) 197 udelay(cur_cmd->offset); 198 else 199 mdelay(cur_cmd->offset); 200 break; 201 case RTW_PWR_CMD_READ: 202 break; 203 default: 204 return -EINVAL; 205 } 206 } 207 208 return 0; 209 } 210 211 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev, 212 const struct rtw_pwr_seq_cmd **cmd_seq) 213 { 214 u8 cut_mask; 215 u8 intf_mask; 216 u8 cut; 217 u32 idx = 0; 218 const struct rtw_pwr_seq_cmd *cmd; 219 int ret; 220 221 cut = rtwdev->hal.cut_version; 222 cut_mask = cut_version_to_mask(cut); 223 switch (rtw_hci_type(rtwdev)) { 224 case RTW_HCI_TYPE_PCIE: 225 intf_mask = BIT(2); 226 break; 227 case RTW_HCI_TYPE_USB: 228 intf_mask = BIT(1); 229 break; 230 default: 231 return -EINVAL; 232 } 233 234 do { 235 cmd = cmd_seq[idx]; 236 if (!cmd) 237 break; 238 239 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd); 240 if (ret) 241 return -EBUSY; 242 243 idx++; 244 } while (1); 245 246 return 0; 247 } 248 249 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on) 250 { 251 struct rtw_chip_info *chip = rtwdev->chip; 252 const struct rtw_pwr_seq_cmd **pwr_seq; 253 u8 rpwm; 254 bool cur_pwr; 255 256 if (rtw_chip_wcpu_11ac(rtwdev)) { 257 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr); 258 259 /* Check FW still exist or not */ 260 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) { 261 rpwm = (rpwm ^ BIT_RPWM_TOGGLE) & BIT_RPWM_TOGGLE; 262 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm); 263 } 264 } 265 266 if (rtw_read8(rtwdev, REG_CR) == 0xea) 267 cur_pwr = false; 268 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 269 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0))) 270 cur_pwr = false; 271 else 272 cur_pwr = true; 273 274 if (pwr_on == cur_pwr) 275 return -EALREADY; 276 277 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; 278 if (rtw_pwr_seq_parser(rtwdev, pwr_seq)) 279 return -EINVAL; 280 281 return 0; 282 } 283 284 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 285 { 286 u8 sys_func_en = rtwdev->chip->sys_func_en; 287 u8 value8; 288 u32 value, tmp; 289 290 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON); 291 value |= BIT_WL_PLATFORM_RST | BIT_DDMA_EN; 292 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value); 293 294 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en); 295 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C; 296 rtw_write8(rtwdev, REG_CR_EXT + 3, value8); 297 298 /* disable boot-from-flash for driver's DL FW */ 299 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL); 300 if (tmp & BIT_BOOT_FSPI_EN) { 301 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); 302 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); 303 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value); 304 } 305 306 return 0; 307 } 308 309 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev) 310 { 311 rtw_write8(rtwdev, REG_CR, 0xff); 312 mdelay(2); 313 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f); 314 mdelay(2); 315 316 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN); 317 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC); 318 319 rtw_write16(rtwdev, REG_CR, 0x2ff); 320 321 return 0; 322 } 323 324 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev) 325 { 326 if (rtw_chip_wcpu_11n(rtwdev)) 327 return __rtw_mac_init_system_cfg_legacy(rtwdev); 328 329 return __rtw_mac_init_system_cfg(rtwdev); 330 } 331 332 int rtw_mac_power_on(struct rtw_dev *rtwdev) 333 { 334 int ret = 0; 335 336 ret = rtw_mac_pre_system_cfg(rtwdev); 337 if (ret) 338 goto err; 339 340 ret = rtw_mac_power_switch(rtwdev, true); 341 if (ret == -EALREADY) { 342 rtw_mac_power_switch(rtwdev, false); 343 ret = rtw_mac_power_switch(rtwdev, true); 344 if (ret) 345 goto err; 346 } else if (ret) { 347 goto err; 348 } 349 350 ret = rtw_mac_init_system_cfg(rtwdev); 351 if (ret) 352 goto err; 353 354 return 0; 355 356 err: 357 rtw_err(rtwdev, "mac power on failed"); 358 return ret; 359 } 360 361 void rtw_mac_power_off(struct rtw_dev *rtwdev) 362 { 363 rtw_mac_power_switch(rtwdev, false); 364 } 365 366 static bool check_firmware_size(const u8 *data, u32 size) 367 { 368 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 369 u32 dmem_size; 370 u32 imem_size; 371 u32 emem_size; 372 u32 real_size; 373 374 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 375 imem_size = le32_to_cpu(fw_hdr->imem_size); 376 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 377 le32_to_cpu(fw_hdr->emem_size) : 0; 378 379 dmem_size += FW_HDR_CHKSUM_SIZE; 380 imem_size += FW_HDR_CHKSUM_SIZE; 381 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 382 real_size = FW_HDR_SIZE + dmem_size + imem_size + emem_size; 383 if (real_size != size) 384 return false; 385 386 return true; 387 } 388 389 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable) 390 { 391 if (enable) { 392 /* cpu io interface enable */ 393 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 394 395 /* cpu enable */ 396 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 397 } else { 398 /* cpu io interface disable */ 399 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 400 401 /* cpu disable */ 402 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF); 403 } 404 } 405 406 #define DLFW_RESTORE_REG_NUM 6 407 408 static void download_firmware_reg_backup(struct rtw_dev *rtwdev, 409 struct rtw_backup_info *bckp) 410 { 411 u8 tmp; 412 u8 bckp_idx = 0; 413 414 /* set HIQ to hi priority */ 415 bckp[bckp_idx].len = 1; 416 bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; 417 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1); 418 bckp_idx++; 419 tmp = RTW_DMA_MAPPING_HIGH << 6; 420 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp); 421 422 /* DLFW only use HIQ, map HIQ to hi priority */ 423 bckp[bckp_idx].len = 1; 424 bckp[bckp_idx].reg = REG_CR; 425 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR); 426 bckp_idx++; 427 bckp[bckp_idx].len = 4; 428 bckp[bckp_idx].reg = REG_H2CQ_CSR; 429 bckp[bckp_idx].val = BIT_H2CQ_FULL; 430 bckp_idx++; 431 tmp = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; 432 rtw_write8(rtwdev, REG_CR, tmp); 433 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 434 435 /* Config hi priority queue and public priority queue page number */ 436 bckp[bckp_idx].len = 2; 437 bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; 438 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1); 439 bckp_idx++; 440 bckp[bckp_idx].len = 4; 441 bckp[bckp_idx].reg = REG_RQPN_CTRL_2; 442 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN; 443 bckp_idx++; 444 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200); 445 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val); 446 447 /* Disable beacon related functions */ 448 tmp = rtw_read8(rtwdev, REG_BCN_CTRL); 449 bckp[bckp_idx].len = 1; 450 bckp[bckp_idx].reg = REG_BCN_CTRL; 451 bckp[bckp_idx].val = tmp; 452 bckp_idx++; 453 tmp = (u8)((tmp & (~BIT_EN_BCN_FUNCTION)) | BIT_DIS_TSF_UDT); 454 rtw_write8(rtwdev, REG_BCN_CTRL, tmp); 455 456 WARN(bckp_idx != DLFW_RESTORE_REG_NUM, "wrong backup number\n"); 457 } 458 459 static void download_firmware_reset_platform(struct rtw_dev *rtwdev) 460 { 461 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 462 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 463 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16); 464 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8); 465 } 466 467 static void download_firmware_reg_restore(struct rtw_dev *rtwdev, 468 struct rtw_backup_info *bckp, 469 u8 bckp_num) 470 { 471 rtw_restore_reg(rtwdev, bckp, bckp_num); 472 } 473 474 #define TX_DESC_SIZE 48 475 476 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 477 const u8 *data, u32 size) 478 { 479 u8 *buf; 480 int ret; 481 482 buf = kmemdup(data, size, GFP_KERNEL); 483 if (!buf) 484 return -ENOMEM; 485 486 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 487 kfree(buf); 488 return ret; 489 } 490 491 static int 492 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size) 493 { 494 int ret; 495 496 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 497 !((size + TX_DESC_SIZE) & (512 - 1))) 498 size += 1; 499 500 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size); 501 if (ret) 502 rtw_err(rtwdev, "failed to download rsvd page\n"); 503 504 return ret; 505 } 506 507 static int 508 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl) 509 { 510 rtw_write32(rtwdev, REG_DDMA_CH0SA, src); 511 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst); 512 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl); 513 514 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 515 return -EBUSY; 516 517 return 0; 518 } 519 520 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst, 521 u32 len, u8 first) 522 { 523 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; 524 525 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) 526 return -EBUSY; 527 528 ch0_ctrl |= len & BIT_MASK_DDMACH0_DLEN; 529 if (!first) 530 ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; 531 532 if (iddma_enable(rtwdev, src, dst, ch0_ctrl)) 533 return -EBUSY; 534 535 return 0; 536 } 537 538 static bool 539 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr) 540 { 541 u8 fw_ctrl; 542 543 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL); 544 545 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { 546 if (addr < OCPBASE_DMEM_88XX) { 547 fw_ctrl |= BIT_IMEM_DW_OK; 548 fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; 549 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 550 } else { 551 fw_ctrl |= BIT_DMEM_DW_OK; 552 fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; 553 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 554 } 555 556 rtw_err(rtwdev, "invalid fw checksum\n"); 557 558 return false; 559 } 560 561 if (addr < OCPBASE_DMEM_88XX) { 562 fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); 563 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 564 } else { 565 fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); 566 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 567 } 568 569 return true; 570 } 571 572 static int 573 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data, 574 u32 src, u32 dst, u32 size) 575 { 576 struct rtw_chip_info *chip = rtwdev->chip; 577 u32 desc_size = chip->tx_pkt_desc_sz; 578 u8 first_part; 579 u32 mem_offset; 580 u32 residue_size; 581 u32 pkt_size; 582 u32 max_size = 0x1000; 583 u32 val; 584 int ret; 585 586 mem_offset = 0; 587 first_part = 1; 588 residue_size = size; 589 590 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL); 591 val |= BIT_DDMACH0_RESET_CHKSUM_STS; 592 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val); 593 594 while (residue_size) { 595 if (residue_size >= max_size) 596 pkt_size = max_size; 597 else 598 pkt_size = residue_size; 599 600 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7), 601 data + mem_offset, pkt_size); 602 if (ret) 603 return ret; 604 605 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX + 606 src + desc_size, 607 dst + mem_offset, pkt_size, 608 first_part); 609 if (ret) 610 return ret; 611 612 first_part = 0; 613 mem_offset += pkt_size; 614 residue_size -= pkt_size; 615 } 616 617 if (!check_fw_checksum(rtwdev, dst)) 618 return -EINVAL; 619 620 return 0; 621 } 622 623 static int 624 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size) 625 { 626 const struct rtw_fw_hdr *fw_hdr = (const struct rtw_fw_hdr *)data; 627 const u8 *cur_fw; 628 u16 val; 629 u32 imem_size; 630 u32 dmem_size; 631 u32 emem_size; 632 u32 addr; 633 int ret; 634 635 dmem_size = le32_to_cpu(fw_hdr->dmem_size); 636 imem_size = le32_to_cpu(fw_hdr->imem_size); 637 emem_size = (fw_hdr->mem_usage & BIT(4)) ? 638 le32_to_cpu(fw_hdr->emem_size) : 0; 639 dmem_size += FW_HDR_CHKSUM_SIZE; 640 imem_size += FW_HDR_CHKSUM_SIZE; 641 emem_size += emem_size ? FW_HDR_CHKSUM_SIZE : 0; 642 643 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800); 644 val |= BIT_MCUFWDL_EN; 645 rtw_write16(rtwdev, REG_MCUFW_CTRL, val); 646 647 cur_fw = data + FW_HDR_SIZE; 648 addr = le32_to_cpu(fw_hdr->dmem_addr); 649 addr &= ~BIT(31); 650 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size); 651 if (ret) 652 return ret; 653 654 cur_fw = data + FW_HDR_SIZE + dmem_size; 655 addr = le32_to_cpu(fw_hdr->imem_addr); 656 addr &= ~BIT(31); 657 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size); 658 if (ret) 659 return ret; 660 661 if (emem_size) { 662 cur_fw = data + FW_HDR_SIZE + dmem_size + imem_size; 663 addr = le32_to_cpu(fw_hdr->emem_addr); 664 addr &= ~BIT(31); 665 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, 666 emem_size); 667 if (ret) 668 return ret; 669 } 670 671 return 0; 672 } 673 674 static int download_firmware_validate(struct rtw_dev *rtwdev) 675 { 676 u32 fw_key; 677 678 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) { 679 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK; 680 if (fw_key == ILLEGAL_KEY_GROUP) 681 rtw_err(rtwdev, "invalid fw key\n"); 682 return -EINVAL; 683 } 684 685 return 0; 686 } 687 688 static void download_firmware_end_flow(struct rtw_dev *rtwdev) 689 { 690 u16 fw_ctrl; 691 692 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF); 693 694 /* Check IMEM & DMEM checksum is OK or not */ 695 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL); 696 if ((fw_ctrl & BIT_CHECK_SUM_OK) != BIT_CHECK_SUM_OK) 697 return; 698 699 fw_ctrl = (fw_ctrl | BIT_FW_DW_RDY) & ~BIT_MCUFWDL_EN; 700 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl); 701 } 702 703 static int __rtw_download_firmware(struct rtw_dev *rtwdev, 704 struct rtw_fw_state *fw) 705 { 706 struct rtw_backup_info bckp[DLFW_RESTORE_REG_NUM]; 707 const u8 *data = fw->firmware->data; 708 u32 size = fw->firmware->size; 709 u32 ltecoex_bckp; 710 int ret; 711 712 if (!check_firmware_size(data, size)) 713 return -EINVAL; 714 715 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp)) 716 return -EBUSY; 717 718 wlan_cpu_enable(rtwdev, false); 719 720 download_firmware_reg_backup(rtwdev, bckp); 721 download_firmware_reset_platform(rtwdev); 722 723 ret = start_download_firmware(rtwdev, data, size); 724 if (ret) 725 goto dlfw_fail; 726 727 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM); 728 729 download_firmware_end_flow(rtwdev); 730 731 wlan_cpu_enable(rtwdev, true); 732 733 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) 734 return -EBUSY; 735 736 ret = download_firmware_validate(rtwdev); 737 if (ret) 738 goto dlfw_fail; 739 740 /* reset desc and index */ 741 rtw_hci_setup(rtwdev); 742 743 rtwdev->h2c.last_box_num = 0; 744 rtwdev->h2c.seq = 0; 745 746 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 747 748 return 0; 749 750 dlfw_fail: 751 /* Disable FWDL_EN */ 752 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 753 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN); 754 755 return ret; 756 } 757 758 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en) 759 { 760 int try; 761 762 if (en) { 763 wlan_cpu_enable(rtwdev, false); 764 wlan_cpu_enable(rtwdev, true); 765 766 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 767 768 for (try = 0; try < 10; try++) { 769 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN) 770 goto fwdl_ready; 771 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 772 msleep(20); 773 } 774 rtw_err(rtwdev, "failed to check fw download ready\n"); 775 fwdl_ready: 776 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN); 777 } else { 778 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN); 779 } 780 } 781 782 static void 783 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size) 784 { 785 u32 val32; 786 u32 block_nr; 787 u32 remain_size; 788 u32 write_addr = FW_START_ADDR_LEGACY; 789 const __le32 *ptr = (const __le32 *)data; 790 u32 block; 791 __le32 remain_data = 0; 792 793 block_nr = size >> DLFW_BLK_SIZE_SHIFT_LEGACY; 794 remain_size = size & (DLFW_BLK_SIZE_LEGACY - 1); 795 796 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 797 val32 &= ~BIT_ROM_PGE; 798 val32 |= (page << BIT_SHIFT_ROM_PGE) & BIT_ROM_PGE; 799 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 800 801 for (block = 0; block < block_nr; block++) { 802 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr)); 803 804 write_addr += DLFW_BLK_SIZE_LEGACY; 805 ptr++; 806 } 807 808 if (remain_size) { 809 memcpy(&remain_data, ptr, remain_size); 810 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data)); 811 } 812 } 813 814 static int 815 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size) 816 { 817 u32 page; 818 u32 total_page; 819 u32 last_page_size; 820 821 data += sizeof(struct rtw_fw_hdr_legacy); 822 size -= sizeof(struct rtw_fw_hdr_legacy); 823 824 total_page = size >> DLFW_PAGE_SIZE_SHIFT_LEGACY; 825 last_page_size = size & (DLFW_PAGE_SIZE_LEGACY - 1); 826 827 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT); 828 829 for (page = 0; page < total_page; page++) { 830 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY); 831 data += DLFW_PAGE_SIZE_LEGACY; 832 } 833 if (last_page_size) 834 write_firmware_page(rtwdev, page, data, last_page_size); 835 836 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) { 837 rtw_err(rtwdev, "failed to check download firmware report\n"); 838 return -EINVAL; 839 } 840 841 return 0; 842 } 843 844 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev) 845 { 846 u32 val32; 847 int try; 848 849 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 850 val32 |= BIT_MCUFWDL_RDY; 851 val32 &= ~BIT_WINTINI_RDY; 852 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32); 853 854 wlan_cpu_enable(rtwdev, false); 855 wlan_cpu_enable(rtwdev, true); 856 857 for (try = 0; try < 10; try++) { 858 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL); 859 if ((val32 & FW_READY_LEGACY) == FW_READY_LEGACY) 860 return 0; 861 msleep(20); 862 } 863 864 rtw_err(rtwdev, "failed to validate firmware\n"); 865 return -EINVAL; 866 } 867 868 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev, 869 struct rtw_fw_state *fw) 870 { 871 int ret = 0; 872 873 en_download_firmware_legacy(rtwdev, true); 874 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size); 875 en_download_firmware_legacy(rtwdev, false); 876 if (ret) 877 goto out; 878 879 ret = download_firmware_validate_legacy(rtwdev); 880 if (ret) 881 goto out; 882 883 /* reset desc and index */ 884 rtw_hci_setup(rtwdev); 885 886 rtwdev->h2c.last_box_num = 0; 887 rtwdev->h2c.seq = 0; 888 889 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 890 891 out: 892 return ret; 893 } 894 895 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw) 896 { 897 if (rtw_chip_wcpu_11n(rtwdev)) 898 return __rtw_download_firmware_legacy(rtwdev, fw); 899 900 return __rtw_download_firmware(rtwdev, fw); 901 } 902 903 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues) 904 { 905 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn; 906 u32 prio_queues = 0; 907 908 if (queues & BIT(IEEE80211_AC_VO)) 909 prio_queues |= BIT(rqpn->dma_map_vo); 910 if (queues & BIT(IEEE80211_AC_VI)) 911 prio_queues |= BIT(rqpn->dma_map_vi); 912 if (queues & BIT(IEEE80211_AC_BE)) 913 prio_queues |= BIT(rqpn->dma_map_be); 914 if (queues & BIT(IEEE80211_AC_BK)) 915 prio_queues |= BIT(rqpn->dma_map_bk); 916 917 return prio_queues; 918 } 919 920 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev, 921 u32 prio_queue, bool drop) 922 { 923 struct rtw_chip_info *chip = rtwdev->chip; 924 const struct rtw_prioq_addr *addr; 925 bool wsize; 926 u16 avail_page, rsvd_page; 927 int i; 928 929 if (prio_queue >= RTW_DMA_MAPPING_MAX) 930 return; 931 932 addr = &chip->prioq_addrs->prio[prio_queue]; 933 wsize = chip->prioq_addrs->wsize; 934 935 /* check if all of the reserved pages are available for 100 msecs */ 936 for (i = 0; i < 5; i++) { 937 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) : 938 rtw_read8(rtwdev, addr->rsvd); 939 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) : 940 rtw_read8(rtwdev, addr->avail); 941 if (rsvd_page == avail_page) 942 return; 943 944 msleep(20); 945 } 946 947 /* priority queue is still not empty, throw a warning, 948 * 949 * Note that if we want to flush the tx queue when having a lot of 950 * traffic (ex, 100Mbps up), some of the packets could be dropped. 951 * And it requires like ~2secs to flush the full priority queue. 952 */ 953 if (!drop) 954 rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue); 955 } 956 957 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev, 958 u32 prio_queues, bool drop) 959 { 960 u32 q; 961 962 for (q = 0; q < RTW_DMA_MAPPING_MAX; q++) 963 if (prio_queues & BIT(q)) 964 __rtw_mac_flush_prio_queue(rtwdev, q, drop); 965 } 966 967 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 968 { 969 u32 prio_queues = 0; 970 971 /* If all of the hardware queues are requested to flush, 972 * or the priority queues are not mapped yet, 973 * flush all of the priority queues 974 */ 975 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn) 976 prio_queues = BIT(RTW_DMA_MAPPING_MAX) - 1; 977 else 978 prio_queues = get_priority_queues(rtwdev, queues); 979 980 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop); 981 } 982 983 static int txdma_queue_mapping(struct rtw_dev *rtwdev) 984 { 985 struct rtw_chip_info *chip = rtwdev->chip; 986 const struct rtw_rqpn *rqpn = NULL; 987 u16 txdma_pq_map = 0; 988 989 switch (rtw_hci_type(rtwdev)) { 990 case RTW_HCI_TYPE_PCIE: 991 rqpn = &chip->rqpn_table[1]; 992 break; 993 case RTW_HCI_TYPE_USB: 994 if (rtwdev->hci.bulkout_num == 2) 995 rqpn = &chip->rqpn_table[2]; 996 else if (rtwdev->hci.bulkout_num == 3) 997 rqpn = &chip->rqpn_table[3]; 998 else if (rtwdev->hci.bulkout_num == 4) 999 rqpn = &chip->rqpn_table[4]; 1000 else 1001 return -EINVAL; 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 1007 rtwdev->fifo.rqpn = rqpn; 1008 txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi); 1009 txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg); 1010 txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk); 1011 txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be); 1012 txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi); 1013 txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo); 1014 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map); 1015 1016 rtw_write8(rtwdev, REG_CR, 0); 1017 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE); 1018 if (rtw_chip_wcpu_11ac(rtwdev)) 1019 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL); 1020 1021 return 0; 1022 } 1023 1024 static int set_trx_fifo_info(struct rtw_dev *rtwdev) 1025 { 1026 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1027 struct rtw_chip_info *chip = rtwdev->chip; 1028 u16 cur_pg_addr; 1029 u8 csi_buf_pg_num = chip->csi_buf_pg_num; 1030 1031 /* config rsvd page num */ 1032 fifo->rsvd_drv_pg_num = 8; 1033 fifo->txff_pg_num = chip->txff_size >> 7; 1034 if (rtw_chip_wcpu_11n(rtwdev)) 1035 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num; 1036 else 1037 fifo->rsvd_pg_num = fifo->rsvd_drv_pg_num + 1038 RSVD_PG_H2C_EXTRAINFO_NUM + 1039 RSVD_PG_H2C_STATICINFO_NUM + 1040 RSVD_PG_H2CQ_NUM + 1041 RSVD_PG_CPU_INSTRUCTION_NUM + 1042 RSVD_PG_FW_TXBUF_NUM + 1043 csi_buf_pg_num; 1044 1045 if (fifo->rsvd_pg_num > fifo->txff_pg_num) 1046 return -ENOMEM; 1047 1048 fifo->acq_pg_num = fifo->txff_pg_num - fifo->rsvd_pg_num; 1049 fifo->rsvd_boundary = fifo->txff_pg_num - fifo->rsvd_pg_num; 1050 1051 cur_pg_addr = fifo->txff_pg_num; 1052 if (rtw_chip_wcpu_11ac(rtwdev)) { 1053 cur_pg_addr -= csi_buf_pg_num; 1054 fifo->rsvd_csibuf_addr = cur_pg_addr; 1055 cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; 1056 fifo->rsvd_fw_txbuf_addr = cur_pg_addr; 1057 cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; 1058 fifo->rsvd_cpu_instr_addr = cur_pg_addr; 1059 cur_pg_addr -= RSVD_PG_H2CQ_NUM; 1060 fifo->rsvd_h2cq_addr = cur_pg_addr; 1061 cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; 1062 fifo->rsvd_h2c_sta_info_addr = cur_pg_addr; 1063 cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; 1064 fifo->rsvd_h2c_info_addr = cur_pg_addr; 1065 } 1066 cur_pg_addr -= fifo->rsvd_drv_pg_num; 1067 fifo->rsvd_drv_addr = cur_pg_addr; 1068 1069 if (fifo->rsvd_boundary != fifo->rsvd_drv_addr) { 1070 rtw_err(rtwdev, "wrong rsvd driver address\n"); 1071 return -EINVAL; 1072 } 1073 1074 return 0; 1075 } 1076 1077 static int __priority_queue_cfg(struct rtw_dev *rtwdev, 1078 const struct rtw_page_table *pg_tbl, 1079 u16 pubq_num) 1080 { 1081 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1082 struct rtw_chip_info *chip = rtwdev->chip; 1083 1084 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num); 1085 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num); 1086 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num); 1087 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num); 1088 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num); 1089 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN); 1090 1091 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary); 1092 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16); 1093 1094 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary); 1095 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); 1096 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); 1097 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); 1098 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); 1099 1100 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) 1101 return -EBUSY; 1102 1103 rtw_write8(rtwdev, REG_CR + 3, 0); 1104 1105 return 0; 1106 } 1107 1108 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev, 1109 const struct rtw_page_table *pg_tbl, 1110 u16 pubq_num) 1111 { 1112 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1113 struct rtw_chip_info *chip = rtwdev->chip; 1114 u32 val32; 1115 1116 val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num); 1117 rtw_write32(rtwdev, REG_RQPN_NPQ, val32); 1118 val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num); 1119 rtw_write32(rtwdev, REG_RQPN, val32); 1120 1121 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary); 1122 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1); 1123 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary); 1124 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary); 1125 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary); 1126 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary); 1127 1128 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT); 1129 1130 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0)) 1131 return -EBUSY; 1132 1133 return 0; 1134 } 1135 1136 static int priority_queue_cfg(struct rtw_dev *rtwdev) 1137 { 1138 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1139 struct rtw_chip_info *chip = rtwdev->chip; 1140 const struct rtw_page_table *pg_tbl = NULL; 1141 u16 pubq_num; 1142 int ret; 1143 1144 ret = set_trx_fifo_info(rtwdev); 1145 if (ret) 1146 return ret; 1147 1148 switch (rtw_hci_type(rtwdev)) { 1149 case RTW_HCI_TYPE_PCIE: 1150 pg_tbl = &chip->page_table[1]; 1151 break; 1152 case RTW_HCI_TYPE_USB: 1153 if (rtwdev->hci.bulkout_num == 2) 1154 pg_tbl = &chip->page_table[2]; 1155 else if (rtwdev->hci.bulkout_num == 3) 1156 pg_tbl = &chip->page_table[3]; 1157 else if (rtwdev->hci.bulkout_num == 4) 1158 pg_tbl = &chip->page_table[4]; 1159 else 1160 return -EINVAL; 1161 break; 1162 default: 1163 return -EINVAL; 1164 } 1165 1166 pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num - 1167 pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num; 1168 if (rtw_chip_wcpu_11n(rtwdev)) 1169 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num); 1170 else 1171 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num); 1172 } 1173 1174 static int init_h2c(struct rtw_dev *rtwdev) 1175 { 1176 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 1177 u8 value8; 1178 u32 value32; 1179 u32 h2cq_addr; 1180 u32 h2cq_size; 1181 u32 h2cq_free; 1182 u32 wp, rp; 1183 1184 if (rtw_chip_wcpu_11n(rtwdev)) 1185 return 0; 1186 1187 h2cq_addr = fifo->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT; 1188 h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT; 1189 1190 value32 = rtw_read32(rtwdev, REG_H2C_HEAD); 1191 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1192 rtw_write32(rtwdev, REG_H2C_HEAD, value32); 1193 1194 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR); 1195 value32 = (value32 & 0xFFFC0000) | h2cq_addr; 1196 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32); 1197 1198 value32 = rtw_read32(rtwdev, REG_H2C_TAIL); 1199 value32 &= 0xFFFC0000; 1200 value32 |= (h2cq_addr + h2cq_size); 1201 rtw_write32(rtwdev, REG_H2C_TAIL, value32); 1202 1203 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1204 value8 = (u8)((value8 & 0xFC) | 0x01); 1205 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1206 1207 value8 = rtw_read8(rtwdev, REG_H2C_INFO); 1208 value8 = (u8)((value8 & 0xFB) | 0x04); 1209 rtw_write8(rtwdev, REG_H2C_INFO, value8); 1210 1211 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1); 1212 value8 = (u8)((value8 & 0x7f) | 0x80); 1213 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8); 1214 1215 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF; 1216 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF; 1217 h2cq_free = wp >= rp ? h2cq_size - (wp - rp) : rp - wp; 1218 1219 if (h2cq_size != h2cq_free) { 1220 rtw_err(rtwdev, "H2C queue mismatch\n"); 1221 return -EINVAL; 1222 } 1223 1224 return 0; 1225 } 1226 1227 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev) 1228 { 1229 int ret; 1230 1231 ret = txdma_queue_mapping(rtwdev); 1232 if (ret) 1233 return ret; 1234 1235 ret = priority_queue_cfg(rtwdev); 1236 if (ret) 1237 return ret; 1238 1239 ret = init_h2c(rtwdev); 1240 if (ret) 1241 return ret; 1242 1243 return 0; 1244 } 1245 1246 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev) 1247 { 1248 u8 value8; 1249 1250 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE); 1251 if (rtw_chip_wcpu_11ac(rtwdev)) { 1252 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1); 1253 value8 &= 0xF0; 1254 /* For rxdesc len = 0 issue */ 1255 value8 |= 0xF; 1256 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8); 1257 } 1258 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS); 1259 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9)); 1260 1261 return 0; 1262 } 1263 1264 int rtw_mac_init(struct rtw_dev *rtwdev) 1265 { 1266 struct rtw_chip_info *chip = rtwdev->chip; 1267 int ret; 1268 1269 ret = rtw_init_trx_cfg(rtwdev); 1270 if (ret) 1271 return ret; 1272 1273 ret = chip->ops->mac_init(rtwdev); 1274 if (ret) 1275 return ret; 1276 1277 ret = rtw_drv_info_cfg(rtwdev); 1278 if (ret) 1279 return ret; 1280 1281 rtw_hci_interface_cfg(rtwdev); 1282 1283 return 0; 1284 } 1285