1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define FIFO_DUMP_ADDR 0x8000 20 21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 22 #define DLFW_PAGE_SIZE_LEGACY 0x1000 23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 24 #define DLFW_BLK_SIZE_LEGACY 4 25 #define FW_START_ADDR_LEGACY 0x1000 26 27 enum rtw_c2h_cmd_id { 28 C2H_CCX_TX_RPT = 0x03, 29 C2H_BT_INFO = 0x09, 30 C2H_BT_MP_INFO = 0x0b, 31 C2H_RA_RPT = 0x0c, 32 C2H_HW_FEATURE_REPORT = 0x19, 33 C2H_WLAN_INFO = 0x27, 34 C2H_WLAN_RFON = 0x32, 35 C2H_HW_FEATURE_DUMP = 0xfd, 36 C2H_HALMAC = 0xff, 37 }; 38 39 enum rtw_c2h_cmd_id_ext { 40 C2H_CCX_RPT = 0x0f, 41 }; 42 43 struct rtw_c2h_cmd { 44 u8 id; 45 u8 seq; 46 u8 payload[]; 47 } __packed; 48 49 enum rtw_rsvd_packet_type { 50 RSVD_BEACON, 51 RSVD_DUMMY, 52 RSVD_PS_POLL, 53 RSVD_PROBE_RESP, 54 RSVD_NULL, 55 RSVD_QOS_NULL, 56 RSVD_LPS_PG_DPK, 57 RSVD_LPS_PG_INFO, 58 RSVD_PROBE_REQ, 59 RSVD_NLO_INFO, 60 RSVD_CH_INFO, 61 }; 62 63 enum rtw_fw_rf_type { 64 FW_RF_1T2R = 0, 65 FW_RF_2T4R = 1, 66 FW_RF_2T2R = 2, 67 FW_RF_2T3R = 3, 68 FW_RF_1T1R = 4, 69 FW_RF_2T2R_GREEN = 5, 70 FW_RF_3T3R = 6, 71 FW_RF_3T4R = 7, 72 FW_RF_4T4R = 8, 73 FW_RF_MAX_TYPE = 0xF, 74 }; 75 76 enum rtw_fw_feature { 77 FW_FEATURE_SIG = BIT(0), 78 FW_FEATURE_LPS_C2H = BIT(1), 79 FW_FEATURE_LCLK = BIT(2), 80 FW_FEATURE_PG = BIT(3), 81 FW_FEATURE_MAX = BIT(31), 82 }; 83 84 struct rtw_coex_info_req { 85 u8 seq; 86 u8 op_code; 87 u8 para1; 88 u8 para2; 89 u8 para3; 90 }; 91 92 struct rtw_iqk_para { 93 u8 clear; 94 u8 segment_iqk; 95 }; 96 97 struct rtw_lps_pg_dpk_hdr { 98 u16 dpk_path_ok; 99 u8 dpk_txagc[2]; 100 u16 dpk_gs[2]; 101 u32 coef[2][20]; 102 u8 dpk_ch; 103 } __packed; 104 105 struct rtw_lps_pg_info_hdr { 106 u8 macid; 107 u8 mbssid; 108 u8 pattern_count; 109 u8 mu_tab_group_id; 110 u8 sec_cam_count; 111 u8 tx_bu_page_count; 112 u16 rsvd; 113 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 114 } __packed; 115 116 struct rtw_rsvd_page { 117 /* associated with each vif */ 118 struct list_head vif_list; 119 struct rtw_vif *rtwvif; 120 121 /* associated when build rsvd page */ 122 struct list_head build_list; 123 124 struct sk_buff *skb; 125 enum rtw_rsvd_packet_type type; 126 u8 page; 127 bool add_txdesc; 128 struct cfg80211_ssid *ssid; 129 }; 130 131 enum rtw_keep_alive_pkt_type { 132 KEEP_ALIVE_NULL_PKT = 0, 133 KEEP_ALIVE_ARP_RSP = 1, 134 }; 135 136 struct rtw_nlo_info_hdr { 137 u8 nlo_count; 138 u8 hidden_ap_count; 139 u8 rsvd1[2]; 140 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 141 u8 rsvd2[8]; 142 u8 ssid_len[16]; 143 u8 chiper[16]; 144 u8 rsvd3[16]; 145 u8 location[8]; 146 } __packed; 147 148 enum rtw_packet_type { 149 RTW_PACKET_PROBE_REQ = 0x00, 150 151 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 152 }; 153 154 struct rtw_fw_wow_keep_alive_para { 155 bool adopt; 156 u8 pkt_type; 157 u8 period; /* unit: sec */ 158 }; 159 160 struct rtw_fw_wow_disconnect_para { 161 bool adopt; 162 u8 period; /* unit: sec */ 163 u8 retry_count; 164 }; 165 166 struct rtw_ch_switch_option { 167 u8 periodic_option; 168 u32 tsf_high; 169 u32 tsf_low; 170 u8 dest_ch_en; 171 u8 absolute_time_en; 172 u8 dest_ch; 173 u8 normal_period; 174 u8 normal_period_sel; 175 u8 normal_cycle; 176 u8 slow_period; 177 u8 slow_period_sel; 178 u8 nlo_en; 179 }; 180 181 struct rtw_fw_hdr { 182 __le16 signature; 183 u8 category; 184 u8 function; 185 __le16 version; /* 0x04 */ 186 u8 subversion; 187 u8 subindex; 188 __le32 rsvd; /* 0x08 */ 189 __le32 feature; /* 0x0C */ 190 u8 month; /* 0x10 */ 191 u8 day; 192 u8 hour; 193 u8 min; 194 __le16 year; /* 0x14 */ 195 __le16 rsvd3; 196 u8 mem_usage; /* 0x18 */ 197 u8 rsvd4[3]; 198 __le16 h2c_fmt_ver; /* 0x1C */ 199 __le16 rsvd5; 200 __le32 dmem_addr; /* 0x20 */ 201 __le32 dmem_size; 202 __le32 rsvd6; 203 __le32 rsvd7; 204 __le32 imem_size; /* 0x30 */ 205 __le32 emem_size; 206 __le32 emem_addr; 207 __le32 imem_addr; 208 } __packed; 209 210 struct rtw_fw_hdr_legacy { 211 __le16 signature; 212 u8 category; 213 u8 function; 214 __le16 version; /* 0x04 */ 215 u8 subversion1; 216 u8 subversion2; 217 u8 month; /* 0x08 */ 218 u8 day; 219 u8 hour; 220 u8 minute; 221 __le16 size; 222 __le16 rsvd2; 223 __le32 idx; /* 0x10 */ 224 __le32 rsvd3; 225 __le32 rsvd4; /* 0x18 */ 226 __le32 rsvd5; 227 } __packed; 228 229 /* C2H */ 230 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) 231 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) 232 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) 233 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) 234 235 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 236 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 237 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 238 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 239 240 /* PKT H2C */ 241 #define H2C_PKT_CMD_ID 0xFF 242 #define H2C_PKT_CATEGORY 0x01 243 244 #define H2C_PKT_GENERAL_INFO 0x0D 245 #define H2C_PKT_PHYDM_INFO 0x11 246 #define H2C_PKT_IQK 0x0E 247 248 #define H2C_PKT_CH_SWITCH 0x02 249 #define H2C_PKT_UPDATE_PKT 0x0C 250 251 #define H2C_PKT_CH_SWITCH_LEN 0x20 252 #define H2C_PKT_UPDATE_PKT_LEN 0x4 253 254 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 255 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 256 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 257 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 258 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 259 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 260 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 261 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 262 263 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 264 { 265 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 266 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 267 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 268 } 269 270 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 271 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 272 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 273 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 274 275 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 276 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 277 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 278 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 279 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 280 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 281 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 282 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 283 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 284 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 285 #define IQK_SET_CLEAR(h2c_pkt, value) \ 286 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 287 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 288 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 289 290 #define CHSW_INFO_SET_CH(pkt, value) \ 291 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 292 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 293 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 294 #define CHSW_INFO_SET_BW(pkt, value) \ 295 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 296 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 297 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 298 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 299 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 300 301 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 302 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 303 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 304 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 305 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 306 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 307 308 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 309 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 310 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 311 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 312 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 313 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 314 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 315 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 316 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 317 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 318 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 319 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 320 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 321 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 322 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 323 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 324 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 325 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 326 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 327 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 328 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 329 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 330 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 331 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 332 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 333 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 334 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 335 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 336 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 337 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 338 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 339 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 340 341 /* Command H2C */ 342 #define H2C_CMD_RSVD_PAGE 0x0 343 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 344 #define H2C_CMD_SET_PWR_MODE 0x20 345 #define H2C_CMD_LPS_PG_INFO 0x2b 346 #define H2C_CMD_RA_INFO 0x40 347 #define H2C_CMD_RSSI_MONITOR 0x42 348 #define H2C_CMD_WL_PHY_INFO 0x58 349 350 #define H2C_CMD_COEX_TDMA_TYPE 0x60 351 #define H2C_CMD_QUERY_BT_INFO 0x61 352 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 353 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 354 #define H2C_CMD_WL_CH_INFO 0x66 355 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 356 #define H2C_CMD_BT_WIFI_CONTROL 0x69 357 #define H2C_CMD_WIFI_CALIBRATION 0x6d 358 359 #define H2C_CMD_KEEP_ALIVE 0x03 360 #define H2C_CMD_DISCONNECT_DECISION 0x04 361 #define H2C_CMD_WOWLAN 0x80 362 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 363 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 364 #define H2C_CMD_NLO_INFO 0x8C 365 366 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 367 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 368 369 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 370 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 371 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 372 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 373 374 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ 375 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) 376 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ 377 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) 378 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ 379 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 380 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ 381 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 382 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ 383 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 384 385 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 386 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 387 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 388 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 389 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 390 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 391 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 392 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 393 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 394 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 395 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 396 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 397 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 398 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 399 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 400 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 401 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 402 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 403 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 404 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 405 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 406 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 407 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 408 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 409 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 410 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 411 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 412 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 413 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 414 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 415 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 416 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 417 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 418 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 419 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 420 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 421 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 422 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 423 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 424 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 425 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 426 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 427 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 428 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 429 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 430 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 431 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 432 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 433 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 434 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 435 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 436 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 437 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 438 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 439 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 440 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 441 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 442 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 443 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 444 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 445 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 446 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 447 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 448 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 449 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 450 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 451 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 452 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 453 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 454 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 455 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 456 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 457 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 458 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 459 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 460 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 461 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 462 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 463 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 464 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 465 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 466 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 467 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 468 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 469 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 470 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 471 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 473 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 475 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 476 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 477 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 478 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 479 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 480 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 481 482 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 483 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 484 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 485 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 486 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 487 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 488 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 489 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 490 491 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 492 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 493 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 494 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 495 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 496 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 497 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 498 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 499 500 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 501 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 502 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 503 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 504 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 505 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 506 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 507 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 508 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 509 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 510 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 511 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 512 513 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 514 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 515 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 516 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 517 518 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 519 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 520 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 521 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 522 523 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 524 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 525 #define SET_NLO_PS_32K(h2c_pkt, value) \ 526 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 527 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 528 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 529 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 530 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 531 532 #define GET_FW_DUMP_LEN(_header) \ 533 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) 534 #define GET_FW_DUMP_SEQ(_header) \ 535 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) 536 #define GET_FW_DUMP_MORE(_header) \ 537 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) 538 #define GET_FW_DUMP_VERSION(_header) \ 539 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) 540 #define GET_FW_DUMP_TLV_TYPE(_header) \ 541 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) 542 #define GET_FW_DUMP_TLV_LEN(_header) \ 543 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) 544 #define GET_FW_DUMP_TLV_VAL(_header) \ 545 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) 546 547 #define RFK_SET_INFORM_START(h2c_pkt, value) \ 548 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 549 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 550 { 551 u32 pkt_offset; 552 553 pkt_offset = *((u32 *)skb->cb); 554 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 555 } 556 557 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 558 struct sk_buff *skb); 559 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 560 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 561 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 562 563 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 564 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); 565 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 566 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 567 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 568 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 569 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 570 struct rtw_coex_info_req *req); 571 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 572 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 573 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 574 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 575 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 576 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 577 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 578 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 579 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); 580 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 581 u8 *buf, u32 size); 582 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, 583 struct rtw_vif *rtwvif); 584 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, 585 struct rtw_vif *rtwvif); 586 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, 587 struct rtw_vif *rtwvif); 588 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, 589 struct rtw_vif *rtwvif); 590 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); 591 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 592 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 593 u32 offset, u32 size, u32 *buf); 594 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 595 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 596 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 597 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 598 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 599 u8 pairwise_key_enc, 600 u8 group_key_enc); 601 602 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 603 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 604 struct cfg80211_ssid *ssid); 605 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 606 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); 607 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); 608 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, 609 u32 *buffer); 610 611 #endif 612