1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 #define FW_HDR_VERSION 4 15 #define FW_HDR_SUBVERSION 6 16 #define FW_HDR_SUBINDEX 7 17 #define FW_HDR_MONTH 16 18 #define FW_HDR_DATE 17 19 #define FW_HDR_HOUR 18 20 #define FW_HDR_MIN 19 21 #define FW_HDR_YEAR 20 22 #define FW_HDR_MEM_USAGE 24 23 #define FW_HDR_H2C_FMT_VER 28 24 #define FW_HDR_DMEM_ADDR 32 25 #define FW_HDR_DMEM_SIZE 36 26 #define FW_HDR_IMEM_SIZE 48 27 #define FW_HDR_EMEM_SIZE 52 28 #define FW_HDR_EMEM_ADDR 56 29 #define FW_HDR_IMEM_ADDR 60 30 31 #define FIFO_PAGE_SIZE_SHIFT 12 32 #define FIFO_PAGE_SIZE 4096 33 #define RSVD_PAGE_START_ADDR 0x780 34 #define FIFO_DUMP_ADDR 0x8000 35 36 enum rtw_c2h_cmd_id { 37 C2H_BT_INFO = 0x09, 38 C2H_HW_FEATURE_REPORT = 0x19, 39 C2H_HW_FEATURE_DUMP = 0xfd, 40 C2H_HALMAC = 0xff, 41 }; 42 43 enum rtw_c2h_cmd_id_ext { 44 C2H_CCX_RPT = 0x0f, 45 }; 46 47 struct rtw_c2h_cmd { 48 u8 id; 49 u8 seq; 50 u8 payload[0]; 51 } __packed; 52 53 enum rtw_rsvd_packet_type { 54 RSVD_BEACON, 55 RSVD_PS_POLL, 56 RSVD_PROBE_RESP, 57 RSVD_NULL, 58 RSVD_QOS_NULL, 59 }; 60 61 enum rtw_fw_rf_type { 62 FW_RF_1T2R = 0, 63 FW_RF_2T4R = 1, 64 FW_RF_2T2R = 2, 65 FW_RF_2T3R = 3, 66 FW_RF_1T1R = 4, 67 FW_RF_2T2R_GREEN = 5, 68 FW_RF_3T3R = 6, 69 FW_RF_3T4R = 7, 70 FW_RF_4T4R = 8, 71 FW_RF_MAX_TYPE = 0xF, 72 }; 73 74 struct rtw_iqk_para { 75 u8 clear; 76 u8 segment_iqk; 77 }; 78 79 struct rtw_rsvd_page { 80 struct list_head list; 81 struct sk_buff *skb; 82 enum rtw_rsvd_packet_type type; 83 u8 page; 84 bool add_txdesc; 85 }; 86 87 /* C2H */ 88 #define GET_CCX_REPORT_SEQNUM(c2h_payload) (c2h_payload[8] & 0xfc) 89 #define GET_CCX_REPORT_STATUS(c2h_payload) (c2h_payload[9] & 0xc0) 90 91 /* PKT H2C */ 92 #define H2C_PKT_CMD_ID 0xFF 93 #define H2C_PKT_CATEGORY 0x01 94 95 #define H2C_PKT_GENERAL_INFO 0x0D 96 #define H2C_PKT_PHYDM_INFO 0x11 97 #define H2C_PKT_IQK 0x0E 98 99 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 100 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 101 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 102 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 103 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 104 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 105 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 106 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 107 108 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 109 { 110 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 111 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 112 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 113 } 114 115 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 116 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 117 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 118 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 119 120 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 121 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 122 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 123 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 124 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 125 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 126 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 127 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 128 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 129 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 130 #define IQK_SET_CLEAR(h2c_pkt, value) \ 131 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 132 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 133 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 134 135 /* Command H2C */ 136 #define H2C_CMD_RSVD_PAGE 0x0 137 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 138 #define H2C_CMD_SET_PWR_MODE 0x20 139 #define H2C_CMD_RA_INFO 0x40 140 #define H2C_CMD_RSSI_MONITOR 0x42 141 142 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 143 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 144 145 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 146 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 147 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 148 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 149 150 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 151 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 152 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 153 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 154 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 155 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 156 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 157 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 158 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 159 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 160 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 161 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 162 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 163 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 164 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 165 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 166 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 167 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 168 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 169 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 170 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 171 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 172 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 173 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 174 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 175 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 176 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 177 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 178 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 179 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 180 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 181 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 182 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 183 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 184 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 185 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 186 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 187 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 188 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 189 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 190 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 191 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 192 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 193 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 194 195 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 196 { 197 u32 pkt_offset; 198 199 pkt_offset = *((u32 *)skb->cb); 200 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 201 } 202 203 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 204 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 205 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 206 207 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 208 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 209 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 210 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 211 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 212 void rtw_add_rsvd_page(struct rtw_dev *rtwdev, enum rtw_rsvd_packet_type type, 213 bool txdesc); 214 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 215 u8 *buf, u32 size); 216 void rtw_reset_rsvd_page(struct rtw_dev *rtwdev); 217 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev, 218 struct ieee80211_vif *vif); 219 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 220 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 221 u32 offset, u32 size, u32 *buf); 222 #endif 223