1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTW_FW_H_
6 #define __RTW_FW_H_
7 
8 #define H2C_PKT_SIZE		32
9 #define H2C_PKT_HDR_SIZE	8
10 
11 /* FW bin information */
12 #define FW_HDR_SIZE			64
13 #define FW_HDR_CHKSUM_SIZE		8
14 
15 #define FW_NLO_INFO_CHECK_SIZE		4
16 
17 #define FIFO_PAGE_SIZE_SHIFT		12
18 #define FIFO_PAGE_SIZE			4096
19 #define FIFO_DUMP_ADDR			0x8000
20 
21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY	12
22 #define DLFW_PAGE_SIZE_LEGACY		0x1000
23 #define DLFW_BLK_SIZE_SHIFT_LEGACY	2
24 #define DLFW_BLK_SIZE_LEGACY		4
25 #define FW_START_ADDR_LEGACY		0x1000
26 
27 #define BCN_LOSS_CNT			10
28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE	0
29 #define BCN_FILTER_CONNECTION_LOSS	1
30 #define BCN_FILTER_CONNECTED		2
31 #define BCN_FILTER_NOTIFY_BEACON_LOSS	3
32 
33 #define SCAN_NOTIFY_TIMEOUT  msecs_to_jiffies(10)
34 
35 #define RTW_CHANNEL_TIME		45
36 #define RTW_OFF_CHAN_TIME		100
37 #define RTW_PASS_CHAN_TIME		105
38 #define RTW_DFS_CHAN_TIME		20
39 #define RTW_CH_INFO_SIZE		4
40 #define RTW_EX_CH_INFO_SIZE		3
41 #define RTW_EX_CH_INFO_HDR_SIZE		2
42 #define RTW_SCAN_WIDTH			0
43 #define RTW_PRI_CH_IDX			1
44 #define RTW_PROBE_PG_CNT		2
45 
46 enum rtw_c2h_cmd_id {
47 	C2H_CCX_TX_RPT = 0x03,
48 	C2H_BT_INFO = 0x09,
49 	C2H_BT_MP_INFO = 0x0b,
50 	C2H_RA_RPT = 0x0c,
51 	C2H_HW_FEATURE_REPORT = 0x19,
52 	C2H_WLAN_INFO = 0x27,
53 	C2H_WLAN_RFON = 0x32,
54 	C2H_BCN_FILTER_NOTIFY = 0x36,
55 	C2H_ADAPTIVITY = 0x37,
56 	C2H_SCAN_RESULT = 0x38,
57 	C2H_HW_FEATURE_DUMP = 0xfd,
58 	C2H_HALMAC = 0xff,
59 };
60 
61 enum rtw_c2h_cmd_id_ext {
62 	C2H_SCAN_STATUS_RPT = 0x3,
63 	C2H_CCX_RPT = 0x0f,
64 	C2H_CHAN_SWITCH = 0x22,
65 };
66 
67 struct rtw_c2h_cmd {
68 	u8 id;
69 	u8 seq;
70 	u8 payload[];
71 } __packed;
72 
73 struct rtw_c2h_adaptivity {
74 	u8 density;
75 	u8 igi;
76 	u8 l2h_th_init;
77 	u8 l2h;
78 	u8 h2l;
79 	u8 option;
80 } __packed;
81 
82 enum rtw_rsvd_packet_type {
83 	RSVD_BEACON,
84 	RSVD_DUMMY,
85 	RSVD_PS_POLL,
86 	RSVD_PROBE_RESP,
87 	RSVD_NULL,
88 	RSVD_QOS_NULL,
89 	RSVD_LPS_PG_DPK,
90 	RSVD_LPS_PG_INFO,
91 	RSVD_PROBE_REQ,
92 	RSVD_NLO_INFO,
93 	RSVD_CH_INFO,
94 };
95 
96 enum rtw_fw_rf_type {
97 	FW_RF_1T2R = 0,
98 	FW_RF_2T4R = 1,
99 	FW_RF_2T2R = 2,
100 	FW_RF_2T3R = 3,
101 	FW_RF_1T1R = 4,
102 	FW_RF_2T2R_GREEN = 5,
103 	FW_RF_3T3R = 6,
104 	FW_RF_3T4R = 7,
105 	FW_RF_4T4R = 8,
106 	FW_RF_MAX_TYPE = 0xF,
107 };
108 
109 enum rtw_fw_feature {
110 	FW_FEATURE_SIG = BIT(0),
111 	FW_FEATURE_LPS_C2H = BIT(1),
112 	FW_FEATURE_LCLK = BIT(2),
113 	FW_FEATURE_PG = BIT(3),
114 	FW_FEATURE_TX_WAKE = BIT(4),
115 	FW_FEATURE_BCN_FILTER = BIT(5),
116 	FW_FEATURE_NOTIFY_SCAN = BIT(6),
117 	FW_FEATURE_ADAPTIVITY = BIT(7),
118 	FW_FEATURE_SCAN_OFFLOAD = BIT(8),
119 	FW_FEATURE_MAX = BIT(31),
120 };
121 
122 enum rtw_beacon_filter_offload_mode {
123 	BCN_FILTER_OFFLOAD_MODE_0 = 0,
124 	BCN_FILTER_OFFLOAD_MODE_1,
125 	BCN_FILTER_OFFLOAD_MODE_2,
126 	BCN_FILTER_OFFLOAD_MODE_3,
127 
128 	BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0,
129 };
130 
131 struct rtw_coex_info_req {
132 	u8 seq;
133 	u8 op_code;
134 	u8 para1;
135 	u8 para2;
136 	u8 para3;
137 };
138 
139 struct rtw_iqk_para {
140 	u8 clear;
141 	u8 segment_iqk;
142 };
143 
144 struct rtw_lps_pg_dpk_hdr {
145 	u16 dpk_path_ok;
146 	u8 dpk_txagc[2];
147 	u16 dpk_gs[2];
148 	u32 coef[2][20];
149 	u8 dpk_ch;
150 } __packed;
151 
152 struct rtw_lps_pg_info_hdr {
153 	u8 macid;
154 	u8 mbssid;
155 	u8 pattern_count;
156 	u8 mu_tab_group_id;
157 	u8 sec_cam_count;
158 	u8 tx_bu_page_count;
159 	u16 rsvd;
160 	u8 sec_cam[MAX_PG_CAM_BACKUP_NUM];
161 } __packed;
162 
163 struct rtw_rsvd_page {
164 	/* associated with each vif */
165 	struct list_head vif_list;
166 	struct rtw_vif *rtwvif;
167 
168 	/* associated when build rsvd page */
169 	struct list_head build_list;
170 
171 	struct sk_buff *skb;
172 	enum rtw_rsvd_packet_type type;
173 	u8 page;
174 	bool add_txdesc;
175 	struct cfg80211_ssid *ssid;
176 	u16 probe_req_size;
177 };
178 
179 enum rtw_keep_alive_pkt_type {
180 	KEEP_ALIVE_NULL_PKT = 0,
181 	KEEP_ALIVE_ARP_RSP = 1,
182 };
183 
184 struct rtw_nlo_info_hdr {
185 	u8 nlo_count;
186 	u8 hidden_ap_count;
187 	u8 rsvd1[2];
188 	u8 pattern_check[FW_NLO_INFO_CHECK_SIZE];
189 	u8 rsvd2[8];
190 	u8 ssid_len[16];
191 	u8 chiper[16];
192 	u8 rsvd3[16];
193 	u8 location[8];
194 } __packed;
195 
196 enum rtw_packet_type {
197 	RTW_PACKET_PROBE_REQ = 0x00,
198 
199 	RTW_PACKET_UNDEFINE = 0x7FFFFFFF,
200 };
201 
202 struct rtw_fw_wow_keep_alive_para {
203 	bool adopt;
204 	u8 pkt_type;
205 	u8 period;		/* unit: sec */
206 };
207 
208 struct rtw_fw_wow_disconnect_para {
209 	bool adopt;
210 	u8 period;		/* unit: sec */
211 	u8 retry_count;
212 };
213 
214 enum rtw_channel_type {
215 	RTW_CHANNEL_PASSIVE,
216 	RTW_CHANNEL_ACTIVE,
217 	RTW_CHANNEL_RADAR,
218 };
219 
220 enum rtw_scan_extra_id {
221 	RTW_SCAN_EXTRA_ID_DFS,
222 };
223 
224 enum rtw_scan_extra_info {
225 	RTW_SCAN_EXTRA_ACTION_SCAN,
226 };
227 
228 enum rtw_scan_report_code {
229 	RTW_SCAN_REPORT_SUCCESS = 0x00,
230 	RTW_SCAN_REPORT_ERR_PHYDM = 0x01,
231 	RTW_SCAN_REPORT_ERR_ID = 0x02,
232 	RTW_SCAN_REPORT_ERR_TX = 0x03,
233 	RTW_SCAN_REPORT_CANCELED = 0x10,
234 	RTW_SCAN_REPORT_CANCELED_EXT = 0x11,
235 	RTW_SCAN_REPORT_FW_DISABLED = 0xF0,
236 };
237 
238 enum rtw_scan_notify_id {
239 	RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
240 	RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
241 	RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
242 	RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03,
243 	RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04,
244 	RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05,
245 	RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06,
246 	RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07,
247 	RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08,
248 	RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09,
249 	RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A,
250 };
251 
252 enum rtw_scan_notify_status {
253 	RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00,
254 	RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01,
255 	RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02,
256 	RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03,
257 };
258 
259 struct rtw_ch_switch_option {
260 	u8 periodic_option;
261 	u32 tsf_high;
262 	u32 tsf_low;
263 	u8 dest_ch_en;
264 	u8 absolute_time_en;
265 	u8 dest_ch;
266 	u8 normal_period;
267 	u8 normal_period_sel;
268 	u8 normal_cycle;
269 	u8 slow_period;
270 	u8 slow_period_sel;
271 	u8 nlo_en;
272 	bool switch_en;
273 	bool back_op_en;
274 };
275 
276 struct rtw_fw_hdr {
277 	__le16 signature;
278 	u8 category;
279 	u8 function;
280 	__le16 version;		/* 0x04 */
281 	u8 subversion;
282 	u8 subindex;
283 	__le32 rsvd;		/* 0x08 */
284 	__le32 feature;		/* 0x0C */
285 	u8 month;		/* 0x10 */
286 	u8 day;
287 	u8 hour;
288 	u8 min;
289 	__le16 year;		/* 0x14 */
290 	__le16 rsvd3;
291 	u8 mem_usage;		/* 0x18 */
292 	u8 rsvd4[3];
293 	__le16 h2c_fmt_ver;	/* 0x1C */
294 	__le16 rsvd5;
295 	__le32 dmem_addr;	/* 0x20 */
296 	__le32 dmem_size;
297 	__le32 rsvd6;
298 	__le32 rsvd7;
299 	__le32 imem_size;	/* 0x30 */
300 	__le32 emem_size;
301 	__le32 emem_addr;
302 	__le32 imem_addr;
303 } __packed;
304 
305 struct rtw_fw_hdr_legacy {
306 	__le16 signature;
307 	u8 category;
308 	u8 function;
309 	__le16 version;	/* 0x04 */
310 	u8 subversion1;
311 	u8 subversion2;
312 	u8 month;	/* 0x08 */
313 	u8 day;
314 	u8 hour;
315 	u8 minute;
316 	__le16 size;
317 	__le16 rsvd2;
318 	__le32 idx;	/* 0x10 */
319 	__le32 rsvd3;
320 	__le32 rsvd4;	/* 0x18 */
321 	__le32 rsvd5;
322 } __packed;
323 
324 /* C2H */
325 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload)	(c2h_payload[6] & 0xfc)
326 #define GET_CCX_REPORT_STATUS_V0(c2h_payload)	(c2h_payload[0] & 0xc0)
327 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload)	(c2h_payload[8] & 0xfc)
328 #define GET_CCX_REPORT_STATUS_V1(c2h_payload)	(c2h_payload[9] & 0xc0)
329 
330 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload)	(c2h_payload[2] & 0xff)
331 
332 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload)	(c2h_payload[2])
333 #define GET_CHAN_SWITCH_ID(c2h_payload)		(c2h_payload[3])
334 #define GET_CHAN_SWITCH_STATUS(c2h_payload)	(c2h_payload[4])
335 #define GET_RA_REPORT_RATE(c2h_payload)		(c2h_payload[0] & 0x7f)
336 #define GET_RA_REPORT_SGI(c2h_payload)		((c2h_payload[0] & 0x80) >> 7)
337 #define GET_RA_REPORT_BW(c2h_payload)		(c2h_payload[6])
338 #define GET_RA_REPORT_MACID(c2h_payload)	(c2h_payload[1])
339 
340 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload)	(c2h_payload[1] & 0xf)
341 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload)	(c2h_payload[1] & 0x10)
342 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload)	(c2h_payload[2] - 100)
343 
344 /* PKT H2C */
345 #define H2C_PKT_CMD_ID 0xFF
346 #define H2C_PKT_CATEGORY 0x01
347 
348 #define H2C_PKT_GENERAL_INFO 0x0D
349 #define H2C_PKT_PHYDM_INFO 0x11
350 #define H2C_PKT_IQK 0x0E
351 
352 #define H2C_PKT_CH_SWITCH 0x02
353 #define H2C_PKT_UPDATE_PKT 0x0C
354 #define H2C_PKT_SCAN_OFFLOAD 0x19
355 
356 #define H2C_PKT_CH_SWITCH_LEN 0x20
357 #define H2C_PKT_UPDATE_PKT_LEN 0x4
358 
359 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value)                                   \
360 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
361 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value)                                     \
362 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
363 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value)                                 \
364 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
365 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value)                                  \
366 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
367 
368 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
369 {
370 	SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
371 	SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
372 	SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
373 }
374 
375 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value)                             \
376 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
377 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value)                        \
378 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
379 
380 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value)                                \
381 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
382 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value)                                 \
383 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
384 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value)                                 \
385 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
386 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value)                           \
387 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
388 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value)                           \
389 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
390 #define IQK_SET_CLEAR(h2c_pkt, value)                                          \
391 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
392 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value)                                    \
393 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
394 
395 #define CHSW_INFO_SET_CH(pkt, value)					       \
396 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))
397 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value)				       \
398 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))
399 #define CHSW_INFO_SET_BW(pkt, value)					       \
400 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))
401 #define CHSW_INFO_SET_TIMEOUT(pkt, value)				       \
402 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))
403 #define CHSW_INFO_SET_ACTION_ID(pkt, value)				       \
404 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))
405 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value)				       \
406 	le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31))
407 
408 #define CH_INFO_SET_CH(pkt, value)					       \
409 	u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
410 #define CH_INFO_SET_PRI_CH_IDX(pkt, value)				       \
411 	u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
412 #define CH_INFO_SET_BW(pkt, value)					       \
413 	u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
414 #define CH_INFO_SET_TIMEOUT(pkt, value)					       \
415 	u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
416 #define CH_INFO_SET_ACTION_ID(pkt, value)				       \
417 	u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
418 #define CH_INFO_SET_EXTRA_INFO(pkt, value)				       \
419 	u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7))
420 
421 #define EXTRA_CH_INFO_SET_ID(pkt, value)				       \
422 	u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
423 #define EXTRA_CH_INFO_SET_INFO(pkt, value)				       \
424 	u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7))
425 #define EXTRA_CH_INFO_SET_SIZE(pkt, value)				       \
426 	u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
427 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value)			       \
428 	u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))
429 
430 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value)				       \
431 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))
432 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value)				       \
433 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
434 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value)				       \
435 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))
436 
437 #define CH_SWITCH_SET_START(h2c_pkt, value)				       \
438 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
439 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value)			       \
440 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
441 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value)			       \
442 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
443 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value)			       \
444 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))
445 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value)				       \
446 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5))
447 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value)			       \
448 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6))
449 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value)				       \
450 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
451 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value)				       \
452 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
453 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value)			       \
454 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
455 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value)				       \
456 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
457 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value)				       \
458 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
459 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value)			       \
460 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))
461 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value)			       \
462 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))
463 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value)			       \
464 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))
465 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value)			       \
466 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))
467 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value)			       \
468 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))
469 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value)				       \
470 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))
471 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value)				       \
472 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))
473 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value)				       \
474 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))
475 
476 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value)				       \
477 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
478 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value)			       \
479 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
480 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value)			       \
481 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
482 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value)			       \
483 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3))
484 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value)			       \
485 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4))
486 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value)				       \
487 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
488 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value)			       \
489 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))
490 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value)			       \
491 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
492 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value)				       \
493 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))
494 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value)			       \
495 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))
496 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value)				       \
497 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))
498 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value)			       \
499 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))
500 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value)			       \
501 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))
502 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value)			       \
503 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))
504 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value)				       \
505 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))
506 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value)			       \
507 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))
508 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value)			       \
509 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))
510 
511 /* Command H2C */
512 #define H2C_CMD_RSVD_PAGE		0x0
513 #define H2C_CMD_MEDIA_STATUS_RPT	0x01
514 #define H2C_CMD_SET_PWR_MODE		0x20
515 #define H2C_CMD_LPS_PG_INFO		0x2b
516 #define H2C_CMD_RA_INFO			0x40
517 #define H2C_CMD_RSSI_MONITOR		0x42
518 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0	0x56
519 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1	0x57
520 #define H2C_CMD_WL_PHY_INFO		0x58
521 #define H2C_CMD_SCAN			0x59
522 #define H2C_CMD_ADAPTIVITY		0x5A
523 
524 #define H2C_CMD_COEX_TDMA_TYPE		0x60
525 #define H2C_CMD_QUERY_BT_INFO		0x61
526 #define H2C_CMD_FORCE_BT_TX_POWER	0x62
527 #define H2C_CMD_IGNORE_WLAN_ACTION	0x63
528 #define H2C_CMD_WL_CH_INFO		0x66
529 #define H2C_CMD_QUERY_BT_MP_INFO	0x67
530 #define H2C_CMD_BT_WIFI_CONTROL		0x69
531 #define H2C_CMD_WIFI_CALIBRATION	0x6d
532 
533 #define H2C_CMD_KEEP_ALIVE		0x03
534 #define H2C_CMD_DISCONNECT_DECISION	0x04
535 #define H2C_CMD_WOWLAN			0x80
536 #define H2C_CMD_REMOTE_WAKE_CTRL	0x81
537 #define H2C_CMD_AOAC_GLOBAL_INFO	0x82
538 #define H2C_CMD_NLO_INFO		0x8C
539 
540 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value)				       \
541 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
542 
543 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value)                           \
544 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
545 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value)                             \
546 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
547 
548 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value)				       \
549 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))
550 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value)				       \
551 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))
552 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value)			       \
553 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
554 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value)			       \
555 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
556 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value)				       \
557 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
558 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value)			       \
559 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
560 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value)		       \
561 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16))
562 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value)			       \
563 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))
564 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value)		       \
565 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))
566 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value)		       \
567 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
568 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value)		       \
569 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))
570 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value)		       \
571 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))
572 
573 #define SET_SCAN_START(h2c_pkt, value)					       \
574 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
575 
576 #define SET_ADAPTIVITY_MODE(h2c_pkt, value)				       \
577 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))
578 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value)				       \
579 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
580 #define SET_ADAPTIVITY_IGI(h2c_pkt, value)				       \
581 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
582 #define SET_ADAPTIVITY_L2H(h2c_pkt, value)				       \
583 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
584 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value)				       \
585 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
586 
587 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value)                                  \
588 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
589 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value)                                  \
590 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
591 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value)                              \
592 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
593 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value)                        \
594 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
595 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value)                               \
596 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
597 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value)                             \
598 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
599 #define LPS_PG_INFO_LOC(h2c_pkt, value)                                        \
600 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
601 #define LPS_PG_DPK_LOC(h2c_pkt, value)                                         \
602 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
603 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value)                                      \
604 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
605 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value)				       \
606 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
607 #define SET_RSSI_INFO_MACID(h2c_pkt, value)                                    \
608 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
609 #define SET_RSSI_INFO_RSSI(h2c_pkt, value)                                     \
610 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
611 #define SET_RSSI_INFO_STBC(h2c_pkt, value)                                     \
612 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
613 #define SET_RA_INFO_MACID(h2c_pkt, value)                                      \
614 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
615 #define SET_RA_INFO_RATE_ID(h2c_pkt, value)                                    \
616 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
617 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value)                                \
618 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
619 #define SET_RA_INFO_SGI_EN(h2c_pkt, value)                                     \
620 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
621 #define SET_RA_INFO_BW_MODE(h2c_pkt, value)                                    \
622 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
623 #define SET_RA_INFO_LDPC(h2c_pkt, value)                                       \
624 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
625 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value)                                  \
626 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
627 #define SET_RA_INFO_VHT_EN(h2c_pkt, value)                                     \
628 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
629 #define SET_RA_INFO_DIS_PT(h2c_pkt, value)                                     \
630 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
631 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value)                                   \
632 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
633 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value)                                   \
634 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
635 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value)                                   \
636 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
637 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value)                                   \
638 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
639 #define SET_QUERY_BT_INFO(h2c_pkt, value)                                      \
640 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
641 #define SET_WL_CH_INFO_LINK(h2c_pkt, value)                                    \
642 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
643 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value)                                    \
644 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
645 #define SET_WL_CH_INFO_BW(h2c_pkt, value)                                      \
646 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
647 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value)                                     \
648 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
649 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value)                                 \
650 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
651 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value)                                   \
652 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
653 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value)                                   \
654 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
655 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value)                                   \
656 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
657 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value)                                  \
658 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
659 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value)                              \
660 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
661 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value)                               \
662 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
663 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value)                               \
664 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
665 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value)                               \
666 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
667 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value)                               \
668 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
669 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value)                               \
670 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
671 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value)                            \
672 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
673 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value)                              \
674 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
675 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value)                              \
676 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
677 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value)                              \
678 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
679 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value)                              \
680 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
681 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value)                              \
682 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
683 
684 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value)				       \
685 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
686 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value)				       \
687 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
688 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value)				       \
689 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
690 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value)			       \
691 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
692 
693 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value)			       \
694 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
695 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value)			       \
696 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
697 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value)		       \
698 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
699 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value)		       \
700 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
701 
702 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value)				       \
703 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
704 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value)			       \
705 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
706 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value)			       \
707 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
708 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value)			       \
709 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11))
710 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value)			       \
711 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14))
712 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value)			       \
713 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15))
714 
715 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value)			       \
716 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
717 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value)		       \
718 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12))
719 
720 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value)		       \
721 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
722 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value)		       \
723 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
724 
725 #define SET_NLO_FUN_EN(h2c_pkt, value)                                         \
726 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
727 #define SET_NLO_PS_32K(h2c_pkt, value)                                         \
728 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
729 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value)                                \
730 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
731 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value)                                   \
732 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
733 
734 #define GET_FW_DUMP_LEN(_header)					\
735 	le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))
736 #define GET_FW_DUMP_SEQ(_header)					\
737 	le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))
738 #define GET_FW_DUMP_MORE(_header)					\
739 	le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23))
740 #define GET_FW_DUMP_VERSION(_header)					\
741 	le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))
742 #define GET_FW_DUMP_TLV_TYPE(_header)					\
743 	le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))
744 #define GET_FW_DUMP_TLV_LEN(_header)					\
745 	le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))
746 #define GET_FW_DUMP_TLV_VAL(_header)					\
747 	le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))
748 
749 #define RFK_SET_INFORM_START(h2c_pkt, value)				\
750 	le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
751 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
752 {
753 	u32 pkt_offset;
754 
755 	pkt_offset = *((u32 *)skb->cb);
756 	return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
757 }
758 
759 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw,
760 					enum rtw_fw_feature feature)
761 {
762 	return !!(fw->feature & feature);
763 }
764 
765 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
766 			       struct sk_buff *skb);
767 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
768 void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
769 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
770 
771 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
772 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
773 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
774 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev);
775 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
776 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
777 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
778 			     struct rtw_coex_info_req *req);
779 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
780 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
781 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
782 			   u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
783 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
784 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
785 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
786 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
787 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev);
788 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
789 				 struct ieee80211_vif *vif);
790 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
791 				u8 *buf, u32 size);
792 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev,
793 			  struct rtw_vif *rtwvif);
794 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev,
795 			   struct rtw_vif *rtwvif);
796 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev,
797 			   struct rtw_vif *rtwvif);
798 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
799 			   struct rtw_vif *rtwvif);
800 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev);
801 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
802 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
803 			   u32 offset, u32 size, u32 *buf);
804 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
805 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
806 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable);
807 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable);
808 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev,
809 				     u8 pairwise_key_enc,
810 				     u8 group_key_enc);
811 
812 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable);
813 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev,
814 				 struct cfg80211_ssid *ssid);
815 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable);
816 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c);
817 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev);
818 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size,
819 		     u32 *buffer);
820 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
821 void rtw_fw_adaptivity(struct rtw_dev *rtwdev);
822 void rtw_store_op_chan(struct rtw_dev *rtwdev);
823 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
824 		       struct ieee80211_scan_request *req);
825 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
826 			  bool aborted);
827 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
828 			bool enable);
829 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb);
830 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb);
831 void rtw_hw_scan_abort(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
832 #endif
833