1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define FIFO_DUMP_ADDR 0x8000 20 21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 22 #define DLFW_PAGE_SIZE_LEGACY 0x1000 23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 24 #define DLFW_BLK_SIZE_LEGACY 4 25 #define FW_START_ADDR_LEGACY 0x1000 26 27 #define BCN_LOSS_CNT 10 28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0 29 #define BCN_FILTER_CONNECTION_LOSS 1 30 #define BCN_FILTER_CONNECTED 2 31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3 32 33 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10) 34 35 enum rtw_c2h_cmd_id { 36 C2H_CCX_TX_RPT = 0x03, 37 C2H_BT_INFO = 0x09, 38 C2H_BT_MP_INFO = 0x0b, 39 C2H_RA_RPT = 0x0c, 40 C2H_HW_FEATURE_REPORT = 0x19, 41 C2H_WLAN_INFO = 0x27, 42 C2H_WLAN_RFON = 0x32, 43 C2H_BCN_FILTER_NOTIFY = 0x36, 44 C2H_SCAN_RESULT = 0x38, 45 C2H_HW_FEATURE_DUMP = 0xfd, 46 C2H_HALMAC = 0xff, 47 }; 48 49 enum rtw_c2h_cmd_id_ext { 50 C2H_CCX_RPT = 0x0f, 51 }; 52 53 struct rtw_c2h_cmd { 54 u8 id; 55 u8 seq; 56 u8 payload[]; 57 } __packed; 58 59 enum rtw_rsvd_packet_type { 60 RSVD_BEACON, 61 RSVD_DUMMY, 62 RSVD_PS_POLL, 63 RSVD_PROBE_RESP, 64 RSVD_NULL, 65 RSVD_QOS_NULL, 66 RSVD_LPS_PG_DPK, 67 RSVD_LPS_PG_INFO, 68 RSVD_PROBE_REQ, 69 RSVD_NLO_INFO, 70 RSVD_CH_INFO, 71 }; 72 73 enum rtw_fw_rf_type { 74 FW_RF_1T2R = 0, 75 FW_RF_2T4R = 1, 76 FW_RF_2T2R = 2, 77 FW_RF_2T3R = 3, 78 FW_RF_1T1R = 4, 79 FW_RF_2T2R_GREEN = 5, 80 FW_RF_3T3R = 6, 81 FW_RF_3T4R = 7, 82 FW_RF_4T4R = 8, 83 FW_RF_MAX_TYPE = 0xF, 84 }; 85 86 enum rtw_fw_feature { 87 FW_FEATURE_SIG = BIT(0), 88 FW_FEATURE_LPS_C2H = BIT(1), 89 FW_FEATURE_LCLK = BIT(2), 90 FW_FEATURE_PG = BIT(3), 91 FW_FEATURE_BCN_FILTER = BIT(5), 92 FW_FEATURE_NOTIFY_SCAN = BIT(6), 93 FW_FEATURE_MAX = BIT(31), 94 }; 95 96 enum rtw_beacon_filter_offload_mode { 97 BCN_FILTER_OFFLOAD_MODE_0 = 0, 98 BCN_FILTER_OFFLOAD_MODE_1, 99 BCN_FILTER_OFFLOAD_MODE_2, 100 BCN_FILTER_OFFLOAD_MODE_3, 101 102 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_1, 103 }; 104 105 struct rtw_coex_info_req { 106 u8 seq; 107 u8 op_code; 108 u8 para1; 109 u8 para2; 110 u8 para3; 111 }; 112 113 struct rtw_iqk_para { 114 u8 clear; 115 u8 segment_iqk; 116 }; 117 118 struct rtw_lps_pg_dpk_hdr { 119 u16 dpk_path_ok; 120 u8 dpk_txagc[2]; 121 u16 dpk_gs[2]; 122 u32 coef[2][20]; 123 u8 dpk_ch; 124 } __packed; 125 126 struct rtw_lps_pg_info_hdr { 127 u8 macid; 128 u8 mbssid; 129 u8 pattern_count; 130 u8 mu_tab_group_id; 131 u8 sec_cam_count; 132 u8 tx_bu_page_count; 133 u16 rsvd; 134 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 135 } __packed; 136 137 struct rtw_rsvd_page { 138 /* associated with each vif */ 139 struct list_head vif_list; 140 struct rtw_vif *rtwvif; 141 142 /* associated when build rsvd page */ 143 struct list_head build_list; 144 145 struct sk_buff *skb; 146 enum rtw_rsvd_packet_type type; 147 u8 page; 148 bool add_txdesc; 149 struct cfg80211_ssid *ssid; 150 }; 151 152 enum rtw_keep_alive_pkt_type { 153 KEEP_ALIVE_NULL_PKT = 0, 154 KEEP_ALIVE_ARP_RSP = 1, 155 }; 156 157 struct rtw_nlo_info_hdr { 158 u8 nlo_count; 159 u8 hidden_ap_count; 160 u8 rsvd1[2]; 161 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 162 u8 rsvd2[8]; 163 u8 ssid_len[16]; 164 u8 chiper[16]; 165 u8 rsvd3[16]; 166 u8 location[8]; 167 } __packed; 168 169 enum rtw_packet_type { 170 RTW_PACKET_PROBE_REQ = 0x00, 171 172 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 173 }; 174 175 struct rtw_fw_wow_keep_alive_para { 176 bool adopt; 177 u8 pkt_type; 178 u8 period; /* unit: sec */ 179 }; 180 181 struct rtw_fw_wow_disconnect_para { 182 bool adopt; 183 u8 period; /* unit: sec */ 184 u8 retry_count; 185 }; 186 187 struct rtw_ch_switch_option { 188 u8 periodic_option; 189 u32 tsf_high; 190 u32 tsf_low; 191 u8 dest_ch_en; 192 u8 absolute_time_en; 193 u8 dest_ch; 194 u8 normal_period; 195 u8 normal_period_sel; 196 u8 normal_cycle; 197 u8 slow_period; 198 u8 slow_period_sel; 199 u8 nlo_en; 200 }; 201 202 struct rtw_fw_hdr { 203 __le16 signature; 204 u8 category; 205 u8 function; 206 __le16 version; /* 0x04 */ 207 u8 subversion; 208 u8 subindex; 209 __le32 rsvd; /* 0x08 */ 210 __le32 feature; /* 0x0C */ 211 u8 month; /* 0x10 */ 212 u8 day; 213 u8 hour; 214 u8 min; 215 __le16 year; /* 0x14 */ 216 __le16 rsvd3; 217 u8 mem_usage; /* 0x18 */ 218 u8 rsvd4[3]; 219 __le16 h2c_fmt_ver; /* 0x1C */ 220 __le16 rsvd5; 221 __le32 dmem_addr; /* 0x20 */ 222 __le32 dmem_size; 223 __le32 rsvd6; 224 __le32 rsvd7; 225 __le32 imem_size; /* 0x30 */ 226 __le32 emem_size; 227 __le32 emem_addr; 228 __le32 imem_addr; 229 } __packed; 230 231 struct rtw_fw_hdr_legacy { 232 __le16 signature; 233 u8 category; 234 u8 function; 235 __le16 version; /* 0x04 */ 236 u8 subversion1; 237 u8 subversion2; 238 u8 month; /* 0x08 */ 239 u8 day; 240 u8 hour; 241 u8 minute; 242 __le16 size; 243 __le16 rsvd2; 244 __le32 idx; /* 0x10 */ 245 __le32 rsvd3; 246 __le32 rsvd4; /* 0x18 */ 247 __le32 rsvd5; 248 } __packed; 249 250 /* C2H */ 251 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) 252 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) 253 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) 254 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) 255 256 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 257 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 258 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 259 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 260 261 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf) 262 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10) 263 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100) 264 265 /* PKT H2C */ 266 #define H2C_PKT_CMD_ID 0xFF 267 #define H2C_PKT_CATEGORY 0x01 268 269 #define H2C_PKT_GENERAL_INFO 0x0D 270 #define H2C_PKT_PHYDM_INFO 0x11 271 #define H2C_PKT_IQK 0x0E 272 273 #define H2C_PKT_CH_SWITCH 0x02 274 #define H2C_PKT_UPDATE_PKT 0x0C 275 276 #define H2C_PKT_CH_SWITCH_LEN 0x20 277 #define H2C_PKT_UPDATE_PKT_LEN 0x4 278 279 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 280 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 281 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 282 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 283 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 284 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 285 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 286 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 287 288 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 289 { 290 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 291 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 292 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 293 } 294 295 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 296 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 297 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 298 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 299 300 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 301 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 302 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 303 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 304 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 305 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 306 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 307 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 308 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 309 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 310 #define IQK_SET_CLEAR(h2c_pkt, value) \ 311 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 312 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 313 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 314 315 #define CHSW_INFO_SET_CH(pkt, value) \ 316 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 317 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 318 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 319 #define CHSW_INFO_SET_BW(pkt, value) \ 320 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 321 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 322 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 323 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 324 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 325 326 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 327 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 328 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 329 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 330 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 331 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 332 333 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 334 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 335 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 336 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 337 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 338 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 339 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 340 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 341 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 342 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 343 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 344 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 345 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 346 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 347 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 348 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 349 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 350 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 351 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 352 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 353 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 354 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 355 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 356 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 357 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 358 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 359 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 360 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 361 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 362 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 363 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 364 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 365 366 /* Command H2C */ 367 #define H2C_CMD_RSVD_PAGE 0x0 368 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 369 #define H2C_CMD_SET_PWR_MODE 0x20 370 #define H2C_CMD_LPS_PG_INFO 0x2b 371 #define H2C_CMD_RA_INFO 0x40 372 #define H2C_CMD_RSSI_MONITOR 0x42 373 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56 374 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57 375 #define H2C_CMD_WL_PHY_INFO 0x58 376 #define H2C_CMD_SCAN 0x59 377 378 #define H2C_CMD_COEX_TDMA_TYPE 0x60 379 #define H2C_CMD_QUERY_BT_INFO 0x61 380 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 381 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 382 #define H2C_CMD_WL_CH_INFO 0x66 383 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 384 #define H2C_CMD_BT_WIFI_CONTROL 0x69 385 #define H2C_CMD_WIFI_CALIBRATION 0x6d 386 387 #define H2C_CMD_KEEP_ALIVE 0x03 388 #define H2C_CMD_DISCONNECT_DECISION 0x04 389 #define H2C_CMD_WOWLAN 0x80 390 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 391 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 392 #define H2C_CMD_NLO_INFO 0x8C 393 394 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 395 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 396 397 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 398 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 399 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 400 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 401 402 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ 403 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) 404 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ 405 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) 406 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ 407 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 408 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ 409 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 410 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ 411 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 412 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \ 413 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 414 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \ 415 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16)) 416 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \ 417 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17)) 418 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \ 419 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21)) 420 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \ 421 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 422 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \ 423 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0)) 424 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \ 425 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4)) 426 427 #define SET_SCAN_START(h2c_pkt, value) \ 428 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 429 430 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 431 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 432 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 433 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 434 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 435 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 436 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 437 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 438 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 439 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 440 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 441 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 442 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 443 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 444 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 445 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 446 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 447 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 448 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 449 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 450 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 451 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 452 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 453 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 454 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 455 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 456 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 457 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 458 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 459 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 460 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 461 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 462 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 463 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 464 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 465 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 466 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 467 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 468 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 469 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 470 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 471 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 472 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 473 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 474 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 475 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 476 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 477 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 478 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 479 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 480 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 481 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 482 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 483 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 484 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 485 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 486 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 487 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 488 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 489 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 490 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 491 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 492 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 493 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 494 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 495 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 496 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 497 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 498 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 499 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 500 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 501 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 502 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 503 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 504 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 505 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 506 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 507 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 508 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 509 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 510 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 511 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 512 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 513 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 514 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 515 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 516 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 517 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 518 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 519 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 520 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 521 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 522 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 523 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 524 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 525 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 526 527 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 528 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 529 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 530 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 531 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 532 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 533 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 534 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 535 536 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 537 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 538 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 539 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 540 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 541 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 542 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 543 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 544 545 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 546 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 547 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 548 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 549 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 550 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 551 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 552 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 553 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 554 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 555 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 556 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 557 558 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 559 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 560 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 561 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 562 563 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 564 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 565 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 566 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 567 568 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 569 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 570 #define SET_NLO_PS_32K(h2c_pkt, value) \ 571 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 572 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 573 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 574 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 575 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 576 577 #define GET_FW_DUMP_LEN(_header) \ 578 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) 579 #define GET_FW_DUMP_SEQ(_header) \ 580 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) 581 #define GET_FW_DUMP_MORE(_header) \ 582 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) 583 #define GET_FW_DUMP_VERSION(_header) \ 584 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) 585 #define GET_FW_DUMP_TLV_TYPE(_header) \ 586 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) 587 #define GET_FW_DUMP_TLV_LEN(_header) \ 588 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) 589 #define GET_FW_DUMP_TLV_VAL(_header) \ 590 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) 591 592 #define RFK_SET_INFORM_START(h2c_pkt, value) \ 593 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 594 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 595 { 596 u32 pkt_offset; 597 598 pkt_offset = *((u32 *)skb->cb); 599 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 600 } 601 602 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw, 603 enum rtw_fw_feature feature) 604 { 605 return !!(fw->feature & feature); 606 } 607 608 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 609 struct sk_buff *skb); 610 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 611 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 612 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 613 614 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 615 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); 616 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 617 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 618 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 619 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 620 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 621 struct rtw_coex_info_req *req); 622 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 623 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 624 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 625 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 626 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 627 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 628 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 629 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 630 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); 631 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect, 632 struct ieee80211_vif *vif); 633 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 634 u8 *buf, u32 size); 635 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, 636 struct rtw_vif *rtwvif); 637 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, 638 struct rtw_vif *rtwvif); 639 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, 640 struct rtw_vif *rtwvif); 641 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, 642 struct rtw_vif *rtwvif); 643 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); 644 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 645 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 646 u32 offset, u32 size, u32 *buf); 647 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 648 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 649 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 650 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 651 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 652 u8 pairwise_key_enc, 653 u8 group_key_enc); 654 655 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 656 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 657 struct cfg80211_ssid *ssid); 658 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 659 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); 660 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); 661 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, 662 u32 *buffer); 663 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 664 #endif 665