1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define FIFO_DUMP_ADDR 0x8000 20 21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 22 #define DLFW_PAGE_SIZE_LEGACY 0x1000 23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 24 #define DLFW_BLK_SIZE_LEGACY 4 25 #define FW_START_ADDR_LEGACY 0x1000 26 27 #define BCN_LOSS_CNT 10 28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0 29 #define BCN_FILTER_CONNECTION_LOSS 1 30 #define BCN_FILTER_CONNECTED 2 31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3 32 33 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10) 34 35 #define RTW_CHANNEL_TIME 45 36 #define RTW_OFF_CHAN_TIME 100 37 #define RTW_PASS_CHAN_TIME 105 38 #define RTW_DFS_CHAN_TIME 20 39 #define RTW_CH_INFO_SIZE 4 40 #define RTW_EX_CH_INFO_SIZE 3 41 #define RTW_EX_CH_INFO_HDR_SIZE 2 42 #define RTW_SCAN_WIDTH 0 43 #define RTW_PRI_CH_IDX 1 44 #define RTW_PROBE_PG_CNT 2 45 46 enum rtw_c2h_cmd_id { 47 C2H_CCX_TX_RPT = 0x03, 48 C2H_BT_INFO = 0x09, 49 C2H_BT_MP_INFO = 0x0b, 50 C2H_BT_HID_INFO = 0x45, 51 C2H_RA_RPT = 0x0c, 52 C2H_HW_FEATURE_REPORT = 0x19, 53 C2H_WLAN_INFO = 0x27, 54 C2H_WLAN_RFON = 0x32, 55 C2H_BCN_FILTER_NOTIFY = 0x36, 56 C2H_ADAPTIVITY = 0x37, 57 C2H_SCAN_RESULT = 0x38, 58 C2H_HW_FEATURE_DUMP = 0xfd, 59 C2H_HALMAC = 0xff, 60 }; 61 62 enum rtw_c2h_cmd_id_ext { 63 C2H_SCAN_STATUS_RPT = 0x3, 64 C2H_CCX_RPT = 0x0f, 65 C2H_CHAN_SWITCH = 0x22, 66 }; 67 68 struct rtw_c2h_cmd { 69 u8 id; 70 u8 seq; 71 u8 payload[]; 72 } __packed; 73 74 struct rtw_c2h_adaptivity { 75 u8 density; 76 u8 igi; 77 u8 l2h_th_init; 78 u8 l2h; 79 u8 h2l; 80 u8 option; 81 } __packed; 82 83 enum rtw_rsvd_packet_type { 84 RSVD_BEACON, 85 RSVD_DUMMY, 86 RSVD_PS_POLL, 87 RSVD_PROBE_RESP, 88 RSVD_NULL, 89 RSVD_QOS_NULL, 90 RSVD_LPS_PG_DPK, 91 RSVD_LPS_PG_INFO, 92 RSVD_PROBE_REQ, 93 RSVD_NLO_INFO, 94 RSVD_CH_INFO, 95 }; 96 97 enum rtw_fw_rf_type { 98 FW_RF_1T2R = 0, 99 FW_RF_2T4R = 1, 100 FW_RF_2T2R = 2, 101 FW_RF_2T3R = 3, 102 FW_RF_1T1R = 4, 103 FW_RF_2T2R_GREEN = 5, 104 FW_RF_3T3R = 6, 105 FW_RF_3T4R = 7, 106 FW_RF_4T4R = 8, 107 FW_RF_MAX_TYPE = 0xF, 108 }; 109 110 enum rtw_fw_feature { 111 FW_FEATURE_SIG = BIT(0), 112 FW_FEATURE_LPS_C2H = BIT(1), 113 FW_FEATURE_LCLK = BIT(2), 114 FW_FEATURE_PG = BIT(3), 115 FW_FEATURE_TX_WAKE = BIT(4), 116 FW_FEATURE_BCN_FILTER = BIT(5), 117 FW_FEATURE_NOTIFY_SCAN = BIT(6), 118 FW_FEATURE_ADAPTIVITY = BIT(7), 119 FW_FEATURE_SCAN_OFFLOAD = BIT(8), 120 FW_FEATURE_MAX = BIT(31), 121 }; 122 123 enum rtw_beacon_filter_offload_mode { 124 BCN_FILTER_OFFLOAD_MODE_0 = 0, 125 BCN_FILTER_OFFLOAD_MODE_1, 126 BCN_FILTER_OFFLOAD_MODE_2, 127 BCN_FILTER_OFFLOAD_MODE_3, 128 129 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0, 130 }; 131 132 struct rtw_coex_info_req { 133 u8 seq; 134 u8 op_code; 135 u8 para1; 136 u8 para2; 137 u8 para3; 138 }; 139 140 struct rtw_iqk_para { 141 u8 clear; 142 u8 segment_iqk; 143 }; 144 145 struct rtw_lps_pg_dpk_hdr { 146 u16 dpk_path_ok; 147 u8 dpk_txagc[2]; 148 u16 dpk_gs[2]; 149 u32 coef[2][20]; 150 u8 dpk_ch; 151 } __packed; 152 153 struct rtw_lps_pg_info_hdr { 154 u8 macid; 155 u8 mbssid; 156 u8 pattern_count; 157 u8 mu_tab_group_id; 158 u8 sec_cam_count; 159 u8 tx_bu_page_count; 160 u16 rsvd; 161 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 162 } __packed; 163 164 struct rtw_rsvd_page { 165 /* associated with each vif */ 166 struct list_head vif_list; 167 struct rtw_vif *rtwvif; 168 169 /* associated when build rsvd page */ 170 struct list_head build_list; 171 172 struct sk_buff *skb; 173 enum rtw_rsvd_packet_type type; 174 u8 page; 175 bool add_txdesc; 176 struct cfg80211_ssid *ssid; 177 u16 probe_req_size; 178 }; 179 180 enum rtw_keep_alive_pkt_type { 181 KEEP_ALIVE_NULL_PKT = 0, 182 KEEP_ALIVE_ARP_RSP = 1, 183 }; 184 185 struct rtw_nlo_info_hdr { 186 u8 nlo_count; 187 u8 hidden_ap_count; 188 u8 rsvd1[2]; 189 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 190 u8 rsvd2[8]; 191 u8 ssid_len[16]; 192 u8 chiper[16]; 193 u8 rsvd3[16]; 194 u8 location[8]; 195 } __packed; 196 197 enum rtw_packet_type { 198 RTW_PACKET_PROBE_REQ = 0x00, 199 200 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 201 }; 202 203 struct rtw_fw_wow_keep_alive_para { 204 bool adopt; 205 u8 pkt_type; 206 u8 period; /* unit: sec */ 207 }; 208 209 struct rtw_fw_wow_disconnect_para { 210 bool adopt; 211 u8 period; /* unit: sec */ 212 u8 retry_count; 213 }; 214 215 enum rtw_channel_type { 216 RTW_CHANNEL_PASSIVE, 217 RTW_CHANNEL_ACTIVE, 218 RTW_CHANNEL_RADAR, 219 }; 220 221 enum rtw_scan_extra_id { 222 RTW_SCAN_EXTRA_ID_DFS, 223 }; 224 225 enum rtw_scan_extra_info { 226 RTW_SCAN_EXTRA_ACTION_SCAN, 227 }; 228 229 enum rtw_scan_report_code { 230 RTW_SCAN_REPORT_SUCCESS = 0x00, 231 RTW_SCAN_REPORT_ERR_PHYDM = 0x01, 232 RTW_SCAN_REPORT_ERR_ID = 0x02, 233 RTW_SCAN_REPORT_ERR_TX = 0x03, 234 RTW_SCAN_REPORT_CANCELED = 0x10, 235 RTW_SCAN_REPORT_CANCELED_EXT = 0x11, 236 RTW_SCAN_REPORT_FW_DISABLED = 0xF0, 237 }; 238 239 enum rtw_scan_notify_id { 240 RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00, 241 RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01, 242 RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02, 243 RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03, 244 RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04, 245 RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05, 246 RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06, 247 RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07, 248 RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08, 249 RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09, 250 RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A, 251 }; 252 253 enum rtw_scan_notify_status { 254 RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00, 255 RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01, 256 RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02, 257 RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03, 258 }; 259 260 struct rtw_ch_switch_option { 261 u8 periodic_option; 262 u32 tsf_high; 263 u32 tsf_low; 264 u8 dest_ch_en; 265 u8 absolute_time_en; 266 u8 dest_ch; 267 u8 normal_period; 268 u8 normal_period_sel; 269 u8 normal_cycle; 270 u8 slow_period; 271 u8 slow_period_sel; 272 u8 nlo_en; 273 bool switch_en; 274 bool back_op_en; 275 }; 276 277 struct rtw_fw_hdr { 278 __le16 signature; 279 u8 category; 280 u8 function; 281 __le16 version; /* 0x04 */ 282 u8 subversion; 283 u8 subindex; 284 __le32 rsvd; /* 0x08 */ 285 __le32 feature; /* 0x0C */ 286 u8 month; /* 0x10 */ 287 u8 day; 288 u8 hour; 289 u8 min; 290 __le16 year; /* 0x14 */ 291 __le16 rsvd3; 292 u8 mem_usage; /* 0x18 */ 293 u8 rsvd4[3]; 294 __le16 h2c_fmt_ver; /* 0x1C */ 295 __le16 rsvd5; 296 __le32 dmem_addr; /* 0x20 */ 297 __le32 dmem_size; 298 __le32 rsvd6; 299 __le32 rsvd7; 300 __le32 imem_size; /* 0x30 */ 301 __le32 emem_size; 302 __le32 emem_addr; 303 __le32 imem_addr; 304 } __packed; 305 306 struct rtw_fw_hdr_legacy { 307 __le16 signature; 308 u8 category; 309 u8 function; 310 __le16 version; /* 0x04 */ 311 u8 subversion1; 312 u8 subversion2; 313 u8 month; /* 0x08 */ 314 u8 day; 315 u8 hour; 316 u8 minute; 317 __le16 size; 318 __le16 rsvd2; 319 __le32 idx; /* 0x10 */ 320 __le32 rsvd3; 321 __le32 rsvd4; /* 0x18 */ 322 __le32 rsvd5; 323 } __packed; 324 325 /* C2H */ 326 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) 327 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) 328 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) 329 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) 330 331 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff) 332 333 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2]) 334 #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3]) 335 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4]) 336 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 337 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 338 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 339 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 340 341 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf) 342 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10) 343 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100) 344 345 /* PKT H2C */ 346 #define H2C_PKT_CMD_ID 0xFF 347 #define H2C_PKT_CATEGORY 0x01 348 349 #define H2C_PKT_GENERAL_INFO 0x0D 350 #define H2C_PKT_PHYDM_INFO 0x11 351 #define H2C_PKT_IQK 0x0E 352 353 #define H2C_PKT_CH_SWITCH 0x02 354 #define H2C_PKT_UPDATE_PKT 0x0C 355 #define H2C_PKT_SCAN_OFFLOAD 0x19 356 357 #define H2C_PKT_CH_SWITCH_LEN 0x20 358 #define H2C_PKT_UPDATE_PKT_LEN 0x4 359 360 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 361 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 362 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 363 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 364 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 365 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 366 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 367 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 368 369 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 370 { 371 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 372 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 373 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 374 } 375 376 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 377 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 378 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 379 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 380 381 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 382 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 383 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 384 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 385 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 386 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 387 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 388 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 389 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 390 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 391 #define IQK_SET_CLEAR(h2c_pkt, value) \ 392 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 393 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 394 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 395 396 #define CHSW_INFO_SET_CH(pkt, value) \ 397 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 398 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 399 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 400 #define CHSW_INFO_SET_BW(pkt, value) \ 401 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 402 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 403 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 404 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 405 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 406 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value) \ 407 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31)) 408 409 #define CH_INFO_SET_CH(pkt, value) \ 410 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0)) 411 #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \ 412 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0)) 413 #define CH_INFO_SET_BW(pkt, value) \ 414 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4)) 415 #define CH_INFO_SET_TIMEOUT(pkt, value) \ 416 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0)) 417 #define CH_INFO_SET_ACTION_ID(pkt, value) \ 418 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0)) 419 #define CH_INFO_SET_EXTRA_INFO(pkt, value) \ 420 u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7)) 421 422 #define EXTRA_CH_INFO_SET_ID(pkt, value) \ 423 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0)) 424 #define EXTRA_CH_INFO_SET_INFO(pkt, value) \ 425 u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7)) 426 #define EXTRA_CH_INFO_SET_SIZE(pkt, value) \ 427 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0)) 428 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value) \ 429 u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0)) 430 431 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 432 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 433 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 434 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 435 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 436 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 437 438 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 439 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 440 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 441 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 442 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 443 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 444 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 445 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 446 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \ 447 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5)) 448 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \ 449 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6)) 450 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 451 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 452 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 453 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 454 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 455 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 456 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ 457 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 458 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 459 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 460 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 461 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 462 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 463 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 464 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 465 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 466 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 467 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 468 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 469 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 470 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 471 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 472 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 473 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 474 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 475 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 476 477 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \ 478 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 479 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \ 480 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 481 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \ 482 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 483 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \ 484 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3)) 485 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \ 486 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4)) 487 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \ 488 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 489 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \ 490 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16)) 491 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \ 492 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 493 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \ 494 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8)) 495 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \ 496 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16)) 497 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \ 498 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20)) 499 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \ 500 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24)) 501 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \ 502 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0)) 503 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \ 504 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16)) 505 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \ 506 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0)) 507 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \ 508 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4)) 509 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \ 510 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8)) 511 512 /* Command H2C */ 513 #define H2C_CMD_RSVD_PAGE 0x0 514 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 515 #define H2C_CMD_SET_PWR_MODE 0x20 516 #define H2C_CMD_LPS_PG_INFO 0x2b 517 #define H2C_CMD_RA_INFO 0x40 518 #define H2C_CMD_RSSI_MONITOR 0x42 519 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56 520 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57 521 #define H2C_CMD_WL_PHY_INFO 0x58 522 #define H2C_CMD_SCAN 0x59 523 #define H2C_CMD_ADAPTIVITY 0x5A 524 525 #define H2C_CMD_COEX_TDMA_TYPE 0x60 526 #define H2C_CMD_QUERY_BT_INFO 0x61 527 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 528 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 529 #define H2C_CMD_WL_CH_INFO 0x66 530 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 531 #define H2C_CMD_BT_WIFI_CONTROL 0x69 532 #define H2C_CMD_WIFI_CALIBRATION 0x6d 533 #define H2C_CMD_QUERY_BT_HID_INFO 0x73 534 535 #define H2C_CMD_KEEP_ALIVE 0x03 536 #define H2C_CMD_DISCONNECT_DECISION 0x04 537 #define H2C_CMD_WOWLAN 0x80 538 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 539 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 540 #define H2C_CMD_NLO_INFO 0x8C 541 542 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 543 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 544 545 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 546 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 547 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 548 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 549 550 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ 551 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) 552 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ 553 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) 554 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ 555 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 556 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ 557 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 558 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ 559 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 560 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \ 561 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 562 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \ 563 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16)) 564 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \ 565 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17)) 566 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \ 567 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21)) 568 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \ 569 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 570 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \ 571 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0)) 572 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \ 573 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4)) 574 575 #define SET_SCAN_START(h2c_pkt, value) \ 576 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 577 578 #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \ 579 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8)) 580 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \ 581 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 582 #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \ 583 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 584 #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \ 585 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 586 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \ 587 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 588 589 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 590 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 591 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 592 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 593 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 594 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 595 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 596 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 597 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 598 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 599 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 600 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 601 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 602 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 603 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 604 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 605 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 606 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 607 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 608 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 609 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 610 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 611 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 612 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 613 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 614 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 615 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 616 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 617 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 618 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 619 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 620 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 621 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 622 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 623 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 624 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 625 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 626 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 627 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 628 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 629 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 630 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 631 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 632 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 633 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 634 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 635 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 636 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 637 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 638 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 639 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 640 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 641 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 642 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 643 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 644 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 645 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 646 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 647 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 648 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 649 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 650 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 651 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 652 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 653 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 654 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 655 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 656 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 657 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 658 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 659 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 660 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 661 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 662 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 663 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 664 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 665 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 666 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 667 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 668 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 669 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 670 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 671 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 672 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 673 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 674 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 675 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 676 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 677 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 678 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 679 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 680 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 681 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 682 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 683 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 684 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 685 686 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \ 687 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 688 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \ 689 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 690 691 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 692 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 693 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 694 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 695 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 696 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 697 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 698 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 699 700 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 701 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 702 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 703 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 704 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 705 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 706 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 707 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 708 709 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 710 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 711 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 712 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 713 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 714 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 715 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 716 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 717 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 718 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 719 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 720 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 721 722 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 723 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 724 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 725 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 726 727 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 728 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 729 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 730 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 731 732 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 733 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 734 #define SET_NLO_PS_32K(h2c_pkt, value) \ 735 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 736 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 737 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 738 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 739 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 740 741 #define GET_FW_DUMP_LEN(_header) \ 742 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) 743 #define GET_FW_DUMP_SEQ(_header) \ 744 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) 745 #define GET_FW_DUMP_MORE(_header) \ 746 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) 747 #define GET_FW_DUMP_VERSION(_header) \ 748 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) 749 #define GET_FW_DUMP_TLV_TYPE(_header) \ 750 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) 751 #define GET_FW_DUMP_TLV_LEN(_header) \ 752 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) 753 #define GET_FW_DUMP_TLV_VAL(_header) \ 754 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) 755 756 #define RFK_SET_INFORM_START(h2c_pkt, value) \ 757 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 758 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 759 { 760 u32 pkt_offset; 761 762 pkt_offset = *((u32 *)skb->cb); 763 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 764 } 765 766 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw, 767 enum rtw_fw_feature feature) 768 { 769 return !!(fw->feature & feature); 770 } 771 772 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 773 struct sk_buff *skb); 774 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 775 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 776 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 777 778 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 779 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); 780 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 781 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 782 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 783 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 784 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 785 struct rtw_coex_info_req *req); 786 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 787 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 788 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 789 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 790 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data); 791 792 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 793 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 794 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 795 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 796 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); 797 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect, 798 struct ieee80211_vif *vif); 799 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 800 u8 *buf, u32 size); 801 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, 802 struct rtw_vif *rtwvif); 803 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, 804 struct rtw_vif *rtwvif); 805 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, 806 struct rtw_vif *rtwvif); 807 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, 808 struct rtw_vif *rtwvif); 809 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); 810 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 811 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 812 u32 offset, u32 size, u32 *buf); 813 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 814 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 815 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 816 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 817 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 818 u8 pairwise_key_enc, 819 u8 group_key_enc); 820 821 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 822 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 823 struct cfg80211_ssid *ssid); 824 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 825 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); 826 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); 827 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, 828 u32 *buffer); 829 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 830 void rtw_fw_adaptivity(struct rtw_dev *rtwdev); 831 void rtw_store_op_chan(struct rtw_dev *rtwdev); 832 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 833 struct ieee80211_scan_request *req); 834 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 835 bool aborted); 836 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 837 bool enable); 838 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb); 839 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb); 840 void rtw_hw_scan_abort(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 841 #endif 842