1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FIFO_PAGE_SIZE_SHIFT 12 16 #define FIFO_PAGE_SIZE 4096 17 #define RSVD_PAGE_START_ADDR 0x780 18 #define FIFO_DUMP_ADDR 0x8000 19 20 enum rtw_c2h_cmd_id { 21 C2H_BT_INFO = 0x09, 22 C2H_BT_MP_INFO = 0x0b, 23 C2H_RA_RPT = 0x0c, 24 C2H_HW_FEATURE_REPORT = 0x19, 25 C2H_WLAN_INFO = 0x27, 26 C2H_HW_FEATURE_DUMP = 0xfd, 27 C2H_HALMAC = 0xff, 28 }; 29 30 enum rtw_c2h_cmd_id_ext { 31 C2H_CCX_RPT = 0x0f, 32 }; 33 34 struct rtw_c2h_cmd { 35 u8 id; 36 u8 seq; 37 u8 payload[0]; 38 } __packed; 39 40 enum rtw_rsvd_packet_type { 41 RSVD_BEACON, 42 RSVD_PS_POLL, 43 RSVD_PROBE_RESP, 44 RSVD_NULL, 45 RSVD_QOS_NULL, 46 RSVD_LPS_PG_DPK, 47 RSVD_LPS_PG_INFO, 48 }; 49 50 enum rtw_fw_rf_type { 51 FW_RF_1T2R = 0, 52 FW_RF_2T4R = 1, 53 FW_RF_2T2R = 2, 54 FW_RF_2T3R = 3, 55 FW_RF_1T1R = 4, 56 FW_RF_2T2R_GREEN = 5, 57 FW_RF_3T3R = 6, 58 FW_RF_3T4R = 7, 59 FW_RF_4T4R = 8, 60 FW_RF_MAX_TYPE = 0xF, 61 }; 62 63 struct rtw_coex_info_req { 64 u8 seq; 65 u8 op_code; 66 u8 para1; 67 u8 para2; 68 u8 para3; 69 }; 70 71 struct rtw_iqk_para { 72 u8 clear; 73 u8 segment_iqk; 74 }; 75 76 struct rtw_lps_pg_dpk_hdr { 77 u16 dpk_path_ok; 78 u8 dpk_txagc[2]; 79 u16 dpk_gs[2]; 80 u32 coef[2][20]; 81 u8 dpk_ch; 82 } __packed; 83 84 struct rtw_lps_pg_info_hdr { 85 u8 macid; 86 u8 mbssid; 87 u8 pattern_count; 88 u8 mu_tab_group_id; 89 u8 sec_cam_count; 90 u8 tx_bu_page_count; 91 u16 rsvd; 92 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 93 } __packed; 94 95 struct rtw_rsvd_page { 96 struct list_head list; 97 struct sk_buff *skb; 98 enum rtw_rsvd_packet_type type; 99 u8 page; 100 bool add_txdesc; 101 }; 102 103 struct rtw_fw_hdr { 104 __le16 signature; 105 u8 category; 106 u8 function; 107 __le16 version; /* 0x04 */ 108 u8 subversion; 109 u8 subindex; 110 __le32 rsvd; /* 0x08 */ 111 __le32 rsvd2; /* 0x0C */ 112 u8 month; /* 0x10 */ 113 u8 day; 114 u8 hour; 115 u8 min; 116 __le16 year; /* 0x14 */ 117 __le16 rsvd3; 118 u8 mem_usage; /* 0x18 */ 119 u8 rsvd4[3]; 120 __le16 h2c_fmt_ver; /* 0x1C */ 121 __le16 rsvd5; 122 __le32 dmem_addr; /* 0x20 */ 123 __le32 dmem_size; 124 __le32 rsvd6; 125 __le32 rsvd7; 126 __le32 imem_size; /* 0x30 */ 127 __le32 emem_size; 128 __le32 emem_addr; 129 __le32 imem_addr; 130 } __packed; 131 132 /* C2H */ 133 #define GET_CCX_REPORT_SEQNUM(c2h_payload) (c2h_payload[8] & 0xfc) 134 #define GET_CCX_REPORT_STATUS(c2h_payload) (c2h_payload[9] & 0xc0) 135 136 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 137 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 138 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 139 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 140 141 /* PKT H2C */ 142 #define H2C_PKT_CMD_ID 0xFF 143 #define H2C_PKT_CATEGORY 0x01 144 145 #define H2C_PKT_GENERAL_INFO 0x0D 146 #define H2C_PKT_PHYDM_INFO 0x11 147 #define H2C_PKT_IQK 0x0E 148 149 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 150 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 151 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 152 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 153 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 154 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 155 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 156 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 157 158 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 159 { 160 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 161 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 162 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 163 } 164 165 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 166 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 167 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 168 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 169 170 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 171 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 172 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 173 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 174 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 175 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 176 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 177 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 178 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 179 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 180 #define IQK_SET_CLEAR(h2c_pkt, value) \ 181 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 182 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 183 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 184 185 /* Command H2C */ 186 #define H2C_CMD_RSVD_PAGE 0x0 187 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 188 #define H2C_CMD_SET_PWR_MODE 0x20 189 #define H2C_CMD_LPS_PG_INFO 0x2b 190 #define H2C_CMD_RA_INFO 0x40 191 #define H2C_CMD_RSSI_MONITOR 0x42 192 193 #define H2C_CMD_COEX_TDMA_TYPE 0x60 194 #define H2C_CMD_QUERY_BT_INFO 0x61 195 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 196 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 197 #define H2C_CMD_WL_CH_INFO 0x66 198 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 199 #define H2C_CMD_BT_WIFI_CONTROL 0x69 200 201 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 202 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 203 204 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 205 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 206 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 207 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 208 209 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 210 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 211 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 212 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 213 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 214 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 215 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 216 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 217 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 218 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 219 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 220 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 221 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 222 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 223 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 224 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 225 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 226 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 227 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 228 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 229 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 230 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 231 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 232 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 233 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 234 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 235 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 236 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 237 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 238 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 239 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 240 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 241 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 242 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 243 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 244 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 245 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 246 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 247 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 248 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 249 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 250 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 251 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 252 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 253 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 254 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 255 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 256 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 257 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 258 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 259 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 260 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 261 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 262 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 263 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 264 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 265 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 266 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 267 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 268 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 269 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 270 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 271 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 272 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 273 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 274 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 275 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 276 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 277 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 278 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 279 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 280 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 281 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 282 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 283 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 284 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 285 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 286 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 287 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 288 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 289 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 290 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 291 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 292 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 293 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 294 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 295 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 296 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 297 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 298 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 299 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 300 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 301 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 302 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 303 304 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 305 { 306 u32 pkt_offset; 307 308 pkt_offset = *((u32 *)skb->cb); 309 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 310 } 311 312 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 313 struct sk_buff *skb); 314 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 315 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 316 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 317 318 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 319 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 320 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 321 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 322 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 323 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 324 struct rtw_coex_info_req *req); 325 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 326 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 327 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 328 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 329 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 330 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 331 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 332 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 333 void rtw_add_rsvd_page(struct rtw_dev *rtwdev, enum rtw_rsvd_packet_type type, 334 bool txdesc); 335 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 336 u8 *buf, u32 size); 337 void rtw_reset_rsvd_page(struct rtw_dev *rtwdev); 338 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev, 339 struct ieee80211_vif *vif); 340 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 341 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 342 u32 offset, u32 size, u32 *buf); 343 #endif 344