1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "fw.h" 7 #include "tx.h" 8 #include "reg.h" 9 #include "debug.h" 10 11 void rtw_fw_c2h_cmd_handle_ext(struct rtw_dev *rtwdev, struct sk_buff *skb) 12 { 13 struct rtw_c2h_cmd *c2h; 14 u8 sub_cmd_id; 15 16 c2h = get_c2h_from_skb(skb); 17 sub_cmd_id = c2h->payload[0]; 18 19 switch (sub_cmd_id) { 20 case C2H_CCX_RPT: 21 rtw_tx_report_handle(rtwdev, skb); 22 break; 23 default: 24 break; 25 } 26 } 27 28 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb) 29 { 30 struct rtw_c2h_cmd *c2h; 31 u32 pkt_offset; 32 u8 len; 33 34 pkt_offset = *((u32 *)skb->cb); 35 c2h = (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 36 len = skb->len - pkt_offset - 2; 37 38 rtw_dbg(rtwdev, RTW_DBG_FW, "recv C2H, id=0x%02x, seq=0x%02x, len=%d\n", 39 c2h->id, c2h->seq, len); 40 41 switch (c2h->id) { 42 case C2H_HALMAC: 43 rtw_fw_c2h_cmd_handle_ext(rtwdev, skb); 44 break; 45 default: 46 break; 47 } 48 } 49 50 void rtw_fw_send_h2c_command(struct rtw_dev *rtwdev, u8 *h2c) 51 { 52 u8 box; 53 u8 box_state; 54 u32 box_reg, box_ex_reg; 55 u32 h2c_wait; 56 int idx; 57 58 rtw_dbg(rtwdev, RTW_DBG_FW, 59 "send H2C content %02x%02x%02x%02x %02x%02x%02x%02x\n", 60 h2c[3], h2c[2], h2c[1], h2c[0], 61 h2c[7], h2c[6], h2c[5], h2c[4]); 62 63 spin_lock(&rtwdev->h2c.lock); 64 65 box = rtwdev->h2c.last_box_num; 66 switch (box) { 67 case 0: 68 box_reg = REG_HMEBOX0; 69 box_ex_reg = REG_HMEBOX0_EX; 70 break; 71 case 1: 72 box_reg = REG_HMEBOX1; 73 box_ex_reg = REG_HMEBOX1_EX; 74 break; 75 case 2: 76 box_reg = REG_HMEBOX2; 77 box_ex_reg = REG_HMEBOX2_EX; 78 break; 79 case 3: 80 box_reg = REG_HMEBOX3; 81 box_ex_reg = REG_HMEBOX3_EX; 82 break; 83 default: 84 WARN(1, "invalid h2c mail box number\n"); 85 goto out; 86 } 87 88 h2c_wait = 20; 89 do { 90 box_state = rtw_read8(rtwdev, REG_HMETFR); 91 } while ((box_state >> box) & 0x1 && --h2c_wait > 0); 92 93 if (!h2c_wait) { 94 rtw_err(rtwdev, "failed to send h2c command\n"); 95 goto out; 96 } 97 98 for (idx = 0; idx < 4; idx++) 99 rtw_write8(rtwdev, box_reg + idx, h2c[idx]); 100 for (idx = 0; idx < 4; idx++) 101 rtw_write8(rtwdev, box_ex_reg + idx, h2c[idx + 4]); 102 103 if (++rtwdev->h2c.last_box_num >= 4) 104 rtwdev->h2c.last_box_num = 0; 105 106 out: 107 spin_unlock(&rtwdev->h2c.lock); 108 } 109 110 static void rtw_fw_send_h2c_packet(struct rtw_dev *rtwdev, u8 *h2c_pkt) 111 { 112 int ret; 113 114 spin_lock(&rtwdev->h2c.lock); 115 116 FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, rtwdev->h2c.seq); 117 ret = rtw_hci_write_data_h2c(rtwdev, h2c_pkt, H2C_PKT_SIZE); 118 if (ret) 119 rtw_err(rtwdev, "failed to send h2c packet\n"); 120 rtwdev->h2c.seq++; 121 122 spin_unlock(&rtwdev->h2c.lock); 123 } 124 125 void 126 rtw_fw_send_general_info(struct rtw_dev *rtwdev) 127 { 128 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 129 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 130 u16 total_size = H2C_PKT_HDR_SIZE + 4; 131 132 rtw_h2c_pkt_set_header(h2c_pkt, H2C_PKT_GENERAL_INFO); 133 134 SET_PKT_H2C_TOTAL_LEN(h2c_pkt, total_size); 135 136 GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, 137 fifo->rsvd_fw_txbuf_addr - 138 fifo->rsvd_boundary); 139 140 rtw_fw_send_h2c_packet(rtwdev, h2c_pkt); 141 } 142 143 void 144 rtw_fw_send_phydm_info(struct rtw_dev *rtwdev) 145 { 146 struct rtw_hal *hal = &rtwdev->hal; 147 struct rtw_efuse *efuse = &rtwdev->efuse; 148 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 149 u16 total_size = H2C_PKT_HDR_SIZE + 8; 150 u8 fw_rf_type = 0; 151 152 if (hal->rf_type == RF_1T1R) 153 fw_rf_type = FW_RF_1T1R; 154 else if (hal->rf_type == RF_2T2R) 155 fw_rf_type = FW_RF_2T2R; 156 157 rtw_h2c_pkt_set_header(h2c_pkt, H2C_PKT_PHYDM_INFO); 158 159 SET_PKT_H2C_TOTAL_LEN(h2c_pkt, total_size); 160 PHYDM_INFO_SET_REF_TYPE(h2c_pkt, efuse->rfe_option); 161 PHYDM_INFO_SET_RF_TYPE(h2c_pkt, fw_rf_type); 162 PHYDM_INFO_SET_CUT_VER(h2c_pkt, hal->cut_version); 163 PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, hal->antenna_tx); 164 PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, hal->antenna_rx); 165 166 rtw_fw_send_h2c_packet(rtwdev, h2c_pkt); 167 } 168 169 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para) 170 { 171 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 172 u16 total_size = H2C_PKT_HDR_SIZE + 1; 173 174 rtw_h2c_pkt_set_header(h2c_pkt, H2C_PKT_IQK); 175 SET_PKT_H2C_TOTAL_LEN(h2c_pkt, total_size); 176 IQK_SET_CLEAR(h2c_pkt, para->clear); 177 IQK_SET_SEGMENT_IQK(h2c_pkt, para->segment_iqk); 178 179 rtw_fw_send_h2c_packet(rtwdev, h2c_pkt); 180 } 181 182 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 183 { 184 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 185 u8 rssi = ewma_rssi_read(&si->avg_rssi); 186 bool stbc_en = si->stbc_en ? true : false; 187 188 SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_RSSI_MONITOR); 189 190 SET_RSSI_INFO_MACID(h2c_pkt, si->mac_id); 191 SET_RSSI_INFO_RSSI(h2c_pkt, rssi); 192 SET_RSSI_INFO_STBC(h2c_pkt, stbc_en); 193 194 rtw_fw_send_h2c_command(rtwdev, h2c_pkt); 195 } 196 197 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si) 198 { 199 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 200 bool no_update = si->updated; 201 bool disable_pt = true; 202 203 SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_RA_INFO); 204 205 SET_RA_INFO_MACID(h2c_pkt, si->mac_id); 206 SET_RA_INFO_RATE_ID(h2c_pkt, si->rate_id); 207 SET_RA_INFO_INIT_RA_LVL(h2c_pkt, si->init_ra_lv); 208 SET_RA_INFO_SGI_EN(h2c_pkt, si->sgi_enable); 209 SET_RA_INFO_BW_MODE(h2c_pkt, si->bw_mode); 210 SET_RA_INFO_LDPC(h2c_pkt, si->ldpc_en); 211 SET_RA_INFO_NO_UPDATE(h2c_pkt, no_update); 212 SET_RA_INFO_VHT_EN(h2c_pkt, si->vht_enable); 213 SET_RA_INFO_DIS_PT(h2c_pkt, disable_pt); 214 SET_RA_INFO_RA_MASK0(h2c_pkt, (si->ra_mask & 0xff)); 215 SET_RA_INFO_RA_MASK1(h2c_pkt, (si->ra_mask & 0xff00) >> 8); 216 SET_RA_INFO_RA_MASK2(h2c_pkt, (si->ra_mask & 0xff0000) >> 16); 217 SET_RA_INFO_RA_MASK3(h2c_pkt, (si->ra_mask & 0xff000000) >> 24); 218 219 si->init_ra_lv = 0; 220 si->updated = true; 221 222 rtw_fw_send_h2c_command(rtwdev, h2c_pkt); 223 } 224 225 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool connect) 226 { 227 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 228 229 SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_MEDIA_STATUS_RPT); 230 MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, connect); 231 MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, mac_id); 232 233 rtw_fw_send_h2c_command(rtwdev, h2c_pkt); 234 } 235 236 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev) 237 { 238 struct rtw_lps_conf *conf = &rtwdev->lps_conf; 239 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 240 241 SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_SET_PWR_MODE); 242 243 SET_PWR_MODE_SET_MODE(h2c_pkt, conf->mode); 244 SET_PWR_MODE_SET_RLBM(h2c_pkt, conf->rlbm); 245 SET_PWR_MODE_SET_SMART_PS(h2c_pkt, conf->smart_ps); 246 SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, conf->awake_interval); 247 SET_PWR_MODE_SET_PORT_ID(h2c_pkt, conf->port_id); 248 SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, conf->state); 249 250 rtw_fw_send_h2c_command(rtwdev, h2c_pkt); 251 } 252 253 static u8 rtw_get_rsvd_page_location(struct rtw_dev *rtwdev, 254 enum rtw_rsvd_packet_type type) 255 { 256 struct rtw_rsvd_page *rsvd_pkt; 257 u8 location = 0; 258 259 list_for_each_entry(rsvd_pkt, &rtwdev->rsvd_page_list, list) { 260 if (type == rsvd_pkt->type) 261 location = rsvd_pkt->page; 262 } 263 264 return location; 265 } 266 267 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev) 268 { 269 u8 h2c_pkt[H2C_PKT_SIZE] = {0}; 270 u8 location = 0; 271 272 SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_RSVD_PAGE); 273 274 location = rtw_get_rsvd_page_location(rtwdev, RSVD_PROBE_RESP); 275 *(h2c_pkt + 1) = location; 276 rtw_dbg(rtwdev, RTW_DBG_FW, "RSVD_PROBE_RESP loc: %d\n", location); 277 278 location = rtw_get_rsvd_page_location(rtwdev, RSVD_PS_POLL); 279 *(h2c_pkt + 2) = location; 280 rtw_dbg(rtwdev, RTW_DBG_FW, "RSVD_PS_POLL loc: %d\n", location); 281 282 location = rtw_get_rsvd_page_location(rtwdev, RSVD_NULL); 283 *(h2c_pkt + 3) = location; 284 rtw_dbg(rtwdev, RTW_DBG_FW, "RSVD_NULL loc: %d\n", location); 285 286 location = rtw_get_rsvd_page_location(rtwdev, RSVD_QOS_NULL); 287 *(h2c_pkt + 4) = location; 288 rtw_dbg(rtwdev, RTW_DBG_FW, "RSVD_QOS_NULL loc: %d\n", location); 289 290 rtw_fw_send_h2c_command(rtwdev, h2c_pkt); 291 } 292 293 static struct sk_buff * 294 rtw_beacon_get(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 295 { 296 struct sk_buff *skb_new; 297 298 if (vif->type != NL80211_IFTYPE_AP && 299 vif->type != NL80211_IFTYPE_ADHOC && 300 !ieee80211_vif_is_mesh(vif)) { 301 skb_new = alloc_skb(1, GFP_KERNEL); 302 if (!skb_new) 303 return NULL; 304 skb_put(skb_new, 1); 305 } else { 306 skb_new = ieee80211_beacon_get(hw, vif); 307 } 308 309 return skb_new; 310 } 311 312 static struct sk_buff *rtw_get_rsvd_page_skb(struct ieee80211_hw *hw, 313 struct ieee80211_vif *vif, 314 enum rtw_rsvd_packet_type type) 315 { 316 struct sk_buff *skb_new; 317 318 switch (type) { 319 case RSVD_BEACON: 320 skb_new = rtw_beacon_get(hw, vif); 321 break; 322 case RSVD_PS_POLL: 323 skb_new = ieee80211_pspoll_get(hw, vif); 324 break; 325 case RSVD_PROBE_RESP: 326 skb_new = ieee80211_proberesp_get(hw, vif); 327 break; 328 case RSVD_NULL: 329 skb_new = ieee80211_nullfunc_get(hw, vif, false); 330 break; 331 case RSVD_QOS_NULL: 332 skb_new = ieee80211_nullfunc_get(hw, vif, true); 333 break; 334 default: 335 return NULL; 336 } 337 338 if (!skb_new) 339 return NULL; 340 341 return skb_new; 342 } 343 344 static void rtw_fill_rsvd_page_desc(struct rtw_dev *rtwdev, struct sk_buff *skb) 345 { 346 struct rtw_tx_pkt_info pkt_info; 347 struct rtw_chip_info *chip = rtwdev->chip; 348 u8 *pkt_desc; 349 350 memset(&pkt_info, 0, sizeof(pkt_info)); 351 rtw_rsvd_page_pkt_info_update(rtwdev, &pkt_info, skb); 352 pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz); 353 memset(pkt_desc, 0, chip->tx_pkt_desc_sz); 354 rtw_tx_fill_tx_desc(&pkt_info, skb); 355 } 356 357 static inline u8 rtw_len_to_page(unsigned int len, u8 page_size) 358 { 359 return DIV_ROUND_UP(len, page_size); 360 } 361 362 static void rtw_rsvd_page_list_to_buf(struct rtw_dev *rtwdev, u8 page_size, 363 u8 page_margin, u32 page, u8 *buf, 364 struct rtw_rsvd_page *rsvd_pkt) 365 { 366 struct sk_buff *skb = rsvd_pkt->skb; 367 368 if (rsvd_pkt->add_txdesc) 369 rtw_fill_rsvd_page_desc(rtwdev, skb); 370 371 if (page >= 1) 372 memcpy(buf + page_margin + page_size * (page - 1), 373 skb->data, skb->len); 374 else 375 memcpy(buf, skb->data, skb->len); 376 } 377 378 void rtw_add_rsvd_page(struct rtw_dev *rtwdev, enum rtw_rsvd_packet_type type, 379 bool txdesc) 380 { 381 struct rtw_rsvd_page *rsvd_pkt; 382 383 lockdep_assert_held(&rtwdev->mutex); 384 385 list_for_each_entry(rsvd_pkt, &rtwdev->rsvd_page_list, list) { 386 if (rsvd_pkt->type == type) 387 return; 388 } 389 390 rsvd_pkt = kmalloc(sizeof(*rsvd_pkt), GFP_KERNEL); 391 if (!rsvd_pkt) 392 return; 393 394 rsvd_pkt->type = type; 395 rsvd_pkt->add_txdesc = txdesc; 396 list_add_tail(&rsvd_pkt->list, &rtwdev->rsvd_page_list); 397 } 398 399 void rtw_reset_rsvd_page(struct rtw_dev *rtwdev) 400 { 401 struct rtw_rsvd_page *rsvd_pkt, *tmp; 402 403 lockdep_assert_held(&rtwdev->mutex); 404 405 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, list) { 406 if (rsvd_pkt->type == RSVD_BEACON) 407 continue; 408 list_del(&rsvd_pkt->list); 409 kfree(rsvd_pkt); 410 } 411 } 412 413 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 414 u8 *buf, u32 size) 415 { 416 u8 bckp[2]; 417 u8 val; 418 u16 rsvd_pg_head; 419 int ret; 420 421 lockdep_assert_held(&rtwdev->mutex); 422 423 if (!size) 424 return -EINVAL; 425 426 pg_addr &= BIT_MASK_BCN_HEAD_1_V1; 427 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, pg_addr | BIT_BCN_VALID_V1); 428 429 val = rtw_read8(rtwdev, REG_CR + 1); 430 bckp[0] = val; 431 val |= BIT_ENSWBCN >> 8; 432 rtw_write8(rtwdev, REG_CR + 1, val); 433 434 val = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL + 2); 435 bckp[1] = val; 436 val &= ~(BIT_EN_BCNQ_DL >> 16); 437 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 2, val); 438 439 ret = rtw_hci_write_data_rsvd_page(rtwdev, buf, size); 440 if (ret) { 441 rtw_err(rtwdev, "failed to write data to rsvd page\n"); 442 goto restore; 443 } 444 445 if (!check_hw_ready(rtwdev, REG_FIFOPAGE_CTRL_2, BIT_BCN_VALID_V1, 1)) { 446 rtw_err(rtwdev, "error beacon valid\n"); 447 ret = -EBUSY; 448 } 449 450 restore: 451 rsvd_pg_head = rtwdev->fifo.rsvd_boundary; 452 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, 453 rsvd_pg_head | BIT_BCN_VALID_V1); 454 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 2, bckp[1]); 455 rtw_write8(rtwdev, REG_CR + 1, bckp[0]); 456 457 return ret; 458 } 459 460 static int rtw_download_drv_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, u32 size) 461 { 462 u32 pg_size; 463 u32 pg_num = 0; 464 u16 pg_addr = 0; 465 466 pg_size = rtwdev->chip->page_size; 467 pg_num = size / pg_size + ((size & (pg_size - 1)) ? 1 : 0); 468 if (pg_num > rtwdev->fifo.rsvd_drv_pg_num) 469 return -ENOMEM; 470 471 pg_addr = rtwdev->fifo.rsvd_drv_addr; 472 473 return rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size); 474 } 475 476 static u8 *rtw_build_rsvd_page(struct rtw_dev *rtwdev, 477 struct ieee80211_vif *vif, u32 *size) 478 { 479 struct ieee80211_hw *hw = rtwdev->hw; 480 struct rtw_chip_info *chip = rtwdev->chip; 481 struct sk_buff *iter; 482 struct rtw_rsvd_page *rsvd_pkt; 483 u32 page = 0; 484 u8 total_page = 0; 485 u8 page_size, page_margin, tx_desc_sz; 486 u8 *buf; 487 488 page_size = chip->page_size; 489 tx_desc_sz = chip->tx_pkt_desc_sz; 490 page_margin = page_size - tx_desc_sz; 491 492 list_for_each_entry(rsvd_pkt, &rtwdev->rsvd_page_list, list) { 493 iter = rtw_get_rsvd_page_skb(hw, vif, rsvd_pkt->type); 494 if (!iter) { 495 rtw_err(rtwdev, "fail to build rsvd packet\n"); 496 goto release_skb; 497 } 498 rsvd_pkt->skb = iter; 499 rsvd_pkt->page = total_page; 500 if (rsvd_pkt->add_txdesc) 501 total_page += rtw_len_to_page(iter->len + tx_desc_sz, 502 page_size); 503 else 504 total_page += rtw_len_to_page(iter->len, page_size); 505 } 506 507 if (total_page > rtwdev->fifo.rsvd_drv_pg_num) { 508 rtw_err(rtwdev, "rsvd page over size: %d\n", total_page); 509 goto release_skb; 510 } 511 512 *size = (total_page - 1) * page_size + page_margin; 513 buf = kzalloc(*size, GFP_KERNEL); 514 if (!buf) 515 goto release_skb; 516 517 list_for_each_entry(rsvd_pkt, &rtwdev->rsvd_page_list, list) { 518 rtw_rsvd_page_list_to_buf(rtwdev, page_size, page_margin, 519 page, buf, rsvd_pkt); 520 page += rtw_len_to_page(rsvd_pkt->skb->len, page_size); 521 } 522 list_for_each_entry(rsvd_pkt, &rtwdev->rsvd_page_list, list) 523 kfree_skb(rsvd_pkt->skb); 524 525 return buf; 526 527 release_skb: 528 list_for_each_entry(rsvd_pkt, &rtwdev->rsvd_page_list, list) 529 kfree_skb(rsvd_pkt->skb); 530 531 return NULL; 532 } 533 534 static int 535 rtw_download_beacon(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 536 { 537 struct ieee80211_hw *hw = rtwdev->hw; 538 struct sk_buff *skb; 539 int ret = 0; 540 541 skb = rtw_beacon_get(hw, vif); 542 if (!skb) { 543 rtw_err(rtwdev, "failed to get beacon skb\n"); 544 ret = -ENOMEM; 545 goto out; 546 } 547 548 ret = rtw_download_drv_rsvd_page(rtwdev, skb->data, skb->len); 549 if (ret) 550 rtw_err(rtwdev, "failed to download drv rsvd page\n"); 551 552 dev_kfree_skb(skb); 553 554 out: 555 return ret; 556 } 557 558 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev, struct ieee80211_vif *vif) 559 { 560 u8 *buf; 561 u32 size; 562 int ret; 563 564 buf = rtw_build_rsvd_page(rtwdev, vif, &size); 565 if (!buf) { 566 rtw_err(rtwdev, "failed to build rsvd page pkt\n"); 567 return -ENOMEM; 568 } 569 570 ret = rtw_download_drv_rsvd_page(rtwdev, buf, size); 571 if (ret) { 572 rtw_err(rtwdev, "failed to download drv rsvd page\n"); 573 goto free; 574 } 575 576 ret = rtw_download_beacon(rtwdev, vif); 577 if (ret) { 578 rtw_err(rtwdev, "failed to download beacon\n"); 579 goto free; 580 } 581 582 free: 583 kfree(buf); 584 585 return ret; 586 } 587 588 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 589 u32 offset, u32 size, u32 *buf) 590 { 591 struct rtw_fifo_conf *fifo = &rtwdev->fifo; 592 u32 residue, i; 593 u16 start_pg; 594 u16 idx = 0; 595 u16 ctl; 596 u8 rcr; 597 598 if (size & 0x3) { 599 rtw_warn(rtwdev, "should be 4-byte aligned\n"); 600 return -EINVAL; 601 } 602 603 offset += fifo->rsvd_boundary << TX_PAGE_SIZE_SHIFT; 604 residue = offset & (FIFO_PAGE_SIZE - 1); 605 start_pg = offset >> FIFO_PAGE_SIZE_SHIFT; 606 start_pg += RSVD_PAGE_START_ADDR; 607 608 rcr = rtw_read8(rtwdev, REG_RCR + 2); 609 ctl = rtw_read16(rtwdev, REG_PKTBUF_DBG_CTRL) & 0xf000; 610 611 /* disable rx clock gate */ 612 rtw_write8(rtwdev, REG_RCR, rcr | BIT(3)); 613 614 do { 615 rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, start_pg | ctl); 616 617 for (i = FIFO_DUMP_ADDR + residue; 618 i < FIFO_DUMP_ADDR + FIFO_PAGE_SIZE; i += 4) { 619 buf[idx++] = rtw_read32(rtwdev, i); 620 size -= 4; 621 if (size == 0) 622 goto out; 623 } 624 625 residue = 0; 626 start_pg++; 627 } while (size); 628 629 out: 630 rtw_write16(rtwdev, REG_PKTBUF_DBG_CTRL, ctl); 631 rtw_write8(rtwdev, REG_RCR + 2, rcr); 632 return 0; 633 } 634