1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_COEX_H__ 6 #define __RTW_COEX_H__ 7 8 #define COEX_CCK_2 0x1 9 #define COEX_RESP_ACK_BY_WL_FW 0x1 10 #define COEX_REQUEST_TIMEOUT msecs_to_jiffies(10) 11 12 #define COEX_MIN_DELAY 10 /* delay unit in ms */ 13 #define COEX_RFK_TIMEOUT 600 /* RFK timeout in ms */ 14 15 #define COEX_RF_OFF 0x0 16 #define COEX_RF_ON 0x1 17 18 #define COEX_H2C69_WL_LEAKAP 0xc 19 #define PARA1_H2C69_DIS_5MS 0x1 20 #define PARA1_H2C69_EN_5MS 0x0 21 22 #define COEX_H2C69_TDMA_SLOT 0xb 23 #define PARA1_H2C69_TDMA_4SLOT 0xc1 24 #define PARA1_H2C69_TDMA_2SLOT 0x1 25 #define PARA1_H2C69_TBTT_TIMES GENMASK(5, 0) 26 #define PARA1_H2C69_TBTT_DIV100 BIT(7) 27 28 #define COEX_H2C69_TOGGLE_TABLE_A 0xd 29 #define COEX_H2C69_TOGGLE_TABLE_B 0x7 30 31 #define TDMA_4SLOT BIT(8) 32 33 #define TDMA_TIMER_TYPE_2SLOT 0 34 #define TDMA_TIMER_TYPE_4SLOT 3 35 36 #define COEX_RSSI_STEP 4 37 38 #define COEX_RSSI_HIGH(rssi) \ 39 ({ typeof(rssi) __rssi__ = rssi; \ 40 (__rssi__ == COEX_RSSI_STATE_HIGH || \ 41 __rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); }) 42 43 #define COEX_RSSI_MEDIUM(rssi) \ 44 ({ typeof(rssi) __rssi__ = rssi; \ 45 (__rssi__ == COEX_RSSI_STATE_MEDIUM || \ 46 __rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); }) 47 48 #define COEX_RSSI_LOW(rssi) \ 49 ({ typeof(rssi) __rssi__ = rssi; \ 50 (__rssi__ == COEX_RSSI_STATE_LOW || \ 51 __rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); }) 52 53 #define GET_COEX_RESP_BT_SUPP_VER(payload) \ 54 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 32)) 55 #define GET_COEX_RESP_BT_SUPP_FEAT(payload) \ 56 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24)) 57 #define GET_COEX_RESP_BT_PATCH_VER(payload) \ 58 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(55, 24)) 59 #define GET_COEX_RESP_BT_REG_VAL(payload) \ 60 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24)) 61 #define GET_COEX_RESP_BT_SCAN_TYPE(payload) \ 62 le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24)) 63 64 enum coex_mp_info_op { 65 BT_MP_INFO_OP_PATCH_VER = 0x00, 66 BT_MP_INFO_OP_READ_REG = 0x11, 67 BT_MP_INFO_OP_SUPP_FEAT = 0x2a, 68 BT_MP_INFO_OP_SUPP_VER = 0x2b, 69 BT_MP_INFO_OP_SCAN_TYPE = 0x2d, 70 BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32, 71 }; 72 73 enum coex_set_ant_phase { 74 COEX_SET_ANT_INIT, 75 COEX_SET_ANT_WONLY, 76 COEX_SET_ANT_WOFF, 77 COEX_SET_ANT_2G, 78 COEX_SET_ANT_5G, 79 COEX_SET_ANT_POWERON, 80 COEX_SET_ANT_2G_WLBT, 81 COEX_SET_ANT_2G_FREERUN, 82 83 COEX_SET_ANT_MAX 84 }; 85 86 enum coex_runreason { 87 COEX_RSN_2GSCANSTART = 0, 88 COEX_RSN_5GSCANSTART = 1, 89 COEX_RSN_SCANFINISH = 2, 90 COEX_RSN_2GSWITCHBAND = 3, 91 COEX_RSN_5GSWITCHBAND = 4, 92 COEX_RSN_2GCONSTART = 5, 93 COEX_RSN_5GCONSTART = 6, 94 COEX_RSN_2GCONFINISH = 7, 95 COEX_RSN_5GCONFINISH = 8, 96 COEX_RSN_2GMEDIA = 9, 97 COEX_RSN_5GMEDIA = 10, 98 COEX_RSN_MEDIADISCON = 11, 99 COEX_RSN_BTINFO = 12, 100 COEX_RSN_LPS = 13, 101 COEX_RSN_WLSTATUS = 14, 102 COEX_RSN_BTSTATUS = 15, 103 104 COEX_RSN_MAX 105 }; 106 107 enum coex_lte_coex_table_type { 108 COEX_CTT_WL_VS_LTE, 109 COEX_CTT_BT_VS_LTE, 110 }; 111 112 enum coex_gnt_setup_state { 113 COEX_GNT_SET_HW_PTA = 0x0, 114 COEX_GNT_SET_SW_LOW = 0x1, 115 COEX_GNT_SET_SW_HIGH = 0x3, 116 }; 117 118 enum coex_ext_ant_switch_pos_type { 119 COEX_SWITCH_TO_BT, 120 COEX_SWITCH_TO_WLG, 121 COEX_SWITCH_TO_WLA, 122 COEX_SWITCH_TO_NOCARE, 123 COEX_SWITCH_TO_WLG_BT, 124 125 COEX_SWITCH_TO_MAX 126 }; 127 128 enum coex_ext_ant_switch_ctrl_type { 129 COEX_SWITCH_CTRL_BY_BBSW, 130 COEX_SWITCH_CTRL_BY_PTA, 131 COEX_SWITCH_CTRL_BY_ANTDIV, 132 COEX_SWITCH_CTRL_BY_MAC, 133 COEX_SWITCH_CTRL_BY_BT, 134 COEX_SWITCH_CTRL_BY_FW, 135 136 COEX_SWITCH_CTRL_MAX 137 }; 138 139 enum coex_algorithm { 140 COEX_ALGO_NOPROFILE = 0, 141 COEX_ALGO_HFP = 1, 142 COEX_ALGO_HID = 2, 143 COEX_ALGO_A2DP = 3, 144 COEX_ALGO_PAN = 4, 145 COEX_ALGO_A2DP_HID = 5, 146 COEX_ALGO_A2DP_PAN = 6, 147 COEX_ALGO_PAN_HID = 7, 148 COEX_ALGO_A2DP_PAN_HID = 8, 149 150 COEX_ALGO_MAX 151 }; 152 153 enum coex_bt_profile { 154 BPM_NOPROFILE = 0, 155 BPM_HFP = BIT(0), 156 BPM_HID = BIT(1), 157 BPM_A2DP = BIT(2), 158 BPM_PAN = BIT(3), 159 BPM_HID_HFP = BPM_HID | BPM_HFP, 160 BPM_A2DP_HFP = BPM_A2DP | BPM_HFP, 161 BPM_A2DP_HID = BPM_A2DP | BPM_HID, 162 BPM_A2DP_HID_HFP = BPM_A2DP | BPM_HID | BPM_HFP, 163 BPM_PAN_HFP = BPM_PAN | BPM_HFP, 164 BPM_PAN_HID = BPM_PAN | BPM_HID, 165 BPM_PAN_HID_HFP = BPM_PAN | BPM_HID | BPM_HFP, 166 BPM_PAN_A2DP = BPM_PAN | BPM_A2DP, 167 BPM_PAN_A2DP_HFP = BPM_PAN | BPM_A2DP | BPM_HFP, 168 BPM_PAN_A2DP_HID = BPM_PAN | BPM_A2DP | BPM_HID, 169 BPM_PAN_A2DP_HID_HFP = BPM_PAN | BPM_A2DP | BPM_HID | BPM_HFP, 170 }; 171 172 enum coex_wl_link_mode { 173 COEX_WLINK_2G1PORT = 0x0, 174 COEX_WLINK_5G = 0x3, 175 COEX_WLINK_MAX 176 }; 177 178 enum coex_wl2bt_scoreboard { 179 COEX_SCBD_ACTIVE = BIT(0), 180 COEX_SCBD_ONOFF = BIT(1), 181 COEX_SCBD_SCAN = BIT(2), 182 COEX_SCBD_UNDERTEST = BIT(3), 183 COEX_SCBD_RXGAIN = BIT(4), 184 COEX_SCBD_BT_RFK = BIT(5), 185 COEX_SCBD_WLBUSY = BIT(6), 186 COEX_SCBD_EXTFEM = BIT(8), 187 COEX_SCBD_TDMA = BIT(9), 188 COEX_SCBD_FIX2M = BIT(10), 189 COEX_SCBD_ALL = GENMASK(15, 0), 190 }; 191 192 enum coex_power_save_type { 193 COEX_PS_WIFI_NATIVE = 0, 194 COEX_PS_LPS_ON = 1, 195 COEX_PS_LPS_OFF = 2, 196 }; 197 198 enum coex_rssi_state { 199 COEX_RSSI_STATE_HIGH, 200 COEX_RSSI_STATE_MEDIUM, 201 COEX_RSSI_STATE_LOW, 202 COEX_RSSI_STATE_STAY_HIGH, 203 COEX_RSSI_STATE_STAY_MEDIUM, 204 COEX_RSSI_STATE_STAY_LOW, 205 }; 206 207 enum coex_notify_type_ips { 208 COEX_IPS_LEAVE = 0x0, 209 COEX_IPS_ENTER = 0x1, 210 }; 211 212 enum coex_notify_type_lps { 213 COEX_LPS_DISABLE = 0x0, 214 COEX_LPS_ENABLE = 0x1, 215 }; 216 217 enum coex_notify_type_scan { 218 COEX_SCAN_FINISH, 219 COEX_SCAN_START, 220 COEX_SCAN_START_2G, 221 COEX_SCAN_START_5G, 222 }; 223 224 enum coex_notify_type_switchband { 225 COEX_NOT_SWITCH, 226 COEX_SWITCH_TO_24G, 227 COEX_SWITCH_TO_5G, 228 COEX_SWITCH_TO_24G_NOFORSCAN, 229 }; 230 231 enum coex_notify_type_associate { 232 COEX_ASSOCIATE_FINISH, 233 COEX_ASSOCIATE_START, 234 COEX_ASSOCIATE_5G_FINISH, 235 COEX_ASSOCIATE_5G_START, 236 }; 237 238 enum coex_notify_type_media_status { 239 COEX_MEDIA_DISCONNECT, 240 COEX_MEDIA_CONNECT, 241 COEX_MEDIA_CONNECT_5G, 242 }; 243 244 enum coex_bt_status { 245 COEX_BTSTATUS_NCON_IDLE = 0, 246 COEX_BTSTATUS_CON_IDLE = 1, 247 COEX_BTSTATUS_INQ_PAGE = 2, 248 COEX_BTSTATUS_ACL_BUSY = 3, 249 COEX_BTSTATUS_SCO_BUSY = 4, 250 COEX_BTSTATUS_ACL_SCO_BUSY = 5, 251 252 COEX_BTSTATUS_MAX 253 }; 254 255 enum coex_wl_tput_dir { 256 COEX_WL_TPUT_TX = 0x0, 257 COEX_WL_TPUT_RX = 0x1, 258 COEX_WL_TPUT_MAX 259 }; 260 261 enum coex_wl_priority_mask { 262 COEX_WLPRI_RX_RSP = 2, 263 COEX_WLPRI_TX_RSP = 3, 264 COEX_WLPRI_TX_BEACON = 4, 265 COEX_WLPRI_TX_OFDM = 11, 266 COEX_WLPRI_TX_CCK = 12, 267 COEX_WLPRI_TX_BEACONQ = 27, 268 COEX_WLPRI_RX_CCK = 28, 269 COEX_WLPRI_RX_OFDM = 29, 270 COEX_WLPRI_MAX 271 }; 272 273 enum coex_commom_chip_setup { 274 COEX_CSETUP_INIT_HW = 0x0, 275 COEX_CSETUP_ANT_SWITCH = 0x1, 276 COEX_CSETUP_GNT_FIX = 0x2, 277 COEX_CSETUP_GNT_DEBUG = 0x3, 278 COEX_CSETUP_RFE_TYPE = 0x4, 279 COEX_CSETUP_COEXINFO_HW = 0x5, 280 COEX_CSETUP_WL_TX_POWER = 0x6, 281 COEX_CSETUP_WL_RX_GAIN = 0x7, 282 COEX_CSETUP_WLAN_ACT_IPS = 0x8, 283 COEX_CSETUP_MAX 284 }; 285 286 enum coex_indirect_reg_type { 287 COEX_INDIRECT_1700 = 0x0, 288 COEX_INDIRECT_7C0 = 0x1, 289 COEX_INDIRECT_MAX 290 }; 291 292 enum coex_pstdma_type { 293 COEX_PSTDMA_FORCE_LPSOFF = 0x0, 294 COEX_PSTDMA_FORCE_LPSON = 0x1, 295 COEX_PSTDMA_MAX 296 }; 297 298 enum coex_btrssi_type { 299 COEX_BTRSSI_RATIO = 0x0, 300 COEX_BTRSSI_DBM = 0x1, 301 COEX_BTRSSI_MAX 302 }; 303 304 struct coex_table_para { 305 u32 bt; 306 u32 wl; 307 }; 308 309 struct coex_tdma_para { 310 u8 para[5]; 311 }; 312 313 struct coex_5g_afh_map { 314 u32 wl_5g_ch; 315 u8 bt_skip_ch; 316 u8 bt_skip_span; 317 }; 318 319 struct coex_rf_para { 320 u8 wl_pwr_dec_lvl; 321 u8 bt_pwr_dec_lvl; 322 bool wl_low_gain_en; 323 u8 bt_lna_lvl; 324 }; 325 326 static inline void rtw_coex_set_init(struct rtw_dev *rtwdev) 327 { 328 struct rtw_chip_info *chip = rtwdev->chip; 329 330 chip->ops->coex_set_init(rtwdev); 331 } 332 333 static inline 334 void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type) 335 { 336 struct rtw_chip_info *chip = rtwdev->chip; 337 338 if (!chip->ops->coex_set_ant_switch) 339 return; 340 341 chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type); 342 } 343 344 static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev) 345 { 346 struct rtw_chip_info *chip = rtwdev->chip; 347 348 chip->ops->coex_set_gnt_fix(rtwdev); 349 } 350 351 static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev) 352 { 353 struct rtw_chip_info *chip = rtwdev->chip; 354 355 chip->ops->coex_set_gnt_debug(rtwdev); 356 } 357 358 static inline void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev) 359 { 360 struct rtw_chip_info *chip = rtwdev->chip; 361 362 chip->ops->coex_set_rfe_type(rtwdev); 363 } 364 365 static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 366 { 367 struct rtw_chip_info *chip = rtwdev->chip; 368 369 chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr); 370 } 371 372 static inline 373 void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 374 { 375 struct rtw_chip_info *chip = rtwdev->chip; 376 377 chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain); 378 } 379 380 void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb); 381 u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr); 382 void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr, 383 u32 mask, u32 val); 384 void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set); 385 386 void rtw_coex_bt_relink_work(struct work_struct *work); 387 void rtw_coex_bt_reenable_work(struct work_struct *work); 388 void rtw_coex_defreeze_work(struct work_struct *work); 389 void rtw_coex_wl_remain_work(struct work_struct *work); 390 void rtw_coex_bt_remain_work(struct work_struct *work); 391 void rtw_coex_wl_connecting_work(struct work_struct *work); 392 void rtw_coex_bt_multi_link_remain_work(struct work_struct *work); 393 void rtw_coex_wl_ccklock_work(struct work_struct *work); 394 395 void rtw_coex_power_on_setting(struct rtw_dev *rtwdev); 396 void rtw_coex_power_off_setting(struct rtw_dev *rtwdev); 397 void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only); 398 void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type); 399 void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type); 400 void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type); 401 void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 type); 402 void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 type); 403 void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length); 404 void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length); 405 void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type); 406 void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev, u32 type); 407 void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m); 408 409 static inline bool rtw_coex_disabled(struct rtw_dev *rtwdev) 410 { 411 struct rtw_coex *coex = &rtwdev->coex; 412 struct rtw_coex_stat *coex_stat = &coex->stat; 413 414 return coex_stat->bt_disabled; 415 } 416 417 #endif 418