1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation
3  */
4 
5 #ifndef __RTW_COEX_H__
6 #define __RTW_COEX_H__
7 
8 /* BT profile map bit definition */
9 #define BPM_HFP		BIT(0)
10 #define BPM_HID		BIT(1)
11 #define BPM_A2DP		BIT(2)
12 #define BPM_PAN		BIT(3)
13 
14 #define COEX_RESP_ACK_BY_WL_FW	0x1
15 #define COEX_REQUEST_TIMEOUT	msecs_to_jiffies(10)
16 
17 #define COEX_MIN_DELAY		10 /* delay unit in ms */
18 #define COEX_RFK_TIMEOUT	600 /* RFK timeout in ms */
19 
20 #define COEX_RF_OFF	0x0
21 #define COEX_RF_ON	0x1
22 
23 #define COEX_H2C69_WL_LEAKAP	0xc
24 #define PARA1_H2C69_DIS_5MS	0x1
25 #define PARA1_H2C69_EN_5MS	0x0
26 
27 #define COEX_H2C69_TDMA_SLOT	0xb
28 #define PARA1_H2C69_TDMA_4SLOT	0xc1
29 #define PARA1_H2C69_TDMA_2SLOT	0x1
30 
31 #define TDMA_4SLOT	BIT(8)
32 
33 #define COEX_RSSI_STEP		4
34 #define COEX_RSSI_HIGH(rssi) \
35 	({ typeof(rssi) __rssi__ = rssi; \
36 	   (__rssi__ == COEX_RSSI_STATE_HIGH || \
37 	    __rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); })
38 
39 #define COEX_RSSI_MEDIUM(rssi) \
40 	({ typeof(rssi) __rssi__ = rssi; \
41 	   (__rssi__ == COEX_RSSI_STATE_MEDIUM || \
42 	    __rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); })
43 
44 #define COEX_RSSI_LOW(rssi) \
45 	({ typeof(rssi) __rssi__ = rssi; \
46 	   (__rssi__ == COEX_RSSI_STATE_LOW || \
47 	    __rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); })
48 
49 #define GET_COEX_RESP_BT_SCAN_TYPE(payload)				\
50 	le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24))
51 
52 enum coex_mp_info_op {
53 	BT_MP_INFO_OP_PATCH_VER	= 0x00,
54 	BT_MP_INFO_OP_READ_REG	= 0x11,
55 	BT_MP_INFO_OP_SUPP_FEAT	= 0x2a,
56 	BT_MP_INFO_OP_SUPP_VER	= 0x2b,
57 	BT_MP_INFO_OP_SCAN_TYPE	= 0x2d,
58 	BT_MP_INFO_OP_LNA_CONSTRAINT	= 0x32,
59 };
60 
61 enum coex_set_ant_phase {
62 	COEX_SET_ANT_INIT,
63 	COEX_SET_ANT_WONLY,
64 	COEX_SET_ANT_WOFF,
65 	COEX_SET_ANT_2G,
66 	COEX_SET_ANT_5G,
67 	COEX_SET_ANT_POWERON,
68 	COEX_SET_ANT_2G_WLBT,
69 	COEX_SET_ANT_2G_FREERUN,
70 
71 	COEX_SET_ANT_MAX
72 };
73 
74 enum coex_runreason {
75 	COEX_RSN_2GSCANSTART	= 0,
76 	COEX_RSN_5GSCANSTART	= 1,
77 	COEX_RSN_SCANFINISH	= 2,
78 	COEX_RSN_2GSWITCHBAND	= 3,
79 	COEX_RSN_5GSWITCHBAND	= 4,
80 	COEX_RSN_2GCONSTART	= 5,
81 	COEX_RSN_5GCONSTART	= 6,
82 	COEX_RSN_2GCONFINISH	= 7,
83 	COEX_RSN_5GCONFINISH	= 8,
84 	COEX_RSN_2GMEDIA	= 9,
85 	COEX_RSN_5GMEDIA	= 10,
86 	COEX_RSN_MEDIADISCON	= 11,
87 	COEX_RSN_BTINFO		= 12,
88 	COEX_RSN_LPS		= 13,
89 	COEX_RSN_WLSTATUS	= 14,
90 
91 	COEX_RSN_MAX
92 };
93 
94 enum coex_lte_coex_table_type {
95 	COEX_CTT_WL_VS_LTE,
96 	COEX_CTT_BT_VS_LTE,
97 };
98 
99 enum coex_gnt_setup_state {
100 	COEX_GNT_SET_HW_PTA	= 0x0,
101 	COEX_GNT_SET_SW_LOW	= 0x1,
102 	COEX_GNT_SET_SW_HIGH	= 0x3,
103 };
104 
105 enum coex_ext_ant_switch_pos_type {
106 	COEX_SWITCH_TO_BT,
107 	COEX_SWITCH_TO_WLG,
108 	COEX_SWITCH_TO_WLA,
109 	COEX_SWITCH_TO_NOCARE,
110 	COEX_SWITCH_TO_WLG_BT,
111 
112 	COEX_SWITCH_TO_MAX
113 };
114 
115 enum coex_ext_ant_switch_ctrl_type {
116 	COEX_SWITCH_CTRL_BY_BBSW,
117 	COEX_SWITCH_CTRL_BY_PTA,
118 	COEX_SWITCH_CTRL_BY_ANTDIV,
119 	COEX_SWITCH_CTRL_BY_MAC,
120 	COEX_SWITCH_CTRL_BY_BT,
121 	COEX_SWITCH_CTRL_BY_FW,
122 
123 	COEX_SWITCH_CTRL_MAX
124 };
125 
126 enum coex_algorithm {
127 	COEX_ALGO_NOPROFILE	= 0,
128 	COEX_ALGO_HFP		= 1,
129 	COEX_ALGO_HID		= 2,
130 	COEX_ALGO_A2DP		= 3,
131 	COEX_ALGO_PAN		= 4,
132 	COEX_ALGO_A2DP_HID	= 5,
133 	COEX_ALGO_A2DP_PAN	= 6,
134 	COEX_ALGO_PAN_HID	= 7,
135 	COEX_ALGO_A2DP_PAN_HID	= 8,
136 
137 	COEX_ALGO_MAX
138 };
139 
140 enum coex_wl_link_mode {
141 	COEX_WLINK_2G1PORT	= 0x0,
142 	COEX_WLINK_5G		= 0x3,
143 	COEX_WLINK_MAX
144 };
145 
146 enum coex_wl2bt_scoreboard {
147 	COEX_SCBD_ACTIVE	= BIT(0),
148 	COEX_SCBD_ONOFF		= BIT(1),
149 	COEX_SCBD_SCAN		= BIT(2),
150 	COEX_SCBD_UNDERTEST	= BIT(3),
151 	COEX_SCBD_RXGAIN	= BIT(4),
152 	COEX_SCBD_BT_RFK	= BIT(5),
153 	COEX_SCBD_WLBUSY	= BIT(6),
154 	COEX_SCBD_EXTFEM	= BIT(8),
155 	COEX_SCBD_TDMA		= BIT(9),
156 	COEX_SCBD_FIX2M		= BIT(10),
157 	COEX_SCBD_ALL		= GENMASK(15, 0),
158 };
159 
160 enum coex_power_save_type {
161 	COEX_PS_WIFI_NATIVE	= 0,
162 	COEX_PS_LPS_ON		= 1,
163 	COEX_PS_LPS_OFF		= 2,
164 };
165 
166 enum coex_rssi_state {
167 	COEX_RSSI_STATE_HIGH,
168 	COEX_RSSI_STATE_MEDIUM,
169 	COEX_RSSI_STATE_LOW,
170 	COEX_RSSI_STATE_STAY_HIGH,
171 	COEX_RSSI_STATE_STAY_MEDIUM,
172 	COEX_RSSI_STATE_STAY_LOW,
173 };
174 
175 enum coex_notify_type_ips {
176 	COEX_IPS_LEAVE		= 0x0,
177 	COEX_IPS_ENTER		= 0x1,
178 };
179 
180 enum coex_notify_type_lps {
181 	COEX_LPS_DISABLE	= 0x0,
182 	COEX_LPS_ENABLE		= 0x1,
183 };
184 
185 enum coex_notify_type_scan {
186 	COEX_SCAN_FINISH,
187 	COEX_SCAN_START,
188 	COEX_SCAN_START_2G,
189 	COEX_SCAN_START_5G,
190 };
191 
192 enum coex_notify_type_switchband {
193 	COEX_NOT_SWITCH,
194 	COEX_SWITCH_TO_24G,
195 	COEX_SWITCH_TO_5G,
196 	COEX_SWITCH_TO_24G_NOFORSCAN,
197 };
198 
199 enum coex_notify_type_associate {
200 	COEX_ASSOCIATE_FINISH,
201 	COEX_ASSOCIATE_START,
202 	COEX_ASSOCIATE_5G_FINISH,
203 	COEX_ASSOCIATE_5G_START,
204 };
205 
206 enum coex_notify_type_media_status {
207 	COEX_MEDIA_DISCONNECT,
208 	COEX_MEDIA_CONNECT,
209 	COEX_MEDIA_CONNECT_5G,
210 };
211 
212 enum coex_bt_status {
213 	COEX_BTSTATUS_NCON_IDLE		= 0,
214 	COEX_BTSTATUS_CON_IDLE		= 1,
215 	COEX_BTSTATUS_INQ_PAGE		= 2,
216 	COEX_BTSTATUS_ACL_BUSY		= 3,
217 	COEX_BTSTATUS_SCO_BUSY		= 4,
218 	COEX_BTSTATUS_ACL_SCO_BUSY	= 5,
219 
220 	COEX_BTSTATUS_MAX
221 };
222 
223 enum coex_wl_tput_dir {
224 	COEX_WL_TPUT_TX			= 0x0,
225 	COEX_WL_TPUT_RX			= 0x1,
226 	COEX_WL_TPUT_MAX
227 };
228 
229 enum coex_wl_priority_mask {
230 	COEX_WLPRI_RX_RSP	= 2,
231 	COEX_WLPRI_TX_RSP	= 3,
232 	COEX_WLPRI_TX_BEACON	= 4,
233 	COEX_WLPRI_TX_OFDM	= 11,
234 	COEX_WLPRI_TX_CCK	= 12,
235 	COEX_WLPRI_TX_BEACONQ	= 27,
236 	COEX_WLPRI_RX_CCK	= 28,
237 	COEX_WLPRI_RX_OFDM	= 29,
238 	COEX_WLPRI_MAX
239 };
240 
241 enum coex_commom_chip_setup {
242 	COEX_CSETUP_INIT_HW		= 0x0,
243 	COEX_CSETUP_ANT_SWITCH		= 0x1,
244 	COEX_CSETUP_GNT_FIX		= 0x2,
245 	COEX_CSETUP_GNT_DEBUG		= 0x3,
246 	COEX_CSETUP_RFE_TYPE		= 0x4,
247 	COEX_CSETUP_COEXINFO_HW		= 0x5,
248 	COEX_CSETUP_WL_TX_POWER		= 0x6,
249 	COEX_CSETUP_WL_RX_GAIN		= 0x7,
250 	COEX_CSETUP_WLAN_ACT_IPS	= 0x8,
251 	COEX_CSETUP_MAX
252 };
253 
254 enum coex_indirect_reg_type {
255 	COEX_INDIRECT_1700		= 0x0,
256 	COEX_INDIRECT_7C0		= 0x1,
257 	COEX_INDIRECT_MAX
258 };
259 
260 enum coex_pstdma_type {
261 	COEX_PSTDMA_FORCE_LPSOFF	= 0x0,
262 	COEX_PSTDMA_FORCE_LPSON		= 0x1,
263 	COEX_PSTDMA_MAX
264 };
265 
266 enum coex_btrssi_type {
267 	COEX_BTRSSI_RATIO		= 0x0,
268 	COEX_BTRSSI_DBM			= 0x1,
269 	COEX_BTRSSI_MAX
270 };
271 
272 struct coex_table_para {
273 	u32 bt;
274 	u32 wl;
275 };
276 
277 struct coex_tdma_para {
278 	u8 para[5];
279 };
280 
281 struct coex_5g_afh_map {
282 	u32 wl_5g_ch;
283 	u8 bt_skip_ch;
284 	u8 bt_skip_span;
285 };
286 
287 struct coex_rf_para {
288 	u8 wl_pwr_dec_lvl;
289 	u8 bt_pwr_dec_lvl;
290 	bool wl_low_gain_en;
291 	u8 bt_lna_lvl;
292 };
293 
294 static inline void rtw_coex_set_init(struct rtw_dev *rtwdev)
295 {
296 	struct rtw_chip_info *chip = rtwdev->chip;
297 
298 	chip->ops->coex_set_init(rtwdev);
299 }
300 
301 static inline
302 void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type)
303 {
304 	struct rtw_chip_info *chip = rtwdev->chip;
305 
306 	if (!chip->ops->coex_set_ant_switch)
307 		return;
308 
309 	chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type);
310 }
311 
312 static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev)
313 {
314 	struct rtw_chip_info *chip = rtwdev->chip;
315 
316 	chip->ops->coex_set_gnt_fix(rtwdev);
317 }
318 
319 static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev)
320 {
321 	struct rtw_chip_info *chip = rtwdev->chip;
322 
323 	chip->ops->coex_set_gnt_debug(rtwdev);
324 }
325 
326 static inline  void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev)
327 {
328 	struct rtw_chip_info *chip = rtwdev->chip;
329 
330 	chip->ops->coex_set_rfe_type(rtwdev);
331 }
332 
333 static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
334 {
335 	struct rtw_chip_info *chip = rtwdev->chip;
336 
337 	chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr);
338 }
339 
340 static inline
341 void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
342 {
343 	struct rtw_chip_info *chip = rtwdev->chip;
344 
345 	chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain);
346 }
347 
348 void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb);
349 u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr);
350 void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr,
351 				 u32 mask, u32 val);
352 void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set);
353 
354 void rtw_coex_bt_relink_work(struct work_struct *work);
355 void rtw_coex_bt_reenable_work(struct work_struct *work);
356 void rtw_coex_defreeze_work(struct work_struct *work);
357 
358 void rtw_coex_power_on_setting(struct rtw_dev *rtwdev);
359 void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only);
360 void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type);
361 void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type);
362 void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type);
363 void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 action);
364 void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 status);
365 void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 len);
366 void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length);
367 void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type);
368 void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev);
369 
370 #endif
371