1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_COEX_H__ 6 #define __RTW_COEX_H__ 7 8 /* BT profile map bit definition */ 9 #define BPM_HFP BIT(0) 10 #define BPM_HID BIT(1) 11 #define BPM_A2DP BIT(2) 12 #define BPM_PAN BIT(3) 13 14 #define COEX_RESP_ACK_BY_WL_FW 0x1 15 #define COEX_REQUEST_TIMEOUT msecs_to_jiffies(10) 16 17 #define COEX_MIN_DELAY 10 /* delay unit in ms */ 18 #define COEX_RFK_TIMEOUT 600 /* RFK timeout in ms */ 19 20 #define COEX_RF_OFF 0x0 21 #define COEX_RF_ON 0x1 22 23 #define COEX_H2C69_WL_LEAKAP 0xc 24 #define PARA1_H2C69_DIS_5MS 0x1 25 #define PARA1_H2C69_EN_5MS 0x0 26 27 #define COEX_H2C69_TDMA_SLOT 0xb 28 #define PARA1_H2C69_TDMA_4SLOT 0xc1 29 #define PARA1_H2C69_TDMA_2SLOT 0x1 30 31 #define TDMA_4SLOT BIT(8) 32 33 #define COEX_RSSI_STEP 4 34 #define COEX_RSSI_HIGH(rssi) \ 35 ({ typeof(rssi) __rssi__ = rssi; \ 36 (__rssi__ == COEX_RSSI_STATE_HIGH || \ 37 __rssi__ == COEX_RSSI_STATE_STAY_HIGH ? true : false); }) 38 39 #define COEX_RSSI_MEDIUM(rssi) \ 40 ({ typeof(rssi) __rssi__ = rssi; \ 41 (__rssi__ == COEX_RSSI_STATE_MEDIUM || \ 42 __rssi__ == COEX_RSSI_STATE_STAY_MEDIUM ? true : false); }) 43 44 #define COEX_RSSI_LOW(rssi) \ 45 ({ typeof(rssi) __rssi__ = rssi; \ 46 (__rssi__ == COEX_RSSI_STATE_LOW || \ 47 __rssi__ == COEX_RSSI_STATE_STAY_LOW ? true : false); }) 48 49 #define GET_COEX_RESP_BT_SUPP_VER(payload) \ 50 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 32)) 51 #define GET_COEX_RESP_BT_SUPP_FEAT(payload) \ 52 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24)) 53 #define GET_COEX_RESP_BT_PATCH_VER(payload) \ 54 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(55, 24)) 55 #define GET_COEX_RESP_BT_REG_VAL(payload) \ 56 le64_get_bits(*((__le64 *)(payload)), GENMASK_ULL(39, 24)) 57 #define GET_COEX_RESP_BT_SCAN_TYPE(payload) \ 58 le64_get_bits(*((__le64 *)(payload)), GENMASK(31, 24)) 59 60 enum coex_mp_info_op { 61 BT_MP_INFO_OP_PATCH_VER = 0x00, 62 BT_MP_INFO_OP_READ_REG = 0x11, 63 BT_MP_INFO_OP_SUPP_FEAT = 0x2a, 64 BT_MP_INFO_OP_SUPP_VER = 0x2b, 65 BT_MP_INFO_OP_SCAN_TYPE = 0x2d, 66 BT_MP_INFO_OP_LNA_CONSTRAINT = 0x32, 67 }; 68 69 enum coex_set_ant_phase { 70 COEX_SET_ANT_INIT, 71 COEX_SET_ANT_WONLY, 72 COEX_SET_ANT_WOFF, 73 COEX_SET_ANT_2G, 74 COEX_SET_ANT_5G, 75 COEX_SET_ANT_POWERON, 76 COEX_SET_ANT_2G_WLBT, 77 COEX_SET_ANT_2G_FREERUN, 78 79 COEX_SET_ANT_MAX 80 }; 81 82 enum coex_runreason { 83 COEX_RSN_2GSCANSTART = 0, 84 COEX_RSN_5GSCANSTART = 1, 85 COEX_RSN_SCANFINISH = 2, 86 COEX_RSN_2GSWITCHBAND = 3, 87 COEX_RSN_5GSWITCHBAND = 4, 88 COEX_RSN_2GCONSTART = 5, 89 COEX_RSN_5GCONSTART = 6, 90 COEX_RSN_2GCONFINISH = 7, 91 COEX_RSN_5GCONFINISH = 8, 92 COEX_RSN_2GMEDIA = 9, 93 COEX_RSN_5GMEDIA = 10, 94 COEX_RSN_MEDIADISCON = 11, 95 COEX_RSN_BTINFO = 12, 96 COEX_RSN_LPS = 13, 97 COEX_RSN_WLSTATUS = 14, 98 99 COEX_RSN_MAX 100 }; 101 102 enum coex_lte_coex_table_type { 103 COEX_CTT_WL_VS_LTE, 104 COEX_CTT_BT_VS_LTE, 105 }; 106 107 enum coex_gnt_setup_state { 108 COEX_GNT_SET_HW_PTA = 0x0, 109 COEX_GNT_SET_SW_LOW = 0x1, 110 COEX_GNT_SET_SW_HIGH = 0x3, 111 }; 112 113 enum coex_ext_ant_switch_pos_type { 114 COEX_SWITCH_TO_BT, 115 COEX_SWITCH_TO_WLG, 116 COEX_SWITCH_TO_WLA, 117 COEX_SWITCH_TO_NOCARE, 118 COEX_SWITCH_TO_WLG_BT, 119 120 COEX_SWITCH_TO_MAX 121 }; 122 123 enum coex_ext_ant_switch_ctrl_type { 124 COEX_SWITCH_CTRL_BY_BBSW, 125 COEX_SWITCH_CTRL_BY_PTA, 126 COEX_SWITCH_CTRL_BY_ANTDIV, 127 COEX_SWITCH_CTRL_BY_MAC, 128 COEX_SWITCH_CTRL_BY_BT, 129 COEX_SWITCH_CTRL_BY_FW, 130 131 COEX_SWITCH_CTRL_MAX 132 }; 133 134 enum coex_algorithm { 135 COEX_ALGO_NOPROFILE = 0, 136 COEX_ALGO_HFP = 1, 137 COEX_ALGO_HID = 2, 138 COEX_ALGO_A2DP = 3, 139 COEX_ALGO_PAN = 4, 140 COEX_ALGO_A2DP_HID = 5, 141 COEX_ALGO_A2DP_PAN = 6, 142 COEX_ALGO_PAN_HID = 7, 143 COEX_ALGO_A2DP_PAN_HID = 8, 144 145 COEX_ALGO_MAX 146 }; 147 148 enum coex_wl_link_mode { 149 COEX_WLINK_2G1PORT = 0x0, 150 COEX_WLINK_5G = 0x3, 151 COEX_WLINK_MAX 152 }; 153 154 enum coex_wl2bt_scoreboard { 155 COEX_SCBD_ACTIVE = BIT(0), 156 COEX_SCBD_ONOFF = BIT(1), 157 COEX_SCBD_SCAN = BIT(2), 158 COEX_SCBD_UNDERTEST = BIT(3), 159 COEX_SCBD_RXGAIN = BIT(4), 160 COEX_SCBD_BT_RFK = BIT(5), 161 COEX_SCBD_WLBUSY = BIT(6), 162 COEX_SCBD_EXTFEM = BIT(8), 163 COEX_SCBD_TDMA = BIT(9), 164 COEX_SCBD_FIX2M = BIT(10), 165 COEX_SCBD_ALL = GENMASK(15, 0), 166 }; 167 168 enum coex_power_save_type { 169 COEX_PS_WIFI_NATIVE = 0, 170 COEX_PS_LPS_ON = 1, 171 COEX_PS_LPS_OFF = 2, 172 }; 173 174 enum coex_rssi_state { 175 COEX_RSSI_STATE_HIGH, 176 COEX_RSSI_STATE_MEDIUM, 177 COEX_RSSI_STATE_LOW, 178 COEX_RSSI_STATE_STAY_HIGH, 179 COEX_RSSI_STATE_STAY_MEDIUM, 180 COEX_RSSI_STATE_STAY_LOW, 181 }; 182 183 enum coex_notify_type_ips { 184 COEX_IPS_LEAVE = 0x0, 185 COEX_IPS_ENTER = 0x1, 186 }; 187 188 enum coex_notify_type_lps { 189 COEX_LPS_DISABLE = 0x0, 190 COEX_LPS_ENABLE = 0x1, 191 }; 192 193 enum coex_notify_type_scan { 194 COEX_SCAN_FINISH, 195 COEX_SCAN_START, 196 COEX_SCAN_START_2G, 197 COEX_SCAN_START_5G, 198 }; 199 200 enum coex_notify_type_switchband { 201 COEX_NOT_SWITCH, 202 COEX_SWITCH_TO_24G, 203 COEX_SWITCH_TO_5G, 204 COEX_SWITCH_TO_24G_NOFORSCAN, 205 }; 206 207 enum coex_notify_type_associate { 208 COEX_ASSOCIATE_FINISH, 209 COEX_ASSOCIATE_START, 210 COEX_ASSOCIATE_5G_FINISH, 211 COEX_ASSOCIATE_5G_START, 212 }; 213 214 enum coex_notify_type_media_status { 215 COEX_MEDIA_DISCONNECT, 216 COEX_MEDIA_CONNECT, 217 COEX_MEDIA_CONNECT_5G, 218 }; 219 220 enum coex_bt_status { 221 COEX_BTSTATUS_NCON_IDLE = 0, 222 COEX_BTSTATUS_CON_IDLE = 1, 223 COEX_BTSTATUS_INQ_PAGE = 2, 224 COEX_BTSTATUS_ACL_BUSY = 3, 225 COEX_BTSTATUS_SCO_BUSY = 4, 226 COEX_BTSTATUS_ACL_SCO_BUSY = 5, 227 228 COEX_BTSTATUS_MAX 229 }; 230 231 enum coex_wl_tput_dir { 232 COEX_WL_TPUT_TX = 0x0, 233 COEX_WL_TPUT_RX = 0x1, 234 COEX_WL_TPUT_MAX 235 }; 236 237 enum coex_wl_priority_mask { 238 COEX_WLPRI_RX_RSP = 2, 239 COEX_WLPRI_TX_RSP = 3, 240 COEX_WLPRI_TX_BEACON = 4, 241 COEX_WLPRI_TX_OFDM = 11, 242 COEX_WLPRI_TX_CCK = 12, 243 COEX_WLPRI_TX_BEACONQ = 27, 244 COEX_WLPRI_RX_CCK = 28, 245 COEX_WLPRI_RX_OFDM = 29, 246 COEX_WLPRI_MAX 247 }; 248 249 enum coex_commom_chip_setup { 250 COEX_CSETUP_INIT_HW = 0x0, 251 COEX_CSETUP_ANT_SWITCH = 0x1, 252 COEX_CSETUP_GNT_FIX = 0x2, 253 COEX_CSETUP_GNT_DEBUG = 0x3, 254 COEX_CSETUP_RFE_TYPE = 0x4, 255 COEX_CSETUP_COEXINFO_HW = 0x5, 256 COEX_CSETUP_WL_TX_POWER = 0x6, 257 COEX_CSETUP_WL_RX_GAIN = 0x7, 258 COEX_CSETUP_WLAN_ACT_IPS = 0x8, 259 COEX_CSETUP_MAX 260 }; 261 262 enum coex_indirect_reg_type { 263 COEX_INDIRECT_1700 = 0x0, 264 COEX_INDIRECT_7C0 = 0x1, 265 COEX_INDIRECT_MAX 266 }; 267 268 enum coex_pstdma_type { 269 COEX_PSTDMA_FORCE_LPSOFF = 0x0, 270 COEX_PSTDMA_FORCE_LPSON = 0x1, 271 COEX_PSTDMA_MAX 272 }; 273 274 enum coex_btrssi_type { 275 COEX_BTRSSI_RATIO = 0x0, 276 COEX_BTRSSI_DBM = 0x1, 277 COEX_BTRSSI_MAX 278 }; 279 280 struct coex_table_para { 281 u32 bt; 282 u32 wl; 283 }; 284 285 struct coex_tdma_para { 286 u8 para[5]; 287 }; 288 289 struct coex_5g_afh_map { 290 u32 wl_5g_ch; 291 u8 bt_skip_ch; 292 u8 bt_skip_span; 293 }; 294 295 struct coex_rf_para { 296 u8 wl_pwr_dec_lvl; 297 u8 bt_pwr_dec_lvl; 298 bool wl_low_gain_en; 299 u8 bt_lna_lvl; 300 }; 301 302 static inline void rtw_coex_set_init(struct rtw_dev *rtwdev) 303 { 304 struct rtw_chip_info *chip = rtwdev->chip; 305 306 chip->ops->coex_set_init(rtwdev); 307 } 308 309 static inline 310 void rtw_coex_set_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, u8 pos_type) 311 { 312 struct rtw_chip_info *chip = rtwdev->chip; 313 314 if (!chip->ops->coex_set_ant_switch) 315 return; 316 317 chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type); 318 } 319 320 static inline void rtw_coex_set_gnt_fix(struct rtw_dev *rtwdev) 321 { 322 struct rtw_chip_info *chip = rtwdev->chip; 323 324 chip->ops->coex_set_gnt_fix(rtwdev); 325 } 326 327 static inline void rtw_coex_set_gnt_debug(struct rtw_dev *rtwdev) 328 { 329 struct rtw_chip_info *chip = rtwdev->chip; 330 331 chip->ops->coex_set_gnt_debug(rtwdev); 332 } 333 334 static inline void rtw_coex_set_rfe_type(struct rtw_dev *rtwdev) 335 { 336 struct rtw_chip_info *chip = rtwdev->chip; 337 338 chip->ops->coex_set_rfe_type(rtwdev); 339 } 340 341 static inline void rtw_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 342 { 343 struct rtw_chip_info *chip = rtwdev->chip; 344 345 chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr); 346 } 347 348 static inline 349 void rtw_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 350 { 351 struct rtw_chip_info *chip = rtwdev->chip; 352 353 chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain); 354 } 355 356 void rtw_coex_info_response(struct rtw_dev *rtwdev, struct sk_buff *skb); 357 u32 rtw_coex_read_indirect_reg(struct rtw_dev *rtwdev, u16 addr); 358 void rtw_coex_write_indirect_reg(struct rtw_dev *rtwdev, u16 addr, 359 u32 mask, u32 val); 360 void rtw_coex_write_scbd(struct rtw_dev *rtwdev, u16 bitpos, bool set); 361 362 void rtw_coex_bt_relink_work(struct work_struct *work); 363 void rtw_coex_bt_reenable_work(struct work_struct *work); 364 void rtw_coex_defreeze_work(struct work_struct *work); 365 366 void rtw_coex_power_on_setting(struct rtw_dev *rtwdev); 367 void rtw_coex_init_hw_config(struct rtw_dev *rtwdev, bool wifi_only); 368 void rtw_coex_ips_notify(struct rtw_dev *rtwdev, u8 type); 369 void rtw_coex_lps_notify(struct rtw_dev *rtwdev, u8 type); 370 void rtw_coex_scan_notify(struct rtw_dev *rtwdev, u8 type); 371 void rtw_coex_connect_notify(struct rtw_dev *rtwdev, u8 action); 372 void rtw_coex_media_status_notify(struct rtw_dev *rtwdev, u8 status); 373 void rtw_coex_bt_info_notify(struct rtw_dev *rtwdev, u8 *buf, u8 len); 374 void rtw_coex_wl_fwdbginfo_notify(struct rtw_dev *rtwdev, u8 *buf, u8 length); 375 void rtw_coex_switchband_notify(struct rtw_dev *rtwdev, u8 type); 376 void rtw_coex_wl_status_change_notify(struct rtw_dev *rtwdev); 377 378 void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m); 379 380 #endif 381