1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019  Realtek Corporation.
3  */
4 
5 #ifndef __RTW_BF_H_
6 #define __RTW_BF_H_
7 
8 #define REG_TXBF_CTRL		0x042C
9 #define REG_RRSR		0x0440
10 #define REG_NDPA_OPT_CTRL	0x045F
11 
12 #define REG_ASSOCIATED_BFMER0_INFO	0x06E4
13 #define REG_ASSOCIATED_BFMER1_INFO	0x06EC
14 #define REG_TX_CSI_RPT_PARAM_BW20	0x06F4
15 #define REG_SND_PTCL_CTRL		0x0718
16 #define REG_MU_TX_CTL			0x14C0
17 #define REG_MU_STA_GID_VLD		0x14C4
18 #define REG_MU_STA_USER_POS_INFO	0x14C8
19 #define REG_CSI_RRSR			0x1678
20 #define REG_WMAC_MU_BF_OPTION		0x167C
21 #define REG_WMAC_MU_BF_CTL		0x1680
22 
23 #define BIT_WMAC_USE_NDPARATE			BIT(30)
24 #define BIT_WMAC_TXMU_ACKPOLICY_EN		BIT(6)
25 #define BIT_USE_NDPA_PARAMETER			BIT(30)
26 #define BIT_MU_P1_WAIT_STATE_EN			BIT(16)
27 #define BIT_EN_MU_MIMO				BIT(7)
28 
29 #define R_MU_RL				0xf
30 #define BIT_SHIFT_R_MU_RL		12
31 #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY	4
32 #define BIT_SHIFT_CSI_RATE		24
33 
34 #define BIT_MASK_R_MU_RL (R_MU_RL << BIT_SHIFT_R_MU_RL)
35 #define BIT_MASK_R_MU_TABLE_VALID	0x3f
36 #define BIT_MASK_CSI_RATE_VAL		0x3F
37 #define BIT_MASK_CSI_RATE (BIT_MASK_CSI_RATE_VAL << BIT_SHIFT_CSI_RATE)
38 
39 #define BIT_RXFLTMAP0_ACTIONNOACK	BIT(14)
40 #define BIT_RXFLTMAP1_BF		(BIT(4) | BIT(5))
41 #define BIT_RXFLTMAP1_BF_REPORT_POLL	BIT(4)
42 #define BIT_RXFLTMAP4_BF_REPORT_POLL	BIT(4)
43 
44 #define RTW_NDP_RX_STANDBY_TIME	0x70
45 #define RTW_SND_CTRL_REMOVE	0xD8
46 #define RTW_SND_CTRL_SOUNDING	0xDB
47 
48 enum csi_seg_len {
49 	HAL_CSI_SEG_4K = 0,
50 	HAL_CSI_SEG_8K = 1,
51 	HAL_CSI_SEG_11K = 2,
52 };
53 
54 struct cfg_mumimo_para {
55 	u8 sounding_sts[6];
56 	u16 grouping_bitmap;
57 	u8 mu_tx_en;
58 	u32 given_gid_tab[2];
59 	u32 given_user_pos[4];
60 };
61 
62 struct mu_bfer_init_para {
63 	u16 paid;
64 	u16 csi_para;
65 	u16 my_aid;
66 	enum csi_seg_len csi_length_sel;
67 	u8 bfer_address[ETH_ALEN];
68 };
69 
70 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
71 		     struct ieee80211_bss_conf *bss_conf);
72 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
73 		  struct ieee80211_bss_conf *bss_conf);
74 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
75 			       struct mu_bfer_init_para *param);
76 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
77 			 enum rtw_trx_desc_rate rate);
78 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param);
79 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev);
80 void rtw_bf_del_sounding(struct rtw_dev *rtwdev);
81 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
82 			   struct rtw_bfee *bfee);
83 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
84 			   struct rtw_bfee *bfee);
85 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev, struct rtw_bfee *bfee);
86 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev, struct rtw_bfee *bfee);
87 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
88 			  struct ieee80211_bss_conf *conf);
89 void rtw_bf_phy_init(struct rtw_dev *rtwdev);
90 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
91 			 u8 fixrate_en, u8 *new_rate);
92 static inline void rtw_chip_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
93 					struct rtw_bfee *bfee, bool enable)
94 {
95 	if (rtwdev->chip->ops->config_bfee)
96 		rtwdev->chip->ops->config_bfee(rtwdev, vif, bfee, enable);
97 }
98 
99 static inline void rtw_chip_set_gid_table(struct rtw_dev *rtwdev,
100 					  struct ieee80211_vif *vif,
101 					  struct ieee80211_bss_conf *conf)
102 {
103 	if (rtwdev->chip->ops->set_gid_table)
104 		rtwdev->chip->ops->set_gid_table(rtwdev, vif, conf);
105 }
106 
107 static inline void rtw_chip_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
108 					 u8 fixrate_en, u8 *new_rate)
109 {
110 	if (rtwdev->chip->ops->cfg_csi_rate)
111 		rtwdev->chip->ops->cfg_csi_rate(rtwdev, rssi, cur_rate,
112 						fixrate_en, new_rate);
113 }
114 #endif
115