1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 #define ASPM_L1_LATENCY 7 103 104 #define TOTAL_CAM_ENTRY 32 105 106 /*slot time for 11g. */ 107 #define RTL_SLOT_TIME_9 9 108 #define RTL_SLOT_TIME_20 20 109 110 /*related to tcp/ip. */ 111 #define SNAP_SIZE 6 112 #define PROTOC_TYPE_SIZE 2 113 114 /*related with 802.11 frame*/ 115 #define MAC80211_3ADDR_LEN 24 116 #define MAC80211_4ADDR_LEN 30 117 118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 119 #define CHANNEL_MAX_NUMBER_2G 14 120 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 121 *"phy_GetChnlGroup8812A" and 122 * "Hal_ReadTxPowerInfo8812A" 123 */ 124 #define CHANNEL_MAX_NUMBER_5G_80M 7 125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 126 #define MAX_PG_GROUP 13 127 #define CHANNEL_GROUP_MAX_2G 3 128 #define CHANNEL_GROUP_IDX_5GL 3 129 #define CHANNEL_GROUP_IDX_5GM 6 130 #define CHANNEL_GROUP_IDX_5GH 9 131 #define CHANNEL_GROUP_MAX_5G 9 132 #define CHANNEL_MAX_NUMBER_2G 14 133 #define AVG_THERMAL_NUM 8 134 #define AVG_THERMAL_NUM_88E 4 135 #define AVG_THERMAL_NUM_8723BE 4 136 #define MAX_TID_COUNT 9 137 138 /* for early mode */ 139 #define FCS_LEN 4 140 #define EM_HDR_LEN 8 141 142 enum rtl8192c_h2c_cmd { 143 H2C_AP_OFFLOAD = 0, 144 H2C_SETPWRMODE = 1, 145 H2C_JOINBSSRPT = 2, 146 H2C_RSVDPAGE = 3, 147 H2C_RSSI_REPORT = 5, 148 H2C_RA_MASK = 6, 149 H2C_MACID_PS_MODE = 7, 150 H2C_P2P_PS_OFFLOAD = 8, 151 H2C_MAC_MODE_SEL = 9, 152 H2C_PWRM = 15, 153 H2C_P2P_PS_CTW_CMD = 24, 154 MAX_H2CCMD 155 }; 156 157 enum { 158 H2C_BT_PORT_ID = 0x71, 159 }; 160 161 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6]) 162 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0) 163 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F) 164 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6]) 165 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0) 166 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F) 167 168 #define MAX_TX_COUNT 4 169 #define MAX_REGULATION_NUM 4 170 #define MAX_RF_PATH_NUM 4 171 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */ 172 #define MAX_2_4G_BANDWIDTH_NUM 4 173 #define MAX_5G_BANDWIDTH_NUM 4 174 #define MAX_RF_PATH 4 175 #define MAX_CHNL_GROUP_24G 6 176 #define MAX_CHNL_GROUP_5G 14 177 178 #define TX_PWR_BY_RATE_NUM_BAND 2 179 #define TX_PWR_BY_RATE_NUM_RF 4 180 #define TX_PWR_BY_RATE_NUM_SECTION 12 181 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */ 182 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */ 183 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */ 184 185 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 186 187 #define DEL_SW_IDX_SZ 30 188 189 /* For now, it's just for 8192ee 190 * but not OK yet, keep it 0 191 */ 192 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM 193 194 enum rf_tx_num { 195 RF_1TX = 0, 196 RF_2TX, 197 RF_MAX_TX_NUM, 198 RF_TX_NUM_NONIMPLEMENT, 199 }; 200 201 #define PACKET_NORMAL 0 202 #define PACKET_DHCP 1 203 #define PACKET_ARP 2 204 #define PACKET_EAPOL 3 205 206 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 207 #define RSVD_WOL_PATTERN_NUM 1 208 #define WKFMCAM_ADDR_NUM 6 209 #define WKFMCAM_SIZE 24 210 211 #define MAX_WOL_BIT_MASK_SIZE 16 212 /* MIN LEN keeps 13 here */ 213 #define MIN_WOL_PATTERN_SIZE 13 214 #define MAX_WOL_PATTERN_SIZE 128 215 216 #define WAKE_ON_MAGIC_PACKET BIT(0) 217 #define WAKE_ON_PATTERN_MATCH BIT(1) 218 219 #define WOL_REASON_PTK_UPDATE BIT(0) 220 #define WOL_REASON_GTK_UPDATE BIT(1) 221 #define WOL_REASON_DISASSOC BIT(2) 222 #define WOL_REASON_DEAUTH BIT(3) 223 #define WOL_REASON_AP_LOST BIT(4) 224 #define WOL_REASON_MAGIC_PKT BIT(5) 225 #define WOL_REASON_UNICAST_PKT BIT(6) 226 #define WOL_REASON_PATTERN_PKT BIT(7) 227 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 228 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 229 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 230 231 struct rtlwifi_firmware_header { 232 __le16 signature; 233 u8 category; 234 u8 function; 235 __le16 version; 236 u8 subversion; 237 u8 rsvd1; 238 u8 month; 239 u8 date; 240 u8 hour; 241 u8 minute; 242 __le16 ramcodeSize; 243 __le16 rsvd2; 244 __le32 svnindex; 245 __le32 rsvd3; 246 __le32 rsvd4; 247 __le32 rsvd5; 248 }; 249 250 struct txpower_info_2g { 251 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 252 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 253 /*If only one tx, only BW20 and OFDM are used.*/ 254 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 255 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 256 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 257 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 258 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 259 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 260 }; 261 262 struct txpower_info_5g { 263 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 264 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 265 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 266 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 267 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 268 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 269 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 270 }; 271 272 enum rate_section { 273 CCK = 0, 274 OFDM, 275 HT_MCS0_MCS7, 276 HT_MCS8_MCS15, 277 VHT_1SSMCS0_1SSMCS9, 278 VHT_2SSMCS0_2SSMCS9, 279 MAX_RATE_SECTION, 280 }; 281 282 enum intf_type { 283 INTF_PCI = 0, 284 INTF_USB = 1, 285 }; 286 287 enum radio_path { 288 RF90_PATH_A = 0, 289 RF90_PATH_B = 1, 290 RF90_PATH_C = 2, 291 RF90_PATH_D = 3, 292 }; 293 294 enum radio_mask { 295 RF_MASK_A = BIT(0), 296 RF_MASK_B = BIT(1), 297 RF_MASK_C = BIT(2), 298 RF_MASK_D = BIT(3), 299 }; 300 301 enum regulation_txpwr_lmt { 302 TXPWR_LMT_FCC = 0, 303 TXPWR_LMT_MKK = 1, 304 TXPWR_LMT_ETSI = 2, 305 TXPWR_LMT_WW = 3, 306 307 TXPWR_LMT_MAX_REGULATION_NUM = 4 308 }; 309 310 enum rt_eeprom_type { 311 EEPROM_93C46, 312 EEPROM_93C56, 313 EEPROM_BOOT_EFUSE, 314 }; 315 316 enum ttl_status { 317 RTL_STATUS_INTERFACE_START = 0, 318 }; 319 320 enum hardware_type { 321 HARDWARE_TYPE_RTL8192E, 322 HARDWARE_TYPE_RTL8192U, 323 HARDWARE_TYPE_RTL8192SE, 324 HARDWARE_TYPE_RTL8192SU, 325 HARDWARE_TYPE_RTL8192CE, 326 HARDWARE_TYPE_RTL8192CU, 327 HARDWARE_TYPE_RTL8192DE, 328 HARDWARE_TYPE_RTL8192DU, 329 HARDWARE_TYPE_RTL8723AE, 330 HARDWARE_TYPE_RTL8723U, 331 HARDWARE_TYPE_RTL8188EE, 332 HARDWARE_TYPE_RTL8723BE, 333 HARDWARE_TYPE_RTL8192EE, 334 HARDWARE_TYPE_RTL8821AE, 335 HARDWARE_TYPE_RTL8812AE, 336 HARDWARE_TYPE_RTL8822BE, 337 338 /* keep it last */ 339 HARDWARE_TYPE_NUM 340 }; 341 342 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type) 343 #define IS_NEW_GENERATION_IC(rtlpriv) \ 344 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE) 345 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \ 346 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE) 347 #define IS_HARDWARE_TYPE_8812(rtlpriv) \ 348 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE) 349 #define IS_HARDWARE_TYPE_8821(rtlpriv) \ 350 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE) 351 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \ 352 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE) 353 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \ 354 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE) 355 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \ 356 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE) 357 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \ 358 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE) 359 360 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 361 ((rxmcs) == DESC_RATE1M || \ 362 (rxmcs) == DESC_RATE2M || \ 363 (rxmcs) == DESC_RATE5_5M || \ 364 (rxmcs) == DESC_RATE11M) 365 366 enum scan_operation_backup_opt { 367 SCAN_OPT_BACKUP = 0, 368 SCAN_OPT_BACKUP_BAND0 = 0, 369 SCAN_OPT_BACKUP_BAND1, 370 SCAN_OPT_RESTORE, 371 SCAN_OPT_MAX 372 }; 373 374 /*RF state.*/ 375 enum rf_pwrstate { 376 ERFON, 377 ERFSLEEP, 378 ERFOFF 379 }; 380 381 struct bb_reg_def { 382 u32 rfintfs; 383 u32 rfintfi; 384 u32 rfintfo; 385 u32 rfintfe; 386 u32 rf3wire_offset; 387 u32 rflssi_select; 388 u32 rftxgain_stage; 389 u32 rfhssi_para1; 390 u32 rfhssi_para2; 391 u32 rfsw_ctrl; 392 u32 rfagc_control1; 393 u32 rfagc_control2; 394 u32 rfrxiq_imbal; 395 u32 rfrx_afe; 396 u32 rftxiq_imbal; 397 u32 rftx_afe; 398 u32 rf_rb; /* rflssi_readback */ 399 u32 rf_rbpi; /* rflssi_readbackpi */ 400 }; 401 402 enum io_type { 403 IO_CMD_PAUSE_DM_BY_SCAN = 0, 404 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 405 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 406 IO_CMD_RESUME_DM_BY_SCAN = 2, 407 }; 408 409 enum hw_variables { 410 HW_VAR_ETHER_ADDR = 0x0, 411 HW_VAR_MULTICAST_REG = 0x1, 412 HW_VAR_BASIC_RATE = 0x2, 413 HW_VAR_BSSID = 0x3, 414 HW_VAR_MEDIA_STATUS= 0x4, 415 HW_VAR_SECURITY_CONF= 0x5, 416 HW_VAR_BEACON_INTERVAL = 0x6, 417 HW_VAR_ATIM_WINDOW = 0x7, 418 HW_VAR_LISTEN_INTERVAL = 0x8, 419 HW_VAR_CS_COUNTER = 0x9, 420 HW_VAR_DEFAULTKEY0 = 0xa, 421 HW_VAR_DEFAULTKEY1 = 0xb, 422 HW_VAR_DEFAULTKEY2 = 0xc, 423 HW_VAR_DEFAULTKEY3 = 0xd, 424 HW_VAR_SIFS = 0xe, 425 HW_VAR_R2T_SIFS = 0xf, 426 HW_VAR_DIFS = 0x10, 427 HW_VAR_EIFS = 0x11, 428 HW_VAR_SLOT_TIME = 0x12, 429 HW_VAR_ACK_PREAMBLE = 0x13, 430 HW_VAR_CW_CONFIG = 0x14, 431 HW_VAR_CW_VALUES = 0x15, 432 HW_VAR_RATE_FALLBACK_CONTROL= 0x16, 433 HW_VAR_CONTENTION_WINDOW = 0x17, 434 HW_VAR_RETRY_COUNT = 0x18, 435 HW_VAR_TR_SWITCH = 0x19, 436 HW_VAR_COMMAND = 0x1a, 437 HW_VAR_WPA_CONFIG = 0x1b, 438 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 439 HW_VAR_SHORTGI_DENSITY = 0x1d, 440 HW_VAR_AMPDU_FACTOR = 0x1e, 441 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 442 HW_VAR_AC_PARAM = 0x20, 443 HW_VAR_ACM_CTRL = 0x21, 444 HW_VAR_DIS_Req_Qsize = 0x22, 445 HW_VAR_CCX_CHNL_LOAD = 0x23, 446 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 447 HW_VAR_CCX_CLM_NHM = 0x25, 448 HW_VAR_TxOPLimit = 0x26, 449 HW_VAR_TURBO_MODE = 0x27, 450 HW_VAR_RF_STATE = 0x28, 451 HW_VAR_RF_OFF_BY_HW = 0x29, 452 HW_VAR_BUS_SPEED = 0x2a, 453 HW_VAR_SET_DEV_POWER = 0x2b, 454 455 HW_VAR_RCR = 0x2c, 456 HW_VAR_RATR_0 = 0x2d, 457 HW_VAR_RRSR = 0x2e, 458 HW_VAR_CPU_RST = 0x2f, 459 HW_VAR_CHECK_BSSID = 0x30, 460 HW_VAR_LBK_MODE = 0x31, 461 HW_VAR_AES_11N_FIX = 0x32, 462 HW_VAR_USB_RX_AGGR = 0x33, 463 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 464 HW_VAR_RETRY_LIMIT = 0x35, 465 HW_VAR_INIT_TX_RATE = 0x36, 466 HW_VAR_TX_RATE_REG = 0x37, 467 HW_VAR_EFUSE_USAGE = 0x38, 468 HW_VAR_EFUSE_BYTES = 0x39, 469 HW_VAR_AUTOLOAD_STATUS = 0x3a, 470 HW_VAR_RF_2R_DISABLE = 0x3b, 471 HW_VAR_SET_RPWM = 0x3c, 472 HW_VAR_H2C_FW_PWRMODE = 0x3d, 473 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 474 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 475 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 476 HW_VAR_FW_PSMODE_STATUS = 0x41, 477 HW_VAR_INIT_RTS_RATE = 0x42, 478 HW_VAR_RESUME_CLK_ON = 0x43, 479 HW_VAR_FW_LPS_ACTION = 0x44, 480 HW_VAR_1X1_RECV_COMBINE = 0x45, 481 HW_VAR_STOP_SEND_BEACON = 0x46, 482 HW_VAR_TSF_TIMER = 0x47, 483 HW_VAR_IO_CMD = 0x48, 484 485 HW_VAR_RF_RECOVERY = 0x49, 486 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 487 HW_VAR_WF_MASK = 0x4b, 488 HW_VAR_WF_CRC = 0x4c, 489 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 490 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 491 HW_VAR_RESET_WFCRC = 0x4f, 492 493 HW_VAR_HANDLE_FW_C2H = 0x50, 494 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 495 HW_VAR_AID = 0x52, 496 HW_VAR_HW_SEQ_ENABLE = 0x53, 497 HW_VAR_CORRECT_TSF = 0x54, 498 HW_VAR_BCN_VALID = 0x55, 499 HW_VAR_FWLPS_RF_ON = 0x56, 500 HW_VAR_DUAL_TSF_RST = 0x57, 501 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58, 502 HW_VAR_INT_MIGRATION = 0x59, 503 HW_VAR_INT_AC = 0x5a, 504 HW_VAR_RF_TIMING = 0x5b, 505 506 HAL_DEF_WOWLAN = 0x5c, 507 HW_VAR_MRC = 0x5d, 508 HW_VAR_KEEP_ALIVE = 0x5e, 509 HW_VAR_NAV_UPPER = 0x5f, 510 511 HW_VAR_MGT_FILTER = 0x60, 512 HW_VAR_CTRL_FILTER = 0x61, 513 HW_VAR_DATA_FILTER = 0x62, 514 }; 515 516 enum rt_media_status { 517 RT_MEDIA_DISCONNECT = 0, 518 RT_MEDIA_CONNECT = 1 519 }; 520 521 enum rt_oem_id { 522 RT_CID_DEFAULT = 0, 523 RT_CID_8187_ALPHA0 = 1, 524 RT_CID_8187_SERCOMM_PS = 2, 525 RT_CID_8187_HW_LED = 3, 526 RT_CID_8187_NETGEAR = 4, 527 RT_CID_WHQL = 5, 528 RT_CID_819X_CAMEO = 6, 529 RT_CID_819X_RUNTOP = 7, 530 RT_CID_819X_SENAO = 8, 531 RT_CID_TOSHIBA = 9, 532 RT_CID_819X_NETCORE = 10, 533 RT_CID_NETTRONIX = 11, 534 RT_CID_DLINK = 12, 535 RT_CID_PRONET = 13, 536 RT_CID_COREGA = 14, 537 RT_CID_819X_ALPHA = 15, 538 RT_CID_819X_SITECOM = 16, 539 RT_CID_CCX = 17, 540 RT_CID_819X_LENOVO = 18, 541 RT_CID_819X_QMI = 19, 542 RT_CID_819X_EDIMAX_BELKIN = 20, 543 RT_CID_819X_SERCOMM_BELKIN = 21, 544 RT_CID_819X_CAMEO1 = 22, 545 RT_CID_819X_MSI = 23, 546 RT_CID_819X_ACER = 24, 547 RT_CID_819X_HP = 27, 548 RT_CID_819X_CLEVO = 28, 549 RT_CID_819X_ARCADYAN_BELKIN = 29, 550 RT_CID_819X_SAMSUNG = 30, 551 RT_CID_819X_WNC_COREGA = 31, 552 RT_CID_819X_FOXCOON = 32, 553 RT_CID_819X_DELL = 33, 554 RT_CID_819X_PRONETS = 34, 555 RT_CID_819X_EDIMAX_ASUS = 35, 556 RT_CID_NETGEAR = 36, 557 RT_CID_PLANEX = 37, 558 RT_CID_CC_C = 38, 559 RT_CID_LENOVO_CHINA = 40, 560 }; 561 562 enum hw_descs { 563 HW_DESC_OWN, 564 HW_DESC_RXOWN, 565 HW_DESC_TX_NEXTDESC_ADDR, 566 HW_DESC_TXBUFF_ADDR, 567 HW_DESC_RXBUFF_ADDR, 568 HW_DESC_RXPKT_LEN, 569 HW_DESC_RXERO, 570 HW_DESC_RX_PREPARE, 571 }; 572 573 enum prime_sc { 574 PRIME_CHNL_OFFSET_DONT_CARE = 0, 575 PRIME_CHNL_OFFSET_LOWER = 1, 576 PRIME_CHNL_OFFSET_UPPER = 2, 577 }; 578 579 enum rf_type { 580 RF_1T1R = 0, 581 RF_1T2R = 1, 582 RF_2T2R = 2, 583 RF_2T2R_GREEN = 3, 584 RF_2T3R = 4, 585 RF_2T4R = 5, 586 RF_3T3R = 6, 587 RF_3T4R = 7, 588 RF_4T4R = 8, 589 }; 590 591 enum ht_channel_width { 592 HT_CHANNEL_WIDTH_20 = 0, 593 HT_CHANNEL_WIDTH_20_40 = 1, 594 HT_CHANNEL_WIDTH_80 = 2, 595 HT_CHANNEL_WIDTH_MAX, 596 }; 597 598 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 599 Cipher Suites Encryption Algorithms */ 600 enum rt_enc_alg { 601 NO_ENCRYPTION = 0, 602 WEP40_ENCRYPTION = 1, 603 TKIP_ENCRYPTION = 2, 604 RSERVED_ENCRYPTION = 3, 605 AESCCMP_ENCRYPTION = 4, 606 WEP104_ENCRYPTION = 5, 607 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 608 }; 609 610 enum rtl_hal_state { 611 _HAL_STATE_STOP = 0, 612 _HAL_STATE_START = 1, 613 }; 614 615 enum rtl_desc_rate { 616 DESC_RATE1M = 0x00, 617 DESC_RATE2M = 0x01, 618 DESC_RATE5_5M = 0x02, 619 DESC_RATE11M = 0x03, 620 621 DESC_RATE6M = 0x04, 622 DESC_RATE9M = 0x05, 623 DESC_RATE12M = 0x06, 624 DESC_RATE18M = 0x07, 625 DESC_RATE24M = 0x08, 626 DESC_RATE36M = 0x09, 627 DESC_RATE48M = 0x0a, 628 DESC_RATE54M = 0x0b, 629 630 DESC_RATEMCS0 = 0x0c, 631 DESC_RATEMCS1 = 0x0d, 632 DESC_RATEMCS2 = 0x0e, 633 DESC_RATEMCS3 = 0x0f, 634 DESC_RATEMCS4 = 0x10, 635 DESC_RATEMCS5 = 0x11, 636 DESC_RATEMCS6 = 0x12, 637 DESC_RATEMCS7 = 0x13, 638 DESC_RATEMCS8 = 0x14, 639 DESC_RATEMCS9 = 0x15, 640 DESC_RATEMCS10 = 0x16, 641 DESC_RATEMCS11 = 0x17, 642 DESC_RATEMCS12 = 0x18, 643 DESC_RATEMCS13 = 0x19, 644 DESC_RATEMCS14 = 0x1a, 645 DESC_RATEMCS15 = 0x1b, 646 DESC_RATEMCS15_SG = 0x1c, 647 DESC_RATEMCS32 = 0x20, 648 649 DESC_RATEVHT1SS_MCS0 = 0x2c, 650 DESC_RATEVHT1SS_MCS1 = 0x2d, 651 DESC_RATEVHT1SS_MCS2 = 0x2e, 652 DESC_RATEVHT1SS_MCS3 = 0x2f, 653 DESC_RATEVHT1SS_MCS4 = 0x30, 654 DESC_RATEVHT1SS_MCS5 = 0x31, 655 DESC_RATEVHT1SS_MCS6 = 0x32, 656 DESC_RATEVHT1SS_MCS7 = 0x33, 657 DESC_RATEVHT1SS_MCS8 = 0x34, 658 DESC_RATEVHT1SS_MCS9 = 0x35, 659 DESC_RATEVHT2SS_MCS0 = 0x36, 660 DESC_RATEVHT2SS_MCS1 = 0x37, 661 DESC_RATEVHT2SS_MCS2 = 0x38, 662 DESC_RATEVHT2SS_MCS3 = 0x39, 663 DESC_RATEVHT2SS_MCS4 = 0x3a, 664 DESC_RATEVHT2SS_MCS5 = 0x3b, 665 DESC_RATEVHT2SS_MCS6 = 0x3c, 666 DESC_RATEVHT2SS_MCS7 = 0x3d, 667 DESC_RATEVHT2SS_MCS8 = 0x3e, 668 DESC_RATEVHT2SS_MCS9 = 0x3f, 669 }; 670 671 enum rtl_var_map { 672 /*reg map */ 673 SYS_ISO_CTRL = 0, 674 SYS_FUNC_EN, 675 SYS_CLK, 676 MAC_RCR_AM, 677 MAC_RCR_AB, 678 MAC_RCR_ACRC32, 679 MAC_RCR_ACF, 680 MAC_RCR_AAP, 681 MAC_HIMR, 682 MAC_HIMRE, 683 MAC_HSISR, 684 685 /*efuse map */ 686 EFUSE_TEST, 687 EFUSE_CTRL, 688 EFUSE_CLK, 689 EFUSE_CLK_CTRL, 690 EFUSE_PWC_EV12V, 691 EFUSE_FEN_ELDR, 692 EFUSE_LOADER_CLK_EN, 693 EFUSE_ANA8M, 694 EFUSE_HWSET_MAX_SIZE, 695 EFUSE_MAX_SECTION_MAP, 696 EFUSE_REAL_CONTENT_SIZE, 697 EFUSE_OOB_PROTECT_BYTES_LEN, 698 EFUSE_ACCESS, 699 700 /*CAM map */ 701 RWCAM, 702 WCAMI, 703 RCAMO, 704 CAMDBG, 705 SECR, 706 SEC_CAM_NONE, 707 SEC_CAM_WEP40, 708 SEC_CAM_TKIP, 709 SEC_CAM_AES, 710 SEC_CAM_WEP104, 711 712 /*IMR map */ 713 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 714 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 715 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 716 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 717 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 718 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 719 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 720 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 721 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 722 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 723 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 724 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 725 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 726 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 727 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 728 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 729 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 730 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 731 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 732 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 733 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 734 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 735 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */ 736 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 737 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 738 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 739 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 740 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 741 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 742 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 743 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 744 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 745 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 746 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 747 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 748 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 749 * RTL_IMR_TBDER) */ 750 RTL_IMR_C2HCMD, /*fw interrupt*/ 751 752 /*CCK Rates, TxHT = 0 */ 753 RTL_RC_CCK_RATE1M, 754 RTL_RC_CCK_RATE2M, 755 RTL_RC_CCK_RATE5_5M, 756 RTL_RC_CCK_RATE11M, 757 758 /*OFDM Rates, TxHT = 0 */ 759 RTL_RC_OFDM_RATE6M, 760 RTL_RC_OFDM_RATE9M, 761 RTL_RC_OFDM_RATE12M, 762 RTL_RC_OFDM_RATE18M, 763 RTL_RC_OFDM_RATE24M, 764 RTL_RC_OFDM_RATE36M, 765 RTL_RC_OFDM_RATE48M, 766 RTL_RC_OFDM_RATE54M, 767 768 RTL_RC_HT_RATEMCS7, 769 RTL_RC_HT_RATEMCS15, 770 771 RTL_RC_VHT_RATE_1SS_MCS7, 772 RTL_RC_VHT_RATE_1SS_MCS8, 773 RTL_RC_VHT_RATE_1SS_MCS9, 774 RTL_RC_VHT_RATE_2SS_MCS7, 775 RTL_RC_VHT_RATE_2SS_MCS8, 776 RTL_RC_VHT_RATE_2SS_MCS9, 777 778 /*keep it last */ 779 RTL_VAR_MAP_MAX, 780 }; 781 782 /*Firmware PS mode for control LPS.*/ 783 enum _fw_ps_mode { 784 FW_PS_ACTIVE_MODE = 0, 785 FW_PS_MIN_MODE = 1, 786 FW_PS_MAX_MODE = 2, 787 FW_PS_DTIM_MODE = 3, 788 FW_PS_VOIP_MODE = 4, 789 FW_PS_UAPSD_WMM_MODE = 5, 790 FW_PS_UAPSD_MODE = 6, 791 FW_PS_IBSS_MODE = 7, 792 FW_PS_WWLAN_MODE = 8, 793 FW_PS_PM_Radio_Off = 9, 794 FW_PS_PM_Card_Disable = 10, 795 }; 796 797 enum rt_psmode { 798 EACTIVE, /*Active/Continuous access. */ 799 EMAXPS, /*Max power save mode. */ 800 EFASTPS, /*Fast power save mode. */ 801 EAUTOPS, /*Auto power save mode. */ 802 }; 803 804 /*LED related.*/ 805 enum led_ctl_mode { 806 LED_CTL_POWER_ON = 1, 807 LED_CTL_LINK = 2, 808 LED_CTL_NO_LINK = 3, 809 LED_CTL_TX = 4, 810 LED_CTL_RX = 5, 811 LED_CTL_SITE_SURVEY = 6, 812 LED_CTL_POWER_OFF = 7, 813 LED_CTL_START_TO_LINK = 8, 814 LED_CTL_START_WPS = 9, 815 LED_CTL_STOP_WPS = 10, 816 }; 817 818 enum rtl_led_pin { 819 LED_PIN_GPIO0, 820 LED_PIN_LED0, 821 LED_PIN_LED1, 822 LED_PIN_LED2 823 }; 824 825 /*QoS related.*/ 826 /*acm implementation method.*/ 827 enum acm_method { 828 eAcmWay0_SwAndHw = 0, 829 eAcmWay1_HW = 1, 830 EACMWAY2_SW = 2, 831 }; 832 833 enum macphy_mode { 834 SINGLEMAC_SINGLEPHY = 0, 835 DUALMAC_DUALPHY, 836 DUALMAC_SINGLEPHY, 837 }; 838 839 enum band_type { 840 BAND_ON_2_4G = 0, 841 BAND_ON_5G, 842 BAND_ON_BOTH, 843 BANDMAX 844 }; 845 846 /*aci/aifsn Field. 847 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 848 union aci_aifsn { 849 u8 char_data; 850 851 struct { 852 u8 aifsn:4; 853 u8 acm:1; 854 u8 aci:2; 855 u8 reserved:1; 856 } f; /* Field */ 857 }; 858 859 /*mlme related.*/ 860 enum wireless_mode { 861 WIRELESS_MODE_UNKNOWN = 0x00, 862 WIRELESS_MODE_A = 0x01, 863 WIRELESS_MODE_B = 0x02, 864 WIRELESS_MODE_G = 0x04, 865 WIRELESS_MODE_AUTO = 0x08, 866 WIRELESS_MODE_N_24G = 0x10, 867 WIRELESS_MODE_N_5G = 0x20, 868 WIRELESS_MODE_AC_5G = 0x40, 869 WIRELESS_MODE_AC_24G = 0x80, 870 WIRELESS_MODE_AC_ONLY = 0x100, 871 WIRELESS_MODE_MAX = 0x800 872 }; 873 874 #define IS_WIRELESS_MODE_A(wirelessmode) \ 875 (wirelessmode == WIRELESS_MODE_A) 876 #define IS_WIRELESS_MODE_B(wirelessmode) \ 877 (wirelessmode == WIRELESS_MODE_B) 878 #define IS_WIRELESS_MODE_G(wirelessmode) \ 879 (wirelessmode == WIRELESS_MODE_G) 880 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 881 (wirelessmode == WIRELESS_MODE_N_24G) 882 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 883 (wirelessmode == WIRELESS_MODE_N_5G) 884 885 enum ratr_table_mode { 886 RATR_INX_WIRELESS_NGB = 0, 887 RATR_INX_WIRELESS_NG = 1, 888 RATR_INX_WIRELESS_NB = 2, 889 RATR_INX_WIRELESS_N = 3, 890 RATR_INX_WIRELESS_GB = 4, 891 RATR_INX_WIRELESS_G = 5, 892 RATR_INX_WIRELESS_B = 6, 893 RATR_INX_WIRELESS_MC = 7, 894 RATR_INX_WIRELESS_A = 8, 895 RATR_INX_WIRELESS_AC_5N = 8, 896 RATR_INX_WIRELESS_AC_24N = 9, 897 }; 898 899 enum ratr_table_mode_new { 900 RATEID_IDX_BGN_40M_2SS = 0, 901 RATEID_IDX_BGN_40M_1SS = 1, 902 RATEID_IDX_BGN_20M_2SS_BN = 2, 903 RATEID_IDX_BGN_20M_1SS_BN = 3, 904 RATEID_IDX_GN_N2SS = 4, 905 RATEID_IDX_GN_N1SS = 5, 906 RATEID_IDX_BG = 6, 907 RATEID_IDX_G = 7, 908 RATEID_IDX_B = 8, 909 RATEID_IDX_VHT_2SS = 9, 910 RATEID_IDX_VHT_1SS = 10, 911 RATEID_IDX_MIX1 = 11, 912 RATEID_IDX_MIX2 = 12, 913 RATEID_IDX_VHT_3SS = 13, 914 RATEID_IDX_BGN_3SS = 14, 915 }; 916 917 enum rtl_link_state { 918 MAC80211_NOLINK = 0, 919 MAC80211_LINKING = 1, 920 MAC80211_LINKED = 2, 921 MAC80211_LINKED_SCANNING = 3, 922 }; 923 924 enum act_category { 925 ACT_CAT_QOS = 1, 926 ACT_CAT_DLS = 2, 927 ACT_CAT_BA = 3, 928 ACT_CAT_HT = 7, 929 ACT_CAT_WMM = 17, 930 }; 931 932 enum ba_action { 933 ACT_ADDBAREQ = 0, 934 ACT_ADDBARSP = 1, 935 ACT_DELBA = 2, 936 }; 937 938 enum rt_polarity_ctl { 939 RT_POLARITY_LOW_ACT = 0, 940 RT_POLARITY_HIGH_ACT = 1, 941 }; 942 943 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 944 enum fw_wow_reason_v2 { 945 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 946 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 947 FW_WOW_V2_DISASSOC_EVENT = 0x04, 948 FW_WOW_V2_DEAUTH_EVENT = 0x08, 949 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 950 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 951 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 952 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 953 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 954 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 955 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 956 FW_WOW_V2_REASON_MAX = 0xff, 957 }; 958 959 enum wolpattern_type { 960 UNICAST_PATTERN = 0, 961 MULTICAST_PATTERN = 1, 962 BROADCAST_PATTERN = 2, 963 DONT_CARE_DA = 3, 964 UNKNOWN_TYPE = 4, 965 }; 966 967 enum package_type { 968 PACKAGE_DEFAULT, 969 PACKAGE_QFN68, 970 PACKAGE_TFBGA90, 971 PACKAGE_TFBGA80, 972 PACKAGE_TFBGA79 973 }; 974 975 enum rtl_spec_ver { 976 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */ 977 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */ 978 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */ 979 }; 980 981 enum dm_info_query { 982 DM_INFO_FA_OFDM, 983 DM_INFO_FA_CCK, 984 DM_INFO_FA_TOTAL, 985 DM_INFO_CCA_OFDM, 986 DM_INFO_CCA_CCK, 987 DM_INFO_CCA_ALL, 988 DM_INFO_CRC32_OK_VHT, 989 DM_INFO_CRC32_OK_HT, 990 DM_INFO_CRC32_OK_LEGACY, 991 DM_INFO_CRC32_OK_CCK, 992 DM_INFO_CRC32_ERROR_VHT, 993 DM_INFO_CRC32_ERROR_HT, 994 DM_INFO_CRC32_ERROR_LEGACY, 995 DM_INFO_CRC32_ERROR_CCK, 996 DM_INFO_EDCCA_FLAG, 997 DM_INFO_OFDM_ENABLE, 998 DM_INFO_CCK_ENABLE, 999 DM_INFO_CRC32_OK_HT_AGG, 1000 DM_INFO_CRC32_ERROR_HT_AGG, 1001 DM_INFO_DBG_PORT_0, 1002 DM_INFO_CURR_IGI, 1003 DM_INFO_RSSI_MIN, 1004 DM_INFO_RSSI_MAX, 1005 DM_INFO_CLM_RATIO, 1006 DM_INFO_NHM_RATIO, 1007 DM_INFO_IQK_ALL, 1008 DM_INFO_IQK_OK, 1009 DM_INFO_IQK_NG, 1010 DM_INFO_SIZE, 1011 }; 1012 1013 struct octet_string { 1014 u8 *octet; 1015 u16 length; 1016 }; 1017 1018 struct rtl_hdr_3addr { 1019 __le16 frame_ctl; 1020 __le16 duration_id; 1021 u8 addr1[ETH_ALEN]; 1022 u8 addr2[ETH_ALEN]; 1023 u8 addr3[ETH_ALEN]; 1024 __le16 seq_ctl; 1025 u8 payload[0]; 1026 } __packed; 1027 1028 struct rtl_info_element { 1029 u8 id; 1030 u8 len; 1031 u8 data[0]; 1032 } __packed; 1033 1034 struct rtl_probe_rsp { 1035 struct rtl_hdr_3addr header; 1036 u32 time_stamp[2]; 1037 __le16 beacon_interval; 1038 __le16 capability; 1039 /*SSID, supported rates, FH params, DS params, 1040 CF params, IBSS params, TIM (if beacon), RSN */ 1041 struct rtl_info_element info_element[0]; 1042 } __packed; 1043 1044 /*LED related.*/ 1045 /*ledpin Identify how to implement this SW led.*/ 1046 struct rtl_led { 1047 void *hw; 1048 enum rtl_led_pin ledpin; 1049 bool ledon; 1050 }; 1051 1052 struct rtl_led_ctl { 1053 bool led_opendrain; 1054 struct rtl_led sw_led0; 1055 struct rtl_led sw_led1; 1056 }; 1057 1058 struct rtl_qos_parameters { 1059 __le16 cw_min; 1060 __le16 cw_max; 1061 u8 aifs; 1062 u8 flag; 1063 __le16 tx_op; 1064 } __packed; 1065 1066 struct rt_smooth_data { 1067 u32 elements[100]; /*array to store values */ 1068 u32 index; /*index to current array to store */ 1069 u32 total_num; /*num of valid elements */ 1070 u32 total_val; /*sum of valid elements */ 1071 }; 1072 1073 struct false_alarm_statistics { 1074 u32 cnt_parity_fail; 1075 u32 cnt_rate_illegal; 1076 u32 cnt_crc8_fail; 1077 u32 cnt_mcs_fail; 1078 u32 cnt_fast_fsync_fail; 1079 u32 cnt_sb_search_fail; 1080 u32 cnt_ofdm_fail; 1081 u32 cnt_cck_fail; 1082 u32 cnt_all; 1083 u32 cnt_ofdm_cca; 1084 u32 cnt_cck_cca; 1085 u32 cnt_cca_all; 1086 u32 cnt_bw_usc; 1087 u32 cnt_bw_lsc; 1088 }; 1089 1090 struct init_gain { 1091 u8 xaagccore1; 1092 u8 xbagccore1; 1093 u8 xcagccore1; 1094 u8 xdagccore1; 1095 u8 cca; 1096 1097 }; 1098 1099 struct wireless_stats { 1100 u64 txbytesunicast; 1101 u64 txbytesmulticast; 1102 u64 txbytesbroadcast; 1103 u64 rxbytesunicast; 1104 1105 u64 txbytesunicast_inperiod; 1106 u64 rxbytesunicast_inperiod; 1107 u32 txbytesunicast_inperiod_tp; 1108 u32 rxbytesunicast_inperiod_tp; 1109 u64 txbytesunicast_last; 1110 u64 rxbytesunicast_last; 1111 1112 long rx_snr_db[4]; 1113 /*Correct smoothed ss in Dbm, only used 1114 in driver to report real power now. */ 1115 long recv_signal_power; 1116 long signal_quality; 1117 long last_sigstrength_inpercent; 1118 1119 u32 rssi_calculate_cnt; 1120 u32 pwdb_all_cnt; 1121 1122 /*Transformed, in dbm. Beautified signal 1123 strength for UI, not correct. */ 1124 long signal_strength; 1125 1126 u8 rx_rssi_percentage[4]; 1127 u8 rx_evm_dbm[4]; 1128 u8 rx_evm_percentage[2]; 1129 1130 u16 rx_cfo_short[4]; 1131 u16 rx_cfo_tail[4]; 1132 1133 struct rt_smooth_data ui_rssi; 1134 struct rt_smooth_data ui_link_quality; 1135 }; 1136 1137 struct rate_adaptive { 1138 u8 rate_adaptive_disabled; 1139 u8 ratr_state; 1140 u16 reserve; 1141 1142 u32 high_rssi_thresh_for_ra; 1143 u32 high2low_rssi_thresh_for_ra; 1144 u8 low2high_rssi_thresh_for_ra40m; 1145 u32 low_rssi_thresh_for_ra40m; 1146 u8 low2high_rssi_thresh_for_ra20m; 1147 u32 low_rssi_thresh_for_ra20m; 1148 u32 upper_rssi_threshold_ratr; 1149 u32 middleupper_rssi_threshold_ratr; 1150 u32 middle_rssi_threshold_ratr; 1151 u32 middlelow_rssi_threshold_ratr; 1152 u32 low_rssi_threshold_ratr; 1153 u32 ultralow_rssi_threshold_ratr; 1154 u32 low_rssi_threshold_ratr_40m; 1155 u32 low_rssi_threshold_ratr_20m; 1156 u8 ping_rssi_enable; 1157 u32 ping_rssi_ratr; 1158 u32 ping_rssi_thresh_for_ra; 1159 u32 last_ratr; 1160 u8 pre_ratr_state; 1161 u8 ldpc_thres; 1162 bool use_ldpc; 1163 bool lower_rts_rate; 1164 bool is_special_data; 1165 }; 1166 1167 struct regd_pair_mapping { 1168 u16 reg_dmnenum; 1169 u16 reg_5ghz_ctl; 1170 u16 reg_2ghz_ctl; 1171 }; 1172 1173 struct dynamic_primary_cca { 1174 u8 pricca_flag; 1175 u8 intf_flag; 1176 u8 intf_type; 1177 u8 dup_rts_flag; 1178 u8 monitor_flag; 1179 u8 ch_offset; 1180 u8 mf_state; 1181 }; 1182 1183 struct rtl_regulatory { 1184 s8 alpha2[2]; 1185 u16 country_code; 1186 u16 max_power_level; 1187 u32 tp_scale; 1188 u16 current_rd; 1189 u16 current_rd_ext; 1190 int16_t power_limit; 1191 struct regd_pair_mapping *regpair; 1192 }; 1193 1194 struct rtl_rfkill { 1195 bool rfkill_state; /*0 is off, 1 is on */ 1196 }; 1197 1198 /*for P2P PS**/ 1199 #define P2P_MAX_NOA_NUM 2 1200 1201 enum p2p_role { 1202 P2P_ROLE_DISABLE = 0, 1203 P2P_ROLE_DEVICE = 1, 1204 P2P_ROLE_CLIENT = 2, 1205 P2P_ROLE_GO = 3 1206 }; 1207 1208 enum p2p_ps_state { 1209 P2P_PS_DISABLE = 0, 1210 P2P_PS_ENABLE = 1, 1211 P2P_PS_SCAN = 2, 1212 P2P_PS_SCAN_DONE = 3, 1213 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1214 }; 1215 1216 enum p2p_ps_mode { 1217 P2P_PS_NONE = 0, 1218 P2P_PS_CTWINDOW = 1, 1219 P2P_PS_NOA = 2, 1220 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1221 }; 1222 1223 struct rtl_p2p_ps_info { 1224 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1225 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1226 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1227 /* Client traffic window. A period of time in TU after TBTT. */ 1228 u8 ctwindow; 1229 u8 opp_ps; /* opportunistic power save. */ 1230 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1231 /* Count for owner, Type of client. */ 1232 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1233 /* Max duration for owner, preferred or min acceptable duration 1234 * for client. 1235 */ 1236 u32 noa_duration[P2P_MAX_NOA_NUM]; 1237 /* Length of interval for owner, preferred or max acceptable intervali 1238 * of client. 1239 */ 1240 u32 noa_interval[P2P_MAX_NOA_NUM]; 1241 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1242 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1243 }; 1244 1245 struct p2p_ps_offload_t { 1246 u8 offload_en:1; 1247 u8 role:1; /* 1: Owner, 0: Client */ 1248 u8 ctwindow_en:1; 1249 u8 noa0_en:1; 1250 u8 noa1_en:1; 1251 u8 allstasleep:1; 1252 u8 discovery:1; 1253 u8 reserved:1; 1254 }; 1255 1256 #define IQK_MATRIX_REG_NUM 8 1257 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1258 1259 struct iqk_matrix_regs { 1260 bool iqk_done; 1261 long value[1][IQK_MATRIX_REG_NUM]; 1262 }; 1263 1264 struct phy_parameters { 1265 u16 length; 1266 u32 *pdata; 1267 }; 1268 1269 enum hw_param_tab_index { 1270 PHY_REG_2T, 1271 PHY_REG_1T, 1272 PHY_REG_PG, 1273 RADIOA_2T, 1274 RADIOB_2T, 1275 RADIOA_1T, 1276 RADIOB_1T, 1277 MAC_REG, 1278 AGCTAB_2T, 1279 AGCTAB_1T, 1280 MAX_TAB 1281 }; 1282 1283 struct rtl_phy { 1284 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1285 struct init_gain initgain_backup; 1286 enum io_type current_io_type; 1287 1288 u8 rf_mode; 1289 u8 rf_type; 1290 u8 current_chan_bw; 1291 u8 set_bwmode_inprogress; 1292 u8 sw_chnl_inprogress; 1293 u8 sw_chnl_stage; 1294 u8 sw_chnl_step; 1295 u8 current_channel; 1296 u8 h2c_box_num; 1297 u8 set_io_inprogress; 1298 u8 lck_inprogress; 1299 1300 /* record for power tracking */ 1301 s32 reg_e94; 1302 s32 reg_e9c; 1303 s32 reg_ea4; 1304 s32 reg_eac; 1305 s32 reg_eb4; 1306 s32 reg_ebc; 1307 s32 reg_ec4; 1308 s32 reg_ecc; 1309 u8 rfpienable; 1310 u8 reserve_0; 1311 u16 reserve_1; 1312 u32 reg_c04, reg_c08, reg_874; 1313 u32 adda_backup[16]; 1314 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1315 u32 iqk_bb_backup[10]; 1316 bool iqk_initialized; 1317 1318 bool rfpath_rx_enable[MAX_RF_PATH]; 1319 u8 reg_837; 1320 /* Dual mac */ 1321 bool need_iqk; 1322 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1323 1324 bool rfpi_enable; 1325 bool iqk_in_progress; 1326 1327 u8 pwrgroup_cnt; 1328 u8 cck_high_power; 1329 /* this is for 88E & 8723A */ 1330 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1331 /* MAX_PG_GROUP groups of pwr diff by rates */ 1332 u32 mcs_offset[MAX_PG_GROUP][16]; 1333 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1334 [TX_PWR_BY_RATE_NUM_RF] 1335 [TX_PWR_BY_RATE_NUM_RF] 1336 [TX_PWR_BY_RATE_NUM_RATE]; 1337 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1338 [TX_PWR_BY_RATE_NUM_RF] 1339 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1340 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1341 [TX_PWR_BY_RATE_NUM_RF] 1342 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1343 u8 default_initialgain[4]; 1344 1345 /* the current Tx power level */ 1346 u8 cur_cck_txpwridx; 1347 u8 cur_ofdm24g_txpwridx; 1348 u8 cur_bw20_txpwridx; 1349 u8 cur_bw40_txpwridx; 1350 1351 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1352 [MAX_2_4G_BANDWIDTH_NUM] 1353 [MAX_RATE_SECTION_NUM] 1354 [CHANNEL_MAX_NUMBER_2G] 1355 [MAX_RF_PATH_NUM]; 1356 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1357 [MAX_5G_BANDWIDTH_NUM] 1358 [MAX_RATE_SECTION_NUM] 1359 [CHANNEL_MAX_NUMBER_5G] 1360 [MAX_RF_PATH_NUM]; 1361 1362 u32 rfreg_chnlval[2]; 1363 bool apk_done; 1364 u32 reg_rf3c[2]; /* pathA / pathB */ 1365 1366 u32 backup_rf_0x1a;/*92ee*/ 1367 /* bfsync */ 1368 u8 framesync; 1369 u32 framesync_c34; 1370 1371 u8 num_total_rfpath; 1372 struct phy_parameters hwparam_tables[MAX_TAB]; 1373 u16 rf_pathmap; 1374 1375 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1376 enum rt_polarity_ctl polarity_ctl; 1377 }; 1378 1379 #define MAX_TID_COUNT 9 1380 #define RTL_AGG_STOP 0 1381 #define RTL_AGG_PROGRESS 1 1382 #define RTL_AGG_START 2 1383 #define RTL_AGG_OPERATIONAL 3 1384 #define RTL_AGG_OFF 0 1385 #define RTL_AGG_ON 1 1386 #define RTL_RX_AGG_START 1 1387 #define RTL_RX_AGG_STOP 0 1388 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1389 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1390 1391 struct rtl_ht_agg { 1392 u16 txq_id; 1393 u16 wait_for_ba; 1394 u16 start_idx; 1395 u64 bitmap; 1396 u32 rate_n_flags; 1397 u8 agg_state; 1398 u8 rx_agg_state; 1399 }; 1400 1401 struct rssi_sta { 1402 long undec_sm_pwdb; 1403 long undec_sm_cck; 1404 }; 1405 1406 struct rtl_tid_data { 1407 struct rtl_ht_agg agg; 1408 }; 1409 1410 struct rtl_sta_info { 1411 struct list_head list; 1412 struct rtl_tid_data tids[MAX_TID_COUNT]; 1413 /* just used for ap adhoc or mesh*/ 1414 struct rssi_sta rssi_stat; 1415 u8 rssi_level; 1416 u16 wireless_mode; 1417 u8 ratr_index; 1418 u8 mimo_ps; 1419 u8 mac_addr[ETH_ALEN]; 1420 } __packed; 1421 1422 struct rtl_priv; 1423 struct rtl_io { 1424 struct device *dev; 1425 struct mutex bb_mutex; 1426 1427 /*PCI MEM map */ 1428 unsigned long pci_mem_end; /*shared mem end */ 1429 unsigned long pci_mem_start; /*shared mem start */ 1430 1431 /*PCI IO map */ 1432 unsigned long pci_base_addr; /*device I/O address */ 1433 1434 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1435 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1436 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1437 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1438 u16 len); 1439 1440 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1441 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1442 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1443 1444 }; 1445 1446 struct rtl_mac { 1447 u8 mac_addr[ETH_ALEN]; 1448 u8 mac80211_registered; 1449 u8 beacon_enabled; 1450 1451 u32 tx_ss_num; 1452 u32 rx_ss_num; 1453 1454 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1455 struct ieee80211_hw *hw; 1456 struct ieee80211_vif *vif; 1457 enum nl80211_iftype opmode; 1458 1459 /*Probe Beacon management */ 1460 struct rtl_tid_data tids[MAX_TID_COUNT]; 1461 enum rtl_link_state link_state; 1462 1463 int n_channels; 1464 int n_bitrates; 1465 1466 bool offchan_delay; 1467 u8 p2p; /*using p2p role*/ 1468 bool p2p_in_use; 1469 1470 /*filters */ 1471 u32 rx_conf; 1472 u16 rx_mgt_filter; 1473 u16 rx_ctrl_filter; 1474 u16 rx_data_filter; 1475 1476 bool act_scanning; 1477 u8 cnt_after_linked; 1478 bool skip_scan; 1479 1480 /* early mode */ 1481 /* skb wait queue */ 1482 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1483 1484 u8 ht_stbc_cap; 1485 u8 ht_cur_stbc; 1486 1487 /*vht support*/ 1488 u8 vht_enable; 1489 u8 bw_80; 1490 u8 vht_cur_ldpc; 1491 u8 vht_cur_stbc; 1492 u8 vht_stbc_cap; 1493 u8 vht_ldpc_cap; 1494 1495 /*RDG*/ 1496 bool rdg_en; 1497 1498 /*AP*/ 1499 u8 bssid[ETH_ALEN] __aligned(2); 1500 u32 vendor; 1501 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1502 u32 basic_rates; /* b/g rates */ 1503 u8 ht_enable; 1504 u8 sgi_40; 1505 u8 sgi_20; 1506 u8 bw_40; 1507 u16 mode; /* wireless mode */ 1508 u8 slot_time; 1509 u8 short_preamble; 1510 u8 use_cts_protect; 1511 u8 cur_40_prime_sc; 1512 u8 cur_40_prime_sc_bk; 1513 u8 cur_80_prime_sc; 1514 u64 tsf; 1515 u8 retry_short; 1516 u8 retry_long; 1517 u16 assoc_id; 1518 bool hiddenssid; 1519 1520 /*IBSS*/ 1521 int beacon_interval; 1522 1523 /*AMPDU*/ 1524 u8 min_space_cfg; /*For Min spacing configurations */ 1525 u8 max_mss_density; 1526 u8 current_ampdu_factor; 1527 u8 current_ampdu_density; 1528 1529 /*QOS & EDCA */ 1530 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1531 struct rtl_qos_parameters ac[AC_MAX]; 1532 1533 /* counters */ 1534 u64 last_txok_cnt; 1535 u64 last_rxok_cnt; 1536 u32 last_bt_edca_ul; 1537 u32 last_bt_edca_dl; 1538 }; 1539 1540 struct btdm_8723 { 1541 bool all_off; 1542 bool agc_table_en; 1543 bool adc_back_off_on; 1544 bool b2_ant_hid_en; 1545 bool low_penalty_rate_adaptive; 1546 bool rf_rx_lpf_shrink; 1547 bool reject_aggre_pkt; 1548 bool tra_tdma_on; 1549 u8 tra_tdma_nav; 1550 u8 tra_tdma_ant; 1551 bool tdma_on; 1552 u8 tdma_ant; 1553 u8 tdma_nav; 1554 u8 tdma_dac_swing; 1555 u8 fw_dac_swing_lvl; 1556 bool ps_tdma_on; 1557 u8 ps_tdma_byte[5]; 1558 bool pta_on; 1559 u32 val_0x6c0; 1560 u32 val_0x6c8; 1561 u32 val_0x6cc; 1562 bool sw_dac_swing_on; 1563 u32 sw_dac_swing_lvl; 1564 u32 wlan_act_hi; 1565 u32 wlan_act_lo; 1566 u32 bt_retry_index; 1567 bool dec_bt_pwr; 1568 bool ignore_wlan_act; 1569 }; 1570 1571 struct bt_coexist_8723 { 1572 u32 high_priority_tx; 1573 u32 high_priority_rx; 1574 u32 low_priority_tx; 1575 u32 low_priority_rx; 1576 u8 c2h_bt_info; 1577 bool c2h_bt_info_req_sent; 1578 bool c2h_bt_inquiry_page; 1579 u32 bt_inq_page_start_time; 1580 u8 bt_retry_cnt; 1581 u8 c2h_bt_info_original; 1582 u8 bt_inquiry_page_cnt; 1583 struct btdm_8723 btdm; 1584 }; 1585 1586 struct rtl_hal { 1587 struct ieee80211_hw *hw; 1588 bool driver_is_goingto_unload; 1589 bool up_first_time; 1590 bool first_init; 1591 bool being_init_adapter; 1592 bool bbrf_ready; 1593 bool mac_func_enable; 1594 bool pre_edcca_enable; 1595 struct bt_coexist_8723 hal_coex_8723; 1596 1597 enum intf_type interface; 1598 u16 hw_type; /*92c or 92d or 92s and so on */ 1599 u8 ic_class; 1600 u8 oem_id; 1601 u32 version; /*version of chip */ 1602 u8 state; /*stop 0, start 1 */ 1603 u8 board_type; 1604 u8 package_type; 1605 u8 external_pa; 1606 1607 u8 pa_mode; 1608 u8 pa_type_2g; 1609 u8 pa_type_5g; 1610 u8 lna_type_2g; 1611 u8 lna_type_5g; 1612 u8 external_pa_2g; 1613 u8 external_lna_2g; 1614 u8 external_pa_5g; 1615 u8 external_lna_5g; 1616 u8 type_glna; 1617 u8 type_gpa; 1618 u8 type_alna; 1619 u8 type_apa; 1620 u8 rfe_type; 1621 1622 /*firmware */ 1623 u32 fwsize; 1624 u8 *pfirmware; 1625 u16 fw_version; 1626 u16 fw_subversion; 1627 bool h2c_setinprogress; 1628 u8 last_hmeboxnum; 1629 bool fw_ready; 1630 /*Reserve page start offset except beacon in TxQ. */ 1631 u8 fw_rsvdpage_startoffset; 1632 u8 h2c_txcmd_seq; 1633 u8 current_ra_rate; 1634 1635 /* FW Cmd IO related */ 1636 u16 fwcmd_iomap; 1637 u32 fwcmd_ioparam; 1638 bool set_fwcmd_inprogress; 1639 u8 current_fwcmd_io; 1640 1641 struct p2p_ps_offload_t p2p_ps_offload; 1642 bool fw_clk_change_in_progress; 1643 bool allow_sw_to_change_hwclc; 1644 u8 fw_ps_state; 1645 /**/ 1646 bool driver_going2unload; 1647 1648 /*AMPDU init min space*/ 1649 u8 minspace_cfg; /*For Min spacing configurations */ 1650 1651 /* Dual mac */ 1652 enum macphy_mode macphymode; 1653 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1654 enum band_type current_bandtypebackup; 1655 enum band_type bandset; 1656 /* dual MAC 0--Mac0 1--Mac1 */ 1657 u32 interfaceindex; 1658 /* just for DualMac S3S4 */ 1659 u8 macphyctl_reg; 1660 bool earlymode_enable; 1661 u8 max_earlymode_num; 1662 /* Dual mac*/ 1663 bool during_mac0init_radiob; 1664 bool during_mac1init_radioa; 1665 bool reloadtxpowerindex; 1666 /* True if IMR or IQK have done 1667 for 2.4G in scan progress */ 1668 bool load_imrandiqk_setting_for2g; 1669 1670 bool disable_amsdu_8k; 1671 bool master_of_dmsp; 1672 bool slave_of_dmsp; 1673 1674 u16 rx_tag;/*for 92ee*/ 1675 u8 rts_en; 1676 1677 /*for wowlan*/ 1678 bool wow_enable; 1679 bool enter_pnp_sleep; 1680 bool wake_from_pnp_sleep; 1681 bool wow_enabled; 1682 time64_t last_suspend_sec; 1683 u32 wowlan_fwsize; 1684 u8 *wowlan_firmware; 1685 1686 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1687 1688 bool real_wow_v2_enable; 1689 bool re_init_llt_table; 1690 }; 1691 1692 struct rtl_security { 1693 /*default 0 */ 1694 bool use_sw_sec; 1695 1696 bool being_setkey; 1697 bool use_defaultkey; 1698 /*Encryption Algorithm for Unicast Packet */ 1699 enum rt_enc_alg pairwise_enc_algorithm; 1700 /*Encryption Algorithm for Brocast/Multicast */ 1701 enum rt_enc_alg group_enc_algorithm; 1702 /*Cam Entry Bitmap */ 1703 u32 hwsec_cam_bitmap; 1704 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1705 /*local Key buffer, indx 0 is for 1706 pairwise key 1-4 is for agoup key. */ 1707 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1708 u8 key_len[KEY_BUF_SIZE]; 1709 1710 /*The pointer of Pairwise Key, 1711 it always points to KeyBuf[4] */ 1712 u8 *pairwise_key; 1713 }; 1714 1715 #define ASSOCIATE_ENTRY_NUM 33 1716 1717 struct fast_ant_training { 1718 u8 bssid[6]; 1719 u8 antsel_rx_keep_0; 1720 u8 antsel_rx_keep_1; 1721 u8 antsel_rx_keep_2; 1722 u32 ant_sum[7]; 1723 u32 ant_cnt[7]; 1724 u32 ant_ave[7]; 1725 u8 fat_state; 1726 u32 train_idx; 1727 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1728 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1729 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1730 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1731 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1732 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1733 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1734 u8 rx_idle_ant; 1735 bool becomelinked; 1736 }; 1737 1738 struct dm_phy_dbg_info { 1739 s8 rx_snrdb[4]; 1740 u64 num_qry_phy_status; 1741 u64 num_qry_phy_status_cck; 1742 u64 num_qry_phy_status_ofdm; 1743 u16 num_qry_beacon_pkt; 1744 u16 num_non_be_pkt; 1745 s32 rx_evm[4]; 1746 }; 1747 1748 struct rtl_dm { 1749 /*PHY status for Dynamic Management */ 1750 long entry_min_undec_sm_pwdb; 1751 long undec_sm_cck; 1752 long undec_sm_pwdb; /*out dm */ 1753 long entry_max_undec_sm_pwdb; 1754 s32 ofdm_pkt_cnt; 1755 bool dm_initialgain_enable; 1756 bool dynamic_txpower_enable; 1757 bool current_turbo_edca; 1758 bool is_any_nonbepkts; /*out dm */ 1759 bool is_cur_rdlstate; 1760 bool txpower_trackinginit; 1761 bool disable_framebursting; 1762 bool cck_inch14; 1763 bool txpower_tracking; 1764 bool useramask; 1765 bool rfpath_rxenable[4]; 1766 bool inform_fw_driverctrldm; 1767 bool current_mrc_switch; 1768 u8 txpowercount; 1769 u8 powerindex_backup[6]; 1770 1771 u8 thermalvalue_rxgain; 1772 u8 thermalvalue_iqk; 1773 u8 thermalvalue_lck; 1774 u8 thermalvalue; 1775 u8 last_dtp_lvl; 1776 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1777 u8 thermalvalue_avg_index; 1778 u8 tm_trigger; 1779 bool done_txpower; 1780 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1781 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1782 u8 dm_flag_tmp; 1783 u8 dm_type; 1784 u8 dm_rssi_sel; 1785 u8 txpower_track_control; 1786 bool interrupt_migration; 1787 bool disable_tx_int; 1788 s8 ofdm_index[MAX_RF_PATH]; 1789 u8 default_ofdm_index; 1790 u8 default_cck_index; 1791 s8 cck_index; 1792 s8 delta_power_index[MAX_RF_PATH]; 1793 s8 delta_power_index_last[MAX_RF_PATH]; 1794 s8 power_index_offset[MAX_RF_PATH]; 1795 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1796 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1797 s8 remnant_cck_idx; 1798 bool modify_txagc_flag_path_a; 1799 bool modify_txagc_flag_path_b; 1800 1801 bool one_entry_only; 1802 struct dm_phy_dbg_info dbginfo; 1803 1804 /* Dynamic ATC switch */ 1805 bool atc_status; 1806 bool large_cfo_hit; 1807 bool is_freeze; 1808 int cfo_tail[2]; 1809 int cfo_ave_pre; 1810 int crystal_cap; 1811 u8 cfo_threshold; 1812 u32 packet_count; 1813 u32 packet_count_pre; 1814 u8 tx_rate; 1815 1816 /*88e tx power tracking*/ 1817 u8 swing_idx_ofdm[MAX_RF_PATH]; 1818 u8 swing_idx_ofdm_cur; 1819 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1820 bool swing_flag_ofdm; 1821 u8 swing_idx_cck; 1822 u8 swing_idx_cck_cur; 1823 u8 swing_idx_cck_base; 1824 bool swing_flag_cck; 1825 1826 s8 swing_diff_2g; 1827 s8 swing_diff_5g; 1828 1829 /* DMSP */ 1830 bool supp_phymode_switch; 1831 1832 /* DulMac */ 1833 struct fast_ant_training fat_table; 1834 1835 u8 resp_tx_path; 1836 u8 path_sel; 1837 u32 patha_sum; 1838 u32 pathb_sum; 1839 u32 patha_cnt; 1840 u32 pathb_cnt; 1841 1842 u8 pre_channel; 1843 u8 *p_channel; 1844 u8 linked_interval; 1845 1846 u64 last_tx_ok_cnt; 1847 u64 last_rx_ok_cnt; 1848 }; 1849 1850 #define EFUSE_MAX_LOGICAL_SIZE 512 1851 1852 struct rtl_efuse { 1853 const struct rtl_efuse_ops *efuse_ops; 1854 bool autoLoad_ok; 1855 bool bootfromefuse; 1856 u16 max_physical_size; 1857 1858 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1859 u16 efuse_usedbytes; 1860 u8 efuse_usedpercentage; 1861 #ifdef EFUSE_REPG_WORKAROUND 1862 bool efuse_re_pg_sec1flag; 1863 u8 efuse_re_pg_data[8]; 1864 #endif 1865 1866 u8 autoload_failflag; 1867 u8 autoload_status; 1868 1869 short epromtype; 1870 u16 eeprom_vid; 1871 u16 eeprom_did; 1872 u16 eeprom_svid; 1873 u16 eeprom_smid; 1874 u8 eeprom_oemid; 1875 u16 eeprom_channelplan; 1876 u8 eeprom_version; 1877 u8 board_type; 1878 u8 external_pa; 1879 1880 u8 dev_addr[6]; 1881 u8 wowlan_enable; 1882 u8 antenna_div_cfg; 1883 u8 antenna_div_type; 1884 1885 bool txpwr_fromeprom; 1886 u8 eeprom_crystalcap; 1887 u8 eeprom_tssi[2]; 1888 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1889 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1890 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1891 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1892 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1893 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1894 1895 u8 internal_pa_5g[2]; /* pathA / pathB */ 1896 u8 eeprom_c9; 1897 u8 eeprom_cc; 1898 1899 /*For power group */ 1900 u8 eeprom_pwrgroup[2][3]; 1901 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1902 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1903 1904 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1905 /*For HT 40MHZ pwr */ 1906 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1907 /*For HT 40MHZ pwr */ 1908 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1909 1910 /*--------------------------------------------------------* 1911 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1912 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1913 * define new arrays in Windows code. 1914 * BUT, in linux code, we use the same array for all ICs. 1915 * 1916 * The Correspondance relation between two arrays is: 1917 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1918 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1919 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1920 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1921 * 1922 * Sizes of these arrays are decided by the larger ones. 1923 */ 1924 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1925 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1926 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1927 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1928 1929 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1930 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1931 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1932 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1933 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1934 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1935 1936 u8 txpwr_safetyflag; /* Band edge enable flag */ 1937 u16 eeprom_txpowerdiff; 1938 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1939 u8 antenna_txpwdiff[3]; 1940 1941 u8 eeprom_regulatory; 1942 u8 eeprom_thermalmeter; 1943 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1944 u16 tssi_13dbm; 1945 u8 crystalcap; /* CrystalCap. */ 1946 u8 delta_iqk; 1947 u8 delta_lck; 1948 1949 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1950 bool apk_thermalmeterignore; 1951 1952 bool b1x1_recvcombine; 1953 bool b1ss_support; 1954 1955 /*channel plan */ 1956 u8 channel_plan; 1957 }; 1958 1959 struct rtl_efuse_ops { 1960 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data); 1961 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type, 1962 u16 offset, u32 *value); 1963 }; 1964 1965 struct rtl_tx_report { 1966 atomic_t sn; 1967 u16 last_sent_sn; 1968 unsigned long last_sent_time; 1969 u16 last_recv_sn; 1970 }; 1971 1972 struct rtl_ps_ctl { 1973 bool pwrdomain_protect; 1974 bool in_powersavemode; 1975 bool rfchange_inprogress; 1976 bool swrf_processing; 1977 bool hwradiooff; 1978 /* 1979 * just for PCIE ASPM 1980 * If it supports ASPM, Offset[560h] = 0x40, 1981 * otherwise Offset[560h] = 0x00. 1982 * */ 1983 bool support_aspm; 1984 bool support_backdoor; 1985 1986 /*for LPS */ 1987 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1988 bool swctrl_lps; 1989 bool leisure_ps; 1990 bool fwctrl_lps; 1991 u8 fwctrl_psmode; 1992 /*For Fw control LPS mode */ 1993 u8 reg_fwctrl_lps; 1994 /*Record Fw PS mode status. */ 1995 bool fw_current_inpsmode; 1996 u8 reg_max_lps_awakeintvl; 1997 bool report_linked; 1998 bool low_power_enable;/*for 32k*/ 1999 2000 /*for IPS */ 2001 bool inactiveps; 2002 2003 u32 rfoff_reason; 2004 2005 /*RF OFF Level */ 2006 u32 cur_ps_level; 2007 u32 reg_rfps_level; 2008 2009 /*just for PCIE ASPM */ 2010 u8 const_amdpci_aspm; 2011 bool pwrdown_mode; 2012 2013 enum rf_pwrstate inactive_pwrstate; 2014 enum rf_pwrstate rfpwr_state; /*cur power state */ 2015 2016 /* for SW LPS*/ 2017 bool sw_ps_enabled; 2018 bool state; 2019 bool state_inap; 2020 bool multi_buffered; 2021 u16 nullfunc_seq; 2022 unsigned int dtim_counter; 2023 unsigned int sleep_ms; 2024 unsigned long last_sleep_jiffies; 2025 unsigned long last_awake_jiffies; 2026 unsigned long last_delaylps_stamp_jiffies; 2027 unsigned long last_dtim; 2028 unsigned long last_beacon; 2029 unsigned long last_action; 2030 unsigned long last_slept; 2031 2032 /*For P2P PS */ 2033 struct rtl_p2p_ps_info p2p_ps_info; 2034 u8 pwr_mode; 2035 u8 smart_ps; 2036 2037 /* wake up on line */ 2038 u8 wo_wlan_mode; 2039 u8 arp_offload_enable; 2040 u8 gtk_offload_enable; 2041 /* Used for WOL, indicates the reason for waking event.*/ 2042 u32 wakeup_reason; 2043 }; 2044 2045 struct rtl_stats { 2046 u8 psaddr[ETH_ALEN]; 2047 u32 mac_time[2]; 2048 s8 rssi; 2049 u8 signal; 2050 u8 noise; 2051 u8 rate; /* hw desc rate */ 2052 u8 received_channel; 2053 u8 control; 2054 u8 mask; 2055 u8 freq; 2056 u16 len; 2057 u64 tsf; 2058 u32 beacon_time; 2059 u8 nic_type; 2060 u16 length; 2061 u8 signalquality; /*in 0-100 index. */ 2062 /* 2063 * Real power in dBm for this packet, 2064 * no beautification and aggregation. 2065 * */ 2066 s32 recvsignalpower; 2067 s8 rxpower; /*in dBm Translate from PWdB */ 2068 u8 signalstrength; /*in 0-100 index. */ 2069 u16 hwerror:1; 2070 u16 crc:1; 2071 u16 icv:1; 2072 u16 shortpreamble:1; 2073 u16 antenna:1; 2074 u16 decrypted:1; 2075 u16 wakeup:1; 2076 u32 timestamp_low; 2077 u32 timestamp_high; 2078 bool shift; 2079 2080 u8 rx_drvinfo_size; 2081 u8 rx_bufshift; 2082 bool isampdu; 2083 bool isfirst_ampdu; 2084 bool rx_is40Mhzpacket; 2085 u8 rx_packet_bw; 2086 u32 rx_pwdb_all; 2087 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2088 s8 rx_mimo_signalquality[4]; 2089 u8 rx_mimo_evm_dbm[4]; 2090 u16 cfo_short[4]; /* per-path's Cfo_short */ 2091 u16 cfo_tail[4]; 2092 2093 s8 rx_mimo_sig_qual[4]; 2094 u8 rx_pwr[4]; /* per-path's pwdb */ 2095 u8 rx_snr[4]; /* per-path's SNR */ 2096 u8 bandwidth; 2097 u8 bt_coex_pwr_adjust; 2098 bool packet_matchbssid; 2099 bool is_cck; 2100 bool is_ht; 2101 bool packet_toself; 2102 bool packet_beacon; /*for rssi */ 2103 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2104 2105 bool is_vht; 2106 bool is_short_gi; 2107 u8 vht_nss; 2108 2109 u8 packet_report_type; 2110 2111 u32 macid; 2112 u8 wake_match; 2113 u32 bt_rx_rssi_percentage; 2114 u32 macid_valid_entry[2]; 2115 }; 2116 2117 2118 struct rt_link_detect { 2119 /* count for roaming */ 2120 u32 bcn_rx_inperiod; 2121 u32 roam_times; 2122 2123 u32 num_tx_in4period[4]; 2124 u32 num_rx_in4period[4]; 2125 2126 u32 num_tx_inperiod; 2127 u32 num_rx_inperiod; 2128 2129 bool busytraffic; 2130 bool tx_busy_traffic; 2131 bool rx_busy_traffic; 2132 bool higher_busytraffic; 2133 bool higher_busyrxtraffic; 2134 2135 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2136 u32 tidtx_inperiod[MAX_TID_COUNT]; 2137 bool higher_busytxtraffic[MAX_TID_COUNT]; 2138 }; 2139 2140 struct rtl_tcb_desc { 2141 u8 packet_bw:2; 2142 u8 multicast:1; 2143 u8 broadcast:1; 2144 2145 u8 rts_stbc:1; 2146 u8 rts_enable:1; 2147 u8 cts_enable:1; 2148 u8 rts_use_shortpreamble:1; 2149 u8 rts_use_shortgi:1; 2150 u8 rts_sc:1; 2151 u8 rts_bw:1; 2152 u8 rts_rate; 2153 2154 u8 use_shortgi:1; 2155 u8 use_shortpreamble:1; 2156 u8 use_driver_rate:1; 2157 u8 disable_ratefallback:1; 2158 2159 u8 use_spe_rpt:1; 2160 2161 u8 ratr_index; 2162 u8 mac_id; 2163 u8 hw_rate; 2164 2165 u8 last_inipkt:1; 2166 u8 cmd_or_init:1; 2167 u8 queue_index; 2168 2169 /* early mode */ 2170 u8 empkt_num; 2171 /* The max value by HW */ 2172 u32 empkt_len[10]; 2173 bool tx_enable_sw_calc_duration; 2174 }; 2175 2176 struct rtl_wow_pattern { 2177 u8 type; 2178 u16 crc; 2179 u32 mask[4]; 2180 }; 2181 2182 /* struct to store contents of interrupt vectors */ 2183 struct rtl_int { 2184 u32 inta; 2185 u32 intb; 2186 u32 intc; 2187 u32 intd; 2188 }; 2189 2190 struct rtl_hal_ops { 2191 int (*init_sw_vars) (struct ieee80211_hw *hw); 2192 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2193 void (*read_chip_version)(struct ieee80211_hw *hw); 2194 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2195 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2196 struct rtl_int *intvec); 2197 int (*hw_init) (struct ieee80211_hw *hw); 2198 void (*hw_disable) (struct ieee80211_hw *hw); 2199 void (*hw_suspend) (struct ieee80211_hw *hw); 2200 void (*hw_resume) (struct ieee80211_hw *hw); 2201 void (*enable_interrupt) (struct ieee80211_hw *hw); 2202 void (*disable_interrupt) (struct ieee80211_hw *hw); 2203 int (*set_network_type) (struct ieee80211_hw *hw, 2204 enum nl80211_iftype type); 2205 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2206 bool check_bssid); 2207 void (*set_bw_mode) (struct ieee80211_hw *hw, 2208 enum nl80211_channel_type ch_type); 2209 u8(*switch_channel) (struct ieee80211_hw *hw); 2210 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2211 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2212 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2213 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2214 u32 add_msr, u32 rm_msr); 2215 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2216 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2217 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2218 struct ieee80211_sta *sta, u8 rssi_leve, 2219 bool update_bw); 2220 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2221 u8 *desc, u8 queue_index, 2222 struct sk_buff *skb, dma_addr_t addr); 2223 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2224 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2225 u8 queue_index); 2226 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2227 u8 queue_index); 2228 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2229 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2230 u8 *pbd_desc_tx, 2231 struct ieee80211_tx_info *info, 2232 struct ieee80211_sta *sta, 2233 struct sk_buff *skb, u8 hw_queue, 2234 struct rtl_tcb_desc *ptcb_desc); 2235 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2236 u32 buffer_len, bool bIsPsPoll); 2237 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2238 bool firstseg, bool lastseg, 2239 struct sk_buff *skb); 2240 void (*fill_tx_special_desc)(struct ieee80211_hw *hw, 2241 u8 *pdesc, u8 *pbd_desc, 2242 struct sk_buff *skb, u8 hw_queue); 2243 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2244 struct rtl_stats *stats, 2245 struct ieee80211_rx_status *rx_status, 2246 u8 *pdesc, struct sk_buff *skb); 2247 void (*set_channel_access) (struct ieee80211_hw *hw); 2248 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2249 void (*dm_watchdog) (struct ieee80211_hw *hw); 2250 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2251 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2252 enum rf_pwrstate rfpwr_state); 2253 void (*led_control) (struct ieee80211_hw *hw, 2254 enum led_ctl_mode ledaction); 2255 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2256 u8 desc_name, u8 *val); 2257 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2258 u8 desc_name); 2259 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2260 u8 hw_queue, u16 index); 2261 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2262 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2263 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2264 u8 *macaddr, bool is_group, u8 enc_algo, 2265 bool is_wepkey, bool clear_all); 2266 void (*init_sw_leds) (struct ieee80211_hw *hw); 2267 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2268 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2269 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2270 u32 data); 2271 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2272 u32 regaddr, u32 bitmask); 2273 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2274 u32 regaddr, u32 bitmask, u32 data); 2275 void (*linked_set_reg) (struct ieee80211_hw *hw); 2276 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2277 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2278 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2279 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2280 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2281 u8 *powerlevel); 2282 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2283 u8 *ppowerlevel, u8 channel); 2284 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2285 u8 configtype); 2286 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2287 u8 configtype); 2288 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2289 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2290 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2291 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2292 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2293 bool mstate); 2294 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2295 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2296 u32 cmd_len, u8 *p_cmdbuffer); 2297 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw); 2298 bool (*get_btc_status) (void); 2299 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2300 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2301 const struct rtl_stats *status, struct sk_buff *skb); 2302 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2303 struct rtl_wow_pattern *rtl_pattern, 2304 u8 index); 2305 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2306 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len, 2307 u8 *val); 2308 }; 2309 2310 struct rtl_intf_ops { 2311 /*com */ 2312 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2313 int (*adapter_start) (struct ieee80211_hw *hw); 2314 void (*adapter_stop) (struct ieee80211_hw *hw); 2315 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2316 struct rtl_priv **buddy_priv); 2317 2318 int (*adapter_tx) (struct ieee80211_hw *hw, 2319 struct ieee80211_sta *sta, 2320 struct sk_buff *skb, 2321 struct rtl_tcb_desc *ptcb_desc); 2322 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2323 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2324 bool (*waitq_insert) (struct ieee80211_hw *hw, 2325 struct ieee80211_sta *sta, 2326 struct sk_buff *skb); 2327 2328 /*pci */ 2329 void (*disable_aspm) (struct ieee80211_hw *hw); 2330 void (*enable_aspm) (struct ieee80211_hw *hw); 2331 2332 /*usb */ 2333 }; 2334 2335 struct rtl_mod_params { 2336 /* default: 0,0 */ 2337 u64 debug_mask; 2338 /* default: 0 = using hardware encryption */ 2339 bool sw_crypto; 2340 2341 /* default: 0 = DBG_EMERG (0)*/ 2342 int debug_level; 2343 2344 /* default: 1 = using no linked power save */ 2345 bool inactiveps; 2346 2347 /* default: 1 = using linked sw power save */ 2348 bool swctrl_lps; 2349 2350 /* default: 1 = using linked fw power save */ 2351 bool fwctrl_lps; 2352 2353 /* default: 0 = not using MSI interrupts mode 2354 * submodules should set their own default value 2355 */ 2356 bool msi_support; 2357 2358 /* default: 0 = dma 32 */ 2359 bool dma64; 2360 2361 /* default: 1 = enable aspm */ 2362 int aspm_support; 2363 2364 /* default 0: 1 means disable */ 2365 bool disable_watchdog; 2366 2367 /* default 0: 1 means do not disable interrupts */ 2368 bool int_clear; 2369 2370 /* select antenna */ 2371 int ant_sel; 2372 }; 2373 2374 struct rtl_hal_usbint_cfg { 2375 /* data - rx */ 2376 u32 in_ep_num; 2377 u32 rx_urb_num; 2378 u32 rx_max_size; 2379 2380 /* op - rx */ 2381 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2382 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2383 struct sk_buff_head *); 2384 2385 /* tx */ 2386 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2387 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2388 struct sk_buff *); 2389 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2390 struct sk_buff_head *); 2391 2392 /* endpoint mapping */ 2393 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2394 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2395 }; 2396 2397 struct rtl_hal_cfg { 2398 u8 bar_id; 2399 bool write_readback; 2400 char *name; 2401 char *alt_fw_name; 2402 struct rtl_hal_ops *ops; 2403 struct rtl_mod_params *mod_params; 2404 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2405 enum rtl_spec_ver spec_ver; 2406 2407 /*this map used for some registers or vars 2408 defined int HAL but used in MAIN */ 2409 u32 maps[RTL_VAR_MAP_MAX]; 2410 2411 }; 2412 2413 struct rtl_locks { 2414 /* mutex */ 2415 struct mutex conf_mutex; 2416 struct mutex ips_mutex; /* mutex for enter/leave IPS */ 2417 struct mutex lps_mutex; /* mutex for enter/leave LPS */ 2418 2419 /*spin lock */ 2420 spinlock_t irq_th_lock; 2421 spinlock_t h2c_lock; 2422 spinlock_t rf_ps_lock; 2423 spinlock_t rf_lock; 2424 spinlock_t waitq_lock; 2425 spinlock_t entry_list_lock; 2426 spinlock_t usb_lock; 2427 spinlock_t c2hcmd_lock; 2428 spinlock_t scan_list_lock; /* lock for the scan list */ 2429 2430 /*FW clock change */ 2431 spinlock_t fw_ps_lock; 2432 2433 /*Dual mac*/ 2434 spinlock_t cck_and_rw_pagea_lock; 2435 2436 spinlock_t iqk_lock; 2437 }; 2438 2439 struct rtl_works { 2440 struct ieee80211_hw *hw; 2441 2442 /*timer */ 2443 struct timer_list watchdog_timer; 2444 struct timer_list dualmac_easyconcurrent_retrytimer; 2445 struct timer_list fw_clockoff_timer; 2446 struct timer_list fast_antenna_training_timer; 2447 /*task */ 2448 struct tasklet_struct irq_tasklet; 2449 struct tasklet_struct irq_prepare_bcn_tasklet; 2450 2451 /*work queue */ 2452 struct workqueue_struct *rtl_wq; 2453 struct delayed_work watchdog_wq; 2454 struct delayed_work ips_nic_off_wq; 2455 struct delayed_work c2hcmd_wq; 2456 2457 /* For SW LPS */ 2458 struct delayed_work ps_work; 2459 struct delayed_work ps_rfon_wq; 2460 struct delayed_work fwevt_wq; 2461 2462 struct work_struct lps_change_work; 2463 struct work_struct fill_h2c_cmd; 2464 }; 2465 2466 struct rtl_debug { 2467 /* add for debug */ 2468 struct dentry *debugfs_dir; 2469 char debugfs_name[20]; 2470 }; 2471 2472 #define MIMO_PS_STATIC 0 2473 #define MIMO_PS_DYNAMIC 1 2474 #define MIMO_PS_NOLIMIT 3 2475 2476 struct rtl_dualmac_easy_concurrent_ctl { 2477 enum band_type currentbandtype_backfordmdp; 2478 bool close_bbandrf_for_dmsp; 2479 bool change_to_dmdp; 2480 bool change_to_dmsp; 2481 bool switch_in_process; 2482 }; 2483 2484 struct rtl_dmsp_ctl { 2485 bool activescan_for_slaveofdmsp; 2486 bool scan_for_anothermac_fordmsp; 2487 bool scan_for_itself_fordmsp; 2488 bool writedig_for_anothermacofdmsp; 2489 u32 curdigvalue_for_anothermacofdmsp; 2490 bool changecckpdstate_for_anothermacofdmsp; 2491 u8 curcckpdstate_for_anothermacofdmsp; 2492 bool changetxhighpowerlvl_for_anothermacofdmsp; 2493 u8 curtxhighlvl_for_anothermacofdmsp; 2494 long rssivalmin_for_anothermacofdmsp; 2495 }; 2496 2497 struct ps_t { 2498 u8 pre_ccastate; 2499 u8 cur_ccasate; 2500 u8 pre_rfstate; 2501 u8 cur_rfstate; 2502 u8 initialize; 2503 long rssi_val_min; 2504 }; 2505 2506 struct dig_t { 2507 u32 rssi_lowthresh; 2508 u32 rssi_highthresh; 2509 u32 fa_lowthresh; 2510 u32 fa_highthresh; 2511 long last_min_undec_pwdb_for_dm; 2512 long rssi_highpower_lowthresh; 2513 long rssi_highpower_highthresh; 2514 u32 recover_cnt; 2515 u32 pre_igvalue; 2516 u32 cur_igvalue; 2517 long rssi_val; 2518 u8 dig_enable_flag; 2519 u8 dig_ext_port_stage; 2520 u8 dig_algorithm; 2521 u8 dig_twoport_algorithm; 2522 u8 dig_dbgmode; 2523 u8 dig_slgorithm_switch; 2524 u8 cursta_cstate; 2525 u8 presta_cstate; 2526 u8 curmultista_cstate; 2527 u8 stop_dig; 2528 s8 back_val; 2529 s8 back_range_max; 2530 s8 back_range_min; 2531 u8 rx_gain_max; 2532 u8 rx_gain_min; 2533 u8 min_undec_pwdb_for_dm; 2534 u8 rssi_val_min; 2535 u8 pre_cck_cca_thres; 2536 u8 cur_cck_cca_thres; 2537 u8 pre_cck_pd_state; 2538 u8 cur_cck_pd_state; 2539 u8 pre_cck_fa_state; 2540 u8 cur_cck_fa_state; 2541 u8 pre_ccastate; 2542 u8 cur_ccasate; 2543 u8 large_fa_hit; 2544 u8 forbidden_igi; 2545 u8 dig_state; 2546 u8 dig_highpwrstate; 2547 u8 cur_sta_cstate; 2548 u8 pre_sta_cstate; 2549 u8 cur_ap_cstate; 2550 u8 pre_ap_cstate; 2551 u8 cur_pd_thstate; 2552 u8 pre_pd_thstate; 2553 u8 cur_cs_ratiostate; 2554 u8 pre_cs_ratiostate; 2555 u8 backoff_enable_flag; 2556 s8 backoffval_range_max; 2557 s8 backoffval_range_min; 2558 u8 dig_min_0; 2559 u8 dig_min_1; 2560 u8 bt30_cur_igi; 2561 bool media_connect_0; 2562 bool media_connect_1; 2563 2564 u32 antdiv_rssi_max; 2565 u32 rssi_max; 2566 }; 2567 2568 struct rtl_global_var { 2569 /* from this list we can get 2570 * other adapter's rtl_priv */ 2571 struct list_head glb_priv_list; 2572 spinlock_t glb_list_lock; 2573 }; 2574 2575 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */ 2576 2577 struct rtl_btc_info { 2578 u8 bt_type; 2579 u8 btcoexist; 2580 u8 ant_num; 2581 u8 single_ant_path; 2582 2583 u8 ap_num; 2584 bool in_4way; 2585 unsigned long in_4way_ts; 2586 }; 2587 2588 struct bt_coexist_info { 2589 struct rtl_btc_ops *btc_ops; 2590 struct rtl_btc_info btc_info; 2591 /* btc context */ 2592 void *btc_context; 2593 void *wifi_only_context; 2594 /* EEPROM BT info. */ 2595 u8 eeprom_bt_coexist; 2596 u8 eeprom_bt_type; 2597 u8 eeprom_bt_ant_num; 2598 u8 eeprom_bt_ant_isol; 2599 u8 eeprom_bt_radio_shared; 2600 2601 u8 bt_coexistence; 2602 u8 bt_ant_num; 2603 u8 bt_coexist_type; 2604 u8 bt_state; 2605 u8 bt_cur_state; /* 0:on, 1:off */ 2606 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2607 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2608 u8 bt_service; 2609 u8 bt_radio_shared_type; 2610 u8 bt_rfreg_origin_1e; 2611 u8 bt_rfreg_origin_1f; 2612 u8 bt_rssi_state; 2613 u32 ratio_tx; 2614 u32 ratio_pri; 2615 u32 bt_edca_ul; 2616 u32 bt_edca_dl; 2617 2618 bool init_set; 2619 bool bt_busy_traffic; 2620 bool bt_traffic_mode_set; 2621 bool bt_non_traffic_mode_set; 2622 2623 bool fw_coexist_all_off; 2624 bool sw_coexist_all_off; 2625 bool hw_coexist_all_off; 2626 u32 cstate; 2627 u32 previous_state; 2628 u32 cstate_h; 2629 u32 previous_state_h; 2630 2631 u8 bt_pre_rssi_state; 2632 u8 bt_pre_rssi_state1; 2633 2634 u8 reg_bt_iso; 2635 u8 reg_bt_sco; 2636 bool balance_on; 2637 u8 bt_active_zero_cnt; 2638 bool cur_bt_disabled; 2639 bool pre_bt_disabled; 2640 2641 u8 bt_profile_case; 2642 u8 bt_profile_action; 2643 bool bt_busy; 2644 bool hold_for_bt_operation; 2645 u8 lps_counter; 2646 }; 2647 2648 struct rtl_btc_ops { 2649 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2650 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv); 2651 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv); 2652 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2653 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv); 2654 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2655 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv); 2656 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2657 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2658 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2659 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv, 2660 u8 scantype); 2661 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2662 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2663 enum rt_media_status mstatus); 2664 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2665 void (*btc_halt_notify)(struct rtl_priv *rtlpriv); 2666 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2667 u8 *tmp_buf, u8 length); 2668 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv, 2669 u8 *tmp_buf, u8 length); 2670 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2671 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2672 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2673 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2674 u8 pkt_type); 2675 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type, 2676 bool scanning); 2677 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv, 2678 u8 type, bool scanning); 2679 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv, 2680 struct seq_file *m); 2681 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len); 2682 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv); 2683 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv); 2684 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv); 2685 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg, 2686 u8 *ctrl_agg_size, u8 *agg_size); 2687 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv); 2688 }; 2689 2690 struct proxim { 2691 bool proxim_on; 2692 2693 void *proximity_priv; 2694 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2695 struct sk_buff *skb); 2696 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2697 }; 2698 2699 struct rtl_c2hcmd { 2700 struct list_head list; 2701 u8 tag; 2702 u8 len; 2703 u8 *val; 2704 }; 2705 2706 struct rtl_bssid_entry { 2707 struct list_head list; 2708 u8 bssid[ETH_ALEN]; 2709 u32 age; 2710 }; 2711 2712 struct rtl_scan_list { 2713 int num; 2714 struct list_head list; /* sort by age */ 2715 }; 2716 2717 struct rtl_priv { 2718 struct ieee80211_hw *hw; 2719 struct completion firmware_loading_complete; 2720 struct list_head list; 2721 struct rtl_priv *buddy_priv; 2722 struct rtl_global_var *glb_var; 2723 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2724 struct rtl_dmsp_ctl dmsp_ctl; 2725 struct rtl_locks locks; 2726 struct rtl_works works; 2727 struct rtl_mac mac80211; 2728 struct rtl_hal rtlhal; 2729 struct rtl_regulatory regd; 2730 struct rtl_rfkill rfkill; 2731 struct rtl_io io; 2732 struct rtl_phy phy; 2733 struct rtl_dm dm; 2734 struct rtl_security sec; 2735 struct rtl_efuse efuse; 2736 struct rtl_led_ctl ledctl; 2737 struct rtl_tx_report tx_report; 2738 struct rtl_scan_list scan_list; 2739 2740 struct rtl_ps_ctl psc; 2741 struct rate_adaptive ra; 2742 struct dynamic_primary_cca primarycca; 2743 struct wireless_stats stats; 2744 struct rt_link_detect link_info; 2745 struct false_alarm_statistics falsealm_cnt; 2746 2747 struct rtl_rate_priv *rate_priv; 2748 2749 /* sta entry list for ap adhoc or mesh */ 2750 struct list_head entry_list; 2751 2752 /* c2hcmd list for kthread level access */ 2753 struct list_head c2hcmd_list; 2754 2755 struct rtl_debug dbg; 2756 int max_fw_size; 2757 2758 /* 2759 *hal_cfg : for diff cards 2760 *intf_ops : for diff interrface usb/pcie 2761 */ 2762 struct rtl_hal_cfg *cfg; 2763 const struct rtl_intf_ops *intf_ops; 2764 2765 /*this var will be set by set_bit, 2766 and was used to indicate status of 2767 interface or hardware */ 2768 unsigned long status; 2769 2770 /* tables for dm */ 2771 struct dig_t dm_digtable; 2772 struct ps_t dm_pstable; 2773 2774 u32 reg_874; 2775 u32 reg_c70; 2776 u32 reg_85c; 2777 u32 reg_a74; 2778 bool reg_init; /* true if regs saved */ 2779 bool bt_operation_on; 2780 __le32 *usb_data; 2781 int usb_data_index; 2782 bool initialized; 2783 bool enter_ps; /* true when entering PS */ 2784 u8 rate_mask[5]; 2785 2786 /* intel Proximity, should be alloc mem 2787 * in intel Proximity module and can only 2788 * be used in intel Proximity mode 2789 */ 2790 struct proxim proximity; 2791 2792 /*for bt coexist use*/ 2793 struct bt_coexist_info btcoexist; 2794 2795 /* separate 92ee from other ICs, 2796 * 92ee use new trx flow. 2797 */ 2798 bool use_new_trx_flow; 2799 2800 #ifdef CONFIG_PM 2801 struct wiphy_wowlan_support wowlan; 2802 #endif 2803 /*This must be the last item so 2804 that it points to the data allocated 2805 beyond this structure like: 2806 rtl_pci_priv or rtl_usb_priv */ 2807 u8 priv[0] __aligned(sizeof(void *)); 2808 }; 2809 2810 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2811 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2812 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2813 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2814 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2815 2816 2817 /*************************************** 2818 Bluetooth Co-existence Related 2819 ****************************************/ 2820 2821 enum bt_ant_num { 2822 ANT_X2 = 0, 2823 ANT_X1 = 1, 2824 }; 2825 2826 enum bt_co_type { 2827 BT_2WIRE = 0, 2828 BT_ISSC_3WIRE = 1, 2829 BT_ACCEL = 2, 2830 BT_CSR_BC4 = 3, 2831 BT_CSR_BC8 = 4, 2832 BT_RTL8756 = 5, 2833 BT_RTL8723A = 6, 2834 BT_RTL8821A = 7, 2835 BT_RTL8723B = 8, 2836 BT_RTL8192E = 9, 2837 BT_RTL8812A = 11, 2838 }; 2839 2840 enum bt_total_ant_num { 2841 ANT_TOTAL_X2 = 0, 2842 ANT_TOTAL_X1 = 1 2843 }; 2844 2845 enum bt_cur_state { 2846 BT_OFF = 0, 2847 BT_ON = 1, 2848 }; 2849 2850 enum bt_service_type { 2851 BT_SCO = 0, 2852 BT_A2DP = 1, 2853 BT_HID = 2, 2854 BT_HID_IDLE = 3, 2855 BT_SCAN = 4, 2856 BT_IDLE = 5, 2857 BT_OTHER_ACTION = 6, 2858 BT_BUSY = 7, 2859 BT_OTHERBUSY = 8, 2860 BT_PAN = 9, 2861 }; 2862 2863 enum bt_radio_shared { 2864 BT_RADIO_SHARED = 0, 2865 BT_RADIO_INDIVIDUAL = 1, 2866 }; 2867 2868 2869 /**************************************** 2870 mem access macro define start 2871 Call endian free function when 2872 1. Read/write packet content. 2873 2. Before write integer to IO. 2874 3. After read integer from IO. 2875 ****************************************/ 2876 /* Convert little data endian to host ordering */ 2877 #define EF1BYTE(_val) \ 2878 ((u8)(_val)) 2879 #define EF2BYTE(_val) \ 2880 (le16_to_cpu(_val)) 2881 #define EF4BYTE(_val) \ 2882 (le32_to_cpu(_val)) 2883 2884 /* Read data from memory */ 2885 #define READEF1BYTE(_ptr) \ 2886 EF1BYTE(*((u8 *)(_ptr))) 2887 /* Read le16 data from memory and convert to host ordering */ 2888 #define READEF2BYTE(_ptr) \ 2889 EF2BYTE(*(_ptr)) 2890 #define READEF4BYTE(_ptr) \ 2891 EF4BYTE(*(_ptr)) 2892 2893 /* Create a bit mask 2894 * Examples: 2895 * BIT_LEN_MASK_32(0) => 0x00000000 2896 * BIT_LEN_MASK_32(1) => 0x00000001 2897 * BIT_LEN_MASK_32(2) => 0x00000003 2898 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2899 */ 2900 #define BIT_LEN_MASK_32(__bitlen) \ 2901 (0xFFFFFFFF >> (32 - (__bitlen))) 2902 #define BIT_LEN_MASK_16(__bitlen) \ 2903 (0xFFFF >> (16 - (__bitlen))) 2904 #define BIT_LEN_MASK_8(__bitlen) \ 2905 (0xFF >> (8 - (__bitlen))) 2906 2907 /* Create an offset bit mask 2908 * Examples: 2909 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2910 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2911 */ 2912 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2913 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2914 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2915 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2916 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2917 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2918 2919 /*Description: 2920 * Return 4-byte value in host byte ordering from 2921 * 4-byte pointer in little-endian system. 2922 */ 2923 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2924 (EF4BYTE(*((__le32 *)(__pstart)))) 2925 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2926 (EF2BYTE(*((__le16 *)(__pstart)))) 2927 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2928 (EF1BYTE(*((u8 *)(__pstart)))) 2929 2930 /*Description: 2931 Translate subfield (continuous bits in little-endian) of 4-byte 2932 value to host byte ordering.*/ 2933 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2934 ( \ 2935 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2936 BIT_LEN_MASK_32(__bitlen) \ 2937 ) 2938 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2939 ( \ 2940 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2941 BIT_LEN_MASK_16(__bitlen) \ 2942 ) 2943 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2944 ( \ 2945 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2946 BIT_LEN_MASK_8(__bitlen) \ 2947 ) 2948 2949 /* Description: 2950 * Mask subfield (continuous bits in little-endian) of 4-byte value 2951 * and return the result in 4-byte value in host byte ordering. 2952 */ 2953 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2954 ( \ 2955 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2956 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2957 ) 2958 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2959 ( \ 2960 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2961 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2962 ) 2963 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2964 ( \ 2965 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2966 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2967 ) 2968 2969 /* Description: 2970 * Set subfield of little-endian 4-byte value to specified value. 2971 */ 2972 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2973 *((__le32 *)(__pstart)) = \ 2974 cpu_to_le32( \ 2975 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2976 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2977 ) 2978 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2979 *((__le16 *)(__pstart)) = \ 2980 cpu_to_le16( \ 2981 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2982 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2983 ) 2984 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2985 *((u8 *)(__pstart)) = EF1BYTE \ 2986 ( \ 2987 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2988 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2989 ) 2990 2991 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2992 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2993 2994 /**************************************** 2995 mem access macro define end 2996 ****************************************/ 2997 2998 #define byte(x, n) ((x >> (8 * n)) & 0xff) 2999 3000 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 3001 #define RTL_WATCH_DOG_TIME 2000 3002 #define MSECS(t) msecs_to_jiffies(t) 3003 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 3004 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 3005 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 3006 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 3007 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 3008 3009 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 3010 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 3011 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 3012 /*NIC halt, re-initialize hw parameters*/ 3013 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 3014 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 3015 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 3016 /*Always enable ASPM and Clock Req in initialization.*/ 3017 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 3018 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 3019 #define RT_PS_LEVEL_ASPM BIT(7) 3020 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 3021 #define RT_RF_LPS_DISALBE_2R BIT(30) 3022 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 3023 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 3024 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 3025 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 3026 (ppsc->cur_ps_level &= (~(_ps_flg))) 3027 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 3028 (ppsc->cur_ps_level |= _ps_flg) 3029 3030 #define container_of_dwork_rtl(x, y, z) \ 3031 container_of(to_delayed_work(x), y, z) 3032 3033 #define FILL_OCTET_STRING(_os, _octet, _len) \ 3034 (_os).octet = (u8 *)(_octet); \ 3035 (_os).length = (_len); 3036 3037 #define CP_MACADDR(des, src) \ 3038 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 3039 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 3040 (des)[4] = (src)[4], (des)[5] = (src)[5]) 3041 3042 #define LDPC_HT_ENABLE_RX BIT(0) 3043 #define LDPC_HT_ENABLE_TX BIT(1) 3044 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 3045 #define LDPC_HT_CAP_TX BIT(3) 3046 3047 #define STBC_HT_ENABLE_RX BIT(0) 3048 #define STBC_HT_ENABLE_TX BIT(1) 3049 #define STBC_HT_TEST_TX_ENABLE BIT(2) 3050 #define STBC_HT_CAP_TX BIT(3) 3051 3052 #define LDPC_VHT_ENABLE_RX BIT(0) 3053 #define LDPC_VHT_ENABLE_TX BIT(1) 3054 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 3055 #define LDPC_VHT_CAP_TX BIT(3) 3056 3057 #define STBC_VHT_ENABLE_RX BIT(0) 3058 #define STBC_VHT_ENABLE_TX BIT(1) 3059 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 3060 #define STBC_VHT_CAP_TX BIT(3) 3061 3062 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 3063 3064 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 3065 3066 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 3067 { 3068 return rtlpriv->io.read8_sync(rtlpriv, addr); 3069 } 3070 3071 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 3072 { 3073 return rtlpriv->io.read16_sync(rtlpriv, addr); 3074 } 3075 3076 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 3077 { 3078 return rtlpriv->io.read32_sync(rtlpriv, addr); 3079 } 3080 3081 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 3082 { 3083 rtlpriv->io.write8_async(rtlpriv, addr, val8); 3084 3085 if (rtlpriv->cfg->write_readback) 3086 rtlpriv->io.read8_sync(rtlpriv, addr); 3087 } 3088 3089 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw, 3090 u32 addr, u32 val8) 3091 { 3092 struct rtl_priv *rtlpriv = rtl_priv(hw); 3093 3094 rtl_write_byte(rtlpriv, addr, (u8)val8); 3095 } 3096 3097 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 3098 { 3099 rtlpriv->io.write16_async(rtlpriv, addr, val16); 3100 3101 if (rtlpriv->cfg->write_readback) 3102 rtlpriv->io.read16_sync(rtlpriv, addr); 3103 } 3104 3105 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 3106 u32 addr, u32 val32) 3107 { 3108 rtlpriv->io.write32_async(rtlpriv, addr, val32); 3109 3110 if (rtlpriv->cfg->write_readback) 3111 rtlpriv->io.read32_sync(rtlpriv, addr); 3112 } 3113 3114 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 3115 u32 regaddr, u32 bitmask) 3116 { 3117 struct rtl_priv *rtlpriv = hw->priv; 3118 3119 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 3120 } 3121 3122 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 3123 u32 bitmask, u32 data) 3124 { 3125 struct rtl_priv *rtlpriv = hw->priv; 3126 3127 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 3128 } 3129 3130 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw, 3131 u32 regaddr, u32 data) 3132 { 3133 rtl_set_bbreg(hw, regaddr, 0xffffffff, data); 3134 } 3135 3136 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 3137 enum radio_path rfpath, u32 regaddr, 3138 u32 bitmask) 3139 { 3140 struct rtl_priv *rtlpriv = hw->priv; 3141 3142 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 3143 } 3144 3145 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 3146 enum radio_path rfpath, u32 regaddr, 3147 u32 bitmask, u32 data) 3148 { 3149 struct rtl_priv *rtlpriv = hw->priv; 3150 3151 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 3152 } 3153 3154 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 3155 { 3156 return (_HAL_STATE_STOP == rtlhal->state); 3157 } 3158 3159 static inline void set_hal_start(struct rtl_hal *rtlhal) 3160 { 3161 rtlhal->state = _HAL_STATE_START; 3162 } 3163 3164 static inline void set_hal_stop(struct rtl_hal *rtlhal) 3165 { 3166 rtlhal->state = _HAL_STATE_STOP; 3167 } 3168 3169 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3170 { 3171 return rtlphy->rf_type; 3172 } 3173 3174 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3175 { 3176 return (struct ieee80211_hdr *)(skb->data); 3177 } 3178 3179 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3180 { 3181 return rtl_get_hdr(skb)->frame_control; 3182 } 3183 3184 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3185 { 3186 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3187 } 3188 3189 static inline u16 rtl_get_tid(struct sk_buff *skb) 3190 { 3191 return rtl_get_tid_h(rtl_get_hdr(skb)); 3192 } 3193 3194 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3195 struct ieee80211_vif *vif, 3196 const u8 *bssid) 3197 { 3198 return ieee80211_find_sta(vif, bssid); 3199 } 3200 3201 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3202 u8 *mac_addr) 3203 { 3204 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3205 return ieee80211_find_sta(mac->vif, mac_addr); 3206 } 3207 3208 #endif 3209