1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 #define ASPM_L1_LATENCY 7 103 104 #define TOTAL_CAM_ENTRY 32 105 106 /*slot time for 11g. */ 107 #define RTL_SLOT_TIME_9 9 108 #define RTL_SLOT_TIME_20 20 109 110 /*related to tcp/ip. */ 111 #define SNAP_SIZE 6 112 #define PROTOC_TYPE_SIZE 2 113 114 /*related with 802.11 frame*/ 115 #define MAC80211_3ADDR_LEN 24 116 #define MAC80211_4ADDR_LEN 30 117 118 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 119 #define CHANNEL_MAX_NUMBER_2G 14 120 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 121 *"phy_GetChnlGroup8812A" and 122 * "Hal_ReadTxPowerInfo8812A" 123 */ 124 #define CHANNEL_MAX_NUMBER_5G_80M 7 125 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 126 #define MAX_PG_GROUP 13 127 #define CHANNEL_GROUP_MAX_2G 3 128 #define CHANNEL_GROUP_IDX_5GL 3 129 #define CHANNEL_GROUP_IDX_5GM 6 130 #define CHANNEL_GROUP_IDX_5GH 9 131 #define CHANNEL_GROUP_MAX_5G 9 132 #define CHANNEL_MAX_NUMBER_2G 14 133 #define AVG_THERMAL_NUM 8 134 #define AVG_THERMAL_NUM_88E 4 135 #define AVG_THERMAL_NUM_8723BE 4 136 #define MAX_TID_COUNT 9 137 138 /* for early mode */ 139 #define FCS_LEN 4 140 #define EM_HDR_LEN 8 141 142 enum rtl8192c_h2c_cmd { 143 H2C_AP_OFFLOAD = 0, 144 H2C_SETPWRMODE = 1, 145 H2C_JOINBSSRPT = 2, 146 H2C_RSVDPAGE = 3, 147 H2C_RSSI_REPORT = 5, 148 H2C_RA_MASK = 6, 149 H2C_MACID_PS_MODE = 7, 150 H2C_P2P_PS_OFFLOAD = 8, 151 H2C_MAC_MODE_SEL = 9, 152 H2C_PWRM = 15, 153 H2C_P2P_PS_CTW_CMD = 24, 154 MAX_H2CCMD 155 }; 156 157 enum { 158 H2C_BT_PORT_ID = 0x71, 159 }; 160 161 enum rtl_c2h_evt_v1 { 162 C2H_DBG = 0, 163 C2H_LB = 1, 164 C2H_TXBF = 2, 165 C2H_TX_REPORT = 3, 166 C2H_BT_INFO = 9, 167 C2H_BT_MP = 11, 168 C2H_RA_RPT = 12, 169 170 C2H_FW_SWCHNL = 0x10, 171 C2H_IQK_FINISH = 0x11, 172 173 C2H_EXT_V2 = 0xFF, 174 }; 175 176 enum rtl_c2h_evt_v2 { 177 C2H_V2_CCX_RPT = 0x0F, 178 }; 179 180 #define GET_C2H_CMD_ID(c2h) ({u8 *__c2h = c2h; __c2h[0]; }) 181 #define GET_C2H_SEQ(c2h) ({u8 *__c2h = c2h; __c2h[1]; }) 182 #define C2H_DATA_OFFSET 2 183 #define GET_C2H_DATA_PTR(c2h) ({u8 *__c2h = c2h; &__c2h[C2H_DATA_OFFSET]; }) 184 185 #define GET_TX_REPORT_SN_V1(c2h) (c2h[6]) 186 #define GET_TX_REPORT_ST_V1(c2h) (c2h[0] & 0xC0) 187 #define GET_TX_REPORT_RETRY_V1(c2h) (c2h[2] & 0x3F) 188 #define GET_TX_REPORT_SN_V2(c2h) (c2h[6]) 189 #define GET_TX_REPORT_ST_V2(c2h) (c2h[7] & 0xC0) 190 #define GET_TX_REPORT_RETRY_V2(c2h) (c2h[8] & 0x3F) 191 192 #define MAX_TX_COUNT 4 193 #define MAX_REGULATION_NUM 4 194 #define MAX_RF_PATH_NUM 4 195 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */ 196 #define MAX_2_4G_BANDWIDTH_NUM 4 197 #define MAX_5G_BANDWIDTH_NUM 4 198 #define MAX_RF_PATH 4 199 #define MAX_CHNL_GROUP_24G 6 200 #define MAX_CHNL_GROUP_5G 14 201 202 #define TX_PWR_BY_RATE_NUM_BAND 2 203 #define TX_PWR_BY_RATE_NUM_RF 4 204 #define TX_PWR_BY_RATE_NUM_SECTION 12 205 #define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */ 206 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */ 207 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */ 208 209 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 210 211 #define DEL_SW_IDX_SZ 30 212 213 /* For now, it's just for 8192ee 214 * but not OK yet, keep it 0 215 */ 216 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM 217 218 enum rf_tx_num { 219 RF_1TX = 0, 220 RF_2TX, 221 RF_MAX_TX_NUM, 222 RF_TX_NUM_NONIMPLEMENT, 223 }; 224 225 #define PACKET_NORMAL 0 226 #define PACKET_DHCP 1 227 #define PACKET_ARP 2 228 #define PACKET_EAPOL 3 229 230 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 231 #define RSVD_WOL_PATTERN_NUM 1 232 #define WKFMCAM_ADDR_NUM 6 233 #define WKFMCAM_SIZE 24 234 235 #define MAX_WOL_BIT_MASK_SIZE 16 236 /* MIN LEN keeps 13 here */ 237 #define MIN_WOL_PATTERN_SIZE 13 238 #define MAX_WOL_PATTERN_SIZE 128 239 240 #define WAKE_ON_MAGIC_PACKET BIT(0) 241 #define WAKE_ON_PATTERN_MATCH BIT(1) 242 243 #define WOL_REASON_PTK_UPDATE BIT(0) 244 #define WOL_REASON_GTK_UPDATE BIT(1) 245 #define WOL_REASON_DISASSOC BIT(2) 246 #define WOL_REASON_DEAUTH BIT(3) 247 #define WOL_REASON_AP_LOST BIT(4) 248 #define WOL_REASON_MAGIC_PKT BIT(5) 249 #define WOL_REASON_UNICAST_PKT BIT(6) 250 #define WOL_REASON_PATTERN_PKT BIT(7) 251 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 252 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 253 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 254 255 struct rtlwifi_firmware_header { 256 __le16 signature; 257 u8 category; 258 u8 function; 259 __le16 version; 260 u8 subversion; 261 u8 rsvd1; 262 u8 month; 263 u8 date; 264 u8 hour; 265 u8 minute; 266 __le16 ramcodeSize; 267 __le16 rsvd2; 268 __le32 svnindex; 269 __le32 rsvd3; 270 __le32 rsvd4; 271 __le32 rsvd5; 272 }; 273 274 struct txpower_info_2g { 275 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 276 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 277 /*If only one tx, only BW20 and OFDM are used.*/ 278 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 279 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 280 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 281 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 282 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 283 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 284 }; 285 286 struct txpower_info_5g { 287 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 288 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 289 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 290 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 291 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 292 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 293 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 294 }; 295 296 enum rate_section { 297 CCK = 0, 298 OFDM, 299 HT_MCS0_MCS7, 300 HT_MCS8_MCS15, 301 VHT_1SSMCS0_1SSMCS9, 302 VHT_2SSMCS0_2SSMCS9, 303 MAX_RATE_SECTION, 304 }; 305 306 enum intf_type { 307 INTF_PCI = 0, 308 INTF_USB = 1, 309 }; 310 311 enum radio_path { 312 RF90_PATH_A = 0, 313 RF90_PATH_B = 1, 314 RF90_PATH_C = 2, 315 RF90_PATH_D = 3, 316 }; 317 318 enum radio_mask { 319 RF_MASK_A = BIT(0), 320 RF_MASK_B = BIT(1), 321 RF_MASK_C = BIT(2), 322 RF_MASK_D = BIT(3), 323 }; 324 325 enum regulation_txpwr_lmt { 326 TXPWR_LMT_FCC = 0, 327 TXPWR_LMT_MKK = 1, 328 TXPWR_LMT_ETSI = 2, 329 TXPWR_LMT_WW = 3, 330 331 TXPWR_LMT_MAX_REGULATION_NUM = 4 332 }; 333 334 enum rt_eeprom_type { 335 EEPROM_93C46, 336 EEPROM_93C56, 337 EEPROM_BOOT_EFUSE, 338 }; 339 340 enum ttl_status { 341 RTL_STATUS_INTERFACE_START = 0, 342 }; 343 344 enum hardware_type { 345 HARDWARE_TYPE_RTL8192E, 346 HARDWARE_TYPE_RTL8192U, 347 HARDWARE_TYPE_RTL8192SE, 348 HARDWARE_TYPE_RTL8192SU, 349 HARDWARE_TYPE_RTL8192CE, 350 HARDWARE_TYPE_RTL8192CU, 351 HARDWARE_TYPE_RTL8192DE, 352 HARDWARE_TYPE_RTL8192DU, 353 HARDWARE_TYPE_RTL8723AE, 354 HARDWARE_TYPE_RTL8723U, 355 HARDWARE_TYPE_RTL8188EE, 356 HARDWARE_TYPE_RTL8723BE, 357 HARDWARE_TYPE_RTL8192EE, 358 HARDWARE_TYPE_RTL8821AE, 359 HARDWARE_TYPE_RTL8812AE, 360 HARDWARE_TYPE_RTL8822BE, 361 362 /* keep it last */ 363 HARDWARE_TYPE_NUM 364 }; 365 366 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type) 367 #define IS_NEW_GENERATION_IC(rtlpriv) \ 368 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE) 369 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \ 370 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE) 371 #define IS_HARDWARE_TYPE_8812(rtlpriv) \ 372 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE) 373 #define IS_HARDWARE_TYPE_8821(rtlpriv) \ 374 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE) 375 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \ 376 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE) 377 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \ 378 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE) 379 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \ 380 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE) 381 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \ 382 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE) 383 384 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 385 ((rxmcs) == DESC_RATE1M || \ 386 (rxmcs) == DESC_RATE2M || \ 387 (rxmcs) == DESC_RATE5_5M || \ 388 (rxmcs) == DESC_RATE11M) 389 390 enum scan_operation_backup_opt { 391 SCAN_OPT_BACKUP = 0, 392 SCAN_OPT_BACKUP_BAND0 = 0, 393 SCAN_OPT_BACKUP_BAND1, 394 SCAN_OPT_RESTORE, 395 SCAN_OPT_MAX 396 }; 397 398 /*RF state.*/ 399 enum rf_pwrstate { 400 ERFON, 401 ERFSLEEP, 402 ERFOFF 403 }; 404 405 struct bb_reg_def { 406 u32 rfintfs; 407 u32 rfintfi; 408 u32 rfintfo; 409 u32 rfintfe; 410 u32 rf3wire_offset; 411 u32 rflssi_select; 412 u32 rftxgain_stage; 413 u32 rfhssi_para1; 414 u32 rfhssi_para2; 415 u32 rfsw_ctrl; 416 u32 rfagc_control1; 417 u32 rfagc_control2; 418 u32 rfrxiq_imbal; 419 u32 rfrx_afe; 420 u32 rftxiq_imbal; 421 u32 rftx_afe; 422 u32 rf_rb; /* rflssi_readback */ 423 u32 rf_rbpi; /* rflssi_readbackpi */ 424 }; 425 426 enum io_type { 427 IO_CMD_PAUSE_DM_BY_SCAN = 0, 428 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 429 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 430 IO_CMD_RESUME_DM_BY_SCAN = 2, 431 }; 432 433 enum hw_variables { 434 HW_VAR_ETHER_ADDR = 0x0, 435 HW_VAR_MULTICAST_REG = 0x1, 436 HW_VAR_BASIC_RATE = 0x2, 437 HW_VAR_BSSID = 0x3, 438 HW_VAR_MEDIA_STATUS= 0x4, 439 HW_VAR_SECURITY_CONF= 0x5, 440 HW_VAR_BEACON_INTERVAL = 0x6, 441 HW_VAR_ATIM_WINDOW = 0x7, 442 HW_VAR_LISTEN_INTERVAL = 0x8, 443 HW_VAR_CS_COUNTER = 0x9, 444 HW_VAR_DEFAULTKEY0 = 0xa, 445 HW_VAR_DEFAULTKEY1 = 0xb, 446 HW_VAR_DEFAULTKEY2 = 0xc, 447 HW_VAR_DEFAULTKEY3 = 0xd, 448 HW_VAR_SIFS = 0xe, 449 HW_VAR_R2T_SIFS = 0xf, 450 HW_VAR_DIFS = 0x10, 451 HW_VAR_EIFS = 0x11, 452 HW_VAR_SLOT_TIME = 0x12, 453 HW_VAR_ACK_PREAMBLE = 0x13, 454 HW_VAR_CW_CONFIG = 0x14, 455 HW_VAR_CW_VALUES = 0x15, 456 HW_VAR_RATE_FALLBACK_CONTROL= 0x16, 457 HW_VAR_CONTENTION_WINDOW = 0x17, 458 HW_VAR_RETRY_COUNT = 0x18, 459 HW_VAR_TR_SWITCH = 0x19, 460 HW_VAR_COMMAND = 0x1a, 461 HW_VAR_WPA_CONFIG = 0x1b, 462 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 463 HW_VAR_SHORTGI_DENSITY = 0x1d, 464 HW_VAR_AMPDU_FACTOR = 0x1e, 465 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 466 HW_VAR_AC_PARAM = 0x20, 467 HW_VAR_ACM_CTRL = 0x21, 468 HW_VAR_DIS_Req_Qsize = 0x22, 469 HW_VAR_CCX_CHNL_LOAD = 0x23, 470 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 471 HW_VAR_CCX_CLM_NHM = 0x25, 472 HW_VAR_TxOPLimit = 0x26, 473 HW_VAR_TURBO_MODE = 0x27, 474 HW_VAR_RF_STATE = 0x28, 475 HW_VAR_RF_OFF_BY_HW = 0x29, 476 HW_VAR_BUS_SPEED = 0x2a, 477 HW_VAR_SET_DEV_POWER = 0x2b, 478 479 HW_VAR_RCR = 0x2c, 480 HW_VAR_RATR_0 = 0x2d, 481 HW_VAR_RRSR = 0x2e, 482 HW_VAR_CPU_RST = 0x2f, 483 HW_VAR_CHECK_BSSID = 0x30, 484 HW_VAR_LBK_MODE = 0x31, 485 HW_VAR_AES_11N_FIX = 0x32, 486 HW_VAR_USB_RX_AGGR = 0x33, 487 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 488 HW_VAR_RETRY_LIMIT = 0x35, 489 HW_VAR_INIT_TX_RATE = 0x36, 490 HW_VAR_TX_RATE_REG = 0x37, 491 HW_VAR_EFUSE_USAGE = 0x38, 492 HW_VAR_EFUSE_BYTES = 0x39, 493 HW_VAR_AUTOLOAD_STATUS = 0x3a, 494 HW_VAR_RF_2R_DISABLE = 0x3b, 495 HW_VAR_SET_RPWM = 0x3c, 496 HW_VAR_H2C_FW_PWRMODE = 0x3d, 497 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 498 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 499 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 500 HW_VAR_FW_PSMODE_STATUS = 0x41, 501 HW_VAR_INIT_RTS_RATE = 0x42, 502 HW_VAR_RESUME_CLK_ON = 0x43, 503 HW_VAR_FW_LPS_ACTION = 0x44, 504 HW_VAR_1X1_RECV_COMBINE = 0x45, 505 HW_VAR_STOP_SEND_BEACON = 0x46, 506 HW_VAR_TSF_TIMER = 0x47, 507 HW_VAR_IO_CMD = 0x48, 508 509 HW_VAR_RF_RECOVERY = 0x49, 510 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 511 HW_VAR_WF_MASK = 0x4b, 512 HW_VAR_WF_CRC = 0x4c, 513 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 514 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 515 HW_VAR_RESET_WFCRC = 0x4f, 516 517 HW_VAR_HANDLE_FW_C2H = 0x50, 518 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 519 HW_VAR_AID = 0x52, 520 HW_VAR_HW_SEQ_ENABLE = 0x53, 521 HW_VAR_CORRECT_TSF = 0x54, 522 HW_VAR_BCN_VALID = 0x55, 523 HW_VAR_FWLPS_RF_ON = 0x56, 524 HW_VAR_DUAL_TSF_RST = 0x57, 525 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58, 526 HW_VAR_INT_MIGRATION = 0x59, 527 HW_VAR_INT_AC = 0x5a, 528 HW_VAR_RF_TIMING = 0x5b, 529 530 HAL_DEF_WOWLAN = 0x5c, 531 HW_VAR_MRC = 0x5d, 532 HW_VAR_KEEP_ALIVE = 0x5e, 533 HW_VAR_NAV_UPPER = 0x5f, 534 535 HW_VAR_MGT_FILTER = 0x60, 536 HW_VAR_CTRL_FILTER = 0x61, 537 HW_VAR_DATA_FILTER = 0x62, 538 }; 539 540 enum rt_media_status { 541 RT_MEDIA_DISCONNECT = 0, 542 RT_MEDIA_CONNECT = 1 543 }; 544 545 enum rt_oem_id { 546 RT_CID_DEFAULT = 0, 547 RT_CID_8187_ALPHA0 = 1, 548 RT_CID_8187_SERCOMM_PS = 2, 549 RT_CID_8187_HW_LED = 3, 550 RT_CID_8187_NETGEAR = 4, 551 RT_CID_WHQL = 5, 552 RT_CID_819X_CAMEO = 6, 553 RT_CID_819X_RUNTOP = 7, 554 RT_CID_819X_SENAO = 8, 555 RT_CID_TOSHIBA = 9, 556 RT_CID_819X_NETCORE = 10, 557 RT_CID_NETTRONIX = 11, 558 RT_CID_DLINK = 12, 559 RT_CID_PRONET = 13, 560 RT_CID_COREGA = 14, 561 RT_CID_819X_ALPHA = 15, 562 RT_CID_819X_SITECOM = 16, 563 RT_CID_CCX = 17, 564 RT_CID_819X_LENOVO = 18, 565 RT_CID_819X_QMI = 19, 566 RT_CID_819X_EDIMAX_BELKIN = 20, 567 RT_CID_819X_SERCOMM_BELKIN = 21, 568 RT_CID_819X_CAMEO1 = 22, 569 RT_CID_819X_MSI = 23, 570 RT_CID_819X_ACER = 24, 571 RT_CID_819X_HP = 27, 572 RT_CID_819X_CLEVO = 28, 573 RT_CID_819X_ARCADYAN_BELKIN = 29, 574 RT_CID_819X_SAMSUNG = 30, 575 RT_CID_819X_WNC_COREGA = 31, 576 RT_CID_819X_FOXCOON = 32, 577 RT_CID_819X_DELL = 33, 578 RT_CID_819X_PRONETS = 34, 579 RT_CID_819X_EDIMAX_ASUS = 35, 580 RT_CID_NETGEAR = 36, 581 RT_CID_PLANEX = 37, 582 RT_CID_CC_C = 38, 583 RT_CID_LENOVO_CHINA = 40, 584 }; 585 586 enum hw_descs { 587 HW_DESC_OWN, 588 HW_DESC_RXOWN, 589 HW_DESC_TX_NEXTDESC_ADDR, 590 HW_DESC_TXBUFF_ADDR, 591 HW_DESC_RXBUFF_ADDR, 592 HW_DESC_RXPKT_LEN, 593 HW_DESC_RXERO, 594 HW_DESC_RX_PREPARE, 595 }; 596 597 enum prime_sc { 598 PRIME_CHNL_OFFSET_DONT_CARE = 0, 599 PRIME_CHNL_OFFSET_LOWER = 1, 600 PRIME_CHNL_OFFSET_UPPER = 2, 601 }; 602 603 enum rf_type { 604 RF_1T1R = 0, 605 RF_1T2R = 1, 606 RF_2T2R = 2, 607 RF_2T2R_GREEN = 3, 608 RF_2T3R = 4, 609 RF_2T4R = 5, 610 RF_3T3R = 6, 611 RF_3T4R = 7, 612 RF_4T4R = 8, 613 }; 614 615 enum ht_channel_width { 616 HT_CHANNEL_WIDTH_20 = 0, 617 HT_CHANNEL_WIDTH_20_40 = 1, 618 HT_CHANNEL_WIDTH_80 = 2, 619 HT_CHANNEL_WIDTH_MAX, 620 }; 621 622 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 623 Cipher Suites Encryption Algorithms */ 624 enum rt_enc_alg { 625 NO_ENCRYPTION = 0, 626 WEP40_ENCRYPTION = 1, 627 TKIP_ENCRYPTION = 2, 628 RSERVED_ENCRYPTION = 3, 629 AESCCMP_ENCRYPTION = 4, 630 WEP104_ENCRYPTION = 5, 631 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 632 }; 633 634 enum rtl_hal_state { 635 _HAL_STATE_STOP = 0, 636 _HAL_STATE_START = 1, 637 }; 638 639 enum rtl_desc_rate { 640 DESC_RATE1M = 0x00, 641 DESC_RATE2M = 0x01, 642 DESC_RATE5_5M = 0x02, 643 DESC_RATE11M = 0x03, 644 645 DESC_RATE6M = 0x04, 646 DESC_RATE9M = 0x05, 647 DESC_RATE12M = 0x06, 648 DESC_RATE18M = 0x07, 649 DESC_RATE24M = 0x08, 650 DESC_RATE36M = 0x09, 651 DESC_RATE48M = 0x0a, 652 DESC_RATE54M = 0x0b, 653 654 DESC_RATEMCS0 = 0x0c, 655 DESC_RATEMCS1 = 0x0d, 656 DESC_RATEMCS2 = 0x0e, 657 DESC_RATEMCS3 = 0x0f, 658 DESC_RATEMCS4 = 0x10, 659 DESC_RATEMCS5 = 0x11, 660 DESC_RATEMCS6 = 0x12, 661 DESC_RATEMCS7 = 0x13, 662 DESC_RATEMCS8 = 0x14, 663 DESC_RATEMCS9 = 0x15, 664 DESC_RATEMCS10 = 0x16, 665 DESC_RATEMCS11 = 0x17, 666 DESC_RATEMCS12 = 0x18, 667 DESC_RATEMCS13 = 0x19, 668 DESC_RATEMCS14 = 0x1a, 669 DESC_RATEMCS15 = 0x1b, 670 DESC_RATEMCS15_SG = 0x1c, 671 DESC_RATEMCS32 = 0x20, 672 673 DESC_RATEVHT1SS_MCS0 = 0x2c, 674 DESC_RATEVHT1SS_MCS1 = 0x2d, 675 DESC_RATEVHT1SS_MCS2 = 0x2e, 676 DESC_RATEVHT1SS_MCS3 = 0x2f, 677 DESC_RATEVHT1SS_MCS4 = 0x30, 678 DESC_RATEVHT1SS_MCS5 = 0x31, 679 DESC_RATEVHT1SS_MCS6 = 0x32, 680 DESC_RATEVHT1SS_MCS7 = 0x33, 681 DESC_RATEVHT1SS_MCS8 = 0x34, 682 DESC_RATEVHT1SS_MCS9 = 0x35, 683 DESC_RATEVHT2SS_MCS0 = 0x36, 684 DESC_RATEVHT2SS_MCS1 = 0x37, 685 DESC_RATEVHT2SS_MCS2 = 0x38, 686 DESC_RATEVHT2SS_MCS3 = 0x39, 687 DESC_RATEVHT2SS_MCS4 = 0x3a, 688 DESC_RATEVHT2SS_MCS5 = 0x3b, 689 DESC_RATEVHT2SS_MCS6 = 0x3c, 690 DESC_RATEVHT2SS_MCS7 = 0x3d, 691 DESC_RATEVHT2SS_MCS8 = 0x3e, 692 DESC_RATEVHT2SS_MCS9 = 0x3f, 693 }; 694 695 enum rtl_var_map { 696 /*reg map */ 697 SYS_ISO_CTRL = 0, 698 SYS_FUNC_EN, 699 SYS_CLK, 700 MAC_RCR_AM, 701 MAC_RCR_AB, 702 MAC_RCR_ACRC32, 703 MAC_RCR_ACF, 704 MAC_RCR_AAP, 705 MAC_HIMR, 706 MAC_HIMRE, 707 MAC_HSISR, 708 709 /*efuse map */ 710 EFUSE_TEST, 711 EFUSE_CTRL, 712 EFUSE_CLK, 713 EFUSE_CLK_CTRL, 714 EFUSE_PWC_EV12V, 715 EFUSE_FEN_ELDR, 716 EFUSE_LOADER_CLK_EN, 717 EFUSE_ANA8M, 718 EFUSE_HWSET_MAX_SIZE, 719 EFUSE_MAX_SECTION_MAP, 720 EFUSE_REAL_CONTENT_SIZE, 721 EFUSE_OOB_PROTECT_BYTES_LEN, 722 EFUSE_ACCESS, 723 724 /*CAM map */ 725 RWCAM, 726 WCAMI, 727 RCAMO, 728 CAMDBG, 729 SECR, 730 SEC_CAM_NONE, 731 SEC_CAM_WEP40, 732 SEC_CAM_TKIP, 733 SEC_CAM_AES, 734 SEC_CAM_WEP104, 735 736 /*IMR map */ 737 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 738 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 739 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 740 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 741 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 742 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 743 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 744 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 745 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 746 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 747 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 748 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 749 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 750 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 751 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 752 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 753 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 754 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 755 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 756 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 757 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 758 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 759 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */ 760 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 761 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 762 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 763 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 764 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 765 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 766 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 767 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 768 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 769 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 770 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 771 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 772 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 773 * RTL_IMR_TBDER) */ 774 RTL_IMR_C2HCMD, /*fw interrupt*/ 775 776 /*CCK Rates, TxHT = 0 */ 777 RTL_RC_CCK_RATE1M, 778 RTL_RC_CCK_RATE2M, 779 RTL_RC_CCK_RATE5_5M, 780 RTL_RC_CCK_RATE11M, 781 782 /*OFDM Rates, TxHT = 0 */ 783 RTL_RC_OFDM_RATE6M, 784 RTL_RC_OFDM_RATE9M, 785 RTL_RC_OFDM_RATE12M, 786 RTL_RC_OFDM_RATE18M, 787 RTL_RC_OFDM_RATE24M, 788 RTL_RC_OFDM_RATE36M, 789 RTL_RC_OFDM_RATE48M, 790 RTL_RC_OFDM_RATE54M, 791 792 RTL_RC_HT_RATEMCS7, 793 RTL_RC_HT_RATEMCS15, 794 795 RTL_RC_VHT_RATE_1SS_MCS7, 796 RTL_RC_VHT_RATE_1SS_MCS8, 797 RTL_RC_VHT_RATE_1SS_MCS9, 798 RTL_RC_VHT_RATE_2SS_MCS7, 799 RTL_RC_VHT_RATE_2SS_MCS8, 800 RTL_RC_VHT_RATE_2SS_MCS9, 801 802 /*keep it last */ 803 RTL_VAR_MAP_MAX, 804 }; 805 806 /*Firmware PS mode for control LPS.*/ 807 enum _fw_ps_mode { 808 FW_PS_ACTIVE_MODE = 0, 809 FW_PS_MIN_MODE = 1, 810 FW_PS_MAX_MODE = 2, 811 FW_PS_DTIM_MODE = 3, 812 FW_PS_VOIP_MODE = 4, 813 FW_PS_UAPSD_WMM_MODE = 5, 814 FW_PS_UAPSD_MODE = 6, 815 FW_PS_IBSS_MODE = 7, 816 FW_PS_WWLAN_MODE = 8, 817 FW_PS_PM_Radio_Off = 9, 818 FW_PS_PM_Card_Disable = 10, 819 }; 820 821 enum rt_psmode { 822 EACTIVE, /*Active/Continuous access. */ 823 EMAXPS, /*Max power save mode. */ 824 EFASTPS, /*Fast power save mode. */ 825 EAUTOPS, /*Auto power save mode. */ 826 }; 827 828 /*LED related.*/ 829 enum led_ctl_mode { 830 LED_CTL_POWER_ON = 1, 831 LED_CTL_LINK = 2, 832 LED_CTL_NO_LINK = 3, 833 LED_CTL_TX = 4, 834 LED_CTL_RX = 5, 835 LED_CTL_SITE_SURVEY = 6, 836 LED_CTL_POWER_OFF = 7, 837 LED_CTL_START_TO_LINK = 8, 838 LED_CTL_START_WPS = 9, 839 LED_CTL_STOP_WPS = 10, 840 }; 841 842 enum rtl_led_pin { 843 LED_PIN_GPIO0, 844 LED_PIN_LED0, 845 LED_PIN_LED1, 846 LED_PIN_LED2 847 }; 848 849 /*QoS related.*/ 850 /*acm implementation method.*/ 851 enum acm_method { 852 eAcmWay0_SwAndHw = 0, 853 eAcmWay1_HW = 1, 854 EACMWAY2_SW = 2, 855 }; 856 857 enum macphy_mode { 858 SINGLEMAC_SINGLEPHY = 0, 859 DUALMAC_DUALPHY, 860 DUALMAC_SINGLEPHY, 861 }; 862 863 enum band_type { 864 BAND_ON_2_4G = 0, 865 BAND_ON_5G, 866 BAND_ON_BOTH, 867 BANDMAX 868 }; 869 870 /*aci/aifsn Field. 871 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 872 union aci_aifsn { 873 u8 char_data; 874 875 struct { 876 u8 aifsn:4; 877 u8 acm:1; 878 u8 aci:2; 879 u8 reserved:1; 880 } f; /* Field */ 881 }; 882 883 /*mlme related.*/ 884 enum wireless_mode { 885 WIRELESS_MODE_UNKNOWN = 0x00, 886 WIRELESS_MODE_A = 0x01, 887 WIRELESS_MODE_B = 0x02, 888 WIRELESS_MODE_G = 0x04, 889 WIRELESS_MODE_AUTO = 0x08, 890 WIRELESS_MODE_N_24G = 0x10, 891 WIRELESS_MODE_N_5G = 0x20, 892 WIRELESS_MODE_AC_5G = 0x40, 893 WIRELESS_MODE_AC_24G = 0x80, 894 WIRELESS_MODE_AC_ONLY = 0x100, 895 WIRELESS_MODE_MAX = 0x800 896 }; 897 898 #define IS_WIRELESS_MODE_A(wirelessmode) \ 899 (wirelessmode == WIRELESS_MODE_A) 900 #define IS_WIRELESS_MODE_B(wirelessmode) \ 901 (wirelessmode == WIRELESS_MODE_B) 902 #define IS_WIRELESS_MODE_G(wirelessmode) \ 903 (wirelessmode == WIRELESS_MODE_G) 904 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 905 (wirelessmode == WIRELESS_MODE_N_24G) 906 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 907 (wirelessmode == WIRELESS_MODE_N_5G) 908 909 enum ratr_table_mode { 910 RATR_INX_WIRELESS_NGB = 0, 911 RATR_INX_WIRELESS_NG = 1, 912 RATR_INX_WIRELESS_NB = 2, 913 RATR_INX_WIRELESS_N = 3, 914 RATR_INX_WIRELESS_GB = 4, 915 RATR_INX_WIRELESS_G = 5, 916 RATR_INX_WIRELESS_B = 6, 917 RATR_INX_WIRELESS_MC = 7, 918 RATR_INX_WIRELESS_A = 8, 919 RATR_INX_WIRELESS_AC_5N = 8, 920 RATR_INX_WIRELESS_AC_24N = 9, 921 }; 922 923 enum ratr_table_mode_new { 924 RATEID_IDX_BGN_40M_2SS = 0, 925 RATEID_IDX_BGN_40M_1SS = 1, 926 RATEID_IDX_BGN_20M_2SS_BN = 2, 927 RATEID_IDX_BGN_20M_1SS_BN = 3, 928 RATEID_IDX_GN_N2SS = 4, 929 RATEID_IDX_GN_N1SS = 5, 930 RATEID_IDX_BG = 6, 931 RATEID_IDX_G = 7, 932 RATEID_IDX_B = 8, 933 RATEID_IDX_VHT_2SS = 9, 934 RATEID_IDX_VHT_1SS = 10, 935 RATEID_IDX_MIX1 = 11, 936 RATEID_IDX_MIX2 = 12, 937 RATEID_IDX_VHT_3SS = 13, 938 RATEID_IDX_BGN_3SS = 14, 939 }; 940 941 enum rtl_link_state { 942 MAC80211_NOLINK = 0, 943 MAC80211_LINKING = 1, 944 MAC80211_LINKED = 2, 945 MAC80211_LINKED_SCANNING = 3, 946 }; 947 948 enum act_category { 949 ACT_CAT_QOS = 1, 950 ACT_CAT_DLS = 2, 951 ACT_CAT_BA = 3, 952 ACT_CAT_HT = 7, 953 ACT_CAT_WMM = 17, 954 }; 955 956 enum ba_action { 957 ACT_ADDBAREQ = 0, 958 ACT_ADDBARSP = 1, 959 ACT_DELBA = 2, 960 }; 961 962 enum rt_polarity_ctl { 963 RT_POLARITY_LOW_ACT = 0, 964 RT_POLARITY_HIGH_ACT = 1, 965 }; 966 967 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 968 enum fw_wow_reason_v2 { 969 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 970 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 971 FW_WOW_V2_DISASSOC_EVENT = 0x04, 972 FW_WOW_V2_DEAUTH_EVENT = 0x08, 973 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 974 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 975 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 976 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 977 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 978 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 979 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 980 FW_WOW_V2_REASON_MAX = 0xff, 981 }; 982 983 enum wolpattern_type { 984 UNICAST_PATTERN = 0, 985 MULTICAST_PATTERN = 1, 986 BROADCAST_PATTERN = 2, 987 DONT_CARE_DA = 3, 988 UNKNOWN_TYPE = 4, 989 }; 990 991 enum package_type { 992 PACKAGE_DEFAULT, 993 PACKAGE_QFN68, 994 PACKAGE_TFBGA90, 995 PACKAGE_TFBGA80, 996 PACKAGE_TFBGA79 997 }; 998 999 enum rtl_spec_ver { 1000 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */ 1001 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */ 1002 RTL_SPEC_EXT_C2H = BIT(2), /* extend FW C2H (e.g. TX REPORT) */ 1003 }; 1004 1005 enum dm_info_query { 1006 DM_INFO_FA_OFDM, 1007 DM_INFO_FA_CCK, 1008 DM_INFO_FA_TOTAL, 1009 DM_INFO_CCA_OFDM, 1010 DM_INFO_CCA_CCK, 1011 DM_INFO_CCA_ALL, 1012 DM_INFO_CRC32_OK_VHT, 1013 DM_INFO_CRC32_OK_HT, 1014 DM_INFO_CRC32_OK_LEGACY, 1015 DM_INFO_CRC32_OK_CCK, 1016 DM_INFO_CRC32_ERROR_VHT, 1017 DM_INFO_CRC32_ERROR_HT, 1018 DM_INFO_CRC32_ERROR_LEGACY, 1019 DM_INFO_CRC32_ERROR_CCK, 1020 DM_INFO_EDCCA_FLAG, 1021 DM_INFO_OFDM_ENABLE, 1022 DM_INFO_CCK_ENABLE, 1023 DM_INFO_CRC32_OK_HT_AGG, 1024 DM_INFO_CRC32_ERROR_HT_AGG, 1025 DM_INFO_DBG_PORT_0, 1026 DM_INFO_CURR_IGI, 1027 DM_INFO_RSSI_MIN, 1028 DM_INFO_RSSI_MAX, 1029 DM_INFO_CLM_RATIO, 1030 DM_INFO_NHM_RATIO, 1031 DM_INFO_IQK_ALL, 1032 DM_INFO_IQK_OK, 1033 DM_INFO_IQK_NG, 1034 DM_INFO_SIZE, 1035 }; 1036 1037 enum rx_packet_type { 1038 NORMAL_RX, 1039 TX_REPORT1, 1040 TX_REPORT2, 1041 HIS_REPORT, 1042 C2H_PACKET, 1043 }; 1044 1045 struct rtlwifi_tx_info { 1046 int sn; 1047 unsigned long send_time; 1048 }; 1049 1050 static inline struct rtlwifi_tx_info *rtl_tx_skb_cb_info(struct sk_buff *skb) 1051 { 1052 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1053 1054 BUILD_BUG_ON(sizeof(struct rtlwifi_tx_info) > 1055 sizeof(info->status.status_driver_data)); 1056 1057 return (struct rtlwifi_tx_info *)(info->status.status_driver_data); 1058 } 1059 1060 struct octet_string { 1061 u8 *octet; 1062 u16 length; 1063 }; 1064 1065 struct rtl_hdr_3addr { 1066 __le16 frame_ctl; 1067 __le16 duration_id; 1068 u8 addr1[ETH_ALEN]; 1069 u8 addr2[ETH_ALEN]; 1070 u8 addr3[ETH_ALEN]; 1071 __le16 seq_ctl; 1072 u8 payload[0]; 1073 } __packed; 1074 1075 struct rtl_info_element { 1076 u8 id; 1077 u8 len; 1078 u8 data[0]; 1079 } __packed; 1080 1081 struct rtl_probe_rsp { 1082 struct rtl_hdr_3addr header; 1083 u32 time_stamp[2]; 1084 __le16 beacon_interval; 1085 __le16 capability; 1086 /*SSID, supported rates, FH params, DS params, 1087 CF params, IBSS params, TIM (if beacon), RSN */ 1088 struct rtl_info_element info_element[0]; 1089 } __packed; 1090 1091 /*LED related.*/ 1092 /*ledpin Identify how to implement this SW led.*/ 1093 struct rtl_led { 1094 void *hw; 1095 enum rtl_led_pin ledpin; 1096 bool ledon; 1097 }; 1098 1099 struct rtl_led_ctl { 1100 bool led_opendrain; 1101 struct rtl_led sw_led0; 1102 struct rtl_led sw_led1; 1103 }; 1104 1105 struct rtl_qos_parameters { 1106 __le16 cw_min; 1107 __le16 cw_max; 1108 u8 aifs; 1109 u8 flag; 1110 __le16 tx_op; 1111 } __packed; 1112 1113 struct rt_smooth_data { 1114 u32 elements[100]; /*array to store values */ 1115 u32 index; /*index to current array to store */ 1116 u32 total_num; /*num of valid elements */ 1117 u32 total_val; /*sum of valid elements */ 1118 }; 1119 1120 struct false_alarm_statistics { 1121 u32 cnt_parity_fail; 1122 u32 cnt_rate_illegal; 1123 u32 cnt_crc8_fail; 1124 u32 cnt_mcs_fail; 1125 u32 cnt_fast_fsync_fail; 1126 u32 cnt_sb_search_fail; 1127 u32 cnt_ofdm_fail; 1128 u32 cnt_cck_fail; 1129 u32 cnt_all; 1130 u32 cnt_ofdm_cca; 1131 u32 cnt_cck_cca; 1132 u32 cnt_cca_all; 1133 u32 cnt_bw_usc; 1134 u32 cnt_bw_lsc; 1135 }; 1136 1137 struct init_gain { 1138 u8 xaagccore1; 1139 u8 xbagccore1; 1140 u8 xcagccore1; 1141 u8 xdagccore1; 1142 u8 cca; 1143 1144 }; 1145 1146 struct wireless_stats { 1147 u64 txbytesunicast; 1148 u64 txbytesmulticast; 1149 u64 txbytesbroadcast; 1150 u64 rxbytesunicast; 1151 1152 u64 txbytesunicast_inperiod; 1153 u64 rxbytesunicast_inperiod; 1154 u32 txbytesunicast_inperiod_tp; 1155 u32 rxbytesunicast_inperiod_tp; 1156 u64 txbytesunicast_last; 1157 u64 rxbytesunicast_last; 1158 1159 long rx_snr_db[4]; 1160 /*Correct smoothed ss in Dbm, only used 1161 in driver to report real power now. */ 1162 long recv_signal_power; 1163 long signal_quality; 1164 long last_sigstrength_inpercent; 1165 1166 u32 rssi_calculate_cnt; 1167 u32 pwdb_all_cnt; 1168 1169 /*Transformed, in dbm. Beautified signal 1170 strength for UI, not correct. */ 1171 long signal_strength; 1172 1173 u8 rx_rssi_percentage[4]; 1174 u8 rx_evm_dbm[4]; 1175 u8 rx_evm_percentage[2]; 1176 1177 u16 rx_cfo_short[4]; 1178 u16 rx_cfo_tail[4]; 1179 1180 struct rt_smooth_data ui_rssi; 1181 struct rt_smooth_data ui_link_quality; 1182 }; 1183 1184 struct rate_adaptive { 1185 u8 rate_adaptive_disabled; 1186 u8 ratr_state; 1187 u16 reserve; 1188 1189 u32 high_rssi_thresh_for_ra; 1190 u32 high2low_rssi_thresh_for_ra; 1191 u8 low2high_rssi_thresh_for_ra40m; 1192 u32 low_rssi_thresh_for_ra40m; 1193 u8 low2high_rssi_thresh_for_ra20m; 1194 u32 low_rssi_thresh_for_ra20m; 1195 u32 upper_rssi_threshold_ratr; 1196 u32 middleupper_rssi_threshold_ratr; 1197 u32 middle_rssi_threshold_ratr; 1198 u32 middlelow_rssi_threshold_ratr; 1199 u32 low_rssi_threshold_ratr; 1200 u32 ultralow_rssi_threshold_ratr; 1201 u32 low_rssi_threshold_ratr_40m; 1202 u32 low_rssi_threshold_ratr_20m; 1203 u8 ping_rssi_enable; 1204 u32 ping_rssi_ratr; 1205 u32 ping_rssi_thresh_for_ra; 1206 u32 last_ratr; 1207 u8 pre_ratr_state; 1208 u8 ldpc_thres; 1209 bool use_ldpc; 1210 bool lower_rts_rate; 1211 bool is_special_data; 1212 }; 1213 1214 struct regd_pair_mapping { 1215 u16 reg_dmnenum; 1216 u16 reg_5ghz_ctl; 1217 u16 reg_2ghz_ctl; 1218 }; 1219 1220 struct dynamic_primary_cca { 1221 u8 pricca_flag; 1222 u8 intf_flag; 1223 u8 intf_type; 1224 u8 dup_rts_flag; 1225 u8 monitor_flag; 1226 u8 ch_offset; 1227 u8 mf_state; 1228 }; 1229 1230 struct rtl_regulatory { 1231 s8 alpha2[2]; 1232 u16 country_code; 1233 u16 max_power_level; 1234 u32 tp_scale; 1235 u16 current_rd; 1236 u16 current_rd_ext; 1237 int16_t power_limit; 1238 struct regd_pair_mapping *regpair; 1239 }; 1240 1241 struct rtl_rfkill { 1242 bool rfkill_state; /*0 is off, 1 is on */ 1243 }; 1244 1245 /*for P2P PS**/ 1246 #define P2P_MAX_NOA_NUM 2 1247 1248 enum p2p_role { 1249 P2P_ROLE_DISABLE = 0, 1250 P2P_ROLE_DEVICE = 1, 1251 P2P_ROLE_CLIENT = 2, 1252 P2P_ROLE_GO = 3 1253 }; 1254 1255 enum p2p_ps_state { 1256 P2P_PS_DISABLE = 0, 1257 P2P_PS_ENABLE = 1, 1258 P2P_PS_SCAN = 2, 1259 P2P_PS_SCAN_DONE = 3, 1260 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1261 }; 1262 1263 enum p2p_ps_mode { 1264 P2P_PS_NONE = 0, 1265 P2P_PS_CTWINDOW = 1, 1266 P2P_PS_NOA = 2, 1267 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1268 }; 1269 1270 struct rtl_p2p_ps_info { 1271 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1272 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1273 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1274 /* Client traffic window. A period of time in TU after TBTT. */ 1275 u8 ctwindow; 1276 u8 opp_ps; /* opportunistic power save. */ 1277 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1278 /* Count for owner, Type of client. */ 1279 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1280 /* Max duration for owner, preferred or min acceptable duration 1281 * for client. 1282 */ 1283 u32 noa_duration[P2P_MAX_NOA_NUM]; 1284 /* Length of interval for owner, preferred or max acceptable intervali 1285 * of client. 1286 */ 1287 u32 noa_interval[P2P_MAX_NOA_NUM]; 1288 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1289 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1290 }; 1291 1292 struct p2p_ps_offload_t { 1293 u8 offload_en:1; 1294 u8 role:1; /* 1: Owner, 0: Client */ 1295 u8 ctwindow_en:1; 1296 u8 noa0_en:1; 1297 u8 noa1_en:1; 1298 u8 allstasleep:1; 1299 u8 discovery:1; 1300 u8 reserved:1; 1301 }; 1302 1303 #define IQK_MATRIX_REG_NUM 8 1304 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1305 1306 struct iqk_matrix_regs { 1307 bool iqk_done; 1308 long value[1][IQK_MATRIX_REG_NUM]; 1309 }; 1310 1311 struct phy_parameters { 1312 u16 length; 1313 u32 *pdata; 1314 }; 1315 1316 enum hw_param_tab_index { 1317 PHY_REG_2T, 1318 PHY_REG_1T, 1319 PHY_REG_PG, 1320 RADIOA_2T, 1321 RADIOB_2T, 1322 RADIOA_1T, 1323 RADIOB_1T, 1324 MAC_REG, 1325 AGCTAB_2T, 1326 AGCTAB_1T, 1327 MAX_TAB 1328 }; 1329 1330 struct rtl_phy { 1331 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1332 struct init_gain initgain_backup; 1333 enum io_type current_io_type; 1334 1335 u8 rf_mode; 1336 u8 rf_type; 1337 u8 current_chan_bw; 1338 u8 set_bwmode_inprogress; 1339 u8 sw_chnl_inprogress; 1340 u8 sw_chnl_stage; 1341 u8 sw_chnl_step; 1342 u8 current_channel; 1343 u8 h2c_box_num; 1344 u8 set_io_inprogress; 1345 u8 lck_inprogress; 1346 1347 /* record for power tracking */ 1348 s32 reg_e94; 1349 s32 reg_e9c; 1350 s32 reg_ea4; 1351 s32 reg_eac; 1352 s32 reg_eb4; 1353 s32 reg_ebc; 1354 s32 reg_ec4; 1355 s32 reg_ecc; 1356 u8 rfpienable; 1357 u8 reserve_0; 1358 u16 reserve_1; 1359 u32 reg_c04, reg_c08, reg_874; 1360 u32 adda_backup[16]; 1361 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1362 u32 iqk_bb_backup[10]; 1363 bool iqk_initialized; 1364 1365 bool rfpath_rx_enable[MAX_RF_PATH]; 1366 u8 reg_837; 1367 /* Dual mac */ 1368 bool need_iqk; 1369 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1370 1371 bool rfpi_enable; 1372 bool iqk_in_progress; 1373 1374 u8 pwrgroup_cnt; 1375 u8 cck_high_power; 1376 /* this is for 88E & 8723A */ 1377 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1378 /* MAX_PG_GROUP groups of pwr diff by rates */ 1379 u32 mcs_offset[MAX_PG_GROUP][16]; 1380 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1381 [TX_PWR_BY_RATE_NUM_RF] 1382 [TX_PWR_BY_RATE_NUM_RF] 1383 [TX_PWR_BY_RATE_NUM_RATE]; 1384 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1385 [TX_PWR_BY_RATE_NUM_RF] 1386 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1387 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1388 [TX_PWR_BY_RATE_NUM_RF] 1389 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1390 u8 default_initialgain[4]; 1391 1392 /* the current Tx power level */ 1393 u8 cur_cck_txpwridx; 1394 u8 cur_ofdm24g_txpwridx; 1395 u8 cur_bw20_txpwridx; 1396 u8 cur_bw40_txpwridx; 1397 1398 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1399 [MAX_2_4G_BANDWIDTH_NUM] 1400 [MAX_RATE_SECTION_NUM] 1401 [CHANNEL_MAX_NUMBER_2G] 1402 [MAX_RF_PATH_NUM]; 1403 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1404 [MAX_5G_BANDWIDTH_NUM] 1405 [MAX_RATE_SECTION_NUM] 1406 [CHANNEL_MAX_NUMBER_5G] 1407 [MAX_RF_PATH_NUM]; 1408 1409 u32 rfreg_chnlval[2]; 1410 bool apk_done; 1411 u32 reg_rf3c[2]; /* pathA / pathB */ 1412 1413 u32 backup_rf_0x1a;/*92ee*/ 1414 /* bfsync */ 1415 u8 framesync; 1416 u32 framesync_c34; 1417 1418 u8 num_total_rfpath; 1419 struct phy_parameters hwparam_tables[MAX_TAB]; 1420 u16 rf_pathmap; 1421 1422 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1423 enum rt_polarity_ctl polarity_ctl; 1424 }; 1425 1426 #define MAX_TID_COUNT 9 1427 #define RTL_AGG_STOP 0 1428 #define RTL_AGG_PROGRESS 1 1429 #define RTL_AGG_START 2 1430 #define RTL_AGG_OPERATIONAL 3 1431 #define RTL_AGG_OFF 0 1432 #define RTL_AGG_ON 1 1433 #define RTL_RX_AGG_START 1 1434 #define RTL_RX_AGG_STOP 0 1435 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1436 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1437 1438 struct rtl_ht_agg { 1439 u16 txq_id; 1440 u16 wait_for_ba; 1441 u16 start_idx; 1442 u64 bitmap; 1443 u32 rate_n_flags; 1444 u8 agg_state; 1445 u8 rx_agg_state; 1446 }; 1447 1448 struct rssi_sta { 1449 long undec_sm_pwdb; 1450 long undec_sm_cck; 1451 }; 1452 1453 struct rtl_tid_data { 1454 struct rtl_ht_agg agg; 1455 }; 1456 1457 struct rtl_sta_info { 1458 struct list_head list; 1459 struct rtl_tid_data tids[MAX_TID_COUNT]; 1460 /* just used for ap adhoc or mesh*/ 1461 struct rssi_sta rssi_stat; 1462 u8 rssi_level; 1463 u16 wireless_mode; 1464 u8 ratr_index; 1465 u8 mimo_ps; 1466 u8 mac_addr[ETH_ALEN]; 1467 } __packed; 1468 1469 struct rtl_priv; 1470 struct rtl_io { 1471 struct device *dev; 1472 struct mutex bb_mutex; 1473 1474 /*PCI MEM map */ 1475 unsigned long pci_mem_end; /*shared mem end */ 1476 unsigned long pci_mem_start; /*shared mem start */ 1477 1478 /*PCI IO map */ 1479 unsigned long pci_base_addr; /*device I/O address */ 1480 1481 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1482 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1483 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1484 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1485 u16 len); 1486 1487 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1488 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1489 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1490 1491 }; 1492 1493 struct rtl_mac { 1494 u8 mac_addr[ETH_ALEN]; 1495 u8 mac80211_registered; 1496 u8 beacon_enabled; 1497 1498 u32 tx_ss_num; 1499 u32 rx_ss_num; 1500 1501 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1502 struct ieee80211_hw *hw; 1503 struct ieee80211_vif *vif; 1504 enum nl80211_iftype opmode; 1505 1506 /*Probe Beacon management */ 1507 struct rtl_tid_data tids[MAX_TID_COUNT]; 1508 enum rtl_link_state link_state; 1509 1510 int n_channels; 1511 int n_bitrates; 1512 1513 bool offchan_delay; 1514 u8 p2p; /*using p2p role*/ 1515 bool p2p_in_use; 1516 1517 /*filters */ 1518 u32 rx_conf; 1519 u16 rx_mgt_filter; 1520 u16 rx_ctrl_filter; 1521 u16 rx_data_filter; 1522 1523 bool act_scanning; 1524 u8 cnt_after_linked; 1525 bool skip_scan; 1526 1527 /* early mode */ 1528 /* skb wait queue */ 1529 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1530 1531 u8 ht_stbc_cap; 1532 u8 ht_cur_stbc; 1533 1534 /*vht support*/ 1535 u8 vht_enable; 1536 u8 bw_80; 1537 u8 vht_cur_ldpc; 1538 u8 vht_cur_stbc; 1539 u8 vht_stbc_cap; 1540 u8 vht_ldpc_cap; 1541 1542 /*RDG*/ 1543 bool rdg_en; 1544 1545 /*AP*/ 1546 u8 bssid[ETH_ALEN] __aligned(2); 1547 u32 vendor; 1548 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1549 u32 basic_rates; /* b/g rates */ 1550 u8 ht_enable; 1551 u8 sgi_40; 1552 u8 sgi_20; 1553 u8 bw_40; 1554 u16 mode; /* wireless mode */ 1555 u8 slot_time; 1556 u8 short_preamble; 1557 u8 use_cts_protect; 1558 u8 cur_40_prime_sc; 1559 u8 cur_40_prime_sc_bk; 1560 u8 cur_80_prime_sc; 1561 u64 tsf; 1562 u8 retry_short; 1563 u8 retry_long; 1564 u16 assoc_id; 1565 bool hiddenssid; 1566 1567 /*IBSS*/ 1568 int beacon_interval; 1569 1570 /*AMPDU*/ 1571 u8 min_space_cfg; /*For Min spacing configurations */ 1572 u8 max_mss_density; 1573 u8 current_ampdu_factor; 1574 u8 current_ampdu_density; 1575 1576 /*QOS & EDCA */ 1577 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1578 struct rtl_qos_parameters ac[AC_MAX]; 1579 1580 /* counters */ 1581 u64 last_txok_cnt; 1582 u64 last_rxok_cnt; 1583 u32 last_bt_edca_ul; 1584 u32 last_bt_edca_dl; 1585 }; 1586 1587 struct btdm_8723 { 1588 bool all_off; 1589 bool agc_table_en; 1590 bool adc_back_off_on; 1591 bool b2_ant_hid_en; 1592 bool low_penalty_rate_adaptive; 1593 bool rf_rx_lpf_shrink; 1594 bool reject_aggre_pkt; 1595 bool tra_tdma_on; 1596 u8 tra_tdma_nav; 1597 u8 tra_tdma_ant; 1598 bool tdma_on; 1599 u8 tdma_ant; 1600 u8 tdma_nav; 1601 u8 tdma_dac_swing; 1602 u8 fw_dac_swing_lvl; 1603 bool ps_tdma_on; 1604 u8 ps_tdma_byte[5]; 1605 bool pta_on; 1606 u32 val_0x6c0; 1607 u32 val_0x6c8; 1608 u32 val_0x6cc; 1609 bool sw_dac_swing_on; 1610 u32 sw_dac_swing_lvl; 1611 u32 wlan_act_hi; 1612 u32 wlan_act_lo; 1613 u32 bt_retry_index; 1614 bool dec_bt_pwr; 1615 bool ignore_wlan_act; 1616 }; 1617 1618 struct bt_coexist_8723 { 1619 u32 high_priority_tx; 1620 u32 high_priority_rx; 1621 u32 low_priority_tx; 1622 u32 low_priority_rx; 1623 u8 c2h_bt_info; 1624 bool c2h_bt_info_req_sent; 1625 bool c2h_bt_inquiry_page; 1626 u32 bt_inq_page_start_time; 1627 u8 bt_retry_cnt; 1628 u8 c2h_bt_info_original; 1629 u8 bt_inquiry_page_cnt; 1630 struct btdm_8723 btdm; 1631 }; 1632 1633 struct rtl_hal { 1634 struct ieee80211_hw *hw; 1635 bool driver_is_goingto_unload; 1636 bool up_first_time; 1637 bool first_init; 1638 bool being_init_adapter; 1639 bool bbrf_ready; 1640 bool mac_func_enable; 1641 bool pre_edcca_enable; 1642 struct bt_coexist_8723 hal_coex_8723; 1643 1644 enum intf_type interface; 1645 u16 hw_type; /*92c or 92d or 92s and so on */ 1646 u8 ic_class; 1647 u8 oem_id; 1648 u32 version; /*version of chip */ 1649 u8 state; /*stop 0, start 1 */ 1650 u8 board_type; 1651 u8 package_type; 1652 u8 external_pa; 1653 1654 u8 pa_mode; 1655 u8 pa_type_2g; 1656 u8 pa_type_5g; 1657 u8 lna_type_2g; 1658 u8 lna_type_5g; 1659 u8 external_pa_2g; 1660 u8 external_lna_2g; 1661 u8 external_pa_5g; 1662 u8 external_lna_5g; 1663 u8 type_glna; 1664 u8 type_gpa; 1665 u8 type_alna; 1666 u8 type_apa; 1667 u8 rfe_type; 1668 1669 /*firmware */ 1670 u32 fwsize; 1671 u8 *pfirmware; 1672 u16 fw_version; 1673 u16 fw_subversion; 1674 bool h2c_setinprogress; 1675 u8 last_hmeboxnum; 1676 bool fw_ready; 1677 /*Reserve page start offset except beacon in TxQ. */ 1678 u8 fw_rsvdpage_startoffset; 1679 u8 h2c_txcmd_seq; 1680 u8 current_ra_rate; 1681 1682 /* FW Cmd IO related */ 1683 u16 fwcmd_iomap; 1684 u32 fwcmd_ioparam; 1685 bool set_fwcmd_inprogress; 1686 u8 current_fwcmd_io; 1687 1688 struct p2p_ps_offload_t p2p_ps_offload; 1689 bool fw_clk_change_in_progress; 1690 bool allow_sw_to_change_hwclc; 1691 u8 fw_ps_state; 1692 /**/ 1693 bool driver_going2unload; 1694 1695 /*AMPDU init min space*/ 1696 u8 minspace_cfg; /*For Min spacing configurations */ 1697 1698 /* Dual mac */ 1699 enum macphy_mode macphymode; 1700 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1701 enum band_type current_bandtypebackup; 1702 enum band_type bandset; 1703 /* dual MAC 0--Mac0 1--Mac1 */ 1704 u32 interfaceindex; 1705 /* just for DualMac S3S4 */ 1706 u8 macphyctl_reg; 1707 bool earlymode_enable; 1708 u8 max_earlymode_num; 1709 /* Dual mac*/ 1710 bool during_mac0init_radiob; 1711 bool during_mac1init_radioa; 1712 bool reloadtxpowerindex; 1713 /* True if IMR or IQK have done 1714 for 2.4G in scan progress */ 1715 bool load_imrandiqk_setting_for2g; 1716 1717 bool disable_amsdu_8k; 1718 bool master_of_dmsp; 1719 bool slave_of_dmsp; 1720 1721 u16 rx_tag;/*for 92ee*/ 1722 u8 rts_en; 1723 1724 /*for wowlan*/ 1725 bool wow_enable; 1726 bool enter_pnp_sleep; 1727 bool wake_from_pnp_sleep; 1728 bool wow_enabled; 1729 time64_t last_suspend_sec; 1730 u32 wowlan_fwsize; 1731 u8 *wowlan_firmware; 1732 1733 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1734 1735 bool real_wow_v2_enable; 1736 bool re_init_llt_table; 1737 }; 1738 1739 struct rtl_security { 1740 /*default 0 */ 1741 bool use_sw_sec; 1742 1743 bool being_setkey; 1744 bool use_defaultkey; 1745 /*Encryption Algorithm for Unicast Packet */ 1746 enum rt_enc_alg pairwise_enc_algorithm; 1747 /*Encryption Algorithm for Brocast/Multicast */ 1748 enum rt_enc_alg group_enc_algorithm; 1749 /*Cam Entry Bitmap */ 1750 u32 hwsec_cam_bitmap; 1751 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1752 /*local Key buffer, indx 0 is for 1753 pairwise key 1-4 is for agoup key. */ 1754 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1755 u8 key_len[KEY_BUF_SIZE]; 1756 1757 /*The pointer of Pairwise Key, 1758 it always points to KeyBuf[4] */ 1759 u8 *pairwise_key; 1760 }; 1761 1762 #define ASSOCIATE_ENTRY_NUM 33 1763 1764 struct fast_ant_training { 1765 u8 bssid[6]; 1766 u8 antsel_rx_keep_0; 1767 u8 antsel_rx_keep_1; 1768 u8 antsel_rx_keep_2; 1769 u32 ant_sum[7]; 1770 u32 ant_cnt[7]; 1771 u32 ant_ave[7]; 1772 u8 fat_state; 1773 u32 train_idx; 1774 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1775 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1776 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1777 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1778 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1779 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1780 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1781 u8 rx_idle_ant; 1782 bool becomelinked; 1783 }; 1784 1785 struct dm_phy_dbg_info { 1786 s8 rx_snrdb[4]; 1787 u64 num_qry_phy_status; 1788 u64 num_qry_phy_status_cck; 1789 u64 num_qry_phy_status_ofdm; 1790 u16 num_qry_beacon_pkt; 1791 u16 num_non_be_pkt; 1792 s32 rx_evm[4]; 1793 }; 1794 1795 struct rtl_dm { 1796 /*PHY status for Dynamic Management */ 1797 long entry_min_undec_sm_pwdb; 1798 long undec_sm_cck; 1799 long undec_sm_pwdb; /*out dm */ 1800 long entry_max_undec_sm_pwdb; 1801 s32 ofdm_pkt_cnt; 1802 bool dm_initialgain_enable; 1803 bool dynamic_txpower_enable; 1804 bool current_turbo_edca; 1805 bool is_any_nonbepkts; /*out dm */ 1806 bool is_cur_rdlstate; 1807 bool txpower_trackinginit; 1808 bool disable_framebursting; 1809 bool cck_inch14; 1810 bool txpower_tracking; 1811 bool useramask; 1812 bool rfpath_rxenable[4]; 1813 bool inform_fw_driverctrldm; 1814 bool current_mrc_switch; 1815 u8 txpowercount; 1816 u8 powerindex_backup[6]; 1817 1818 u8 thermalvalue_rxgain; 1819 u8 thermalvalue_iqk; 1820 u8 thermalvalue_lck; 1821 u8 thermalvalue; 1822 u8 last_dtp_lvl; 1823 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1824 u8 thermalvalue_avg_index; 1825 u8 tm_trigger; 1826 bool done_txpower; 1827 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1828 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1829 u8 dm_flag_tmp; 1830 u8 dm_type; 1831 u8 dm_rssi_sel; 1832 u8 txpower_track_control; 1833 bool interrupt_migration; 1834 bool disable_tx_int; 1835 s8 ofdm_index[MAX_RF_PATH]; 1836 u8 default_ofdm_index; 1837 u8 default_cck_index; 1838 s8 cck_index; 1839 s8 delta_power_index[MAX_RF_PATH]; 1840 s8 delta_power_index_last[MAX_RF_PATH]; 1841 s8 power_index_offset[MAX_RF_PATH]; 1842 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1843 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1844 s8 remnant_cck_idx; 1845 bool modify_txagc_flag_path_a; 1846 bool modify_txagc_flag_path_b; 1847 1848 bool one_entry_only; 1849 struct dm_phy_dbg_info dbginfo; 1850 1851 /* Dynamic ATC switch */ 1852 bool atc_status; 1853 bool large_cfo_hit; 1854 bool is_freeze; 1855 int cfo_tail[2]; 1856 int cfo_ave_pre; 1857 int crystal_cap; 1858 u8 cfo_threshold; 1859 u32 packet_count; 1860 u32 packet_count_pre; 1861 u8 tx_rate; 1862 1863 /*88e tx power tracking*/ 1864 u8 swing_idx_ofdm[MAX_RF_PATH]; 1865 u8 swing_idx_ofdm_cur; 1866 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1867 bool swing_flag_ofdm; 1868 u8 swing_idx_cck; 1869 u8 swing_idx_cck_cur; 1870 u8 swing_idx_cck_base; 1871 bool swing_flag_cck; 1872 1873 s8 swing_diff_2g; 1874 s8 swing_diff_5g; 1875 1876 /* DMSP */ 1877 bool supp_phymode_switch; 1878 1879 /* DulMac */ 1880 struct fast_ant_training fat_table; 1881 1882 u8 resp_tx_path; 1883 u8 path_sel; 1884 u32 patha_sum; 1885 u32 pathb_sum; 1886 u32 patha_cnt; 1887 u32 pathb_cnt; 1888 1889 u8 pre_channel; 1890 u8 *p_channel; 1891 u8 linked_interval; 1892 1893 u64 last_tx_ok_cnt; 1894 u64 last_rx_ok_cnt; 1895 }; 1896 1897 #define EFUSE_MAX_LOGICAL_SIZE 512 1898 1899 struct rtl_efuse { 1900 const struct rtl_efuse_ops *efuse_ops; 1901 bool autoLoad_ok; 1902 bool bootfromefuse; 1903 u16 max_physical_size; 1904 1905 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1906 u16 efuse_usedbytes; 1907 u8 efuse_usedpercentage; 1908 1909 u8 autoload_failflag; 1910 u8 autoload_status; 1911 1912 short epromtype; 1913 u16 eeprom_vid; 1914 u16 eeprom_did; 1915 u16 eeprom_svid; 1916 u16 eeprom_smid; 1917 u8 eeprom_oemid; 1918 u16 eeprom_channelplan; 1919 u8 eeprom_version; 1920 u8 board_type; 1921 u8 external_pa; 1922 1923 u8 dev_addr[6]; 1924 u8 wowlan_enable; 1925 u8 antenna_div_cfg; 1926 u8 antenna_div_type; 1927 1928 bool txpwr_fromeprom; 1929 u8 eeprom_crystalcap; 1930 u8 eeprom_tssi[2]; 1931 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1932 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1933 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1934 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1935 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1936 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1937 1938 u8 internal_pa_5g[2]; /* pathA / pathB */ 1939 u8 eeprom_c9; 1940 u8 eeprom_cc; 1941 1942 /*For power group */ 1943 u8 eeprom_pwrgroup[2][3]; 1944 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1945 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1946 1947 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1948 /*For HT 40MHZ pwr */ 1949 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1950 /*For HT 40MHZ pwr */ 1951 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1952 1953 /*--------------------------------------------------------* 1954 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1955 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1956 * define new arrays in Windows code. 1957 * BUT, in linux code, we use the same array for all ICs. 1958 * 1959 * The Correspondance relation between two arrays is: 1960 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1961 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1962 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1963 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1964 * 1965 * Sizes of these arrays are decided by the larger ones. 1966 */ 1967 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1968 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1969 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1970 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1971 1972 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1973 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1974 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1975 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1976 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1977 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1978 1979 u8 txpwr_safetyflag; /* Band edge enable flag */ 1980 u16 eeprom_txpowerdiff; 1981 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1982 u8 antenna_txpwdiff[3]; 1983 1984 u8 eeprom_regulatory; 1985 u8 eeprom_thermalmeter; 1986 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1987 u16 tssi_13dbm; 1988 u8 crystalcap; /* CrystalCap. */ 1989 u8 delta_iqk; 1990 u8 delta_lck; 1991 1992 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1993 bool apk_thermalmeterignore; 1994 1995 bool b1x1_recvcombine; 1996 bool b1ss_support; 1997 1998 /*channel plan */ 1999 u8 channel_plan; 2000 }; 2001 2002 struct rtl_efuse_ops { 2003 int (*efuse_onebyte_read)(struct ieee80211_hw *hw, u16 addr, u8 *data); 2004 void (*efuse_logical_map_read)(struct ieee80211_hw *hw, u8 type, 2005 u16 offset, u32 *value); 2006 }; 2007 2008 struct rtl_tx_report { 2009 atomic_t sn; 2010 u16 last_sent_sn; 2011 unsigned long last_sent_time; 2012 u16 last_recv_sn; 2013 struct sk_buff_head queue; 2014 }; 2015 2016 struct rtl_ps_ctl { 2017 bool pwrdomain_protect; 2018 bool in_powersavemode; 2019 bool rfchange_inprogress; 2020 bool swrf_processing; 2021 bool hwradiooff; 2022 /* 2023 * just for PCIE ASPM 2024 * If it supports ASPM, Offset[560h] = 0x40, 2025 * otherwise Offset[560h] = 0x00. 2026 * */ 2027 bool support_aspm; 2028 bool support_backdoor; 2029 2030 /*for LPS */ 2031 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 2032 bool swctrl_lps; 2033 bool leisure_ps; 2034 bool fwctrl_lps; 2035 u8 fwctrl_psmode; 2036 /*For Fw control LPS mode */ 2037 u8 reg_fwctrl_lps; 2038 /*Record Fw PS mode status. */ 2039 bool fw_current_inpsmode; 2040 u8 reg_max_lps_awakeintvl; 2041 bool report_linked; 2042 bool low_power_enable;/*for 32k*/ 2043 2044 /*for IPS */ 2045 bool inactiveps; 2046 2047 u32 rfoff_reason; 2048 2049 /*RF OFF Level */ 2050 u32 cur_ps_level; 2051 u32 reg_rfps_level; 2052 2053 /*just for PCIE ASPM */ 2054 u8 const_amdpci_aspm; 2055 bool pwrdown_mode; 2056 2057 enum rf_pwrstate inactive_pwrstate; 2058 enum rf_pwrstate rfpwr_state; /*cur power state */ 2059 2060 /* for SW LPS*/ 2061 bool sw_ps_enabled; 2062 bool state; 2063 bool state_inap; 2064 bool multi_buffered; 2065 u16 nullfunc_seq; 2066 unsigned int dtim_counter; 2067 unsigned int sleep_ms; 2068 unsigned long last_sleep_jiffies; 2069 unsigned long last_awake_jiffies; 2070 unsigned long last_delaylps_stamp_jiffies; 2071 unsigned long last_dtim; 2072 unsigned long last_beacon; 2073 unsigned long last_action; 2074 unsigned long last_slept; 2075 2076 /*For P2P PS */ 2077 struct rtl_p2p_ps_info p2p_ps_info; 2078 u8 pwr_mode; 2079 u8 smart_ps; 2080 2081 /* wake up on line */ 2082 u8 wo_wlan_mode; 2083 u8 arp_offload_enable; 2084 u8 gtk_offload_enable; 2085 /* Used for WOL, indicates the reason for waking event.*/ 2086 u32 wakeup_reason; 2087 }; 2088 2089 struct rtl_stats { 2090 u8 psaddr[ETH_ALEN]; 2091 u32 mac_time[2]; 2092 s8 rssi; 2093 u8 signal; 2094 u8 noise; 2095 u8 rate; /* hw desc rate */ 2096 u8 received_channel; 2097 u8 control; 2098 u8 mask; 2099 u8 freq; 2100 u16 len; 2101 u64 tsf; 2102 u32 beacon_time; 2103 u8 nic_type; 2104 u16 length; 2105 u8 signalquality; /*in 0-100 index. */ 2106 /* 2107 * Real power in dBm for this packet, 2108 * no beautification and aggregation. 2109 * */ 2110 s32 recvsignalpower; 2111 s8 rxpower; /*in dBm Translate from PWdB */ 2112 u8 signalstrength; /*in 0-100 index. */ 2113 u16 hwerror:1; 2114 u16 crc:1; 2115 u16 icv:1; 2116 u16 shortpreamble:1; 2117 u16 antenna:1; 2118 u16 decrypted:1; 2119 u16 wakeup:1; 2120 u32 timestamp_low; 2121 u32 timestamp_high; 2122 bool shift; 2123 2124 u8 rx_drvinfo_size; 2125 u8 rx_bufshift; 2126 bool isampdu; 2127 bool isfirst_ampdu; 2128 bool rx_is40Mhzpacket; 2129 u8 rx_packet_bw; 2130 u32 rx_pwdb_all; 2131 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2132 s8 rx_mimo_signalquality[4]; 2133 u8 rx_mimo_evm_dbm[4]; 2134 u16 cfo_short[4]; /* per-path's Cfo_short */ 2135 u16 cfo_tail[4]; 2136 2137 s8 rx_mimo_sig_qual[4]; 2138 u8 rx_pwr[4]; /* per-path's pwdb */ 2139 u8 rx_snr[4]; /* per-path's SNR */ 2140 u8 bandwidth; 2141 u8 bt_coex_pwr_adjust; 2142 bool packet_matchbssid; 2143 bool is_cck; 2144 bool is_ht; 2145 bool packet_toself; 2146 bool packet_beacon; /*for rssi */ 2147 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2148 2149 bool is_vht; 2150 bool is_short_gi; 2151 u8 vht_nss; 2152 2153 u8 packet_report_type; 2154 2155 u32 macid; 2156 u8 wake_match; 2157 u32 bt_rx_rssi_percentage; 2158 u32 macid_valid_entry[2]; 2159 }; 2160 2161 2162 struct rt_link_detect { 2163 /* count for roaming */ 2164 u32 bcn_rx_inperiod; 2165 u32 roam_times; 2166 2167 u32 num_tx_in4period[4]; 2168 u32 num_rx_in4period[4]; 2169 2170 u32 num_tx_inperiod; 2171 u32 num_rx_inperiod; 2172 2173 bool busytraffic; 2174 bool tx_busy_traffic; 2175 bool rx_busy_traffic; 2176 bool higher_busytraffic; 2177 bool higher_busyrxtraffic; 2178 2179 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2180 u32 tidtx_inperiod[MAX_TID_COUNT]; 2181 bool higher_busytxtraffic[MAX_TID_COUNT]; 2182 }; 2183 2184 struct rtl_tcb_desc { 2185 u8 packet_bw:2; 2186 u8 multicast:1; 2187 u8 broadcast:1; 2188 2189 u8 rts_stbc:1; 2190 u8 rts_enable:1; 2191 u8 cts_enable:1; 2192 u8 rts_use_shortpreamble:1; 2193 u8 rts_use_shortgi:1; 2194 u8 rts_sc:1; 2195 u8 rts_bw:1; 2196 u8 rts_rate; 2197 2198 u8 use_shortgi:1; 2199 u8 use_shortpreamble:1; 2200 u8 use_driver_rate:1; 2201 u8 disable_ratefallback:1; 2202 2203 u8 use_spe_rpt:1; 2204 2205 u8 ratr_index; 2206 u8 mac_id; 2207 u8 hw_rate; 2208 2209 u8 last_inipkt:1; 2210 u8 cmd_or_init:1; 2211 u8 queue_index; 2212 2213 /* early mode */ 2214 u8 empkt_num; 2215 /* The max value by HW */ 2216 u32 empkt_len[10]; 2217 bool tx_enable_sw_calc_duration; 2218 }; 2219 2220 struct rtl_wow_pattern { 2221 u8 type; 2222 u16 crc; 2223 u32 mask[4]; 2224 }; 2225 2226 /* struct to store contents of interrupt vectors */ 2227 struct rtl_int { 2228 u32 inta; 2229 u32 intb; 2230 u32 intc; 2231 u32 intd; 2232 }; 2233 2234 struct rtl_hal_ops { 2235 int (*init_sw_vars) (struct ieee80211_hw *hw); 2236 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2237 void (*read_chip_version)(struct ieee80211_hw *hw); 2238 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2239 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2240 struct rtl_int *intvec); 2241 int (*hw_init) (struct ieee80211_hw *hw); 2242 void (*hw_disable) (struct ieee80211_hw *hw); 2243 void (*hw_suspend) (struct ieee80211_hw *hw); 2244 void (*hw_resume) (struct ieee80211_hw *hw); 2245 void (*enable_interrupt) (struct ieee80211_hw *hw); 2246 void (*disable_interrupt) (struct ieee80211_hw *hw); 2247 int (*set_network_type) (struct ieee80211_hw *hw, 2248 enum nl80211_iftype type); 2249 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2250 bool check_bssid); 2251 void (*set_bw_mode) (struct ieee80211_hw *hw, 2252 enum nl80211_channel_type ch_type); 2253 u8(*switch_channel) (struct ieee80211_hw *hw); 2254 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2255 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2256 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2257 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2258 u32 add_msr, u32 rm_msr); 2259 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2260 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2261 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2262 struct ieee80211_sta *sta, u8 rssi_leve, 2263 bool update_bw); 2264 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2265 u8 *desc, u8 queue_index, 2266 struct sk_buff *skb, dma_addr_t addr); 2267 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2268 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2269 u8 queue_index); 2270 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2271 u8 queue_index); 2272 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2273 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2274 u8 *pbd_desc_tx, 2275 struct ieee80211_tx_info *info, 2276 struct ieee80211_sta *sta, 2277 struct sk_buff *skb, u8 hw_queue, 2278 struct rtl_tcb_desc *ptcb_desc); 2279 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2280 u32 buffer_len, bool bIsPsPoll); 2281 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2282 bool firstseg, bool lastseg, 2283 struct sk_buff *skb); 2284 void (*fill_tx_special_desc)(struct ieee80211_hw *hw, 2285 u8 *pdesc, u8 *pbd_desc, 2286 struct sk_buff *skb, u8 hw_queue); 2287 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2288 struct rtl_stats *stats, 2289 struct ieee80211_rx_status *rx_status, 2290 u8 *pdesc, struct sk_buff *skb); 2291 void (*set_channel_access) (struct ieee80211_hw *hw); 2292 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2293 void (*dm_watchdog) (struct ieee80211_hw *hw); 2294 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2295 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2296 enum rf_pwrstate rfpwr_state); 2297 void (*led_control) (struct ieee80211_hw *hw, 2298 enum led_ctl_mode ledaction); 2299 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2300 u8 desc_name, u8 *val); 2301 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2302 u8 desc_name); 2303 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2304 u8 hw_queue, u16 index); 2305 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2306 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2307 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2308 u8 *macaddr, bool is_group, u8 enc_algo, 2309 bool is_wepkey, bool clear_all); 2310 void (*init_sw_leds) (struct ieee80211_hw *hw); 2311 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2312 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2313 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2314 u32 data); 2315 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2316 u32 regaddr, u32 bitmask); 2317 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2318 u32 regaddr, u32 bitmask, u32 data); 2319 void (*linked_set_reg) (struct ieee80211_hw *hw); 2320 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2321 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2322 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2323 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2324 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2325 u8 *powerlevel); 2326 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2327 u8 *ppowerlevel, u8 channel); 2328 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2329 u8 configtype); 2330 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2331 u8 configtype); 2332 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2333 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2334 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2335 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2336 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2337 bool mstate); 2338 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2339 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2340 u32 cmd_len, u8 *p_cmdbuffer); 2341 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw); 2342 bool (*get_btc_status) (void); 2343 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2344 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2345 struct rtl_wow_pattern *rtl_pattern, 2346 u8 index); 2347 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2348 void (*c2h_ra_report_handler)(struct ieee80211_hw *hw, 2349 u8 *cmd_buf, u8 cmd_len); 2350 }; 2351 2352 struct rtl_intf_ops { 2353 /*com */ 2354 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2355 int (*adapter_start) (struct ieee80211_hw *hw); 2356 void (*adapter_stop) (struct ieee80211_hw *hw); 2357 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2358 struct rtl_priv **buddy_priv); 2359 2360 int (*adapter_tx) (struct ieee80211_hw *hw, 2361 struct ieee80211_sta *sta, 2362 struct sk_buff *skb, 2363 struct rtl_tcb_desc *ptcb_desc); 2364 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2365 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2366 bool (*waitq_insert) (struct ieee80211_hw *hw, 2367 struct ieee80211_sta *sta, 2368 struct sk_buff *skb); 2369 2370 /*pci */ 2371 void (*disable_aspm) (struct ieee80211_hw *hw); 2372 void (*enable_aspm) (struct ieee80211_hw *hw); 2373 2374 /*usb */ 2375 }; 2376 2377 struct rtl_mod_params { 2378 /* default: 0,0 */ 2379 u64 debug_mask; 2380 /* default: 0 = using hardware encryption */ 2381 bool sw_crypto; 2382 2383 /* default: 0 = DBG_EMERG (0)*/ 2384 int debug_level; 2385 2386 /* default: 1 = using no linked power save */ 2387 bool inactiveps; 2388 2389 /* default: 1 = using linked sw power save */ 2390 bool swctrl_lps; 2391 2392 /* default: 1 = using linked fw power save */ 2393 bool fwctrl_lps; 2394 2395 /* default: 0 = not using MSI interrupts mode 2396 * submodules should set their own default value 2397 */ 2398 bool msi_support; 2399 2400 /* default: 0 = dma 32 */ 2401 bool dma64; 2402 2403 /* default: 1 = enable aspm */ 2404 int aspm_support; 2405 2406 /* default 0: 1 means disable */ 2407 bool disable_watchdog; 2408 2409 /* default 0: 1 means do not disable interrupts */ 2410 bool int_clear; 2411 2412 /* select antenna */ 2413 int ant_sel; 2414 }; 2415 2416 struct rtl_hal_usbint_cfg { 2417 /* data - rx */ 2418 u32 in_ep_num; 2419 u32 rx_urb_num; 2420 u32 rx_max_size; 2421 2422 /* op - rx */ 2423 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2424 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2425 struct sk_buff_head *); 2426 2427 /* tx */ 2428 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2429 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2430 struct sk_buff *); 2431 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2432 struct sk_buff_head *); 2433 2434 /* endpoint mapping */ 2435 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2436 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2437 }; 2438 2439 struct rtl_hal_cfg { 2440 u8 bar_id; 2441 bool write_readback; 2442 char *name; 2443 char *alt_fw_name; 2444 struct rtl_hal_ops *ops; 2445 struct rtl_mod_params *mod_params; 2446 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2447 enum rtl_spec_ver spec_ver; 2448 2449 /*this map used for some registers or vars 2450 defined int HAL but used in MAIN */ 2451 u32 maps[RTL_VAR_MAP_MAX]; 2452 2453 }; 2454 2455 struct rtl_locks { 2456 /* mutex */ 2457 struct mutex conf_mutex; 2458 struct mutex ips_mutex; /* mutex for enter/leave IPS */ 2459 struct mutex lps_mutex; /* mutex for enter/leave LPS */ 2460 2461 /*spin lock */ 2462 spinlock_t irq_th_lock; 2463 spinlock_t h2c_lock; 2464 spinlock_t rf_ps_lock; 2465 spinlock_t rf_lock; 2466 spinlock_t waitq_lock; 2467 spinlock_t entry_list_lock; 2468 spinlock_t usb_lock; 2469 spinlock_t c2hcmd_lock; 2470 spinlock_t scan_list_lock; /* lock for the scan list */ 2471 2472 /*FW clock change */ 2473 spinlock_t fw_ps_lock; 2474 2475 /*Dual mac*/ 2476 spinlock_t cck_and_rw_pagea_lock; 2477 2478 spinlock_t iqk_lock; 2479 }; 2480 2481 struct rtl_works { 2482 struct ieee80211_hw *hw; 2483 2484 /*timer */ 2485 struct timer_list watchdog_timer; 2486 struct timer_list dualmac_easyconcurrent_retrytimer; 2487 struct timer_list fw_clockoff_timer; 2488 struct timer_list fast_antenna_training_timer; 2489 /*task */ 2490 struct tasklet_struct irq_tasklet; 2491 struct tasklet_struct irq_prepare_bcn_tasklet; 2492 2493 /*work queue */ 2494 struct workqueue_struct *rtl_wq; 2495 struct delayed_work watchdog_wq; 2496 struct delayed_work ips_nic_off_wq; 2497 struct delayed_work c2hcmd_wq; 2498 2499 /* For SW LPS */ 2500 struct delayed_work ps_work; 2501 struct delayed_work ps_rfon_wq; 2502 struct delayed_work fwevt_wq; 2503 2504 struct work_struct lps_change_work; 2505 struct work_struct fill_h2c_cmd; 2506 }; 2507 2508 struct rtl_debug { 2509 /* add for debug */ 2510 struct dentry *debugfs_dir; 2511 char debugfs_name[20]; 2512 }; 2513 2514 #define MIMO_PS_STATIC 0 2515 #define MIMO_PS_DYNAMIC 1 2516 #define MIMO_PS_NOLIMIT 3 2517 2518 struct rtl_dualmac_easy_concurrent_ctl { 2519 enum band_type currentbandtype_backfordmdp; 2520 bool close_bbandrf_for_dmsp; 2521 bool change_to_dmdp; 2522 bool change_to_dmsp; 2523 bool switch_in_process; 2524 }; 2525 2526 struct rtl_dmsp_ctl { 2527 bool activescan_for_slaveofdmsp; 2528 bool scan_for_anothermac_fordmsp; 2529 bool scan_for_itself_fordmsp; 2530 bool writedig_for_anothermacofdmsp; 2531 u32 curdigvalue_for_anothermacofdmsp; 2532 bool changecckpdstate_for_anothermacofdmsp; 2533 u8 curcckpdstate_for_anothermacofdmsp; 2534 bool changetxhighpowerlvl_for_anothermacofdmsp; 2535 u8 curtxhighlvl_for_anothermacofdmsp; 2536 long rssivalmin_for_anothermacofdmsp; 2537 }; 2538 2539 struct ps_t { 2540 u8 pre_ccastate; 2541 u8 cur_ccasate; 2542 u8 pre_rfstate; 2543 u8 cur_rfstate; 2544 u8 initialize; 2545 long rssi_val_min; 2546 }; 2547 2548 struct dig_t { 2549 u32 rssi_lowthresh; 2550 u32 rssi_highthresh; 2551 u32 fa_lowthresh; 2552 u32 fa_highthresh; 2553 long last_min_undec_pwdb_for_dm; 2554 long rssi_highpower_lowthresh; 2555 long rssi_highpower_highthresh; 2556 u32 recover_cnt; 2557 u32 pre_igvalue; 2558 u32 cur_igvalue; 2559 long rssi_val; 2560 u8 dig_enable_flag; 2561 u8 dig_ext_port_stage; 2562 u8 dig_algorithm; 2563 u8 dig_twoport_algorithm; 2564 u8 dig_dbgmode; 2565 u8 dig_slgorithm_switch; 2566 u8 cursta_cstate; 2567 u8 presta_cstate; 2568 u8 curmultista_cstate; 2569 u8 stop_dig; 2570 s8 back_val; 2571 s8 back_range_max; 2572 s8 back_range_min; 2573 u8 rx_gain_max; 2574 u8 rx_gain_min; 2575 u8 min_undec_pwdb_for_dm; 2576 u8 rssi_val_min; 2577 u8 pre_cck_cca_thres; 2578 u8 cur_cck_cca_thres; 2579 u8 pre_cck_pd_state; 2580 u8 cur_cck_pd_state; 2581 u8 pre_cck_fa_state; 2582 u8 cur_cck_fa_state; 2583 u8 pre_ccastate; 2584 u8 cur_ccasate; 2585 u8 large_fa_hit; 2586 u8 forbidden_igi; 2587 u8 dig_state; 2588 u8 dig_highpwrstate; 2589 u8 cur_sta_cstate; 2590 u8 pre_sta_cstate; 2591 u8 cur_ap_cstate; 2592 u8 pre_ap_cstate; 2593 u8 cur_pd_thstate; 2594 u8 pre_pd_thstate; 2595 u8 cur_cs_ratiostate; 2596 u8 pre_cs_ratiostate; 2597 u8 backoff_enable_flag; 2598 s8 backoffval_range_max; 2599 s8 backoffval_range_min; 2600 u8 dig_min_0; 2601 u8 dig_min_1; 2602 u8 bt30_cur_igi; 2603 bool media_connect_0; 2604 bool media_connect_1; 2605 2606 u32 antdiv_rssi_max; 2607 u32 rssi_max; 2608 }; 2609 2610 struct rtl_global_var { 2611 /* from this list we can get 2612 * other adapter's rtl_priv */ 2613 struct list_head glb_priv_list; 2614 spinlock_t glb_list_lock; 2615 }; 2616 2617 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */ 2618 2619 struct rtl_btc_info { 2620 u8 bt_type; 2621 u8 btcoexist; 2622 u8 ant_num; 2623 u8 single_ant_path; 2624 2625 u8 ap_num; 2626 bool in_4way; 2627 unsigned long in_4way_ts; 2628 }; 2629 2630 struct bt_coexist_info { 2631 struct rtl_btc_ops *btc_ops; 2632 struct rtl_btc_info btc_info; 2633 /* btc context */ 2634 void *btc_context; 2635 void *wifi_only_context; 2636 /* EEPROM BT info. */ 2637 u8 eeprom_bt_coexist; 2638 u8 eeprom_bt_type; 2639 u8 eeprom_bt_ant_num; 2640 u8 eeprom_bt_ant_isol; 2641 u8 eeprom_bt_radio_shared; 2642 2643 u8 bt_coexistence; 2644 u8 bt_ant_num; 2645 u8 bt_coexist_type; 2646 u8 bt_state; 2647 u8 bt_cur_state; /* 0:on, 1:off */ 2648 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2649 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2650 u8 bt_service; 2651 u8 bt_radio_shared_type; 2652 u8 bt_rfreg_origin_1e; 2653 u8 bt_rfreg_origin_1f; 2654 u8 bt_rssi_state; 2655 u32 ratio_tx; 2656 u32 ratio_pri; 2657 u32 bt_edca_ul; 2658 u32 bt_edca_dl; 2659 2660 bool init_set; 2661 bool bt_busy_traffic; 2662 bool bt_traffic_mode_set; 2663 bool bt_non_traffic_mode_set; 2664 2665 bool fw_coexist_all_off; 2666 bool sw_coexist_all_off; 2667 bool hw_coexist_all_off; 2668 u32 cstate; 2669 u32 previous_state; 2670 u32 cstate_h; 2671 u32 previous_state_h; 2672 2673 u8 bt_pre_rssi_state; 2674 u8 bt_pre_rssi_state1; 2675 2676 u8 reg_bt_iso; 2677 u8 reg_bt_sco; 2678 bool balance_on; 2679 u8 bt_active_zero_cnt; 2680 bool cur_bt_disabled; 2681 bool pre_bt_disabled; 2682 2683 u8 bt_profile_case; 2684 u8 bt_profile_action; 2685 bool bt_busy; 2686 bool hold_for_bt_operation; 2687 u8 lps_counter; 2688 }; 2689 2690 struct rtl_btc_ops { 2691 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2692 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv); 2693 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv); 2694 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2695 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv); 2696 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2697 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv); 2698 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2699 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2700 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2701 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv, 2702 u8 scantype); 2703 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2704 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2705 enum rt_media_status mstatus); 2706 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2707 void (*btc_halt_notify)(struct rtl_priv *rtlpriv); 2708 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2709 u8 *tmp_buf, u8 length); 2710 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv, 2711 u8 *tmp_buf, u8 length); 2712 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2713 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2714 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2715 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2716 u8 pkt_type); 2717 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type, 2718 bool scanning); 2719 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv, 2720 u8 type, bool scanning); 2721 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv, 2722 struct seq_file *m); 2723 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len); 2724 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv); 2725 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv); 2726 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv); 2727 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg, 2728 u8 *ctrl_agg_size, u8 *agg_size); 2729 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv); 2730 }; 2731 2732 struct proxim { 2733 bool proxim_on; 2734 2735 void *proximity_priv; 2736 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2737 struct sk_buff *skb); 2738 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2739 }; 2740 2741 struct rtl_c2hcmd { 2742 struct list_head list; 2743 u8 tag; 2744 u8 len; 2745 u8 *val; 2746 }; 2747 2748 struct rtl_bssid_entry { 2749 struct list_head list; 2750 u8 bssid[ETH_ALEN]; 2751 u32 age; 2752 }; 2753 2754 struct rtl_scan_list { 2755 int num; 2756 struct list_head list; /* sort by age */ 2757 }; 2758 2759 struct rtl_priv { 2760 struct ieee80211_hw *hw; 2761 struct completion firmware_loading_complete; 2762 struct list_head list; 2763 struct rtl_priv *buddy_priv; 2764 struct rtl_global_var *glb_var; 2765 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2766 struct rtl_dmsp_ctl dmsp_ctl; 2767 struct rtl_locks locks; 2768 struct rtl_works works; 2769 struct rtl_mac mac80211; 2770 struct rtl_hal rtlhal; 2771 struct rtl_regulatory regd; 2772 struct rtl_rfkill rfkill; 2773 struct rtl_io io; 2774 struct rtl_phy phy; 2775 struct rtl_dm dm; 2776 struct rtl_security sec; 2777 struct rtl_efuse efuse; 2778 struct rtl_led_ctl ledctl; 2779 struct rtl_tx_report tx_report; 2780 struct rtl_scan_list scan_list; 2781 2782 struct rtl_ps_ctl psc; 2783 struct rate_adaptive ra; 2784 struct dynamic_primary_cca primarycca; 2785 struct wireless_stats stats; 2786 struct rt_link_detect link_info; 2787 struct false_alarm_statistics falsealm_cnt; 2788 2789 struct rtl_rate_priv *rate_priv; 2790 2791 /* sta entry list for ap adhoc or mesh */ 2792 struct list_head entry_list; 2793 2794 /* c2hcmd list for kthread level access */ 2795 struct sk_buff_head c2hcmd_queue; 2796 2797 struct rtl_debug dbg; 2798 int max_fw_size; 2799 2800 /* 2801 *hal_cfg : for diff cards 2802 *intf_ops : for diff interrface usb/pcie 2803 */ 2804 struct rtl_hal_cfg *cfg; 2805 const struct rtl_intf_ops *intf_ops; 2806 2807 /*this var will be set by set_bit, 2808 and was used to indicate status of 2809 interface or hardware */ 2810 unsigned long status; 2811 2812 /* tables for dm */ 2813 struct dig_t dm_digtable; 2814 struct ps_t dm_pstable; 2815 2816 u32 reg_874; 2817 u32 reg_c70; 2818 u32 reg_85c; 2819 u32 reg_a74; 2820 bool reg_init; /* true if regs saved */ 2821 bool bt_operation_on; 2822 __le32 *usb_data; 2823 int usb_data_index; 2824 bool initialized; 2825 bool enter_ps; /* true when entering PS */ 2826 u8 rate_mask[5]; 2827 2828 /* intel Proximity, should be alloc mem 2829 * in intel Proximity module and can only 2830 * be used in intel Proximity mode 2831 */ 2832 struct proxim proximity; 2833 2834 /*for bt coexist use*/ 2835 struct bt_coexist_info btcoexist; 2836 2837 /* separate 92ee from other ICs, 2838 * 92ee use new trx flow. 2839 */ 2840 bool use_new_trx_flow; 2841 2842 #ifdef CONFIG_PM 2843 struct wiphy_wowlan_support wowlan; 2844 #endif 2845 /*This must be the last item so 2846 that it points to the data allocated 2847 beyond this structure like: 2848 rtl_pci_priv or rtl_usb_priv */ 2849 u8 priv[0] __aligned(sizeof(void *)); 2850 }; 2851 2852 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2853 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2854 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2855 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2856 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2857 2858 2859 /*************************************** 2860 Bluetooth Co-existence Related 2861 ****************************************/ 2862 2863 enum bt_ant_num { 2864 ANT_X2 = 0, 2865 ANT_X1 = 1, 2866 }; 2867 2868 enum bt_ant_path { 2869 ANT_MAIN = 0, 2870 ANT_AUX = 1, 2871 }; 2872 2873 enum bt_co_type { 2874 BT_2WIRE = 0, 2875 BT_ISSC_3WIRE = 1, 2876 BT_ACCEL = 2, 2877 BT_CSR_BC4 = 3, 2878 BT_CSR_BC8 = 4, 2879 BT_RTL8756 = 5, 2880 BT_RTL8723A = 6, 2881 BT_RTL8821A = 7, 2882 BT_RTL8723B = 8, 2883 BT_RTL8192E = 9, 2884 BT_RTL8812A = 11, 2885 }; 2886 2887 enum bt_cur_state { 2888 BT_OFF = 0, 2889 BT_ON = 1, 2890 }; 2891 2892 enum bt_service_type { 2893 BT_SCO = 0, 2894 BT_A2DP = 1, 2895 BT_HID = 2, 2896 BT_HID_IDLE = 3, 2897 BT_SCAN = 4, 2898 BT_IDLE = 5, 2899 BT_OTHER_ACTION = 6, 2900 BT_BUSY = 7, 2901 BT_OTHERBUSY = 8, 2902 BT_PAN = 9, 2903 }; 2904 2905 enum bt_radio_shared { 2906 BT_RADIO_SHARED = 0, 2907 BT_RADIO_INDIVIDUAL = 1, 2908 }; 2909 2910 2911 /**************************************** 2912 mem access macro define start 2913 Call endian free function when 2914 1. Read/write packet content. 2915 2. Before write integer to IO. 2916 3. After read integer from IO. 2917 ****************************************/ 2918 /* Convert little data endian to host ordering */ 2919 #define EF1BYTE(_val) \ 2920 ((u8)(_val)) 2921 #define EF2BYTE(_val) \ 2922 (le16_to_cpu(_val)) 2923 #define EF4BYTE(_val) \ 2924 (le32_to_cpu(_val)) 2925 2926 /* Read data from memory */ 2927 #define READEF1BYTE(_ptr) \ 2928 EF1BYTE(*((u8 *)(_ptr))) 2929 /* Read le16 data from memory and convert to host ordering */ 2930 #define READEF2BYTE(_ptr) \ 2931 EF2BYTE(*(_ptr)) 2932 #define READEF4BYTE(_ptr) \ 2933 EF4BYTE(*(_ptr)) 2934 2935 /* Create a bit mask 2936 * Examples: 2937 * BIT_LEN_MASK_32(0) => 0x00000000 2938 * BIT_LEN_MASK_32(1) => 0x00000001 2939 * BIT_LEN_MASK_32(2) => 0x00000003 2940 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2941 */ 2942 #define BIT_LEN_MASK_32(__bitlen) \ 2943 (0xFFFFFFFF >> (32 - (__bitlen))) 2944 #define BIT_LEN_MASK_16(__bitlen) \ 2945 (0xFFFF >> (16 - (__bitlen))) 2946 #define BIT_LEN_MASK_8(__bitlen) \ 2947 (0xFF >> (8 - (__bitlen))) 2948 2949 /* Create an offset bit mask 2950 * Examples: 2951 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2952 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2953 */ 2954 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2955 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2956 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2957 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2958 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2959 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2960 2961 /*Description: 2962 * Return 4-byte value in host byte ordering from 2963 * 4-byte pointer in little-endian system. 2964 */ 2965 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2966 (EF4BYTE(*((__le32 *)(__pstart)))) 2967 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2968 (EF2BYTE(*((__le16 *)(__pstart)))) 2969 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2970 (EF1BYTE(*((u8 *)(__pstart)))) 2971 2972 /*Description: 2973 Translate subfield (continuous bits in little-endian) of 4-byte 2974 value to host byte ordering.*/ 2975 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2976 ( \ 2977 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2978 BIT_LEN_MASK_32(__bitlen) \ 2979 ) 2980 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2981 ( \ 2982 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2983 BIT_LEN_MASK_16(__bitlen) \ 2984 ) 2985 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2986 ( \ 2987 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2988 BIT_LEN_MASK_8(__bitlen) \ 2989 ) 2990 2991 /* Description: 2992 * Mask subfield (continuous bits in little-endian) of 4-byte value 2993 * and return the result in 4-byte value in host byte ordering. 2994 */ 2995 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2996 ( \ 2997 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2998 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2999 ) 3000 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 3001 ( \ 3002 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 3003 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 3004 ) 3005 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 3006 ( \ 3007 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 3008 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 3009 ) 3010 3011 /* Description: 3012 * Set subfield of little-endian 4-byte value to specified value. 3013 */ 3014 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 3015 *((__le32 *)(__pstart)) = \ 3016 cpu_to_le32( \ 3017 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 3018 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 3019 ) 3020 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 3021 *((__le16 *)(__pstart)) = \ 3022 cpu_to_le16( \ 3023 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 3024 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 3025 ) 3026 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 3027 *((u8 *)(__pstart)) = EF1BYTE \ 3028 ( \ 3029 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 3030 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 3031 ) 3032 3033 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 3034 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 3035 3036 /**************************************** 3037 mem access macro define end 3038 ****************************************/ 3039 3040 #define byte(x, n) ((x >> (8 * n)) & 0xff) 3041 3042 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 3043 #define RTL_WATCH_DOG_TIME 2000 3044 #define MSECS(t) msecs_to_jiffies(t) 3045 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 3046 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 3047 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 3048 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 3049 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 3050 3051 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 3052 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 3053 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 3054 /*NIC halt, re-initialize hw parameters*/ 3055 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 3056 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 3057 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 3058 /*Always enable ASPM and Clock Req in initialization.*/ 3059 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 3060 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 3061 #define RT_PS_LEVEL_ASPM BIT(7) 3062 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 3063 #define RT_RF_LPS_DISALBE_2R BIT(30) 3064 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 3065 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 3066 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 3067 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 3068 (ppsc->cur_ps_level &= (~(_ps_flg))) 3069 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 3070 (ppsc->cur_ps_level |= _ps_flg) 3071 3072 #define container_of_dwork_rtl(x, y, z) \ 3073 container_of(to_delayed_work(x), y, z) 3074 3075 #define FILL_OCTET_STRING(_os, _octet, _len) \ 3076 (_os).octet = (u8 *)(_octet); \ 3077 (_os).length = (_len); 3078 3079 #define CP_MACADDR(des, src) \ 3080 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 3081 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 3082 (des)[4] = (src)[4], (des)[5] = (src)[5]) 3083 3084 #define LDPC_HT_ENABLE_RX BIT(0) 3085 #define LDPC_HT_ENABLE_TX BIT(1) 3086 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 3087 #define LDPC_HT_CAP_TX BIT(3) 3088 3089 #define STBC_HT_ENABLE_RX BIT(0) 3090 #define STBC_HT_ENABLE_TX BIT(1) 3091 #define STBC_HT_TEST_TX_ENABLE BIT(2) 3092 #define STBC_HT_CAP_TX BIT(3) 3093 3094 #define LDPC_VHT_ENABLE_RX BIT(0) 3095 #define LDPC_VHT_ENABLE_TX BIT(1) 3096 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 3097 #define LDPC_VHT_CAP_TX BIT(3) 3098 3099 #define STBC_VHT_ENABLE_RX BIT(0) 3100 #define STBC_VHT_ENABLE_TX BIT(1) 3101 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 3102 #define STBC_VHT_CAP_TX BIT(3) 3103 3104 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 3105 3106 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 3107 3108 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 3109 { 3110 return rtlpriv->io.read8_sync(rtlpriv, addr); 3111 } 3112 3113 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 3114 { 3115 return rtlpriv->io.read16_sync(rtlpriv, addr); 3116 } 3117 3118 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 3119 { 3120 return rtlpriv->io.read32_sync(rtlpriv, addr); 3121 } 3122 3123 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 3124 { 3125 rtlpriv->io.write8_async(rtlpriv, addr, val8); 3126 3127 if (rtlpriv->cfg->write_readback) 3128 rtlpriv->io.read8_sync(rtlpriv, addr); 3129 } 3130 3131 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw, 3132 u32 addr, u32 val8) 3133 { 3134 struct rtl_priv *rtlpriv = rtl_priv(hw); 3135 3136 rtl_write_byte(rtlpriv, addr, (u8)val8); 3137 } 3138 3139 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 3140 { 3141 rtlpriv->io.write16_async(rtlpriv, addr, val16); 3142 3143 if (rtlpriv->cfg->write_readback) 3144 rtlpriv->io.read16_sync(rtlpriv, addr); 3145 } 3146 3147 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 3148 u32 addr, u32 val32) 3149 { 3150 rtlpriv->io.write32_async(rtlpriv, addr, val32); 3151 3152 if (rtlpriv->cfg->write_readback) 3153 rtlpriv->io.read32_sync(rtlpriv, addr); 3154 } 3155 3156 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 3157 u32 regaddr, u32 bitmask) 3158 { 3159 struct rtl_priv *rtlpriv = hw->priv; 3160 3161 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 3162 } 3163 3164 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 3165 u32 bitmask, u32 data) 3166 { 3167 struct rtl_priv *rtlpriv = hw->priv; 3168 3169 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 3170 } 3171 3172 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw, 3173 u32 regaddr, u32 data) 3174 { 3175 rtl_set_bbreg(hw, regaddr, 0xffffffff, data); 3176 } 3177 3178 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 3179 enum radio_path rfpath, u32 regaddr, 3180 u32 bitmask) 3181 { 3182 struct rtl_priv *rtlpriv = hw->priv; 3183 3184 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 3185 } 3186 3187 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 3188 enum radio_path rfpath, u32 regaddr, 3189 u32 bitmask, u32 data) 3190 { 3191 struct rtl_priv *rtlpriv = hw->priv; 3192 3193 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 3194 } 3195 3196 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 3197 { 3198 return (_HAL_STATE_STOP == rtlhal->state); 3199 } 3200 3201 static inline void set_hal_start(struct rtl_hal *rtlhal) 3202 { 3203 rtlhal->state = _HAL_STATE_START; 3204 } 3205 3206 static inline void set_hal_stop(struct rtl_hal *rtlhal) 3207 { 3208 rtlhal->state = _HAL_STATE_STOP; 3209 } 3210 3211 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3212 { 3213 return rtlphy->rf_type; 3214 } 3215 3216 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3217 { 3218 return (struct ieee80211_hdr *)(skb->data); 3219 } 3220 3221 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3222 { 3223 return rtl_get_hdr(skb)->frame_control; 3224 } 3225 3226 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3227 { 3228 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3229 } 3230 3231 static inline u16 rtl_get_tid(struct sk_buff *skb) 3232 { 3233 return rtl_get_tid_h(rtl_get_hdr(skb)); 3234 } 3235 3236 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3237 struct ieee80211_vif *vif, 3238 const u8 *bssid) 3239 { 3240 return ieee80211_find_sta(vif, bssid); 3241 } 3242 3243 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3244 u8 *mac_addr) 3245 { 3246 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3247 return ieee80211_find_sta(mac->vif, mac_addr); 3248 } 3249 3250 #endif 3251