1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 103 #define TOTAL_CAM_ENTRY 32 104 105 /*slot time for 11g. */ 106 #define RTL_SLOT_TIME_9 9 107 #define RTL_SLOT_TIME_20 20 108 109 /*related to tcp/ip. */ 110 #define SNAP_SIZE 6 111 #define PROTOC_TYPE_SIZE 2 112 113 /*related with 802.11 frame*/ 114 #define MAC80211_3ADDR_LEN 24 115 #define MAC80211_4ADDR_LEN 30 116 117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 118 #define CHANNEL_MAX_NUMBER_2G 14 119 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to 120 *"phy_GetChnlGroup8812A" and 121 * "Hal_ReadTxPowerInfo8812A" 122 */ 123 #define CHANNEL_MAX_NUMBER_5G_80M 7 124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 125 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to 126 *"phy_GetChnlGroup8812A" and 127 * "Hal_ReadTxPowerInfo8812A" 128 */ 129 #define CHANNEL_MAX_NUMBER_5G_80M 7 130 #define MAX_PG_GROUP 13 131 #define CHANNEL_GROUP_MAX_2G 3 132 #define CHANNEL_GROUP_IDX_5GL 3 133 #define CHANNEL_GROUP_IDX_5GM 6 134 #define CHANNEL_GROUP_IDX_5GH 9 135 #define CHANNEL_GROUP_MAX_5G 9 136 #define CHANNEL_MAX_NUMBER_2G 14 137 #define AVG_THERMAL_NUM 8 138 #define AVG_THERMAL_NUM_88E 4 139 #define AVG_THERMAL_NUM_8723BE 4 140 #define MAX_TID_COUNT 9 141 142 /* for early mode */ 143 #define FCS_LEN 4 144 #define EM_HDR_LEN 8 145 146 enum rtl8192c_h2c_cmd { 147 H2C_AP_OFFLOAD = 0, 148 H2C_SETPWRMODE = 1, 149 H2C_JOINBSSRPT = 2, 150 H2C_RSVDPAGE = 3, 151 H2C_RSSI_REPORT = 5, 152 H2C_RA_MASK = 6, 153 H2C_MACID_PS_MODE = 7, 154 H2C_P2P_PS_OFFLOAD = 8, 155 H2C_MAC_MODE_SEL = 9, 156 H2C_PWRM = 15, 157 H2C_P2P_PS_CTW_CMD = 24, 158 MAX_H2CCMD 159 }; 160 161 #define MAX_TX_COUNT 4 162 #define MAX_REGULATION_NUM 4 163 #define MAX_RF_PATH_NUM 4 164 #define MAX_RATE_SECTION_NUM 6 165 #define MAX_2_4G_BANDWITH_NUM 4 166 #define MAX_5G_BANDWITH_NUM 4 167 #define MAX_RF_PATH 4 168 #define MAX_CHNL_GROUP_24G 6 169 #define MAX_CHNL_GROUP_5G 14 170 171 #define TX_PWR_BY_RATE_NUM_BAND 2 172 #define TX_PWR_BY_RATE_NUM_RF 4 173 #define TX_PWR_BY_RATE_NUM_SECTION 12 174 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 175 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 176 177 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 178 179 #define DEL_SW_IDX_SZ 30 180 #define BAND_NUM 3 181 182 /* For now, it's just for 8192ee 183 * but not OK yet, keep it 0 184 */ 185 #define DMA_IS_64BIT 0 186 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 187 188 enum rf_tx_num { 189 RF_1TX = 0, 190 RF_2TX, 191 RF_MAX_TX_NUM, 192 RF_TX_NUM_NONIMPLEMENT, 193 }; 194 195 #define PACKET_NORMAL 0 196 #define PACKET_DHCP 1 197 #define PACKET_ARP 2 198 #define PACKET_EAPOL 3 199 200 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 201 #define RSVD_WOL_PATTERN_NUM 1 202 #define WKFMCAM_ADDR_NUM 6 203 #define WKFMCAM_SIZE 24 204 205 #define MAX_WOL_BIT_MASK_SIZE 16 206 /* MIN LEN keeps 13 here */ 207 #define MIN_WOL_PATTERN_SIZE 13 208 #define MAX_WOL_PATTERN_SIZE 128 209 210 #define WAKE_ON_MAGIC_PACKET BIT(0) 211 #define WAKE_ON_PATTERN_MATCH BIT(1) 212 213 #define WOL_REASON_PTK_UPDATE BIT(0) 214 #define WOL_REASON_GTK_UPDATE BIT(1) 215 #define WOL_REASON_DISASSOC BIT(2) 216 #define WOL_REASON_DEAUTH BIT(3) 217 #define WOL_REASON_AP_LOST BIT(4) 218 #define WOL_REASON_MAGIC_PKT BIT(5) 219 #define WOL_REASON_UNICAST_PKT BIT(6) 220 #define WOL_REASON_PATTERN_PKT BIT(7) 221 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 222 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 223 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 224 225 struct rtlwifi_firmware_header { 226 __le16 signature; 227 u8 category; 228 u8 function; 229 __le16 version; 230 u8 subversion; 231 u8 rsvd1; 232 u8 month; 233 u8 date; 234 u8 hour; 235 u8 minute; 236 __le16 ramcodeSize; 237 __le16 rsvd2; 238 __le32 svnindex; 239 __le32 rsvd3; 240 __le32 rsvd4; 241 __le32 rsvd5; 242 }; 243 244 struct txpower_info_2g { 245 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 246 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 247 /*If only one tx, only BW20 and OFDM are used.*/ 248 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 249 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 250 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 251 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 252 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 253 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 254 }; 255 256 struct txpower_info_5g { 257 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 258 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 259 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 260 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 261 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 262 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 263 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 264 }; 265 266 enum rate_section { 267 CCK = 0, 268 OFDM, 269 HT_MCS0_MCS7, 270 HT_MCS8_MCS15, 271 VHT_1SSMCS0_1SSMCS9, 272 VHT_2SSMCS0_2SSMCS9, 273 }; 274 275 enum intf_type { 276 INTF_PCI = 0, 277 INTF_USB = 1, 278 }; 279 280 enum radio_path { 281 RF90_PATH_A = 0, 282 RF90_PATH_B = 1, 283 RF90_PATH_C = 2, 284 RF90_PATH_D = 3, 285 }; 286 287 enum regulation_txpwr_lmt { 288 TXPWR_LMT_FCC = 0, 289 TXPWR_LMT_MKK = 1, 290 TXPWR_LMT_ETSI = 2, 291 TXPWR_LMT_WW = 3, 292 293 TXPWR_LMT_MAX_REGULATION_NUM = 4 294 }; 295 296 enum rt_eeprom_type { 297 EEPROM_93C46, 298 EEPROM_93C56, 299 EEPROM_BOOT_EFUSE, 300 }; 301 302 enum ttl_status { 303 RTL_STATUS_INTERFACE_START = 0, 304 }; 305 306 enum hardware_type { 307 HARDWARE_TYPE_RTL8192E, 308 HARDWARE_TYPE_RTL8192U, 309 HARDWARE_TYPE_RTL8192SE, 310 HARDWARE_TYPE_RTL8192SU, 311 HARDWARE_TYPE_RTL8192CE, 312 HARDWARE_TYPE_RTL8192CU, 313 HARDWARE_TYPE_RTL8192DE, 314 HARDWARE_TYPE_RTL8192DU, 315 HARDWARE_TYPE_RTL8723AE, 316 HARDWARE_TYPE_RTL8723U, 317 HARDWARE_TYPE_RTL8188EE, 318 HARDWARE_TYPE_RTL8723BE, 319 HARDWARE_TYPE_RTL8192EE, 320 HARDWARE_TYPE_RTL8821AE, 321 HARDWARE_TYPE_RTL8812AE, 322 323 /* keep it last */ 324 HARDWARE_TYPE_NUM 325 }; 326 327 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \ 328 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) 329 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \ 330 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 331 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \ 332 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) 333 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \ 334 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) 335 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \ 336 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) 337 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \ 338 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) 339 #define IS_HARDWARE_TYPE_8723E(rtlhal) \ 340 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) 341 #define IS_HARDWARE_TYPE_8723U(rtlhal) \ 342 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) 343 #define IS_HARDWARE_TYPE_8192S(rtlhal) \ 344 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) 345 #define IS_HARDWARE_TYPE_8192C(rtlhal) \ 346 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) 347 #define IS_HARDWARE_TYPE_8192D(rtlhal) \ 348 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) 349 #define IS_HARDWARE_TYPE_8723(rtlhal) \ 350 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) 351 352 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 353 ((rxmcs) == DESC_RATE1M || \ 354 (rxmcs) == DESC_RATE2M || \ 355 (rxmcs) == DESC_RATE5_5M || \ 356 (rxmcs) == DESC_RATE11M) 357 358 enum scan_operation_backup_opt { 359 SCAN_OPT_BACKUP = 0, 360 SCAN_OPT_BACKUP_BAND0 = 0, 361 SCAN_OPT_BACKUP_BAND1, 362 SCAN_OPT_RESTORE, 363 SCAN_OPT_MAX 364 }; 365 366 /*RF state.*/ 367 enum rf_pwrstate { 368 ERFON, 369 ERFSLEEP, 370 ERFOFF 371 }; 372 373 struct bb_reg_def { 374 u32 rfintfs; 375 u32 rfintfi; 376 u32 rfintfo; 377 u32 rfintfe; 378 u32 rf3wire_offset; 379 u32 rflssi_select; 380 u32 rftxgain_stage; 381 u32 rfhssi_para1; 382 u32 rfhssi_para2; 383 u32 rfsw_ctrl; 384 u32 rfagc_control1; 385 u32 rfagc_control2; 386 u32 rfrxiq_imbal; 387 u32 rfrx_afe; 388 u32 rftxiq_imbal; 389 u32 rftx_afe; 390 u32 rf_rb; /* rflssi_readback */ 391 u32 rf_rbpi; /* rflssi_readbackpi */ 392 }; 393 394 enum io_type { 395 IO_CMD_PAUSE_DM_BY_SCAN = 0, 396 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 397 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 398 IO_CMD_RESUME_DM_BY_SCAN = 2, 399 }; 400 401 enum hw_variables { 402 HW_VAR_ETHER_ADDR, 403 HW_VAR_MULTICAST_REG, 404 HW_VAR_BASIC_RATE, 405 HW_VAR_BSSID, 406 HW_VAR_MEDIA_STATUS, 407 HW_VAR_SECURITY_CONF, 408 HW_VAR_BEACON_INTERVAL, 409 HW_VAR_ATIM_WINDOW, 410 HW_VAR_LISTEN_INTERVAL, 411 HW_VAR_CS_COUNTER, 412 HW_VAR_DEFAULTKEY0, 413 HW_VAR_DEFAULTKEY1, 414 HW_VAR_DEFAULTKEY2, 415 HW_VAR_DEFAULTKEY3, 416 HW_VAR_SIFS, 417 HW_VAR_R2T_SIFS, 418 HW_VAR_DIFS, 419 HW_VAR_EIFS, 420 HW_VAR_SLOT_TIME, 421 HW_VAR_ACK_PREAMBLE, 422 HW_VAR_CW_CONFIG, 423 HW_VAR_CW_VALUES, 424 HW_VAR_RATE_FALLBACK_CONTROL, 425 HW_VAR_CONTENTION_WINDOW, 426 HW_VAR_RETRY_COUNT, 427 HW_VAR_TR_SWITCH, 428 HW_VAR_COMMAND, 429 HW_VAR_WPA_CONFIG, 430 HW_VAR_AMPDU_MIN_SPACE, 431 HW_VAR_SHORTGI_DENSITY, 432 HW_VAR_AMPDU_FACTOR, 433 HW_VAR_MCS_RATE_AVAILABLE, 434 HW_VAR_AC_PARAM, 435 HW_VAR_ACM_CTRL, 436 HW_VAR_DIS_Req_Qsize, 437 HW_VAR_CCX_CHNL_LOAD, 438 HW_VAR_CCX_NOISE_HISTOGRAM, 439 HW_VAR_CCX_CLM_NHM, 440 HW_VAR_TxOPLimit, 441 HW_VAR_TURBO_MODE, 442 HW_VAR_RF_STATE, 443 HW_VAR_RF_OFF_BY_HW, 444 HW_VAR_BUS_SPEED, 445 HW_VAR_SET_DEV_POWER, 446 447 HW_VAR_RCR, 448 HW_VAR_RATR_0, 449 HW_VAR_RRSR, 450 HW_VAR_CPU_RST, 451 HW_VAR_CHECK_BSSID, 452 HW_VAR_LBK_MODE, 453 HW_VAR_AES_11N_FIX, 454 HW_VAR_USB_RX_AGGR, 455 HW_VAR_USER_CONTROL_TURBO_MODE, 456 HW_VAR_RETRY_LIMIT, 457 HW_VAR_INIT_TX_RATE, 458 HW_VAR_TX_RATE_REG, 459 HW_VAR_EFUSE_USAGE, 460 HW_VAR_EFUSE_BYTES, 461 HW_VAR_AUTOLOAD_STATUS, 462 HW_VAR_RF_2R_DISABLE, 463 HW_VAR_SET_RPWM, 464 HW_VAR_H2C_FW_PWRMODE, 465 HW_VAR_H2C_FW_JOINBSSRPT, 466 HW_VAR_H2C_FW_MEDIASTATUSRPT, 467 HW_VAR_H2C_FW_P2P_PS_OFFLOAD, 468 HW_VAR_FW_PSMODE_STATUS, 469 HW_VAR_INIT_RTS_RATE, 470 HW_VAR_RESUME_CLK_ON, 471 HW_VAR_FW_LPS_ACTION, 472 HW_VAR_1X1_RECV_COMBINE, 473 HW_VAR_STOP_SEND_BEACON, 474 HW_VAR_TSF_TIMER, 475 HW_VAR_IO_CMD, 476 477 HW_VAR_RF_RECOVERY, 478 HW_VAR_H2C_FW_UPDATE_GTK, 479 HW_VAR_WF_MASK, 480 HW_VAR_WF_CRC, 481 HW_VAR_WF_IS_MAC_ADDR, 482 HW_VAR_H2C_FW_OFFLOAD, 483 HW_VAR_RESET_WFCRC, 484 485 HW_VAR_HANDLE_FW_C2H, 486 HW_VAR_DL_FW_RSVD_PAGE, 487 HW_VAR_AID, 488 HW_VAR_HW_SEQ_ENABLE, 489 HW_VAR_CORRECT_TSF, 490 HW_VAR_BCN_VALID, 491 HW_VAR_FWLPS_RF_ON, 492 HW_VAR_DUAL_TSF_RST, 493 HW_VAR_SWITCH_EPHY_WoWLAN, 494 HW_VAR_INT_MIGRATION, 495 HW_VAR_INT_AC, 496 HW_VAR_RF_TIMING, 497 498 HAL_DEF_WOWLAN, 499 HW_VAR_MRC, 500 HW_VAR_KEEP_ALIVE, 501 HW_VAR_NAV_UPPER, 502 503 HW_VAR_MGT_FILTER, 504 HW_VAR_CTRL_FILTER, 505 HW_VAR_DATA_FILTER, 506 }; 507 508 enum rt_media_status { 509 RT_MEDIA_DISCONNECT = 0, 510 RT_MEDIA_CONNECT = 1 511 }; 512 513 enum rt_oem_id { 514 RT_CID_DEFAULT = 0, 515 RT_CID_8187_ALPHA0 = 1, 516 RT_CID_8187_SERCOMM_PS = 2, 517 RT_CID_8187_HW_LED = 3, 518 RT_CID_8187_NETGEAR = 4, 519 RT_CID_WHQL = 5, 520 RT_CID_819X_CAMEO = 6, 521 RT_CID_819X_RUNTOP = 7, 522 RT_CID_819X_SENAO = 8, 523 RT_CID_TOSHIBA = 9, 524 RT_CID_819X_NETCORE = 10, 525 RT_CID_NETTRONIX = 11, 526 RT_CID_DLINK = 12, 527 RT_CID_PRONET = 13, 528 RT_CID_COREGA = 14, 529 RT_CID_819X_ALPHA = 15, 530 RT_CID_819X_SITECOM = 16, 531 RT_CID_CCX = 17, 532 RT_CID_819X_LENOVO = 18, 533 RT_CID_819X_QMI = 19, 534 RT_CID_819X_EDIMAX_BELKIN = 20, 535 RT_CID_819X_SERCOMM_BELKIN = 21, 536 RT_CID_819X_CAMEO1 = 22, 537 RT_CID_819X_MSI = 23, 538 RT_CID_819X_ACER = 24, 539 RT_CID_819X_HP = 27, 540 RT_CID_819X_CLEVO = 28, 541 RT_CID_819X_ARCADYAN_BELKIN = 29, 542 RT_CID_819X_SAMSUNG = 30, 543 RT_CID_819X_WNC_COREGA = 31, 544 RT_CID_819X_FOXCOON = 32, 545 RT_CID_819X_DELL = 33, 546 RT_CID_819X_PRONETS = 34, 547 RT_CID_819X_EDIMAX_ASUS = 35, 548 RT_CID_NETGEAR = 36, 549 RT_CID_PLANEX = 37, 550 RT_CID_CC_C = 38, 551 }; 552 553 enum hw_descs { 554 HW_DESC_OWN, 555 HW_DESC_RXOWN, 556 HW_DESC_TX_NEXTDESC_ADDR, 557 HW_DESC_TXBUFF_ADDR, 558 HW_DESC_RXBUFF_ADDR, 559 HW_DESC_RXPKT_LEN, 560 HW_DESC_RXERO, 561 HW_DESC_RX_PREPARE, 562 }; 563 564 enum prime_sc { 565 PRIME_CHNL_OFFSET_DONT_CARE = 0, 566 PRIME_CHNL_OFFSET_LOWER = 1, 567 PRIME_CHNL_OFFSET_UPPER = 2, 568 }; 569 570 enum rf_type { 571 RF_1T1R = 0, 572 RF_1T2R = 1, 573 RF_2T2R = 2, 574 RF_2T2R_GREEN = 3, 575 }; 576 577 enum ht_channel_width { 578 HT_CHANNEL_WIDTH_20 = 0, 579 HT_CHANNEL_WIDTH_20_40 = 1, 580 HT_CHANNEL_WIDTH_80 = 2, 581 }; 582 583 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 584 Cipher Suites Encryption Algorithms */ 585 enum rt_enc_alg { 586 NO_ENCRYPTION = 0, 587 WEP40_ENCRYPTION = 1, 588 TKIP_ENCRYPTION = 2, 589 RSERVED_ENCRYPTION = 3, 590 AESCCMP_ENCRYPTION = 4, 591 WEP104_ENCRYPTION = 5, 592 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 593 }; 594 595 enum rtl_hal_state { 596 _HAL_STATE_STOP = 0, 597 _HAL_STATE_START = 1, 598 }; 599 600 enum rtl_desc92_rate { 601 DESC_RATE1M = 0x00, 602 DESC_RATE2M = 0x01, 603 DESC_RATE5_5M = 0x02, 604 DESC_RATE11M = 0x03, 605 606 DESC_RATE6M = 0x04, 607 DESC_RATE9M = 0x05, 608 DESC_RATE12M = 0x06, 609 DESC_RATE18M = 0x07, 610 DESC_RATE24M = 0x08, 611 DESC_RATE36M = 0x09, 612 DESC_RATE48M = 0x0a, 613 DESC_RATE54M = 0x0b, 614 615 DESC_RATEMCS0 = 0x0c, 616 DESC_RATEMCS1 = 0x0d, 617 DESC_RATEMCS2 = 0x0e, 618 DESC_RATEMCS3 = 0x0f, 619 DESC_RATEMCS4 = 0x10, 620 DESC_RATEMCS5 = 0x11, 621 DESC_RATEMCS6 = 0x12, 622 DESC_RATEMCS7 = 0x13, 623 DESC_RATEMCS8 = 0x14, 624 DESC_RATEMCS9 = 0x15, 625 DESC_RATEMCS10 = 0x16, 626 DESC_RATEMCS11 = 0x17, 627 DESC_RATEMCS12 = 0x18, 628 DESC_RATEMCS13 = 0x19, 629 DESC_RATEMCS14 = 0x1a, 630 DESC_RATEMCS15 = 0x1b, 631 DESC_RATEMCS15_SG = 0x1c, 632 DESC_RATEMCS32 = 0x20, 633 634 DESC_RATEVHT1SS_MCS0 = 0x2c, 635 DESC_RATEVHT1SS_MCS1 = 0x2d, 636 DESC_RATEVHT1SS_MCS2 = 0x2e, 637 DESC_RATEVHT1SS_MCS3 = 0x2f, 638 DESC_RATEVHT1SS_MCS4 = 0x30, 639 DESC_RATEVHT1SS_MCS5 = 0x31, 640 DESC_RATEVHT1SS_MCS6 = 0x32, 641 DESC_RATEVHT1SS_MCS7 = 0x33, 642 DESC_RATEVHT1SS_MCS8 = 0x34, 643 DESC_RATEVHT1SS_MCS9 = 0x35, 644 DESC_RATEVHT2SS_MCS0 = 0x36, 645 DESC_RATEVHT2SS_MCS1 = 0x37, 646 DESC_RATEVHT2SS_MCS2 = 0x38, 647 DESC_RATEVHT2SS_MCS3 = 0x39, 648 DESC_RATEVHT2SS_MCS4 = 0x3a, 649 DESC_RATEVHT2SS_MCS5 = 0x3b, 650 DESC_RATEVHT2SS_MCS6 = 0x3c, 651 DESC_RATEVHT2SS_MCS7 = 0x3d, 652 DESC_RATEVHT2SS_MCS8 = 0x3e, 653 DESC_RATEVHT2SS_MCS9 = 0x3f, 654 }; 655 656 enum rtl_var_map { 657 /*reg map */ 658 SYS_ISO_CTRL = 0, 659 SYS_FUNC_EN, 660 SYS_CLK, 661 MAC_RCR_AM, 662 MAC_RCR_AB, 663 MAC_RCR_ACRC32, 664 MAC_RCR_ACF, 665 MAC_RCR_AAP, 666 MAC_HIMR, 667 MAC_HIMRE, 668 MAC_HSISR, 669 670 /*efuse map */ 671 EFUSE_TEST, 672 EFUSE_CTRL, 673 EFUSE_CLK, 674 EFUSE_CLK_CTRL, 675 EFUSE_PWC_EV12V, 676 EFUSE_FEN_ELDR, 677 EFUSE_LOADER_CLK_EN, 678 EFUSE_ANA8M, 679 EFUSE_HWSET_MAX_SIZE, 680 EFUSE_MAX_SECTION_MAP, 681 EFUSE_REAL_CONTENT_SIZE, 682 EFUSE_OOB_PROTECT_BYTES_LEN, 683 EFUSE_ACCESS, 684 685 /*CAM map */ 686 RWCAM, 687 WCAMI, 688 RCAMO, 689 CAMDBG, 690 SECR, 691 SEC_CAM_NONE, 692 SEC_CAM_WEP40, 693 SEC_CAM_TKIP, 694 SEC_CAM_AES, 695 SEC_CAM_WEP104, 696 697 /*IMR map */ 698 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 699 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 700 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 701 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 702 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 703 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 704 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 705 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 706 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 707 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 708 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 709 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 710 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 711 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 712 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 713 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 714 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 715 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 716 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 717 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 718 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 719 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 720 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 721 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 722 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 723 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 724 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 725 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 726 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 727 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 728 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 729 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 730 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 731 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 732 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 733 * RTL_IMR_TBDER) */ 734 RTL_IMR_C2HCMD, /*fw interrupt*/ 735 736 /*CCK Rates, TxHT = 0 */ 737 RTL_RC_CCK_RATE1M, 738 RTL_RC_CCK_RATE2M, 739 RTL_RC_CCK_RATE5_5M, 740 RTL_RC_CCK_RATE11M, 741 742 /*OFDM Rates, TxHT = 0 */ 743 RTL_RC_OFDM_RATE6M, 744 RTL_RC_OFDM_RATE9M, 745 RTL_RC_OFDM_RATE12M, 746 RTL_RC_OFDM_RATE18M, 747 RTL_RC_OFDM_RATE24M, 748 RTL_RC_OFDM_RATE36M, 749 RTL_RC_OFDM_RATE48M, 750 RTL_RC_OFDM_RATE54M, 751 752 RTL_RC_HT_RATEMCS7, 753 RTL_RC_HT_RATEMCS15, 754 755 RTL_RC_VHT_RATE_1SS_MCS7, 756 RTL_RC_VHT_RATE_1SS_MCS8, 757 RTL_RC_VHT_RATE_1SS_MCS9, 758 RTL_RC_VHT_RATE_2SS_MCS7, 759 RTL_RC_VHT_RATE_2SS_MCS8, 760 RTL_RC_VHT_RATE_2SS_MCS9, 761 762 /*keep it last */ 763 RTL_VAR_MAP_MAX, 764 }; 765 766 /*Firmware PS mode for control LPS.*/ 767 enum _fw_ps_mode { 768 FW_PS_ACTIVE_MODE = 0, 769 FW_PS_MIN_MODE = 1, 770 FW_PS_MAX_MODE = 2, 771 FW_PS_DTIM_MODE = 3, 772 FW_PS_VOIP_MODE = 4, 773 FW_PS_UAPSD_WMM_MODE = 5, 774 FW_PS_UAPSD_MODE = 6, 775 FW_PS_IBSS_MODE = 7, 776 FW_PS_WWLAN_MODE = 8, 777 FW_PS_PM_Radio_Off = 9, 778 FW_PS_PM_Card_Disable = 10, 779 }; 780 781 enum rt_psmode { 782 EACTIVE, /*Active/Continuous access. */ 783 EMAXPS, /*Max power save mode. */ 784 EFASTPS, /*Fast power save mode. */ 785 EAUTOPS, /*Auto power save mode. */ 786 }; 787 788 /*LED related.*/ 789 enum led_ctl_mode { 790 LED_CTL_POWER_ON = 1, 791 LED_CTL_LINK = 2, 792 LED_CTL_NO_LINK = 3, 793 LED_CTL_TX = 4, 794 LED_CTL_RX = 5, 795 LED_CTL_SITE_SURVEY = 6, 796 LED_CTL_POWER_OFF = 7, 797 LED_CTL_START_TO_LINK = 8, 798 LED_CTL_START_WPS = 9, 799 LED_CTL_STOP_WPS = 10, 800 }; 801 802 enum rtl_led_pin { 803 LED_PIN_GPIO0, 804 LED_PIN_LED0, 805 LED_PIN_LED1, 806 LED_PIN_LED2 807 }; 808 809 /*QoS related.*/ 810 /*acm implementation method.*/ 811 enum acm_method { 812 eAcmWay0_SwAndHw = 0, 813 eAcmWay1_HW = 1, 814 EACMWAY2_SW = 2, 815 }; 816 817 enum macphy_mode { 818 SINGLEMAC_SINGLEPHY = 0, 819 DUALMAC_DUALPHY, 820 DUALMAC_SINGLEPHY, 821 }; 822 823 enum band_type { 824 BAND_ON_2_4G = 0, 825 BAND_ON_5G, 826 BAND_ON_BOTH, 827 BANDMAX 828 }; 829 830 /*aci/aifsn Field. 831 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 832 union aci_aifsn { 833 u8 char_data; 834 835 struct { 836 u8 aifsn:4; 837 u8 acm:1; 838 u8 aci:2; 839 u8 reserved:1; 840 } f; /* Field */ 841 }; 842 843 /*mlme related.*/ 844 enum wireless_mode { 845 WIRELESS_MODE_UNKNOWN = 0x00, 846 WIRELESS_MODE_A = 0x01, 847 WIRELESS_MODE_B = 0x02, 848 WIRELESS_MODE_G = 0x04, 849 WIRELESS_MODE_AUTO = 0x08, 850 WIRELESS_MODE_N_24G = 0x10, 851 WIRELESS_MODE_N_5G = 0x20, 852 WIRELESS_MODE_AC_5G = 0x40, 853 WIRELESS_MODE_AC_24G = 0x80, 854 WIRELESS_MODE_AC_ONLY = 0x100, 855 WIRELESS_MODE_MAX = 0x800 856 }; 857 858 #define IS_WIRELESS_MODE_A(wirelessmode) \ 859 (wirelessmode == WIRELESS_MODE_A) 860 #define IS_WIRELESS_MODE_B(wirelessmode) \ 861 (wirelessmode == WIRELESS_MODE_B) 862 #define IS_WIRELESS_MODE_G(wirelessmode) \ 863 (wirelessmode == WIRELESS_MODE_G) 864 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 865 (wirelessmode == WIRELESS_MODE_N_24G) 866 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 867 (wirelessmode == WIRELESS_MODE_N_5G) 868 869 enum ratr_table_mode { 870 RATR_INX_WIRELESS_NGB = 0, 871 RATR_INX_WIRELESS_NG = 1, 872 RATR_INX_WIRELESS_NB = 2, 873 RATR_INX_WIRELESS_N = 3, 874 RATR_INX_WIRELESS_GB = 4, 875 RATR_INX_WIRELESS_G = 5, 876 RATR_INX_WIRELESS_B = 6, 877 RATR_INX_WIRELESS_MC = 7, 878 RATR_INX_WIRELESS_A = 8, 879 RATR_INX_WIRELESS_AC_5N = 8, 880 RATR_INX_WIRELESS_AC_24N = 9, 881 }; 882 883 enum rtl_link_state { 884 MAC80211_NOLINK = 0, 885 MAC80211_LINKING = 1, 886 MAC80211_LINKED = 2, 887 MAC80211_LINKED_SCANNING = 3, 888 }; 889 890 enum act_category { 891 ACT_CAT_QOS = 1, 892 ACT_CAT_DLS = 2, 893 ACT_CAT_BA = 3, 894 ACT_CAT_HT = 7, 895 ACT_CAT_WMM = 17, 896 }; 897 898 enum ba_action { 899 ACT_ADDBAREQ = 0, 900 ACT_ADDBARSP = 1, 901 ACT_DELBA = 2, 902 }; 903 904 enum rt_polarity_ctl { 905 RT_POLARITY_LOW_ACT = 0, 906 RT_POLARITY_HIGH_ACT = 1, 907 }; 908 909 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 910 enum fw_wow_reason_v2 { 911 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 912 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 913 FW_WOW_V2_DISASSOC_EVENT = 0x04, 914 FW_WOW_V2_DEAUTH_EVENT = 0x08, 915 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 916 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 917 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 918 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 919 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 920 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 921 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 922 FW_WOW_V2_REASON_MAX = 0xff, 923 }; 924 925 enum wolpattern_type { 926 UNICAST_PATTERN = 0, 927 MULTICAST_PATTERN = 1, 928 BROADCAST_PATTERN = 2, 929 DONT_CARE_DA = 3, 930 UNKNOWN_TYPE = 4, 931 }; 932 933 struct octet_string { 934 u8 *octet; 935 u16 length; 936 }; 937 938 struct rtl_hdr_3addr { 939 __le16 frame_ctl; 940 __le16 duration_id; 941 u8 addr1[ETH_ALEN]; 942 u8 addr2[ETH_ALEN]; 943 u8 addr3[ETH_ALEN]; 944 __le16 seq_ctl; 945 u8 payload[0]; 946 } __packed; 947 948 struct rtl_info_element { 949 u8 id; 950 u8 len; 951 u8 data[0]; 952 } __packed; 953 954 struct rtl_probe_rsp { 955 struct rtl_hdr_3addr header; 956 u32 time_stamp[2]; 957 __le16 beacon_interval; 958 __le16 capability; 959 /*SSID, supported rates, FH params, DS params, 960 CF params, IBSS params, TIM (if beacon), RSN */ 961 struct rtl_info_element info_element[0]; 962 } __packed; 963 964 /*LED related.*/ 965 /*ledpin Identify how to implement this SW led.*/ 966 struct rtl_led { 967 void *hw; 968 enum rtl_led_pin ledpin; 969 bool ledon; 970 }; 971 972 struct rtl_led_ctl { 973 bool led_opendrain; 974 struct rtl_led sw_led0; 975 struct rtl_led sw_led1; 976 }; 977 978 struct rtl_qos_parameters { 979 __le16 cw_min; 980 __le16 cw_max; 981 u8 aifs; 982 u8 flag; 983 __le16 tx_op; 984 } __packed; 985 986 struct rt_smooth_data { 987 u32 elements[100]; /*array to store values */ 988 u32 index; /*index to current array to store */ 989 u32 total_num; /*num of valid elements */ 990 u32 total_val; /*sum of valid elements */ 991 }; 992 993 struct false_alarm_statistics { 994 u32 cnt_parity_fail; 995 u32 cnt_rate_illegal; 996 u32 cnt_crc8_fail; 997 u32 cnt_mcs_fail; 998 u32 cnt_fast_fsync_fail; 999 u32 cnt_sb_search_fail; 1000 u32 cnt_ofdm_fail; 1001 u32 cnt_cck_fail; 1002 u32 cnt_all; 1003 u32 cnt_ofdm_cca; 1004 u32 cnt_cck_cca; 1005 u32 cnt_cca_all; 1006 u32 cnt_bw_usc; 1007 u32 cnt_bw_lsc; 1008 }; 1009 1010 struct init_gain { 1011 u8 xaagccore1; 1012 u8 xbagccore1; 1013 u8 xcagccore1; 1014 u8 xdagccore1; 1015 u8 cca; 1016 1017 }; 1018 1019 struct wireless_stats { 1020 unsigned long txbytesunicast; 1021 unsigned long txbytesmulticast; 1022 unsigned long txbytesbroadcast; 1023 unsigned long rxbytesunicast; 1024 1025 long rx_snr_db[4]; 1026 /*Correct smoothed ss in Dbm, only used 1027 in driver to report real power now. */ 1028 long recv_signal_power; 1029 long signal_quality; 1030 long last_sigstrength_inpercent; 1031 1032 u32 rssi_calculate_cnt; 1033 u32 pwdb_all_cnt; 1034 1035 /*Transformed, in dbm. Beautified signal 1036 strength for UI, not correct. */ 1037 long signal_strength; 1038 1039 u8 rx_rssi_percentage[4]; 1040 u8 rx_evm_dbm[4]; 1041 u8 rx_evm_percentage[2]; 1042 1043 u16 rx_cfo_short[4]; 1044 u16 rx_cfo_tail[4]; 1045 1046 struct rt_smooth_data ui_rssi; 1047 struct rt_smooth_data ui_link_quality; 1048 }; 1049 1050 struct rate_adaptive { 1051 u8 rate_adaptive_disabled; 1052 u8 ratr_state; 1053 u16 reserve; 1054 1055 u32 high_rssi_thresh_for_ra; 1056 u32 high2low_rssi_thresh_for_ra; 1057 u8 low2high_rssi_thresh_for_ra40m; 1058 u32 low_rssi_thresh_for_ra40m; 1059 u8 low2high_rssi_thresh_for_ra20m; 1060 u32 low_rssi_thresh_for_ra20m; 1061 u32 upper_rssi_threshold_ratr; 1062 u32 middleupper_rssi_threshold_ratr; 1063 u32 middle_rssi_threshold_ratr; 1064 u32 middlelow_rssi_threshold_ratr; 1065 u32 low_rssi_threshold_ratr; 1066 u32 ultralow_rssi_threshold_ratr; 1067 u32 low_rssi_threshold_ratr_40m; 1068 u32 low_rssi_threshold_ratr_20m; 1069 u8 ping_rssi_enable; 1070 u32 ping_rssi_ratr; 1071 u32 ping_rssi_thresh_for_ra; 1072 u32 last_ratr; 1073 u8 pre_ratr_state; 1074 u8 ldpc_thres; 1075 bool use_ldpc; 1076 bool lower_rts_rate; 1077 bool is_special_data; 1078 }; 1079 1080 struct regd_pair_mapping { 1081 u16 reg_dmnenum; 1082 u16 reg_5ghz_ctl; 1083 u16 reg_2ghz_ctl; 1084 }; 1085 1086 struct dynamic_primary_cca { 1087 u8 pricca_flag; 1088 u8 intf_flag; 1089 u8 intf_type; 1090 u8 dup_rts_flag; 1091 u8 monitor_flag; 1092 u8 ch_offset; 1093 u8 mf_state; 1094 }; 1095 1096 struct rtl_regulatory { 1097 char alpha2[2]; 1098 u16 country_code; 1099 u16 max_power_level; 1100 u32 tp_scale; 1101 u16 current_rd; 1102 u16 current_rd_ext; 1103 int16_t power_limit; 1104 struct regd_pair_mapping *regpair; 1105 }; 1106 1107 struct rtl_rfkill { 1108 bool rfkill_state; /*0 is off, 1 is on */ 1109 }; 1110 1111 /*for P2P PS**/ 1112 #define P2P_MAX_NOA_NUM 2 1113 1114 enum p2p_role { 1115 P2P_ROLE_DISABLE = 0, 1116 P2P_ROLE_DEVICE = 1, 1117 P2P_ROLE_CLIENT = 2, 1118 P2P_ROLE_GO = 3 1119 }; 1120 1121 enum p2p_ps_state { 1122 P2P_PS_DISABLE = 0, 1123 P2P_PS_ENABLE = 1, 1124 P2P_PS_SCAN = 2, 1125 P2P_PS_SCAN_DONE = 3, 1126 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1127 }; 1128 1129 enum p2p_ps_mode { 1130 P2P_PS_NONE = 0, 1131 P2P_PS_CTWINDOW = 1, 1132 P2P_PS_NOA = 2, 1133 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1134 }; 1135 1136 struct rtl_p2p_ps_info { 1137 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1138 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1139 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1140 /* Client traffic window. A period of time in TU after TBTT. */ 1141 u8 ctwindow; 1142 u8 opp_ps; /* opportunistic power save. */ 1143 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1144 /* Count for owner, Type of client. */ 1145 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1146 /* Max duration for owner, preferred or min acceptable duration 1147 * for client. 1148 */ 1149 u32 noa_duration[P2P_MAX_NOA_NUM]; 1150 /* Length of interval for owner, preferred or max acceptable intervali 1151 * of client. 1152 */ 1153 u32 noa_interval[P2P_MAX_NOA_NUM]; 1154 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1155 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1156 }; 1157 1158 struct p2p_ps_offload_t { 1159 u8 offload_en:1; 1160 u8 role:1; /* 1: Owner, 0: Client */ 1161 u8 ctwindow_en:1; 1162 u8 noa0_en:1; 1163 u8 noa1_en:1; 1164 u8 allstasleep:1; 1165 u8 discovery:1; 1166 u8 reserved:1; 1167 }; 1168 1169 #define IQK_MATRIX_REG_NUM 8 1170 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1171 1172 struct iqk_matrix_regs { 1173 bool iqk_done; 1174 long value[1][IQK_MATRIX_REG_NUM]; 1175 }; 1176 1177 struct phy_parameters { 1178 u16 length; 1179 u32 *pdata; 1180 }; 1181 1182 enum hw_param_tab_index { 1183 PHY_REG_2T, 1184 PHY_REG_1T, 1185 PHY_REG_PG, 1186 RADIOA_2T, 1187 RADIOB_2T, 1188 RADIOA_1T, 1189 RADIOB_1T, 1190 MAC_REG, 1191 AGCTAB_2T, 1192 AGCTAB_1T, 1193 MAX_TAB 1194 }; 1195 1196 struct rtl_phy { 1197 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1198 struct init_gain initgain_backup; 1199 enum io_type current_io_type; 1200 1201 u8 rf_mode; 1202 u8 rf_type; 1203 u8 current_chan_bw; 1204 u8 set_bwmode_inprogress; 1205 u8 sw_chnl_inprogress; 1206 u8 sw_chnl_stage; 1207 u8 sw_chnl_step; 1208 u8 current_channel; 1209 u8 h2c_box_num; 1210 u8 set_io_inprogress; 1211 u8 lck_inprogress; 1212 1213 /* record for power tracking */ 1214 s32 reg_e94; 1215 s32 reg_e9c; 1216 s32 reg_ea4; 1217 s32 reg_eac; 1218 s32 reg_eb4; 1219 s32 reg_ebc; 1220 s32 reg_ec4; 1221 s32 reg_ecc; 1222 u8 rfpienable; 1223 u8 reserve_0; 1224 u16 reserve_1; 1225 u32 reg_c04, reg_c08, reg_874; 1226 u32 adda_backup[16]; 1227 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1228 u32 iqk_bb_backup[10]; 1229 bool iqk_initialized; 1230 1231 bool rfpath_rx_enable[MAX_RF_PATH]; 1232 u8 reg_837; 1233 /* Dual mac */ 1234 bool need_iqk; 1235 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1236 1237 bool rfpi_enable; 1238 bool iqk_in_progress; 1239 1240 u8 pwrgroup_cnt; 1241 u8 cck_high_power; 1242 /* this is for 88E & 8723A */ 1243 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1244 /* MAX_PG_GROUP groups of pwr diff by rates */ 1245 u32 mcs_offset[MAX_PG_GROUP][16]; 1246 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1247 [TX_PWR_BY_RATE_NUM_RF] 1248 [TX_PWR_BY_RATE_NUM_RF] 1249 [TX_PWR_BY_RATE_NUM_SECTION]; 1250 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1251 [TX_PWR_BY_RATE_NUM_RF] 1252 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1253 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1254 [TX_PWR_BY_RATE_NUM_RF] 1255 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1256 u8 default_initialgain[4]; 1257 1258 /* the current Tx power level */ 1259 u8 cur_cck_txpwridx; 1260 u8 cur_ofdm24g_txpwridx; 1261 u8 cur_bw20_txpwridx; 1262 u8 cur_bw40_txpwridx; 1263 1264 char txpwr_limit_2_4g[MAX_REGULATION_NUM] 1265 [MAX_2_4G_BANDWITH_NUM] 1266 [MAX_RATE_SECTION_NUM] 1267 [CHANNEL_MAX_NUMBER_2G] 1268 [MAX_RF_PATH_NUM]; 1269 char txpwr_limit_5g[MAX_REGULATION_NUM] 1270 [MAX_5G_BANDWITH_NUM] 1271 [MAX_RATE_SECTION_NUM] 1272 [CHANNEL_MAX_NUMBER_5G] 1273 [MAX_RF_PATH_NUM]; 1274 1275 u32 rfreg_chnlval[2]; 1276 bool apk_done; 1277 u32 reg_rf3c[2]; /* pathA / pathB */ 1278 1279 u32 backup_rf_0x1a;/*92ee*/ 1280 /* bfsync */ 1281 u8 framesync; 1282 u32 framesync_c34; 1283 1284 u8 num_total_rfpath; 1285 struct phy_parameters hwparam_tables[MAX_TAB]; 1286 u16 rf_pathmap; 1287 1288 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1289 enum rt_polarity_ctl polarity_ctl; 1290 }; 1291 1292 #define MAX_TID_COUNT 9 1293 #define RTL_AGG_STOP 0 1294 #define RTL_AGG_PROGRESS 1 1295 #define RTL_AGG_START 2 1296 #define RTL_AGG_OPERATIONAL 3 1297 #define RTL_AGG_OFF 0 1298 #define RTL_AGG_ON 1 1299 #define RTL_RX_AGG_START 1 1300 #define RTL_RX_AGG_STOP 0 1301 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1302 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1303 1304 struct rtl_ht_agg { 1305 u16 txq_id; 1306 u16 wait_for_ba; 1307 u16 start_idx; 1308 u64 bitmap; 1309 u32 rate_n_flags; 1310 u8 agg_state; 1311 u8 rx_agg_state; 1312 }; 1313 1314 struct rssi_sta { 1315 long undec_sm_pwdb; 1316 long undec_sm_cck; 1317 }; 1318 1319 struct rtl_tid_data { 1320 u16 seq_number; 1321 struct rtl_ht_agg agg; 1322 }; 1323 1324 struct rtl_sta_info { 1325 struct list_head list; 1326 u8 ratr_index; 1327 u8 wireless_mode; 1328 u8 mimo_ps; 1329 u8 mac_addr[ETH_ALEN]; 1330 struct rtl_tid_data tids[MAX_TID_COUNT]; 1331 1332 /* just used for ap adhoc or mesh*/ 1333 struct rssi_sta rssi_stat; 1334 } __packed; 1335 1336 struct rtl_priv; 1337 struct rtl_io { 1338 struct device *dev; 1339 struct mutex bb_mutex; 1340 1341 /*PCI MEM map */ 1342 unsigned long pci_mem_end; /*shared mem end */ 1343 unsigned long pci_mem_start; /*shared mem start */ 1344 1345 /*PCI IO map */ 1346 unsigned long pci_base_addr; /*device I/O address */ 1347 1348 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1349 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1350 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1351 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1352 u16 len); 1353 1354 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1355 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1356 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1357 1358 }; 1359 1360 struct rtl_mac { 1361 u8 mac_addr[ETH_ALEN]; 1362 u8 mac80211_registered; 1363 u8 beacon_enabled; 1364 1365 u32 tx_ss_num; 1366 u32 rx_ss_num; 1367 1368 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; 1369 struct ieee80211_hw *hw; 1370 struct ieee80211_vif *vif; 1371 enum nl80211_iftype opmode; 1372 1373 /*Probe Beacon management */ 1374 struct rtl_tid_data tids[MAX_TID_COUNT]; 1375 enum rtl_link_state link_state; 1376 1377 int n_channels; 1378 int n_bitrates; 1379 1380 bool offchan_delay; 1381 u8 p2p; /*using p2p role*/ 1382 bool p2p_in_use; 1383 1384 /*filters */ 1385 u32 rx_conf; 1386 u16 rx_mgt_filter; 1387 u16 rx_ctrl_filter; 1388 u16 rx_data_filter; 1389 1390 bool act_scanning; 1391 u8 cnt_after_linked; 1392 bool skip_scan; 1393 1394 /* early mode */ 1395 /* skb wait queue */ 1396 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1397 1398 u8 ht_stbc_cap; 1399 u8 ht_cur_stbc; 1400 1401 /*vht support*/ 1402 u8 vht_enable; 1403 u8 bw_80; 1404 u8 vht_cur_ldpc; 1405 u8 vht_cur_stbc; 1406 u8 vht_stbc_cap; 1407 u8 vht_ldpc_cap; 1408 1409 /*RDG*/ 1410 bool rdg_en; 1411 1412 /*AP*/ 1413 u8 bssid[ETH_ALEN] __aligned(2); 1414 u32 vendor; 1415 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1416 u32 basic_rates; /* b/g rates */ 1417 u8 ht_enable; 1418 u8 sgi_40; 1419 u8 sgi_20; 1420 u8 bw_40; 1421 u16 mode; /* wireless mode */ 1422 u8 slot_time; 1423 u8 short_preamble; 1424 u8 use_cts_protect; 1425 u8 cur_40_prime_sc; 1426 u8 cur_40_prime_sc_bk; 1427 u8 cur_80_prime_sc; 1428 u64 tsf; 1429 u8 retry_short; 1430 u8 retry_long; 1431 u16 assoc_id; 1432 bool hiddenssid; 1433 1434 /*IBSS*/ 1435 int beacon_interval; 1436 1437 /*AMPDU*/ 1438 u8 min_space_cfg; /*For Min spacing configurations */ 1439 u8 max_mss_density; 1440 u8 current_ampdu_factor; 1441 u8 current_ampdu_density; 1442 1443 /*QOS & EDCA */ 1444 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1445 struct rtl_qos_parameters ac[AC_MAX]; 1446 1447 /* counters */ 1448 u64 last_txok_cnt; 1449 u64 last_rxok_cnt; 1450 u32 last_bt_edca_ul; 1451 u32 last_bt_edca_dl; 1452 }; 1453 1454 struct btdm_8723 { 1455 bool all_off; 1456 bool agc_table_en; 1457 bool adc_back_off_on; 1458 bool b2_ant_hid_en; 1459 bool low_penalty_rate_adaptive; 1460 bool rf_rx_lpf_shrink; 1461 bool reject_aggre_pkt; 1462 bool tra_tdma_on; 1463 u8 tra_tdma_nav; 1464 u8 tra_tdma_ant; 1465 bool tdma_on; 1466 u8 tdma_ant; 1467 u8 tdma_nav; 1468 u8 tdma_dac_swing; 1469 u8 fw_dac_swing_lvl; 1470 bool ps_tdma_on; 1471 u8 ps_tdma_byte[5]; 1472 bool pta_on; 1473 u32 val_0x6c0; 1474 u32 val_0x6c8; 1475 u32 val_0x6cc; 1476 bool sw_dac_swing_on; 1477 u32 sw_dac_swing_lvl; 1478 u32 wlan_act_hi; 1479 u32 wlan_act_lo; 1480 u32 bt_retry_index; 1481 bool dec_bt_pwr; 1482 bool ignore_wlan_act; 1483 }; 1484 1485 struct bt_coexist_8723 { 1486 u32 high_priority_tx; 1487 u32 high_priority_rx; 1488 u32 low_priority_tx; 1489 u32 low_priority_rx; 1490 u8 c2h_bt_info; 1491 bool c2h_bt_info_req_sent; 1492 bool c2h_bt_inquiry_page; 1493 u32 bt_inq_page_start_time; 1494 u8 bt_retry_cnt; 1495 u8 c2h_bt_info_original; 1496 u8 bt_inquiry_page_cnt; 1497 struct btdm_8723 btdm; 1498 }; 1499 1500 struct rtl_hal { 1501 struct ieee80211_hw *hw; 1502 bool driver_is_goingto_unload; 1503 bool up_first_time; 1504 bool first_init; 1505 bool being_init_adapter; 1506 bool bbrf_ready; 1507 bool mac_func_enable; 1508 bool pre_edcca_enable; 1509 struct bt_coexist_8723 hal_coex_8723; 1510 1511 enum intf_type interface; 1512 u16 hw_type; /*92c or 92d or 92s and so on */ 1513 u8 ic_class; 1514 u8 oem_id; 1515 u32 version; /*version of chip */ 1516 u8 state; /*stop 0, start 1 */ 1517 u8 board_type; 1518 u8 external_pa; 1519 1520 u8 pa_mode; 1521 u8 pa_type_2g; 1522 u8 pa_type_5g; 1523 u8 lna_type_2g; 1524 u8 lna_type_5g; 1525 u8 external_pa_2g; 1526 u8 external_lna_2g; 1527 u8 external_pa_5g; 1528 u8 external_lna_5g; 1529 u8 rfe_type; 1530 1531 /*firmware */ 1532 u32 fwsize; 1533 u8 *pfirmware; 1534 u16 fw_version; 1535 u16 fw_subversion; 1536 bool h2c_setinprogress; 1537 u8 last_hmeboxnum; 1538 bool fw_ready; 1539 /*Reserve page start offset except beacon in TxQ. */ 1540 u8 fw_rsvdpage_startoffset; 1541 u8 h2c_txcmd_seq; 1542 u8 current_ra_rate; 1543 1544 /* FW Cmd IO related */ 1545 u16 fwcmd_iomap; 1546 u32 fwcmd_ioparam; 1547 bool set_fwcmd_inprogress; 1548 u8 current_fwcmd_io; 1549 1550 struct p2p_ps_offload_t p2p_ps_offload; 1551 bool fw_clk_change_in_progress; 1552 bool allow_sw_to_change_hwclc; 1553 u8 fw_ps_state; 1554 /**/ 1555 bool driver_going2unload; 1556 1557 /*AMPDU init min space*/ 1558 u8 minspace_cfg; /*For Min spacing configurations */ 1559 1560 /* Dual mac */ 1561 enum macphy_mode macphymode; 1562 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1563 enum band_type current_bandtypebackup; 1564 enum band_type bandset; 1565 /* dual MAC 0--Mac0 1--Mac1 */ 1566 u32 interfaceindex; 1567 /* just for DualMac S3S4 */ 1568 u8 macphyctl_reg; 1569 bool earlymode_enable; 1570 u8 max_earlymode_num; 1571 /* Dual mac*/ 1572 bool during_mac0init_radiob; 1573 bool during_mac1init_radioa; 1574 bool reloadtxpowerindex; 1575 /* True if IMR or IQK have done 1576 for 2.4G in scan progress */ 1577 bool load_imrandiqk_setting_for2g; 1578 1579 bool disable_amsdu_8k; 1580 bool master_of_dmsp; 1581 bool slave_of_dmsp; 1582 1583 u16 rx_tag;/*for 92ee*/ 1584 u8 rts_en; 1585 1586 /*for wowlan*/ 1587 bool wow_enable; 1588 bool enter_pnp_sleep; 1589 bool wake_from_pnp_sleep; 1590 bool wow_enabled; 1591 __kernel_time_t last_suspend_sec; 1592 u32 wowlan_fwsize; 1593 u8 *wowlan_firmware; 1594 1595 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1596 1597 bool real_wow_v2_enable; 1598 bool re_init_llt_table; 1599 }; 1600 1601 struct rtl_security { 1602 /*default 0 */ 1603 bool use_sw_sec; 1604 1605 bool being_setkey; 1606 bool use_defaultkey; 1607 /*Encryption Algorithm for Unicast Packet */ 1608 enum rt_enc_alg pairwise_enc_algorithm; 1609 /*Encryption Algorithm for Brocast/Multicast */ 1610 enum rt_enc_alg group_enc_algorithm; 1611 /*Cam Entry Bitmap */ 1612 u32 hwsec_cam_bitmap; 1613 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1614 /*local Key buffer, indx 0 is for 1615 pairwise key 1-4 is for agoup key. */ 1616 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1617 u8 key_len[KEY_BUF_SIZE]; 1618 1619 /*The pointer of Pairwise Key, 1620 it always points to KeyBuf[4] */ 1621 u8 *pairwise_key; 1622 }; 1623 1624 #define ASSOCIATE_ENTRY_NUM 33 1625 1626 struct fast_ant_training { 1627 u8 bssid[6]; 1628 u8 antsel_rx_keep_0; 1629 u8 antsel_rx_keep_1; 1630 u8 antsel_rx_keep_2; 1631 u32 ant_sum[7]; 1632 u32 ant_cnt[7]; 1633 u32 ant_ave[7]; 1634 u8 fat_state; 1635 u32 train_idx; 1636 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1637 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1638 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1639 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1640 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1641 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1642 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1643 u8 rx_idle_ant; 1644 bool becomelinked; 1645 }; 1646 1647 struct dm_phy_dbg_info { 1648 char rx_snrdb[4]; 1649 u64 num_qry_phy_status; 1650 u64 num_qry_phy_status_cck; 1651 u64 num_qry_phy_status_ofdm; 1652 u16 num_qry_beacon_pkt; 1653 u16 num_non_be_pkt; 1654 s32 rx_evm[4]; 1655 }; 1656 1657 struct rtl_dm { 1658 /*PHY status for Dynamic Management */ 1659 long entry_min_undec_sm_pwdb; 1660 long undec_sm_cck; 1661 long undec_sm_pwdb; /*out dm */ 1662 long entry_max_undec_sm_pwdb; 1663 s32 ofdm_pkt_cnt; 1664 bool dm_initialgain_enable; 1665 bool dynamic_txpower_enable; 1666 bool current_turbo_edca; 1667 bool is_any_nonbepkts; /*out dm */ 1668 bool is_cur_rdlstate; 1669 bool txpower_trackinginit; 1670 bool disable_framebursting; 1671 bool cck_inch14; 1672 bool txpower_tracking; 1673 bool useramask; 1674 bool rfpath_rxenable[4]; 1675 bool inform_fw_driverctrldm; 1676 bool current_mrc_switch; 1677 u8 txpowercount; 1678 u8 powerindex_backup[6]; 1679 1680 u8 thermalvalue_rxgain; 1681 u8 thermalvalue_iqk; 1682 u8 thermalvalue_lck; 1683 u8 thermalvalue; 1684 u8 last_dtp_lvl; 1685 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1686 u8 thermalvalue_avg_index; 1687 u8 tm_trigger; 1688 bool done_txpower; 1689 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1690 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1691 u8 dm_flag_tmp; 1692 u8 dm_type; 1693 u8 dm_rssi_sel; 1694 u8 txpower_track_control; 1695 bool interrupt_migration; 1696 bool disable_tx_int; 1697 char ofdm_index[MAX_RF_PATH]; 1698 u8 default_ofdm_index; 1699 u8 default_cck_index; 1700 char cck_index; 1701 char delta_power_index[MAX_RF_PATH]; 1702 char delta_power_index_last[MAX_RF_PATH]; 1703 char power_index_offset[MAX_RF_PATH]; 1704 char absolute_ofdm_swing_idx[MAX_RF_PATH]; 1705 char remnant_ofdm_swing_idx[MAX_RF_PATH]; 1706 char remnant_cck_idx; 1707 bool modify_txagc_flag_path_a; 1708 bool modify_txagc_flag_path_b; 1709 1710 bool one_entry_only; 1711 struct dm_phy_dbg_info dbginfo; 1712 1713 /* Dynamic ATC switch */ 1714 bool atc_status; 1715 bool large_cfo_hit; 1716 bool is_freeze; 1717 int cfo_tail[2]; 1718 int cfo_ave_pre; 1719 int crystal_cap; 1720 u8 cfo_threshold; 1721 u32 packet_count; 1722 u32 packet_count_pre; 1723 u8 tx_rate; 1724 1725 /*88e tx power tracking*/ 1726 u8 swing_idx_ofdm[MAX_RF_PATH]; 1727 u8 swing_idx_ofdm_cur; 1728 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1729 bool swing_flag_ofdm; 1730 u8 swing_idx_cck; 1731 u8 swing_idx_cck_cur; 1732 u8 swing_idx_cck_base; 1733 bool swing_flag_cck; 1734 1735 char swing_diff_2g; 1736 char swing_diff_5g; 1737 1738 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ]; 1739 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ]; 1740 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ]; 1741 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ]; 1742 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ]; 1743 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ]; 1744 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ]; 1745 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ]; 1746 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ]; 1747 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ]; 1748 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ]; 1749 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ]; 1750 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ]; 1751 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ]; 1752 1753 /* DMSP */ 1754 bool supp_phymode_switch; 1755 1756 /* DulMac */ 1757 struct fast_ant_training fat_table; 1758 1759 u8 resp_tx_path; 1760 u8 path_sel; 1761 u32 patha_sum; 1762 u32 pathb_sum; 1763 u32 patha_cnt; 1764 u32 pathb_cnt; 1765 1766 u8 pre_channel; 1767 u8 *p_channel; 1768 u8 linked_interval; 1769 1770 u64 last_tx_ok_cnt; 1771 u64 last_rx_ok_cnt; 1772 }; 1773 1774 #define EFUSE_MAX_LOGICAL_SIZE 512 1775 1776 struct rtl_efuse { 1777 bool autoLoad_ok; 1778 bool bootfromefuse; 1779 u16 max_physical_size; 1780 1781 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1782 u16 efuse_usedbytes; 1783 u8 efuse_usedpercentage; 1784 #ifdef EFUSE_REPG_WORKAROUND 1785 bool efuse_re_pg_sec1flag; 1786 u8 efuse_re_pg_data[8]; 1787 #endif 1788 1789 u8 autoload_failflag; 1790 u8 autoload_status; 1791 1792 short epromtype; 1793 u16 eeprom_vid; 1794 u16 eeprom_did; 1795 u16 eeprom_svid; 1796 u16 eeprom_smid; 1797 u8 eeprom_oemid; 1798 u16 eeprom_channelplan; 1799 u8 eeprom_version; 1800 u8 board_type; 1801 u8 external_pa; 1802 1803 u8 dev_addr[6]; 1804 u8 wowlan_enable; 1805 u8 antenna_div_cfg; 1806 u8 antenna_div_type; 1807 1808 bool txpwr_fromeprom; 1809 u8 eeprom_crystalcap; 1810 u8 eeprom_tssi[2]; 1811 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1812 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1813 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1814 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1815 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1816 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1817 1818 u8 internal_pa_5g[2]; /* pathA / pathB */ 1819 u8 eeprom_c9; 1820 u8 eeprom_cc; 1821 1822 /*For power group */ 1823 u8 eeprom_pwrgroup[2][3]; 1824 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1825 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1826 1827 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1828 /*For HT 40MHZ pwr */ 1829 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1830 /*For HT 40MHZ pwr */ 1831 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1832 1833 /*--------------------------------------------------------* 1834 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1835 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1836 * define new arrays in Windows code. 1837 * BUT, in linux code, we use the same array for all ICs. 1838 * 1839 * The Correspondance relation between two arrays is: 1840 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1841 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1842 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1843 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1844 * 1845 * Sizes of these arrays are decided by the larger ones. 1846 */ 1847 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1848 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1849 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1850 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1851 1852 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1853 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1854 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1855 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1856 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1857 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1858 1859 u8 txpwr_safetyflag; /* Band edge enable flag */ 1860 u16 eeprom_txpowerdiff; 1861 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1862 u8 antenna_txpwdiff[3]; 1863 1864 u8 eeprom_regulatory; 1865 u8 eeprom_thermalmeter; 1866 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1867 u16 tssi_13dbm; 1868 u8 crystalcap; /* CrystalCap. */ 1869 u8 delta_iqk; 1870 u8 delta_lck; 1871 1872 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1873 bool apk_thermalmeterignore; 1874 1875 bool b1x1_recvcombine; 1876 bool b1ss_support; 1877 1878 /*channel plan */ 1879 u8 channel_plan; 1880 }; 1881 1882 struct rtl_ps_ctl { 1883 bool pwrdomain_protect; 1884 bool in_powersavemode; 1885 bool rfchange_inprogress; 1886 bool swrf_processing; 1887 bool hwradiooff; 1888 /* 1889 * just for PCIE ASPM 1890 * If it supports ASPM, Offset[560h] = 0x40, 1891 * otherwise Offset[560h] = 0x00. 1892 * */ 1893 bool support_aspm; 1894 bool support_backdoor; 1895 1896 /*for LPS */ 1897 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1898 bool swctrl_lps; 1899 bool leisure_ps; 1900 bool fwctrl_lps; 1901 u8 fwctrl_psmode; 1902 /*For Fw control LPS mode */ 1903 u8 reg_fwctrl_lps; 1904 /*Record Fw PS mode status. */ 1905 bool fw_current_inpsmode; 1906 u8 reg_max_lps_awakeintvl; 1907 bool report_linked; 1908 bool low_power_enable;/*for 32k*/ 1909 1910 /*for IPS */ 1911 bool inactiveps; 1912 1913 u32 rfoff_reason; 1914 1915 /*RF OFF Level */ 1916 u32 cur_ps_level; 1917 u32 reg_rfps_level; 1918 1919 /*just for PCIE ASPM */ 1920 u8 const_amdpci_aspm; 1921 bool pwrdown_mode; 1922 1923 enum rf_pwrstate inactive_pwrstate; 1924 enum rf_pwrstate rfpwr_state; /*cur power state */ 1925 1926 /* for SW LPS*/ 1927 bool sw_ps_enabled; 1928 bool state; 1929 bool state_inap; 1930 bool multi_buffered; 1931 u16 nullfunc_seq; 1932 unsigned int dtim_counter; 1933 unsigned int sleep_ms; 1934 unsigned long last_sleep_jiffies; 1935 unsigned long last_awake_jiffies; 1936 unsigned long last_delaylps_stamp_jiffies; 1937 unsigned long last_dtim; 1938 unsigned long last_beacon; 1939 unsigned long last_action; 1940 unsigned long last_slept; 1941 1942 /*For P2P PS */ 1943 struct rtl_p2p_ps_info p2p_ps_info; 1944 u8 pwr_mode; 1945 u8 smart_ps; 1946 1947 /* wake up on line */ 1948 u8 wo_wlan_mode; 1949 u8 arp_offload_enable; 1950 u8 gtk_offload_enable; 1951 /* Used for WOL, indicates the reason for waking event.*/ 1952 u32 wakeup_reason; 1953 /* Record the last waking time for comparison with setting key. */ 1954 u64 last_wakeup_time; 1955 }; 1956 1957 struct rtl_stats { 1958 u8 psaddr[ETH_ALEN]; 1959 u32 mac_time[2]; 1960 s8 rssi; 1961 u8 signal; 1962 u8 noise; 1963 u8 rate; /* hw desc rate */ 1964 u8 received_channel; 1965 u8 control; 1966 u8 mask; 1967 u8 freq; 1968 u16 len; 1969 u64 tsf; 1970 u32 beacon_time; 1971 u8 nic_type; 1972 u16 length; 1973 u8 signalquality; /*in 0-100 index. */ 1974 /* 1975 * Real power in dBm for this packet, 1976 * no beautification and aggregation. 1977 * */ 1978 s32 recvsignalpower; 1979 s8 rxpower; /*in dBm Translate from PWdB */ 1980 u8 signalstrength; /*in 0-100 index. */ 1981 u16 hwerror:1; 1982 u16 crc:1; 1983 u16 icv:1; 1984 u16 shortpreamble:1; 1985 u16 antenna:1; 1986 u16 decrypted:1; 1987 u16 wakeup:1; 1988 u32 timestamp_low; 1989 u32 timestamp_high; 1990 bool shift; 1991 1992 u8 rx_drvinfo_size; 1993 u8 rx_bufshift; 1994 bool isampdu; 1995 bool isfirst_ampdu; 1996 bool rx_is40Mhzpacket; 1997 u8 rx_packet_bw; 1998 u32 rx_pwdb_all; 1999 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2000 s8 rx_mimo_signalquality[4]; 2001 u8 rx_mimo_evm_dbm[4]; 2002 u16 cfo_short[4]; /* per-path's Cfo_short */ 2003 u16 cfo_tail[4]; 2004 2005 s8 rx_mimo_sig_qual[4]; 2006 u8 rx_pwr[4]; /* per-path's pwdb */ 2007 u8 rx_snr[4]; /* per-path's SNR */ 2008 u8 bandwidth; 2009 u8 bt_coex_pwr_adjust; 2010 bool packet_matchbssid; 2011 bool is_cck; 2012 bool is_ht; 2013 bool packet_toself; 2014 bool packet_beacon; /*for rssi */ 2015 char cck_adc_pwdb[4]; /*for rx path selection */ 2016 2017 bool is_vht; 2018 bool is_short_gi; 2019 u8 vht_nss; 2020 2021 u8 packet_report_type; 2022 2023 u32 macid; 2024 u8 wake_match; 2025 u32 bt_rx_rssi_percentage; 2026 u32 macid_valid_entry[2]; 2027 }; 2028 2029 2030 struct rt_link_detect { 2031 /* count for roaming */ 2032 u32 bcn_rx_inperiod; 2033 u32 roam_times; 2034 2035 u32 num_tx_in4period[4]; 2036 u32 num_rx_in4period[4]; 2037 2038 u32 num_tx_inperiod; 2039 u32 num_rx_inperiod; 2040 2041 bool busytraffic; 2042 bool tx_busy_traffic; 2043 bool rx_busy_traffic; 2044 bool higher_busytraffic; 2045 bool higher_busyrxtraffic; 2046 2047 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2048 u32 tidtx_inperiod[MAX_TID_COUNT]; 2049 bool higher_busytxtraffic[MAX_TID_COUNT]; 2050 }; 2051 2052 struct rtl_tcb_desc { 2053 u8 packet_bw:2; 2054 u8 multicast:1; 2055 u8 broadcast:1; 2056 2057 u8 rts_stbc:1; 2058 u8 rts_enable:1; 2059 u8 cts_enable:1; 2060 u8 rts_use_shortpreamble:1; 2061 u8 rts_use_shortgi:1; 2062 u8 rts_sc:1; 2063 u8 rts_bw:1; 2064 u8 rts_rate; 2065 2066 u8 use_shortgi:1; 2067 u8 use_shortpreamble:1; 2068 u8 use_driver_rate:1; 2069 u8 disable_ratefallback:1; 2070 2071 u8 ratr_index; 2072 u8 mac_id; 2073 u8 hw_rate; 2074 2075 u8 last_inipkt:1; 2076 u8 cmd_or_init:1; 2077 u8 queue_index; 2078 2079 /* early mode */ 2080 u8 empkt_num; 2081 /* The max value by HW */ 2082 u32 empkt_len[10]; 2083 bool tx_enable_sw_calc_duration; 2084 }; 2085 2086 struct rtl_wow_pattern { 2087 u8 type; 2088 u16 crc; 2089 u32 mask[4]; 2090 }; 2091 2092 struct rtl_hal_ops { 2093 int (*init_sw_vars) (struct ieee80211_hw *hw); 2094 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2095 void (*read_chip_version)(struct ieee80211_hw *hw); 2096 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2097 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2098 u32 *p_inta, u32 *p_intb); 2099 int (*hw_init) (struct ieee80211_hw *hw); 2100 void (*hw_disable) (struct ieee80211_hw *hw); 2101 void (*hw_suspend) (struct ieee80211_hw *hw); 2102 void (*hw_resume) (struct ieee80211_hw *hw); 2103 void (*enable_interrupt) (struct ieee80211_hw *hw); 2104 void (*disable_interrupt) (struct ieee80211_hw *hw); 2105 int (*set_network_type) (struct ieee80211_hw *hw, 2106 enum nl80211_iftype type); 2107 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2108 bool check_bssid); 2109 void (*set_bw_mode) (struct ieee80211_hw *hw, 2110 enum nl80211_channel_type ch_type); 2111 u8(*switch_channel) (struct ieee80211_hw *hw); 2112 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2113 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2114 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2115 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2116 u32 add_msr, u32 rm_msr); 2117 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2118 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2119 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2120 struct ieee80211_sta *sta, u8 rssi_level); 2121 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2122 u8 *desc, u8 queue_index, 2123 struct sk_buff *skb, dma_addr_t addr); 2124 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2125 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2126 u8 queue_index); 2127 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2128 u8 queue_index); 2129 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2130 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2131 u8 *pbd_desc_tx, 2132 struct ieee80211_tx_info *info, 2133 struct ieee80211_sta *sta, 2134 struct sk_buff *skb, u8 hw_queue, 2135 struct rtl_tcb_desc *ptcb_desc); 2136 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2137 u32 buffer_len, bool bIsPsPoll); 2138 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2139 bool firstseg, bool lastseg, 2140 struct sk_buff *skb); 2141 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2142 struct rtl_stats *stats, 2143 struct ieee80211_rx_status *rx_status, 2144 u8 *pdesc, struct sk_buff *skb); 2145 void (*set_channel_access) (struct ieee80211_hw *hw); 2146 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2147 void (*dm_watchdog) (struct ieee80211_hw *hw); 2148 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2149 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2150 enum rf_pwrstate rfpwr_state); 2151 void (*led_control) (struct ieee80211_hw *hw, 2152 enum led_ctl_mode ledaction); 2153 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2154 u8 desc_name, u8 *val); 2155 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); 2156 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2157 u8 hw_queue, u16 index); 2158 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2159 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2160 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2161 u8 *macaddr, bool is_group, u8 enc_algo, 2162 bool is_wepkey, bool clear_all); 2163 void (*init_sw_leds) (struct ieee80211_hw *hw); 2164 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2165 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2166 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2167 u32 data); 2168 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2169 u32 regaddr, u32 bitmask); 2170 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2171 u32 regaddr, u32 bitmask, u32 data); 2172 void (*linked_set_reg) (struct ieee80211_hw *hw); 2173 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2174 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2175 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2176 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2177 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2178 u8 *powerlevel); 2179 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2180 u8 *ppowerlevel, u8 channel); 2181 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2182 u8 configtype); 2183 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2184 u8 configtype); 2185 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2186 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2187 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2188 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2189 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2190 bool mstate); 2191 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2192 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2193 u32 cmd_len, u8 *p_cmdbuffer); 2194 bool (*get_btc_status) (void); 2195 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2196 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2197 struct rtl_stats status, struct sk_buff *skb); 2198 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2199 struct rtl_wow_pattern *rtl_pattern, 2200 u8 index); 2201 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2202 }; 2203 2204 struct rtl_intf_ops { 2205 /*com */ 2206 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2207 int (*adapter_start) (struct ieee80211_hw *hw); 2208 void (*adapter_stop) (struct ieee80211_hw *hw); 2209 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2210 struct rtl_priv **buddy_priv); 2211 2212 int (*adapter_tx) (struct ieee80211_hw *hw, 2213 struct ieee80211_sta *sta, 2214 struct sk_buff *skb, 2215 struct rtl_tcb_desc *ptcb_desc); 2216 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2217 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2218 bool (*waitq_insert) (struct ieee80211_hw *hw, 2219 struct ieee80211_sta *sta, 2220 struct sk_buff *skb); 2221 2222 /*pci */ 2223 void (*disable_aspm) (struct ieee80211_hw *hw); 2224 void (*enable_aspm) (struct ieee80211_hw *hw); 2225 2226 /*usb */ 2227 }; 2228 2229 struct rtl_mod_params { 2230 /* default: 0 = using hardware encryption */ 2231 bool sw_crypto; 2232 2233 /* default: 0 = DBG_EMERG (0)*/ 2234 int debug; 2235 2236 /* default: 1 = using no linked power save */ 2237 bool inactiveps; 2238 2239 /* default: 1 = using linked sw power save */ 2240 bool swctrl_lps; 2241 2242 /* default: 1 = using linked fw power save */ 2243 bool fwctrl_lps; 2244 2245 /* default: 0 = not using MSI interrupts mode 2246 * submodules should set their own default value 2247 */ 2248 bool msi_support; 2249 2250 /* default 0: 1 means disable */ 2251 bool disable_watchdog; 2252 2253 /* default 0: 1 means do not disable interrupts */ 2254 bool int_clear; 2255 }; 2256 2257 struct rtl_hal_usbint_cfg { 2258 /* data - rx */ 2259 u32 in_ep_num; 2260 u32 rx_urb_num; 2261 u32 rx_max_size; 2262 2263 /* op - rx */ 2264 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2265 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2266 struct sk_buff_head *); 2267 2268 /* tx */ 2269 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2270 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2271 struct sk_buff *); 2272 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2273 struct sk_buff_head *); 2274 2275 /* endpoint mapping */ 2276 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2277 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2278 }; 2279 2280 struct rtl_hal_cfg { 2281 u8 bar_id; 2282 bool write_readback; 2283 char *name; 2284 char *fw_name; 2285 char *alt_fw_name; 2286 char *wowlan_fw_name; 2287 struct rtl_hal_ops *ops; 2288 struct rtl_mod_params *mod_params; 2289 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2290 2291 /*this map used for some registers or vars 2292 defined int HAL but used in MAIN */ 2293 u32 maps[RTL_VAR_MAP_MAX]; 2294 2295 }; 2296 2297 struct rtl_locks { 2298 /* mutex */ 2299 struct mutex conf_mutex; 2300 struct mutex ps_mutex; 2301 2302 /*spin lock */ 2303 spinlock_t ips_lock; 2304 spinlock_t irq_th_lock; 2305 spinlock_t irq_pci_lock; 2306 spinlock_t tx_lock; 2307 spinlock_t h2c_lock; 2308 spinlock_t rf_ps_lock; 2309 spinlock_t rf_lock; 2310 spinlock_t lps_lock; 2311 spinlock_t waitq_lock; 2312 spinlock_t entry_list_lock; 2313 spinlock_t usb_lock; 2314 2315 /*FW clock change */ 2316 spinlock_t fw_ps_lock; 2317 2318 /*Dual mac*/ 2319 spinlock_t cck_and_rw_pagea_lock; 2320 2321 /*Easy concurrent*/ 2322 spinlock_t check_sendpkt_lock; 2323 2324 spinlock_t iqk_lock; 2325 }; 2326 2327 struct rtl_works { 2328 struct ieee80211_hw *hw; 2329 2330 /*timer */ 2331 struct timer_list watchdog_timer; 2332 struct timer_list dualmac_easyconcurrent_retrytimer; 2333 struct timer_list fw_clockoff_timer; 2334 struct timer_list fast_antenna_training_timer; 2335 /*task */ 2336 struct tasklet_struct irq_tasklet; 2337 struct tasklet_struct irq_prepare_bcn_tasklet; 2338 2339 /*work queue */ 2340 struct workqueue_struct *rtl_wq; 2341 struct delayed_work watchdog_wq; 2342 struct delayed_work ips_nic_off_wq; 2343 2344 /* For SW LPS */ 2345 struct delayed_work ps_work; 2346 struct delayed_work ps_rfon_wq; 2347 struct delayed_work fwevt_wq; 2348 2349 struct work_struct lps_change_work; 2350 struct work_struct fill_h2c_cmd; 2351 }; 2352 2353 struct rtl_debug { 2354 u32 dbgp_type[DBGP_TYPE_MAX]; 2355 int global_debuglevel; 2356 u64 global_debugcomponents; 2357 2358 /* add for proc debug */ 2359 struct proc_dir_entry *proc_dir; 2360 char proc_name[20]; 2361 }; 2362 2363 #define MIMO_PS_STATIC 0 2364 #define MIMO_PS_DYNAMIC 1 2365 #define MIMO_PS_NOLIMIT 3 2366 2367 struct rtl_dualmac_easy_concurrent_ctl { 2368 enum band_type currentbandtype_backfordmdp; 2369 bool close_bbandrf_for_dmsp; 2370 bool change_to_dmdp; 2371 bool change_to_dmsp; 2372 bool switch_in_process; 2373 }; 2374 2375 struct rtl_dmsp_ctl { 2376 bool activescan_for_slaveofdmsp; 2377 bool scan_for_anothermac_fordmsp; 2378 bool scan_for_itself_fordmsp; 2379 bool writedig_for_anothermacofdmsp; 2380 u32 curdigvalue_for_anothermacofdmsp; 2381 bool changecckpdstate_for_anothermacofdmsp; 2382 u8 curcckpdstate_for_anothermacofdmsp; 2383 bool changetxhighpowerlvl_for_anothermacofdmsp; 2384 u8 curtxhighlvl_for_anothermacofdmsp; 2385 long rssivalmin_for_anothermacofdmsp; 2386 }; 2387 2388 struct ps_t { 2389 u8 pre_ccastate; 2390 u8 cur_ccasate; 2391 u8 pre_rfstate; 2392 u8 cur_rfstate; 2393 u8 initialize; 2394 long rssi_val_min; 2395 }; 2396 2397 struct dig_t { 2398 u32 rssi_lowthresh; 2399 u32 rssi_highthresh; 2400 u32 fa_lowthresh; 2401 u32 fa_highthresh; 2402 long last_min_undec_pwdb_for_dm; 2403 long rssi_highpower_lowthresh; 2404 long rssi_highpower_highthresh; 2405 u32 recover_cnt; 2406 u32 pre_igvalue; 2407 u32 cur_igvalue; 2408 long rssi_val; 2409 u8 dig_enable_flag; 2410 u8 dig_ext_port_stage; 2411 u8 dig_algorithm; 2412 u8 dig_twoport_algorithm; 2413 u8 dig_dbgmode; 2414 u8 dig_slgorithm_switch; 2415 u8 cursta_cstate; 2416 u8 presta_cstate; 2417 u8 curmultista_cstate; 2418 u8 stop_dig; 2419 char back_val; 2420 char back_range_max; 2421 char back_range_min; 2422 u8 rx_gain_max; 2423 u8 rx_gain_min; 2424 u8 min_undec_pwdb_for_dm; 2425 u8 rssi_val_min; 2426 u8 pre_cck_cca_thres; 2427 u8 cur_cck_cca_thres; 2428 u8 pre_cck_pd_state; 2429 u8 cur_cck_pd_state; 2430 u8 pre_cck_fa_state; 2431 u8 cur_cck_fa_state; 2432 u8 pre_ccastate; 2433 u8 cur_ccasate; 2434 u8 large_fa_hit; 2435 u8 forbidden_igi; 2436 u8 dig_state; 2437 u8 dig_highpwrstate; 2438 u8 cur_sta_cstate; 2439 u8 pre_sta_cstate; 2440 u8 cur_ap_cstate; 2441 u8 pre_ap_cstate; 2442 u8 cur_pd_thstate; 2443 u8 pre_pd_thstate; 2444 u8 cur_cs_ratiostate; 2445 u8 pre_cs_ratiostate; 2446 u8 backoff_enable_flag; 2447 char backoffval_range_max; 2448 char backoffval_range_min; 2449 u8 dig_min_0; 2450 u8 dig_min_1; 2451 u8 bt30_cur_igi; 2452 bool media_connect_0; 2453 bool media_connect_1; 2454 2455 u32 antdiv_rssi_max; 2456 u32 rssi_max; 2457 }; 2458 2459 struct rtl_global_var { 2460 /* from this list we can get 2461 * other adapter's rtl_priv */ 2462 struct list_head glb_priv_list; 2463 spinlock_t glb_list_lock; 2464 }; 2465 2466 struct rtl_btc_info { 2467 u8 bt_type; 2468 u8 btcoexist; 2469 u8 ant_num; 2470 }; 2471 2472 struct bt_coexist_info { 2473 struct rtl_btc_ops *btc_ops; 2474 struct rtl_btc_info btc_info; 2475 /* EEPROM BT info. */ 2476 u8 eeprom_bt_coexist; 2477 u8 eeprom_bt_type; 2478 u8 eeprom_bt_ant_num; 2479 u8 eeprom_bt_ant_isol; 2480 u8 eeprom_bt_radio_shared; 2481 2482 u8 bt_coexistence; 2483 u8 bt_ant_num; 2484 u8 bt_coexist_type; 2485 u8 bt_state; 2486 u8 bt_cur_state; /* 0:on, 1:off */ 2487 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2488 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2489 u8 bt_service; 2490 u8 bt_radio_shared_type; 2491 u8 bt_rfreg_origin_1e; 2492 u8 bt_rfreg_origin_1f; 2493 u8 bt_rssi_state; 2494 u32 ratio_tx; 2495 u32 ratio_pri; 2496 u32 bt_edca_ul; 2497 u32 bt_edca_dl; 2498 2499 bool init_set; 2500 bool bt_busy_traffic; 2501 bool bt_traffic_mode_set; 2502 bool bt_non_traffic_mode_set; 2503 2504 bool fw_coexist_all_off; 2505 bool sw_coexist_all_off; 2506 bool hw_coexist_all_off; 2507 u32 cstate; 2508 u32 previous_state; 2509 u32 cstate_h; 2510 u32 previous_state_h; 2511 2512 u8 bt_pre_rssi_state; 2513 u8 bt_pre_rssi_state1; 2514 2515 u8 reg_bt_iso; 2516 u8 reg_bt_sco; 2517 bool balance_on; 2518 u8 bt_active_zero_cnt; 2519 bool cur_bt_disabled; 2520 bool pre_bt_disabled; 2521 2522 u8 bt_profile_case; 2523 u8 bt_profile_action; 2524 bool bt_busy; 2525 bool hold_for_bt_operation; 2526 u8 lps_counter; 2527 }; 2528 2529 struct rtl_btc_ops { 2530 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2531 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2532 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2533 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2534 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2535 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2536 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2537 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2538 enum rt_media_status mstatus); 2539 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2540 void (*btc_halt_notify) (void); 2541 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2542 u8 *tmp_buf, u8 length); 2543 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2544 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2545 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2546 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2547 u8 pkt_type); 2548 }; 2549 2550 struct proxim { 2551 bool proxim_on; 2552 2553 void *proximity_priv; 2554 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2555 struct sk_buff *skb); 2556 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2557 }; 2558 2559 struct rtl_priv { 2560 struct ieee80211_hw *hw; 2561 struct completion firmware_loading_complete; 2562 struct list_head list; 2563 struct rtl_priv *buddy_priv; 2564 struct rtl_global_var *glb_var; 2565 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2566 struct rtl_dmsp_ctl dmsp_ctl; 2567 struct rtl_locks locks; 2568 struct rtl_works works; 2569 struct rtl_mac mac80211; 2570 struct rtl_hal rtlhal; 2571 struct rtl_regulatory regd; 2572 struct rtl_rfkill rfkill; 2573 struct rtl_io io; 2574 struct rtl_phy phy; 2575 struct rtl_dm dm; 2576 struct rtl_security sec; 2577 struct rtl_efuse efuse; 2578 2579 struct rtl_ps_ctl psc; 2580 struct rate_adaptive ra; 2581 struct dynamic_primary_cca primarycca; 2582 struct wireless_stats stats; 2583 struct rt_link_detect link_info; 2584 struct false_alarm_statistics falsealm_cnt; 2585 2586 struct rtl_rate_priv *rate_priv; 2587 2588 /* sta entry list for ap adhoc or mesh */ 2589 struct list_head entry_list; 2590 2591 struct rtl_debug dbg; 2592 int max_fw_size; 2593 2594 /* 2595 *hal_cfg : for diff cards 2596 *intf_ops : for diff interrface usb/pcie 2597 */ 2598 struct rtl_hal_cfg *cfg; 2599 struct rtl_intf_ops *intf_ops; 2600 2601 /*this var will be set by set_bit, 2602 and was used to indicate status of 2603 interface or hardware */ 2604 unsigned long status; 2605 2606 /* tables for dm */ 2607 struct dig_t dm_digtable; 2608 struct ps_t dm_pstable; 2609 2610 u32 reg_874; 2611 u32 reg_c70; 2612 u32 reg_85c; 2613 u32 reg_a74; 2614 bool reg_init; /* true if regs saved */ 2615 bool bt_operation_on; 2616 __le32 *usb_data; 2617 int usb_data_index; 2618 bool initialized; 2619 bool enter_ps; /* true when entering PS */ 2620 u8 rate_mask[5]; 2621 2622 /* intel Proximity, should be alloc mem 2623 * in intel Proximity module and can only 2624 * be used in intel Proximity mode 2625 */ 2626 struct proxim proximity; 2627 2628 /*for bt coexist use*/ 2629 struct bt_coexist_info btcoexist; 2630 2631 /* separate 92ee from other ICs, 2632 * 92ee use new trx flow. 2633 */ 2634 bool use_new_trx_flow; 2635 2636 #ifdef CONFIG_PM 2637 struct wiphy_wowlan_support wowlan; 2638 #endif 2639 /*This must be the last item so 2640 that it points to the data allocated 2641 beyond this structure like: 2642 rtl_pci_priv or rtl_usb_priv */ 2643 u8 priv[0] __aligned(sizeof(void *)); 2644 }; 2645 2646 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2647 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2648 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2649 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2650 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2651 2652 2653 /*************************************** 2654 Bluetooth Co-existence Related 2655 ****************************************/ 2656 2657 enum bt_ant_num { 2658 ANT_X2 = 0, 2659 ANT_X1 = 1, 2660 }; 2661 2662 enum bt_co_type { 2663 BT_2WIRE = 0, 2664 BT_ISSC_3WIRE = 1, 2665 BT_ACCEL = 2, 2666 BT_CSR_BC4 = 3, 2667 BT_CSR_BC8 = 4, 2668 BT_RTL8756 = 5, 2669 BT_RTL8723A = 6, 2670 BT_RTL8821A = 7, 2671 BT_RTL8723B = 8, 2672 BT_RTL8192E = 9, 2673 BT_RTL8812A = 11, 2674 }; 2675 2676 enum bt_total_ant_num { 2677 ANT_TOTAL_X2 = 0, 2678 ANT_TOTAL_X1 = 1 2679 }; 2680 2681 enum bt_cur_state { 2682 BT_OFF = 0, 2683 BT_ON = 1, 2684 }; 2685 2686 enum bt_service_type { 2687 BT_SCO = 0, 2688 BT_A2DP = 1, 2689 BT_HID = 2, 2690 BT_HID_IDLE = 3, 2691 BT_SCAN = 4, 2692 BT_IDLE = 5, 2693 BT_OTHER_ACTION = 6, 2694 BT_BUSY = 7, 2695 BT_OTHERBUSY = 8, 2696 BT_PAN = 9, 2697 }; 2698 2699 enum bt_radio_shared { 2700 BT_RADIO_SHARED = 0, 2701 BT_RADIO_INDIVIDUAL = 1, 2702 }; 2703 2704 2705 /**************************************** 2706 mem access macro define start 2707 Call endian free function when 2708 1. Read/write packet content. 2709 2. Before write integer to IO. 2710 3. After read integer from IO. 2711 ****************************************/ 2712 /* Convert little data endian to host ordering */ 2713 #define EF1BYTE(_val) \ 2714 ((u8)(_val)) 2715 #define EF2BYTE(_val) \ 2716 (le16_to_cpu(_val)) 2717 #define EF4BYTE(_val) \ 2718 (le32_to_cpu(_val)) 2719 2720 /* Read data from memory */ 2721 #define READEF1BYTE(_ptr) \ 2722 EF1BYTE(*((u8 *)(_ptr))) 2723 /* Read le16 data from memory and convert to host ordering */ 2724 #define READEF2BYTE(_ptr) \ 2725 EF2BYTE(*(_ptr)) 2726 #define READEF4BYTE(_ptr) \ 2727 EF4BYTE(*(_ptr)) 2728 2729 /* Write data to memory */ 2730 #define WRITEEF1BYTE(_ptr, _val) \ 2731 (*((u8 *)(_ptr))) = EF1BYTE(_val) 2732 /* Write le16 data to memory in host ordering */ 2733 #define WRITEEF2BYTE(_ptr, _val) \ 2734 (*((u16 *)(_ptr))) = EF2BYTE(_val) 2735 #define WRITEEF4BYTE(_ptr, _val) \ 2736 (*((u32 *)(_ptr))) = EF2BYTE(_val) 2737 2738 /* Create a bit mask 2739 * Examples: 2740 * BIT_LEN_MASK_32(0) => 0x00000000 2741 * BIT_LEN_MASK_32(1) => 0x00000001 2742 * BIT_LEN_MASK_32(2) => 0x00000003 2743 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2744 */ 2745 #define BIT_LEN_MASK_32(__bitlen) \ 2746 (0xFFFFFFFF >> (32 - (__bitlen))) 2747 #define BIT_LEN_MASK_16(__bitlen) \ 2748 (0xFFFF >> (16 - (__bitlen))) 2749 #define BIT_LEN_MASK_8(__bitlen) \ 2750 (0xFF >> (8 - (__bitlen))) 2751 2752 /* Create an offset bit mask 2753 * Examples: 2754 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2755 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2756 */ 2757 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2758 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2759 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2760 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2761 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2762 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2763 2764 /*Description: 2765 * Return 4-byte value in host byte ordering from 2766 * 4-byte pointer in little-endian system. 2767 */ 2768 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2769 (EF4BYTE(*((__le32 *)(__pstart)))) 2770 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2771 (EF2BYTE(*((__le16 *)(__pstart)))) 2772 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2773 (EF1BYTE(*((u8 *)(__pstart)))) 2774 2775 /*Description: 2776 Translate subfield (continuous bits in little-endian) of 4-byte 2777 value to host byte ordering.*/ 2778 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2779 ( \ 2780 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2781 BIT_LEN_MASK_32(__bitlen) \ 2782 ) 2783 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2784 ( \ 2785 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2786 BIT_LEN_MASK_16(__bitlen) \ 2787 ) 2788 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2789 ( \ 2790 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2791 BIT_LEN_MASK_8(__bitlen) \ 2792 ) 2793 2794 /* Description: 2795 * Mask subfield (continuous bits in little-endian) of 4-byte value 2796 * and return the result in 4-byte value in host byte ordering. 2797 */ 2798 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2799 ( \ 2800 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2801 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2802 ) 2803 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2804 ( \ 2805 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2806 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2807 ) 2808 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2809 ( \ 2810 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2811 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2812 ) 2813 2814 /* Description: 2815 * Set subfield of little-endian 4-byte value to specified value. 2816 */ 2817 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2818 *((u32 *)(__pstart)) = \ 2819 ( \ 2820 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2821 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2822 ); 2823 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2824 *((u16 *)(__pstart)) = \ 2825 ( \ 2826 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2827 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2828 ); 2829 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2830 *((u8 *)(__pstart)) = EF1BYTE \ 2831 ( \ 2832 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2833 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2834 ); 2835 2836 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2837 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2838 2839 /**************************************** 2840 mem access macro define end 2841 ****************************************/ 2842 2843 #define byte(x, n) ((x >> (8 * n)) & 0xff) 2844 2845 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 2846 #define RTL_WATCH_DOG_TIME 2000 2847 #define MSECS(t) msecs_to_jiffies(t) 2848 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 2849 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 2850 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 2851 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 2852 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 2853 2854 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 2855 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 2856 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 2857 /*NIC halt, re-initialize hw parameters*/ 2858 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 2859 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 2860 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 2861 /*Always enable ASPM and Clock Req in initialization.*/ 2862 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 2863 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 2864 #define RT_PS_LEVEL_ASPM BIT(7) 2865 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 2866 #define RT_RF_LPS_DISALBE_2R BIT(30) 2867 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 2868 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 2869 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 2870 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 2871 (ppsc->cur_ps_level &= (~(_ps_flg))) 2872 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 2873 (ppsc->cur_ps_level |= _ps_flg) 2874 2875 #define container_of_dwork_rtl(x, y, z) \ 2876 container_of(container_of(x, struct delayed_work, work), y, z) 2877 2878 #define FILL_OCTET_STRING(_os, _octet, _len) \ 2879 (_os).octet = (u8 *)(_octet); \ 2880 (_os).length = (_len); 2881 2882 #define CP_MACADDR(des, src) \ 2883 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 2884 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2885 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2886 2887 #define LDPC_HT_ENABLE_RX BIT(0) 2888 #define LDPC_HT_ENABLE_TX BIT(1) 2889 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 2890 #define LDPC_HT_CAP_TX BIT(3) 2891 2892 #define STBC_HT_ENABLE_RX BIT(0) 2893 #define STBC_HT_ENABLE_TX BIT(1) 2894 #define STBC_HT_TEST_TX_ENABLE BIT(2) 2895 #define STBC_HT_CAP_TX BIT(3) 2896 2897 #define LDPC_VHT_ENABLE_RX BIT(0) 2898 #define LDPC_VHT_ENABLE_TX BIT(1) 2899 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 2900 #define LDPC_VHT_CAP_TX BIT(3) 2901 2902 #define STBC_VHT_ENABLE_RX BIT(0) 2903 #define STBC_VHT_ENABLE_TX BIT(1) 2904 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 2905 #define STBC_VHT_CAP_TX BIT(3) 2906 2907 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 2908 { 2909 return rtlpriv->io.read8_sync(rtlpriv, addr); 2910 } 2911 2912 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 2913 { 2914 return rtlpriv->io.read16_sync(rtlpriv, addr); 2915 } 2916 2917 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 2918 { 2919 return rtlpriv->io.read32_sync(rtlpriv, addr); 2920 } 2921 2922 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 2923 { 2924 rtlpriv->io.write8_async(rtlpriv, addr, val8); 2925 2926 if (rtlpriv->cfg->write_readback) 2927 rtlpriv->io.read8_sync(rtlpriv, addr); 2928 } 2929 2930 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 2931 { 2932 rtlpriv->io.write16_async(rtlpriv, addr, val16); 2933 2934 if (rtlpriv->cfg->write_readback) 2935 rtlpriv->io.read16_sync(rtlpriv, addr); 2936 } 2937 2938 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 2939 u32 addr, u32 val32) 2940 { 2941 rtlpriv->io.write32_async(rtlpriv, addr, val32); 2942 2943 if (rtlpriv->cfg->write_readback) 2944 rtlpriv->io.read32_sync(rtlpriv, addr); 2945 } 2946 2947 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 2948 u32 regaddr, u32 bitmask) 2949 { 2950 struct rtl_priv *rtlpriv = hw->priv; 2951 2952 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 2953 } 2954 2955 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 2956 u32 bitmask, u32 data) 2957 { 2958 struct rtl_priv *rtlpriv = hw->priv; 2959 2960 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 2961 } 2962 2963 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 2964 enum radio_path rfpath, u32 regaddr, 2965 u32 bitmask) 2966 { 2967 struct rtl_priv *rtlpriv = hw->priv; 2968 2969 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 2970 } 2971 2972 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 2973 enum radio_path rfpath, u32 regaddr, 2974 u32 bitmask, u32 data) 2975 { 2976 struct rtl_priv *rtlpriv = hw->priv; 2977 2978 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 2979 } 2980 2981 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 2982 { 2983 return (_HAL_STATE_STOP == rtlhal->state); 2984 } 2985 2986 static inline void set_hal_start(struct rtl_hal *rtlhal) 2987 { 2988 rtlhal->state = _HAL_STATE_START; 2989 } 2990 2991 static inline void set_hal_stop(struct rtl_hal *rtlhal) 2992 { 2993 rtlhal->state = _HAL_STATE_STOP; 2994 } 2995 2996 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 2997 { 2998 return rtlphy->rf_type; 2999 } 3000 3001 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3002 { 3003 return (struct ieee80211_hdr *)(skb->data); 3004 } 3005 3006 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3007 { 3008 return rtl_get_hdr(skb)->frame_control; 3009 } 3010 3011 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3012 { 3013 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3014 } 3015 3016 static inline u16 rtl_get_tid(struct sk_buff *skb) 3017 { 3018 return rtl_get_tid_h(rtl_get_hdr(skb)); 3019 } 3020 3021 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3022 struct ieee80211_vif *vif, 3023 const u8 *bssid) 3024 { 3025 return ieee80211_find_sta(vif, bssid); 3026 } 3027 3028 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3029 u8 *mac_addr) 3030 { 3031 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3032 return ieee80211_find_sta(mac->vif, mac_addr); 3033 } 3034 3035 #endif 3036