1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 103 #define TOTAL_CAM_ENTRY 32 104 105 /*slot time for 11g. */ 106 #define RTL_SLOT_TIME_9 9 107 #define RTL_SLOT_TIME_20 20 108 109 /*related to tcp/ip. */ 110 #define SNAP_SIZE 6 111 #define PROTOC_TYPE_SIZE 2 112 113 /*related with 802.11 frame*/ 114 #define MAC80211_3ADDR_LEN 24 115 #define MAC80211_4ADDR_LEN 30 116 117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 118 #define CHANNEL_MAX_NUMBER_2G 14 119 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 120 *"phy_GetChnlGroup8812A" and 121 * "Hal_ReadTxPowerInfo8812A" 122 */ 123 #define CHANNEL_MAX_NUMBER_5G_80M 7 124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 125 #define MAX_PG_GROUP 13 126 #define CHANNEL_GROUP_MAX_2G 3 127 #define CHANNEL_GROUP_IDX_5GL 3 128 #define CHANNEL_GROUP_IDX_5GM 6 129 #define CHANNEL_GROUP_IDX_5GH 9 130 #define CHANNEL_GROUP_MAX_5G 9 131 #define CHANNEL_MAX_NUMBER_2G 14 132 #define AVG_THERMAL_NUM 8 133 #define AVG_THERMAL_NUM_88E 4 134 #define AVG_THERMAL_NUM_8723BE 4 135 #define MAX_TID_COUNT 9 136 137 /* for early mode */ 138 #define FCS_LEN 4 139 #define EM_HDR_LEN 8 140 141 enum rtl8192c_h2c_cmd { 142 H2C_AP_OFFLOAD = 0, 143 H2C_SETPWRMODE = 1, 144 H2C_JOINBSSRPT = 2, 145 H2C_RSVDPAGE = 3, 146 H2C_RSSI_REPORT = 5, 147 H2C_RA_MASK = 6, 148 H2C_MACID_PS_MODE = 7, 149 H2C_P2P_PS_OFFLOAD = 8, 150 H2C_MAC_MODE_SEL = 9, 151 H2C_PWRM = 15, 152 H2C_P2P_PS_CTW_CMD = 24, 153 MAX_H2CCMD 154 }; 155 156 #define MAX_TX_COUNT 4 157 #define MAX_REGULATION_NUM 4 158 #define MAX_RF_PATH_NUM 4 159 #define MAX_RATE_SECTION_NUM 6 160 #define MAX_2_4G_BANDWIDTH_NUM 4 161 #define MAX_5G_BANDWIDTH_NUM 4 162 #define MAX_RF_PATH 4 163 #define MAX_CHNL_GROUP_24G 6 164 #define MAX_CHNL_GROUP_5G 14 165 166 #define TX_PWR_BY_RATE_NUM_BAND 2 167 #define TX_PWR_BY_RATE_NUM_RF 4 168 #define TX_PWR_BY_RATE_NUM_SECTION 12 169 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 170 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 171 172 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 173 174 #define DEL_SW_IDX_SZ 30 175 #define BAND_NUM 3 176 177 /* For now, it's just for 8192ee 178 * but not OK yet, keep it 0 179 */ 180 #define DMA_IS_64BIT 0 181 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 182 183 enum rf_tx_num { 184 RF_1TX = 0, 185 RF_2TX, 186 RF_MAX_TX_NUM, 187 RF_TX_NUM_NONIMPLEMENT, 188 }; 189 190 #define PACKET_NORMAL 0 191 #define PACKET_DHCP 1 192 #define PACKET_ARP 2 193 #define PACKET_EAPOL 3 194 195 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 196 #define RSVD_WOL_PATTERN_NUM 1 197 #define WKFMCAM_ADDR_NUM 6 198 #define WKFMCAM_SIZE 24 199 200 #define MAX_WOL_BIT_MASK_SIZE 16 201 /* MIN LEN keeps 13 here */ 202 #define MIN_WOL_PATTERN_SIZE 13 203 #define MAX_WOL_PATTERN_SIZE 128 204 205 #define WAKE_ON_MAGIC_PACKET BIT(0) 206 #define WAKE_ON_PATTERN_MATCH BIT(1) 207 208 #define WOL_REASON_PTK_UPDATE BIT(0) 209 #define WOL_REASON_GTK_UPDATE BIT(1) 210 #define WOL_REASON_DISASSOC BIT(2) 211 #define WOL_REASON_DEAUTH BIT(3) 212 #define WOL_REASON_AP_LOST BIT(4) 213 #define WOL_REASON_MAGIC_PKT BIT(5) 214 #define WOL_REASON_UNICAST_PKT BIT(6) 215 #define WOL_REASON_PATTERN_PKT BIT(7) 216 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 217 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 218 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 219 220 struct rtlwifi_firmware_header { 221 __le16 signature; 222 u8 category; 223 u8 function; 224 __le16 version; 225 u8 subversion; 226 u8 rsvd1; 227 u8 month; 228 u8 date; 229 u8 hour; 230 u8 minute; 231 __le16 ramcodeSize; 232 __le16 rsvd2; 233 __le32 svnindex; 234 __le32 rsvd3; 235 __le32 rsvd4; 236 __le32 rsvd5; 237 }; 238 239 struct txpower_info_2g { 240 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 241 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 242 /*If only one tx, only BW20 and OFDM are used.*/ 243 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 245 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 246 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 247 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 248 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 249 }; 250 251 struct txpower_info_5g { 252 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 253 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 254 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 255 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 256 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 257 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 258 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 259 }; 260 261 enum rate_section { 262 CCK = 0, 263 OFDM, 264 HT_MCS0_MCS7, 265 HT_MCS8_MCS15, 266 VHT_1SSMCS0_1SSMCS9, 267 VHT_2SSMCS0_2SSMCS9, 268 }; 269 270 enum intf_type { 271 INTF_PCI = 0, 272 INTF_USB = 1, 273 }; 274 275 enum radio_path { 276 RF90_PATH_A = 0, 277 RF90_PATH_B = 1, 278 RF90_PATH_C = 2, 279 RF90_PATH_D = 3, 280 }; 281 282 enum regulation_txpwr_lmt { 283 TXPWR_LMT_FCC = 0, 284 TXPWR_LMT_MKK = 1, 285 TXPWR_LMT_ETSI = 2, 286 TXPWR_LMT_WW = 3, 287 288 TXPWR_LMT_MAX_REGULATION_NUM = 4 289 }; 290 291 enum rt_eeprom_type { 292 EEPROM_93C46, 293 EEPROM_93C56, 294 EEPROM_BOOT_EFUSE, 295 }; 296 297 enum ttl_status { 298 RTL_STATUS_INTERFACE_START = 0, 299 }; 300 301 enum hardware_type { 302 HARDWARE_TYPE_RTL8192E, 303 HARDWARE_TYPE_RTL8192U, 304 HARDWARE_TYPE_RTL8192SE, 305 HARDWARE_TYPE_RTL8192SU, 306 HARDWARE_TYPE_RTL8192CE, 307 HARDWARE_TYPE_RTL8192CU, 308 HARDWARE_TYPE_RTL8192DE, 309 HARDWARE_TYPE_RTL8192DU, 310 HARDWARE_TYPE_RTL8723AE, 311 HARDWARE_TYPE_RTL8723U, 312 HARDWARE_TYPE_RTL8188EE, 313 HARDWARE_TYPE_RTL8723BE, 314 HARDWARE_TYPE_RTL8192EE, 315 HARDWARE_TYPE_RTL8821AE, 316 HARDWARE_TYPE_RTL8812AE, 317 HARDWARE_TYPE_RTL8822BE, 318 319 /* keep it last */ 320 HARDWARE_TYPE_NUM 321 }; 322 323 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type) 324 #define IS_NEW_GENERATION_IC(rtlpriv) \ 325 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE) 326 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \ 327 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE) 328 #define IS_HARDWARE_TYPE_8812(rtlpriv) \ 329 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE) 330 #define IS_HARDWARE_TYPE_8821(rtlpriv) \ 331 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE) 332 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \ 333 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE) 334 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \ 335 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE) 336 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \ 337 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE) 338 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \ 339 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE) 340 341 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 342 ((rxmcs) == DESC_RATE1M || \ 343 (rxmcs) == DESC_RATE2M || \ 344 (rxmcs) == DESC_RATE5_5M || \ 345 (rxmcs) == DESC_RATE11M) 346 347 enum scan_operation_backup_opt { 348 SCAN_OPT_BACKUP = 0, 349 SCAN_OPT_BACKUP_BAND0 = 0, 350 SCAN_OPT_BACKUP_BAND1, 351 SCAN_OPT_RESTORE, 352 SCAN_OPT_MAX 353 }; 354 355 /*RF state.*/ 356 enum rf_pwrstate { 357 ERFON, 358 ERFSLEEP, 359 ERFOFF 360 }; 361 362 struct bb_reg_def { 363 u32 rfintfs; 364 u32 rfintfi; 365 u32 rfintfo; 366 u32 rfintfe; 367 u32 rf3wire_offset; 368 u32 rflssi_select; 369 u32 rftxgain_stage; 370 u32 rfhssi_para1; 371 u32 rfhssi_para2; 372 u32 rfsw_ctrl; 373 u32 rfagc_control1; 374 u32 rfagc_control2; 375 u32 rfrxiq_imbal; 376 u32 rfrx_afe; 377 u32 rftxiq_imbal; 378 u32 rftx_afe; 379 u32 rf_rb; /* rflssi_readback */ 380 u32 rf_rbpi; /* rflssi_readbackpi */ 381 }; 382 383 enum io_type { 384 IO_CMD_PAUSE_DM_BY_SCAN = 0, 385 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 386 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 387 IO_CMD_RESUME_DM_BY_SCAN = 2, 388 }; 389 390 enum hw_variables { 391 HW_VAR_ETHER_ADDR = 0x0, 392 HW_VAR_MULTICAST_REG = 0x1, 393 HW_VAR_BASIC_RATE = 0x2, 394 HW_VAR_BSSID = 0x3, 395 HW_VAR_MEDIA_STATUS= 0x4, 396 HW_VAR_SECURITY_CONF= 0x5, 397 HW_VAR_BEACON_INTERVAL = 0x6, 398 HW_VAR_ATIM_WINDOW = 0x7, 399 HW_VAR_LISTEN_INTERVAL = 0x8, 400 HW_VAR_CS_COUNTER = 0x9, 401 HW_VAR_DEFAULTKEY0 = 0xa, 402 HW_VAR_DEFAULTKEY1 = 0xb, 403 HW_VAR_DEFAULTKEY2 = 0xc, 404 HW_VAR_DEFAULTKEY3 = 0xd, 405 HW_VAR_SIFS = 0xe, 406 HW_VAR_R2T_SIFS = 0xf, 407 HW_VAR_DIFS = 0x10, 408 HW_VAR_EIFS = 0x11, 409 HW_VAR_SLOT_TIME = 0x12, 410 HW_VAR_ACK_PREAMBLE = 0x13, 411 HW_VAR_CW_CONFIG = 0x14, 412 HW_VAR_CW_VALUES = 0x15, 413 HW_VAR_RATE_FALLBACK_CONTROL= 0x16, 414 HW_VAR_CONTENTION_WINDOW = 0x17, 415 HW_VAR_RETRY_COUNT = 0x18, 416 HW_VAR_TR_SWITCH = 0x19, 417 HW_VAR_COMMAND = 0x1a, 418 HW_VAR_WPA_CONFIG = 0x1b, 419 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 420 HW_VAR_SHORTGI_DENSITY = 0x1d, 421 HW_VAR_AMPDU_FACTOR = 0x1e, 422 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 423 HW_VAR_AC_PARAM = 0x20, 424 HW_VAR_ACM_CTRL = 0x21, 425 HW_VAR_DIS_Req_Qsize = 0x22, 426 HW_VAR_CCX_CHNL_LOAD = 0x23, 427 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 428 HW_VAR_CCX_CLM_NHM = 0x25, 429 HW_VAR_TxOPLimit = 0x26, 430 HW_VAR_TURBO_MODE = 0x27, 431 HW_VAR_RF_STATE = 0x28, 432 HW_VAR_RF_OFF_BY_HW = 0x29, 433 HW_VAR_BUS_SPEED = 0x2a, 434 HW_VAR_SET_DEV_POWER = 0x2b, 435 436 HW_VAR_RCR = 0x2c, 437 HW_VAR_RATR_0 = 0x2d, 438 HW_VAR_RRSR = 0x2e, 439 HW_VAR_CPU_RST = 0x2f, 440 HW_VAR_CHECK_BSSID = 0x30, 441 HW_VAR_LBK_MODE = 0x31, 442 HW_VAR_AES_11N_FIX = 0x32, 443 HW_VAR_USB_RX_AGGR = 0x33, 444 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 445 HW_VAR_RETRY_LIMIT = 0x35, 446 HW_VAR_INIT_TX_RATE = 0x36, 447 HW_VAR_TX_RATE_REG = 0x37, 448 HW_VAR_EFUSE_USAGE = 0x38, 449 HW_VAR_EFUSE_BYTES = 0x39, 450 HW_VAR_AUTOLOAD_STATUS = 0x3a, 451 HW_VAR_RF_2R_DISABLE = 0x3b, 452 HW_VAR_SET_RPWM = 0x3c, 453 HW_VAR_H2C_FW_PWRMODE = 0x3d, 454 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 455 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 456 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 457 HW_VAR_FW_PSMODE_STATUS = 0x41, 458 HW_VAR_INIT_RTS_RATE = 0x42, 459 HW_VAR_RESUME_CLK_ON = 0x43, 460 HW_VAR_FW_LPS_ACTION = 0x44, 461 HW_VAR_1X1_RECV_COMBINE = 0x45, 462 HW_VAR_STOP_SEND_BEACON = 0x46, 463 HW_VAR_TSF_TIMER = 0x47, 464 HW_VAR_IO_CMD = 0x48, 465 466 HW_VAR_RF_RECOVERY = 0x49, 467 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 468 HW_VAR_WF_MASK = 0x4b, 469 HW_VAR_WF_CRC = 0x4c, 470 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 471 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 472 HW_VAR_RESET_WFCRC = 0x4f, 473 474 HW_VAR_HANDLE_FW_C2H = 0x50, 475 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 476 HW_VAR_AID = 0x52, 477 HW_VAR_HW_SEQ_ENABLE = 0x53, 478 HW_VAR_CORRECT_TSF = 0x54, 479 HW_VAR_BCN_VALID = 0x55, 480 HW_VAR_FWLPS_RF_ON = 0x56, 481 HW_VAR_DUAL_TSF_RST = 0x57, 482 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58, 483 HW_VAR_INT_MIGRATION = 0x59, 484 HW_VAR_INT_AC = 0x5a, 485 HW_VAR_RF_TIMING = 0x5b, 486 487 HAL_DEF_WOWLAN = 0x5c, 488 HW_VAR_MRC = 0x5d, 489 HW_VAR_KEEP_ALIVE = 0x5e, 490 HW_VAR_NAV_UPPER = 0x5f, 491 492 HW_VAR_MGT_FILTER = 0x60, 493 HW_VAR_CTRL_FILTER = 0x61, 494 HW_VAR_DATA_FILTER = 0x62, 495 }; 496 497 enum rt_media_status { 498 RT_MEDIA_DISCONNECT = 0, 499 RT_MEDIA_CONNECT = 1 500 }; 501 502 enum rt_oem_id { 503 RT_CID_DEFAULT = 0, 504 RT_CID_8187_ALPHA0 = 1, 505 RT_CID_8187_SERCOMM_PS = 2, 506 RT_CID_8187_HW_LED = 3, 507 RT_CID_8187_NETGEAR = 4, 508 RT_CID_WHQL = 5, 509 RT_CID_819X_CAMEO = 6, 510 RT_CID_819X_RUNTOP = 7, 511 RT_CID_819X_SENAO = 8, 512 RT_CID_TOSHIBA = 9, 513 RT_CID_819X_NETCORE = 10, 514 RT_CID_NETTRONIX = 11, 515 RT_CID_DLINK = 12, 516 RT_CID_PRONET = 13, 517 RT_CID_COREGA = 14, 518 RT_CID_819X_ALPHA = 15, 519 RT_CID_819X_SITECOM = 16, 520 RT_CID_CCX = 17, 521 RT_CID_819X_LENOVO = 18, 522 RT_CID_819X_QMI = 19, 523 RT_CID_819X_EDIMAX_BELKIN = 20, 524 RT_CID_819X_SERCOMM_BELKIN = 21, 525 RT_CID_819X_CAMEO1 = 22, 526 RT_CID_819X_MSI = 23, 527 RT_CID_819X_ACER = 24, 528 RT_CID_819X_HP = 27, 529 RT_CID_819X_CLEVO = 28, 530 RT_CID_819X_ARCADYAN_BELKIN = 29, 531 RT_CID_819X_SAMSUNG = 30, 532 RT_CID_819X_WNC_COREGA = 31, 533 RT_CID_819X_FOXCOON = 32, 534 RT_CID_819X_DELL = 33, 535 RT_CID_819X_PRONETS = 34, 536 RT_CID_819X_EDIMAX_ASUS = 35, 537 RT_CID_NETGEAR = 36, 538 RT_CID_PLANEX = 37, 539 RT_CID_CC_C = 38, 540 }; 541 542 enum hw_descs { 543 HW_DESC_OWN, 544 HW_DESC_RXOWN, 545 HW_DESC_TX_NEXTDESC_ADDR, 546 HW_DESC_TXBUFF_ADDR, 547 HW_DESC_RXBUFF_ADDR, 548 HW_DESC_RXPKT_LEN, 549 HW_DESC_RXERO, 550 HW_DESC_RX_PREPARE, 551 }; 552 553 enum prime_sc { 554 PRIME_CHNL_OFFSET_DONT_CARE = 0, 555 PRIME_CHNL_OFFSET_LOWER = 1, 556 PRIME_CHNL_OFFSET_UPPER = 2, 557 }; 558 559 enum rf_type { 560 RF_1T1R = 0, 561 RF_1T2R = 1, 562 RF_2T2R = 2, 563 RF_2T2R_GREEN = 3, 564 }; 565 566 enum ht_channel_width { 567 HT_CHANNEL_WIDTH_20 = 0, 568 HT_CHANNEL_WIDTH_20_40 = 1, 569 HT_CHANNEL_WIDTH_80 = 2, 570 }; 571 572 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 573 Cipher Suites Encryption Algorithms */ 574 enum rt_enc_alg { 575 NO_ENCRYPTION = 0, 576 WEP40_ENCRYPTION = 1, 577 TKIP_ENCRYPTION = 2, 578 RSERVED_ENCRYPTION = 3, 579 AESCCMP_ENCRYPTION = 4, 580 WEP104_ENCRYPTION = 5, 581 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 582 }; 583 584 enum rtl_hal_state { 585 _HAL_STATE_STOP = 0, 586 _HAL_STATE_START = 1, 587 }; 588 589 enum rtl_desc_rate { 590 DESC_RATE1M = 0x00, 591 DESC_RATE2M = 0x01, 592 DESC_RATE5_5M = 0x02, 593 DESC_RATE11M = 0x03, 594 595 DESC_RATE6M = 0x04, 596 DESC_RATE9M = 0x05, 597 DESC_RATE12M = 0x06, 598 DESC_RATE18M = 0x07, 599 DESC_RATE24M = 0x08, 600 DESC_RATE36M = 0x09, 601 DESC_RATE48M = 0x0a, 602 DESC_RATE54M = 0x0b, 603 604 DESC_RATEMCS0 = 0x0c, 605 DESC_RATEMCS1 = 0x0d, 606 DESC_RATEMCS2 = 0x0e, 607 DESC_RATEMCS3 = 0x0f, 608 DESC_RATEMCS4 = 0x10, 609 DESC_RATEMCS5 = 0x11, 610 DESC_RATEMCS6 = 0x12, 611 DESC_RATEMCS7 = 0x13, 612 DESC_RATEMCS8 = 0x14, 613 DESC_RATEMCS9 = 0x15, 614 DESC_RATEMCS10 = 0x16, 615 DESC_RATEMCS11 = 0x17, 616 DESC_RATEMCS12 = 0x18, 617 DESC_RATEMCS13 = 0x19, 618 DESC_RATEMCS14 = 0x1a, 619 DESC_RATEMCS15 = 0x1b, 620 DESC_RATEMCS15_SG = 0x1c, 621 DESC_RATEMCS32 = 0x20, 622 623 DESC_RATEVHT1SS_MCS0 = 0x2c, 624 DESC_RATEVHT1SS_MCS1 = 0x2d, 625 DESC_RATEVHT1SS_MCS2 = 0x2e, 626 DESC_RATEVHT1SS_MCS3 = 0x2f, 627 DESC_RATEVHT1SS_MCS4 = 0x30, 628 DESC_RATEVHT1SS_MCS5 = 0x31, 629 DESC_RATEVHT1SS_MCS6 = 0x32, 630 DESC_RATEVHT1SS_MCS7 = 0x33, 631 DESC_RATEVHT1SS_MCS8 = 0x34, 632 DESC_RATEVHT1SS_MCS9 = 0x35, 633 DESC_RATEVHT2SS_MCS0 = 0x36, 634 DESC_RATEVHT2SS_MCS1 = 0x37, 635 DESC_RATEVHT2SS_MCS2 = 0x38, 636 DESC_RATEVHT2SS_MCS3 = 0x39, 637 DESC_RATEVHT2SS_MCS4 = 0x3a, 638 DESC_RATEVHT2SS_MCS5 = 0x3b, 639 DESC_RATEVHT2SS_MCS6 = 0x3c, 640 DESC_RATEVHT2SS_MCS7 = 0x3d, 641 DESC_RATEVHT2SS_MCS8 = 0x3e, 642 DESC_RATEVHT2SS_MCS9 = 0x3f, 643 }; 644 645 enum rtl_var_map { 646 /*reg map */ 647 SYS_ISO_CTRL = 0, 648 SYS_FUNC_EN, 649 SYS_CLK, 650 MAC_RCR_AM, 651 MAC_RCR_AB, 652 MAC_RCR_ACRC32, 653 MAC_RCR_ACF, 654 MAC_RCR_AAP, 655 MAC_HIMR, 656 MAC_HIMRE, 657 MAC_HSISR, 658 659 /*efuse map */ 660 EFUSE_TEST, 661 EFUSE_CTRL, 662 EFUSE_CLK, 663 EFUSE_CLK_CTRL, 664 EFUSE_PWC_EV12V, 665 EFUSE_FEN_ELDR, 666 EFUSE_LOADER_CLK_EN, 667 EFUSE_ANA8M, 668 EFUSE_HWSET_MAX_SIZE, 669 EFUSE_MAX_SECTION_MAP, 670 EFUSE_REAL_CONTENT_SIZE, 671 EFUSE_OOB_PROTECT_BYTES_LEN, 672 EFUSE_ACCESS, 673 674 /*CAM map */ 675 RWCAM, 676 WCAMI, 677 RCAMO, 678 CAMDBG, 679 SECR, 680 SEC_CAM_NONE, 681 SEC_CAM_WEP40, 682 SEC_CAM_TKIP, 683 SEC_CAM_AES, 684 SEC_CAM_WEP104, 685 686 /*IMR map */ 687 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 688 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 689 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 690 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 691 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 692 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 693 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 694 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 695 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 696 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 697 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 698 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 699 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 700 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 701 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 702 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 703 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 704 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 705 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 706 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 707 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 708 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 709 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 710 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 711 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 712 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 713 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 714 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 715 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 716 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 717 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 718 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 719 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 720 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 721 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 722 * RTL_IMR_TBDER) */ 723 RTL_IMR_C2HCMD, /*fw interrupt*/ 724 725 /*CCK Rates, TxHT = 0 */ 726 RTL_RC_CCK_RATE1M, 727 RTL_RC_CCK_RATE2M, 728 RTL_RC_CCK_RATE5_5M, 729 RTL_RC_CCK_RATE11M, 730 731 /*OFDM Rates, TxHT = 0 */ 732 RTL_RC_OFDM_RATE6M, 733 RTL_RC_OFDM_RATE9M, 734 RTL_RC_OFDM_RATE12M, 735 RTL_RC_OFDM_RATE18M, 736 RTL_RC_OFDM_RATE24M, 737 RTL_RC_OFDM_RATE36M, 738 RTL_RC_OFDM_RATE48M, 739 RTL_RC_OFDM_RATE54M, 740 741 RTL_RC_HT_RATEMCS7, 742 RTL_RC_HT_RATEMCS15, 743 744 RTL_RC_VHT_RATE_1SS_MCS7, 745 RTL_RC_VHT_RATE_1SS_MCS8, 746 RTL_RC_VHT_RATE_1SS_MCS9, 747 RTL_RC_VHT_RATE_2SS_MCS7, 748 RTL_RC_VHT_RATE_2SS_MCS8, 749 RTL_RC_VHT_RATE_2SS_MCS9, 750 751 /*keep it last */ 752 RTL_VAR_MAP_MAX, 753 }; 754 755 /*Firmware PS mode for control LPS.*/ 756 enum _fw_ps_mode { 757 FW_PS_ACTIVE_MODE = 0, 758 FW_PS_MIN_MODE = 1, 759 FW_PS_MAX_MODE = 2, 760 FW_PS_DTIM_MODE = 3, 761 FW_PS_VOIP_MODE = 4, 762 FW_PS_UAPSD_WMM_MODE = 5, 763 FW_PS_UAPSD_MODE = 6, 764 FW_PS_IBSS_MODE = 7, 765 FW_PS_WWLAN_MODE = 8, 766 FW_PS_PM_Radio_Off = 9, 767 FW_PS_PM_Card_Disable = 10, 768 }; 769 770 enum rt_psmode { 771 EACTIVE, /*Active/Continuous access. */ 772 EMAXPS, /*Max power save mode. */ 773 EFASTPS, /*Fast power save mode. */ 774 EAUTOPS, /*Auto power save mode. */ 775 }; 776 777 /*LED related.*/ 778 enum led_ctl_mode { 779 LED_CTL_POWER_ON = 1, 780 LED_CTL_LINK = 2, 781 LED_CTL_NO_LINK = 3, 782 LED_CTL_TX = 4, 783 LED_CTL_RX = 5, 784 LED_CTL_SITE_SURVEY = 6, 785 LED_CTL_POWER_OFF = 7, 786 LED_CTL_START_TO_LINK = 8, 787 LED_CTL_START_WPS = 9, 788 LED_CTL_STOP_WPS = 10, 789 }; 790 791 enum rtl_led_pin { 792 LED_PIN_GPIO0, 793 LED_PIN_LED0, 794 LED_PIN_LED1, 795 LED_PIN_LED2 796 }; 797 798 /*QoS related.*/ 799 /*acm implementation method.*/ 800 enum acm_method { 801 eAcmWay0_SwAndHw = 0, 802 eAcmWay1_HW = 1, 803 EACMWAY2_SW = 2, 804 }; 805 806 enum macphy_mode { 807 SINGLEMAC_SINGLEPHY = 0, 808 DUALMAC_DUALPHY, 809 DUALMAC_SINGLEPHY, 810 }; 811 812 enum band_type { 813 BAND_ON_2_4G = 0, 814 BAND_ON_5G, 815 BAND_ON_BOTH, 816 BANDMAX 817 }; 818 819 /*aci/aifsn Field. 820 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 821 union aci_aifsn { 822 u8 char_data; 823 824 struct { 825 u8 aifsn:4; 826 u8 acm:1; 827 u8 aci:2; 828 u8 reserved:1; 829 } f; /* Field */ 830 }; 831 832 /*mlme related.*/ 833 enum wireless_mode { 834 WIRELESS_MODE_UNKNOWN = 0x00, 835 WIRELESS_MODE_A = 0x01, 836 WIRELESS_MODE_B = 0x02, 837 WIRELESS_MODE_G = 0x04, 838 WIRELESS_MODE_AUTO = 0x08, 839 WIRELESS_MODE_N_24G = 0x10, 840 WIRELESS_MODE_N_5G = 0x20, 841 WIRELESS_MODE_AC_5G = 0x40, 842 WIRELESS_MODE_AC_24G = 0x80, 843 WIRELESS_MODE_AC_ONLY = 0x100, 844 WIRELESS_MODE_MAX = 0x800 845 }; 846 847 #define IS_WIRELESS_MODE_A(wirelessmode) \ 848 (wirelessmode == WIRELESS_MODE_A) 849 #define IS_WIRELESS_MODE_B(wirelessmode) \ 850 (wirelessmode == WIRELESS_MODE_B) 851 #define IS_WIRELESS_MODE_G(wirelessmode) \ 852 (wirelessmode == WIRELESS_MODE_G) 853 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 854 (wirelessmode == WIRELESS_MODE_N_24G) 855 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 856 (wirelessmode == WIRELESS_MODE_N_5G) 857 858 enum ratr_table_mode { 859 RATR_INX_WIRELESS_NGB = 0, 860 RATR_INX_WIRELESS_NG = 1, 861 RATR_INX_WIRELESS_NB = 2, 862 RATR_INX_WIRELESS_N = 3, 863 RATR_INX_WIRELESS_GB = 4, 864 RATR_INX_WIRELESS_G = 5, 865 RATR_INX_WIRELESS_B = 6, 866 RATR_INX_WIRELESS_MC = 7, 867 RATR_INX_WIRELESS_A = 8, 868 RATR_INX_WIRELESS_AC_5N = 8, 869 RATR_INX_WIRELESS_AC_24N = 9, 870 }; 871 872 enum rtl_link_state { 873 MAC80211_NOLINK = 0, 874 MAC80211_LINKING = 1, 875 MAC80211_LINKED = 2, 876 MAC80211_LINKED_SCANNING = 3, 877 }; 878 879 enum act_category { 880 ACT_CAT_QOS = 1, 881 ACT_CAT_DLS = 2, 882 ACT_CAT_BA = 3, 883 ACT_CAT_HT = 7, 884 ACT_CAT_WMM = 17, 885 }; 886 887 enum ba_action { 888 ACT_ADDBAREQ = 0, 889 ACT_ADDBARSP = 1, 890 ACT_DELBA = 2, 891 }; 892 893 enum rt_polarity_ctl { 894 RT_POLARITY_LOW_ACT = 0, 895 RT_POLARITY_HIGH_ACT = 1, 896 }; 897 898 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 899 enum fw_wow_reason_v2 { 900 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 901 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 902 FW_WOW_V2_DISASSOC_EVENT = 0x04, 903 FW_WOW_V2_DEAUTH_EVENT = 0x08, 904 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 905 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 906 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 907 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 908 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 909 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 910 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 911 FW_WOW_V2_REASON_MAX = 0xff, 912 }; 913 914 enum wolpattern_type { 915 UNICAST_PATTERN = 0, 916 MULTICAST_PATTERN = 1, 917 BROADCAST_PATTERN = 2, 918 DONT_CARE_DA = 3, 919 UNKNOWN_TYPE = 4, 920 }; 921 922 enum package_type { 923 PACKAGE_DEFAULT, 924 PACKAGE_QFN68, 925 PACKAGE_TFBGA90, 926 PACKAGE_TFBGA80, 927 PACKAGE_TFBGA79 928 }; 929 930 struct octet_string { 931 u8 *octet; 932 u16 length; 933 }; 934 935 struct rtl_hdr_3addr { 936 __le16 frame_ctl; 937 __le16 duration_id; 938 u8 addr1[ETH_ALEN]; 939 u8 addr2[ETH_ALEN]; 940 u8 addr3[ETH_ALEN]; 941 __le16 seq_ctl; 942 u8 payload[0]; 943 } __packed; 944 945 struct rtl_info_element { 946 u8 id; 947 u8 len; 948 u8 data[0]; 949 } __packed; 950 951 struct rtl_probe_rsp { 952 struct rtl_hdr_3addr header; 953 u32 time_stamp[2]; 954 __le16 beacon_interval; 955 __le16 capability; 956 /*SSID, supported rates, FH params, DS params, 957 CF params, IBSS params, TIM (if beacon), RSN */ 958 struct rtl_info_element info_element[0]; 959 } __packed; 960 961 /*LED related.*/ 962 /*ledpin Identify how to implement this SW led.*/ 963 struct rtl_led { 964 void *hw; 965 enum rtl_led_pin ledpin; 966 bool ledon; 967 }; 968 969 struct rtl_led_ctl { 970 bool led_opendrain; 971 struct rtl_led sw_led0; 972 struct rtl_led sw_led1; 973 }; 974 975 struct rtl_qos_parameters { 976 __le16 cw_min; 977 __le16 cw_max; 978 u8 aifs; 979 u8 flag; 980 __le16 tx_op; 981 } __packed; 982 983 struct rt_smooth_data { 984 u32 elements[100]; /*array to store values */ 985 u32 index; /*index to current array to store */ 986 u32 total_num; /*num of valid elements */ 987 u32 total_val; /*sum of valid elements */ 988 }; 989 990 struct false_alarm_statistics { 991 u32 cnt_parity_fail; 992 u32 cnt_rate_illegal; 993 u32 cnt_crc8_fail; 994 u32 cnt_mcs_fail; 995 u32 cnt_fast_fsync_fail; 996 u32 cnt_sb_search_fail; 997 u32 cnt_ofdm_fail; 998 u32 cnt_cck_fail; 999 u32 cnt_all; 1000 u32 cnt_ofdm_cca; 1001 u32 cnt_cck_cca; 1002 u32 cnt_cca_all; 1003 u32 cnt_bw_usc; 1004 u32 cnt_bw_lsc; 1005 }; 1006 1007 struct init_gain { 1008 u8 xaagccore1; 1009 u8 xbagccore1; 1010 u8 xcagccore1; 1011 u8 xdagccore1; 1012 u8 cca; 1013 1014 }; 1015 1016 struct wireless_stats { 1017 unsigned long txbytesunicast; 1018 unsigned long txbytesmulticast; 1019 unsigned long txbytesbroadcast; 1020 unsigned long rxbytesunicast; 1021 1022 long rx_snr_db[4]; 1023 /*Correct smoothed ss in Dbm, only used 1024 in driver to report real power now. */ 1025 long recv_signal_power; 1026 long signal_quality; 1027 long last_sigstrength_inpercent; 1028 1029 u32 rssi_calculate_cnt; 1030 u32 pwdb_all_cnt; 1031 1032 /*Transformed, in dbm. Beautified signal 1033 strength for UI, not correct. */ 1034 long signal_strength; 1035 1036 u8 rx_rssi_percentage[4]; 1037 u8 rx_evm_dbm[4]; 1038 u8 rx_evm_percentage[2]; 1039 1040 u16 rx_cfo_short[4]; 1041 u16 rx_cfo_tail[4]; 1042 1043 struct rt_smooth_data ui_rssi; 1044 struct rt_smooth_data ui_link_quality; 1045 }; 1046 1047 struct rate_adaptive { 1048 u8 rate_adaptive_disabled; 1049 u8 ratr_state; 1050 u16 reserve; 1051 1052 u32 high_rssi_thresh_for_ra; 1053 u32 high2low_rssi_thresh_for_ra; 1054 u8 low2high_rssi_thresh_for_ra40m; 1055 u32 low_rssi_thresh_for_ra40m; 1056 u8 low2high_rssi_thresh_for_ra20m; 1057 u32 low_rssi_thresh_for_ra20m; 1058 u32 upper_rssi_threshold_ratr; 1059 u32 middleupper_rssi_threshold_ratr; 1060 u32 middle_rssi_threshold_ratr; 1061 u32 middlelow_rssi_threshold_ratr; 1062 u32 low_rssi_threshold_ratr; 1063 u32 ultralow_rssi_threshold_ratr; 1064 u32 low_rssi_threshold_ratr_40m; 1065 u32 low_rssi_threshold_ratr_20m; 1066 u8 ping_rssi_enable; 1067 u32 ping_rssi_ratr; 1068 u32 ping_rssi_thresh_for_ra; 1069 u32 last_ratr; 1070 u8 pre_ratr_state; 1071 u8 ldpc_thres; 1072 bool use_ldpc; 1073 bool lower_rts_rate; 1074 bool is_special_data; 1075 }; 1076 1077 struct regd_pair_mapping { 1078 u16 reg_dmnenum; 1079 u16 reg_5ghz_ctl; 1080 u16 reg_2ghz_ctl; 1081 }; 1082 1083 struct dynamic_primary_cca { 1084 u8 pricca_flag; 1085 u8 intf_flag; 1086 u8 intf_type; 1087 u8 dup_rts_flag; 1088 u8 monitor_flag; 1089 u8 ch_offset; 1090 u8 mf_state; 1091 }; 1092 1093 struct rtl_regulatory { 1094 s8 alpha2[2]; 1095 u16 country_code; 1096 u16 max_power_level; 1097 u32 tp_scale; 1098 u16 current_rd; 1099 u16 current_rd_ext; 1100 int16_t power_limit; 1101 struct regd_pair_mapping *regpair; 1102 }; 1103 1104 struct rtl_rfkill { 1105 bool rfkill_state; /*0 is off, 1 is on */ 1106 }; 1107 1108 /*for P2P PS**/ 1109 #define P2P_MAX_NOA_NUM 2 1110 1111 enum p2p_role { 1112 P2P_ROLE_DISABLE = 0, 1113 P2P_ROLE_DEVICE = 1, 1114 P2P_ROLE_CLIENT = 2, 1115 P2P_ROLE_GO = 3 1116 }; 1117 1118 enum p2p_ps_state { 1119 P2P_PS_DISABLE = 0, 1120 P2P_PS_ENABLE = 1, 1121 P2P_PS_SCAN = 2, 1122 P2P_PS_SCAN_DONE = 3, 1123 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1124 }; 1125 1126 enum p2p_ps_mode { 1127 P2P_PS_NONE = 0, 1128 P2P_PS_CTWINDOW = 1, 1129 P2P_PS_NOA = 2, 1130 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1131 }; 1132 1133 struct rtl_p2p_ps_info { 1134 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1135 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1136 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1137 /* Client traffic window. A period of time in TU after TBTT. */ 1138 u8 ctwindow; 1139 u8 opp_ps; /* opportunistic power save. */ 1140 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1141 /* Count for owner, Type of client. */ 1142 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1143 /* Max duration for owner, preferred or min acceptable duration 1144 * for client. 1145 */ 1146 u32 noa_duration[P2P_MAX_NOA_NUM]; 1147 /* Length of interval for owner, preferred or max acceptable intervali 1148 * of client. 1149 */ 1150 u32 noa_interval[P2P_MAX_NOA_NUM]; 1151 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1152 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1153 }; 1154 1155 struct p2p_ps_offload_t { 1156 u8 offload_en:1; 1157 u8 role:1; /* 1: Owner, 0: Client */ 1158 u8 ctwindow_en:1; 1159 u8 noa0_en:1; 1160 u8 noa1_en:1; 1161 u8 allstasleep:1; 1162 u8 discovery:1; 1163 u8 reserved:1; 1164 }; 1165 1166 #define IQK_MATRIX_REG_NUM 8 1167 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1168 1169 struct iqk_matrix_regs { 1170 bool iqk_done; 1171 long value[1][IQK_MATRIX_REG_NUM]; 1172 }; 1173 1174 struct phy_parameters { 1175 u16 length; 1176 u32 *pdata; 1177 }; 1178 1179 enum hw_param_tab_index { 1180 PHY_REG_2T, 1181 PHY_REG_1T, 1182 PHY_REG_PG, 1183 RADIOA_2T, 1184 RADIOB_2T, 1185 RADIOA_1T, 1186 RADIOB_1T, 1187 MAC_REG, 1188 AGCTAB_2T, 1189 AGCTAB_1T, 1190 MAX_TAB 1191 }; 1192 1193 struct rtl_phy { 1194 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1195 struct init_gain initgain_backup; 1196 enum io_type current_io_type; 1197 1198 u8 rf_mode; 1199 u8 rf_type; 1200 u8 current_chan_bw; 1201 u8 set_bwmode_inprogress; 1202 u8 sw_chnl_inprogress; 1203 u8 sw_chnl_stage; 1204 u8 sw_chnl_step; 1205 u8 current_channel; 1206 u8 h2c_box_num; 1207 u8 set_io_inprogress; 1208 u8 lck_inprogress; 1209 1210 /* record for power tracking */ 1211 s32 reg_e94; 1212 s32 reg_e9c; 1213 s32 reg_ea4; 1214 s32 reg_eac; 1215 s32 reg_eb4; 1216 s32 reg_ebc; 1217 s32 reg_ec4; 1218 s32 reg_ecc; 1219 u8 rfpienable; 1220 u8 reserve_0; 1221 u16 reserve_1; 1222 u32 reg_c04, reg_c08, reg_874; 1223 u32 adda_backup[16]; 1224 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1225 u32 iqk_bb_backup[10]; 1226 bool iqk_initialized; 1227 1228 bool rfpath_rx_enable[MAX_RF_PATH]; 1229 u8 reg_837; 1230 /* Dual mac */ 1231 bool need_iqk; 1232 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1233 1234 bool rfpi_enable; 1235 bool iqk_in_progress; 1236 1237 u8 pwrgroup_cnt; 1238 u8 cck_high_power; 1239 /* this is for 88E & 8723A */ 1240 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1241 /* MAX_PG_GROUP groups of pwr diff by rates */ 1242 u32 mcs_offset[MAX_PG_GROUP][16]; 1243 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1244 [TX_PWR_BY_RATE_NUM_RF] 1245 [TX_PWR_BY_RATE_NUM_RF] 1246 [TX_PWR_BY_RATE_NUM_SECTION]; 1247 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1248 [TX_PWR_BY_RATE_NUM_RF] 1249 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1250 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1251 [TX_PWR_BY_RATE_NUM_RF] 1252 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1253 u8 default_initialgain[4]; 1254 1255 /* the current Tx power level */ 1256 u8 cur_cck_txpwridx; 1257 u8 cur_ofdm24g_txpwridx; 1258 u8 cur_bw20_txpwridx; 1259 u8 cur_bw40_txpwridx; 1260 1261 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1262 [MAX_2_4G_BANDWIDTH_NUM] 1263 [MAX_RATE_SECTION_NUM] 1264 [CHANNEL_MAX_NUMBER_2G] 1265 [MAX_RF_PATH_NUM]; 1266 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1267 [MAX_5G_BANDWIDTH_NUM] 1268 [MAX_RATE_SECTION_NUM] 1269 [CHANNEL_MAX_NUMBER_5G] 1270 [MAX_RF_PATH_NUM]; 1271 1272 u32 rfreg_chnlval[2]; 1273 bool apk_done; 1274 u32 reg_rf3c[2]; /* pathA / pathB */ 1275 1276 u32 backup_rf_0x1a;/*92ee*/ 1277 /* bfsync */ 1278 u8 framesync; 1279 u32 framesync_c34; 1280 1281 u8 num_total_rfpath; 1282 struct phy_parameters hwparam_tables[MAX_TAB]; 1283 u16 rf_pathmap; 1284 1285 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1286 enum rt_polarity_ctl polarity_ctl; 1287 }; 1288 1289 #define MAX_TID_COUNT 9 1290 #define RTL_AGG_STOP 0 1291 #define RTL_AGG_PROGRESS 1 1292 #define RTL_AGG_START 2 1293 #define RTL_AGG_OPERATIONAL 3 1294 #define RTL_AGG_OFF 0 1295 #define RTL_AGG_ON 1 1296 #define RTL_RX_AGG_START 1 1297 #define RTL_RX_AGG_STOP 0 1298 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1299 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1300 1301 struct rtl_ht_agg { 1302 u16 txq_id; 1303 u16 wait_for_ba; 1304 u16 start_idx; 1305 u64 bitmap; 1306 u32 rate_n_flags; 1307 u8 agg_state; 1308 u8 rx_agg_state; 1309 }; 1310 1311 struct rssi_sta { 1312 long undec_sm_pwdb; 1313 long undec_sm_cck; 1314 }; 1315 1316 struct rtl_tid_data { 1317 u16 seq_number; 1318 struct rtl_ht_agg agg; 1319 }; 1320 1321 struct rtl_sta_info { 1322 struct list_head list; 1323 struct rtl_tid_data tids[MAX_TID_COUNT]; 1324 /* just used for ap adhoc or mesh*/ 1325 struct rssi_sta rssi_stat; 1326 u16 wireless_mode; 1327 u8 ratr_index; 1328 u8 mimo_ps; 1329 u8 mac_addr[ETH_ALEN]; 1330 } __packed; 1331 1332 struct rtl_priv; 1333 struct rtl_io { 1334 struct device *dev; 1335 struct mutex bb_mutex; 1336 1337 /*PCI MEM map */ 1338 unsigned long pci_mem_end; /*shared mem end */ 1339 unsigned long pci_mem_start; /*shared mem start */ 1340 1341 /*PCI IO map */ 1342 unsigned long pci_base_addr; /*device I/O address */ 1343 1344 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1345 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1346 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1347 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1348 u16 len); 1349 1350 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1351 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1352 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1353 1354 }; 1355 1356 struct rtl_mac { 1357 u8 mac_addr[ETH_ALEN]; 1358 u8 mac80211_registered; 1359 u8 beacon_enabled; 1360 1361 u32 tx_ss_num; 1362 u32 rx_ss_num; 1363 1364 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1365 struct ieee80211_hw *hw; 1366 struct ieee80211_vif *vif; 1367 enum nl80211_iftype opmode; 1368 1369 /*Probe Beacon management */ 1370 struct rtl_tid_data tids[MAX_TID_COUNT]; 1371 enum rtl_link_state link_state; 1372 1373 int n_channels; 1374 int n_bitrates; 1375 1376 bool offchan_delay; 1377 u8 p2p; /*using p2p role*/ 1378 bool p2p_in_use; 1379 1380 /*filters */ 1381 u32 rx_conf; 1382 u16 rx_mgt_filter; 1383 u16 rx_ctrl_filter; 1384 u16 rx_data_filter; 1385 1386 bool act_scanning; 1387 u8 cnt_after_linked; 1388 bool skip_scan; 1389 1390 /* early mode */ 1391 /* skb wait queue */ 1392 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1393 1394 u8 ht_stbc_cap; 1395 u8 ht_cur_stbc; 1396 1397 /*vht support*/ 1398 u8 vht_enable; 1399 u8 bw_80; 1400 u8 vht_cur_ldpc; 1401 u8 vht_cur_stbc; 1402 u8 vht_stbc_cap; 1403 u8 vht_ldpc_cap; 1404 1405 /*RDG*/ 1406 bool rdg_en; 1407 1408 /*AP*/ 1409 u8 bssid[ETH_ALEN] __aligned(2); 1410 u32 vendor; 1411 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1412 u32 basic_rates; /* b/g rates */ 1413 u8 ht_enable; 1414 u8 sgi_40; 1415 u8 sgi_20; 1416 u8 bw_40; 1417 u16 mode; /* wireless mode */ 1418 u8 slot_time; 1419 u8 short_preamble; 1420 u8 use_cts_protect; 1421 u8 cur_40_prime_sc; 1422 u8 cur_40_prime_sc_bk; 1423 u8 cur_80_prime_sc; 1424 u64 tsf; 1425 u8 retry_short; 1426 u8 retry_long; 1427 u16 assoc_id; 1428 bool hiddenssid; 1429 1430 /*IBSS*/ 1431 int beacon_interval; 1432 1433 /*AMPDU*/ 1434 u8 min_space_cfg; /*For Min spacing configurations */ 1435 u8 max_mss_density; 1436 u8 current_ampdu_factor; 1437 u8 current_ampdu_density; 1438 1439 /*QOS & EDCA */ 1440 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1441 struct rtl_qos_parameters ac[AC_MAX]; 1442 1443 /* counters */ 1444 u64 last_txok_cnt; 1445 u64 last_rxok_cnt; 1446 u32 last_bt_edca_ul; 1447 u32 last_bt_edca_dl; 1448 }; 1449 1450 struct btdm_8723 { 1451 bool all_off; 1452 bool agc_table_en; 1453 bool adc_back_off_on; 1454 bool b2_ant_hid_en; 1455 bool low_penalty_rate_adaptive; 1456 bool rf_rx_lpf_shrink; 1457 bool reject_aggre_pkt; 1458 bool tra_tdma_on; 1459 u8 tra_tdma_nav; 1460 u8 tra_tdma_ant; 1461 bool tdma_on; 1462 u8 tdma_ant; 1463 u8 tdma_nav; 1464 u8 tdma_dac_swing; 1465 u8 fw_dac_swing_lvl; 1466 bool ps_tdma_on; 1467 u8 ps_tdma_byte[5]; 1468 bool pta_on; 1469 u32 val_0x6c0; 1470 u32 val_0x6c8; 1471 u32 val_0x6cc; 1472 bool sw_dac_swing_on; 1473 u32 sw_dac_swing_lvl; 1474 u32 wlan_act_hi; 1475 u32 wlan_act_lo; 1476 u32 bt_retry_index; 1477 bool dec_bt_pwr; 1478 bool ignore_wlan_act; 1479 }; 1480 1481 struct bt_coexist_8723 { 1482 u32 high_priority_tx; 1483 u32 high_priority_rx; 1484 u32 low_priority_tx; 1485 u32 low_priority_rx; 1486 u8 c2h_bt_info; 1487 bool c2h_bt_info_req_sent; 1488 bool c2h_bt_inquiry_page; 1489 u32 bt_inq_page_start_time; 1490 u8 bt_retry_cnt; 1491 u8 c2h_bt_info_original; 1492 u8 bt_inquiry_page_cnt; 1493 struct btdm_8723 btdm; 1494 }; 1495 1496 struct rtl_hal { 1497 struct ieee80211_hw *hw; 1498 bool driver_is_goingto_unload; 1499 bool up_first_time; 1500 bool first_init; 1501 bool being_init_adapter; 1502 bool bbrf_ready; 1503 bool mac_func_enable; 1504 bool pre_edcca_enable; 1505 struct bt_coexist_8723 hal_coex_8723; 1506 1507 enum intf_type interface; 1508 u16 hw_type; /*92c or 92d or 92s and so on */ 1509 u8 ic_class; 1510 u8 oem_id; 1511 u32 version; /*version of chip */ 1512 u8 state; /*stop 0, start 1 */ 1513 u8 board_type; 1514 u8 package_type; 1515 u8 external_pa; 1516 1517 u8 pa_mode; 1518 u8 pa_type_2g; 1519 u8 pa_type_5g; 1520 u8 lna_type_2g; 1521 u8 lna_type_5g; 1522 u8 external_pa_2g; 1523 u8 external_lna_2g; 1524 u8 external_pa_5g; 1525 u8 external_lna_5g; 1526 u8 type_glna; 1527 u8 type_gpa; 1528 u8 type_alna; 1529 u8 type_apa; 1530 u8 rfe_type; 1531 1532 /*firmware */ 1533 u32 fwsize; 1534 u8 *pfirmware; 1535 u16 fw_version; 1536 u16 fw_subversion; 1537 bool h2c_setinprogress; 1538 u8 last_hmeboxnum; 1539 bool fw_ready; 1540 /*Reserve page start offset except beacon in TxQ. */ 1541 u8 fw_rsvdpage_startoffset; 1542 u8 h2c_txcmd_seq; 1543 u8 current_ra_rate; 1544 1545 /* FW Cmd IO related */ 1546 u16 fwcmd_iomap; 1547 u32 fwcmd_ioparam; 1548 bool set_fwcmd_inprogress; 1549 u8 current_fwcmd_io; 1550 1551 struct p2p_ps_offload_t p2p_ps_offload; 1552 bool fw_clk_change_in_progress; 1553 bool allow_sw_to_change_hwclc; 1554 u8 fw_ps_state; 1555 /**/ 1556 bool driver_going2unload; 1557 1558 /*AMPDU init min space*/ 1559 u8 minspace_cfg; /*For Min spacing configurations */ 1560 1561 /* Dual mac */ 1562 enum macphy_mode macphymode; 1563 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1564 enum band_type current_bandtypebackup; 1565 enum band_type bandset; 1566 /* dual MAC 0--Mac0 1--Mac1 */ 1567 u32 interfaceindex; 1568 /* just for DualMac S3S4 */ 1569 u8 macphyctl_reg; 1570 bool earlymode_enable; 1571 u8 max_earlymode_num; 1572 /* Dual mac*/ 1573 bool during_mac0init_radiob; 1574 bool during_mac1init_radioa; 1575 bool reloadtxpowerindex; 1576 /* True if IMR or IQK have done 1577 for 2.4G in scan progress */ 1578 bool load_imrandiqk_setting_for2g; 1579 1580 bool disable_amsdu_8k; 1581 bool master_of_dmsp; 1582 bool slave_of_dmsp; 1583 1584 u16 rx_tag;/*for 92ee*/ 1585 u8 rts_en; 1586 1587 /*for wowlan*/ 1588 bool wow_enable; 1589 bool enter_pnp_sleep; 1590 bool wake_from_pnp_sleep; 1591 bool wow_enabled; 1592 __kernel_time_t last_suspend_sec; 1593 u32 wowlan_fwsize; 1594 u8 *wowlan_firmware; 1595 1596 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1597 1598 bool real_wow_v2_enable; 1599 bool re_init_llt_table; 1600 }; 1601 1602 struct rtl_security { 1603 /*default 0 */ 1604 bool use_sw_sec; 1605 1606 bool being_setkey; 1607 bool use_defaultkey; 1608 /*Encryption Algorithm for Unicast Packet */ 1609 enum rt_enc_alg pairwise_enc_algorithm; 1610 /*Encryption Algorithm for Brocast/Multicast */ 1611 enum rt_enc_alg group_enc_algorithm; 1612 /*Cam Entry Bitmap */ 1613 u32 hwsec_cam_bitmap; 1614 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1615 /*local Key buffer, indx 0 is for 1616 pairwise key 1-4 is for agoup key. */ 1617 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1618 u8 key_len[KEY_BUF_SIZE]; 1619 1620 /*The pointer of Pairwise Key, 1621 it always points to KeyBuf[4] */ 1622 u8 *pairwise_key; 1623 }; 1624 1625 #define ASSOCIATE_ENTRY_NUM 33 1626 1627 struct fast_ant_training { 1628 u8 bssid[6]; 1629 u8 antsel_rx_keep_0; 1630 u8 antsel_rx_keep_1; 1631 u8 antsel_rx_keep_2; 1632 u32 ant_sum[7]; 1633 u32 ant_cnt[7]; 1634 u32 ant_ave[7]; 1635 u8 fat_state; 1636 u32 train_idx; 1637 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1638 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1639 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1640 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1641 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1642 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1643 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1644 u8 rx_idle_ant; 1645 bool becomelinked; 1646 }; 1647 1648 struct dm_phy_dbg_info { 1649 s8 rx_snrdb[4]; 1650 u64 num_qry_phy_status; 1651 u64 num_qry_phy_status_cck; 1652 u64 num_qry_phy_status_ofdm; 1653 u16 num_qry_beacon_pkt; 1654 u16 num_non_be_pkt; 1655 s32 rx_evm[4]; 1656 }; 1657 1658 struct rtl_dm { 1659 /*PHY status for Dynamic Management */ 1660 long entry_min_undec_sm_pwdb; 1661 long undec_sm_cck; 1662 long undec_sm_pwdb; /*out dm */ 1663 long entry_max_undec_sm_pwdb; 1664 s32 ofdm_pkt_cnt; 1665 bool dm_initialgain_enable; 1666 bool dynamic_txpower_enable; 1667 bool current_turbo_edca; 1668 bool is_any_nonbepkts; /*out dm */ 1669 bool is_cur_rdlstate; 1670 bool txpower_trackinginit; 1671 bool disable_framebursting; 1672 bool cck_inch14; 1673 bool txpower_tracking; 1674 bool useramask; 1675 bool rfpath_rxenable[4]; 1676 bool inform_fw_driverctrldm; 1677 bool current_mrc_switch; 1678 u8 txpowercount; 1679 u8 powerindex_backup[6]; 1680 1681 u8 thermalvalue_rxgain; 1682 u8 thermalvalue_iqk; 1683 u8 thermalvalue_lck; 1684 u8 thermalvalue; 1685 u8 last_dtp_lvl; 1686 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1687 u8 thermalvalue_avg_index; 1688 u8 tm_trigger; 1689 bool done_txpower; 1690 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1691 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1692 u8 dm_flag_tmp; 1693 u8 dm_type; 1694 u8 dm_rssi_sel; 1695 u8 txpower_track_control; 1696 bool interrupt_migration; 1697 bool disable_tx_int; 1698 s8 ofdm_index[MAX_RF_PATH]; 1699 u8 default_ofdm_index; 1700 u8 default_cck_index; 1701 s8 cck_index; 1702 s8 delta_power_index[MAX_RF_PATH]; 1703 s8 delta_power_index_last[MAX_RF_PATH]; 1704 s8 power_index_offset[MAX_RF_PATH]; 1705 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1706 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1707 s8 remnant_cck_idx; 1708 bool modify_txagc_flag_path_a; 1709 bool modify_txagc_flag_path_b; 1710 1711 bool one_entry_only; 1712 struct dm_phy_dbg_info dbginfo; 1713 1714 /* Dynamic ATC switch */ 1715 bool atc_status; 1716 bool large_cfo_hit; 1717 bool is_freeze; 1718 int cfo_tail[2]; 1719 int cfo_ave_pre; 1720 int crystal_cap; 1721 u8 cfo_threshold; 1722 u32 packet_count; 1723 u32 packet_count_pre; 1724 u8 tx_rate; 1725 1726 /*88e tx power tracking*/ 1727 u8 swing_idx_ofdm[MAX_RF_PATH]; 1728 u8 swing_idx_ofdm_cur; 1729 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1730 bool swing_flag_ofdm; 1731 u8 swing_idx_cck; 1732 u8 swing_idx_cck_cur; 1733 u8 swing_idx_cck_base; 1734 bool swing_flag_cck; 1735 1736 s8 swing_diff_2g; 1737 s8 swing_diff_5g; 1738 1739 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ]; 1740 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ]; 1741 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ]; 1742 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ]; 1743 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ]; 1744 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ]; 1745 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ]; 1746 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ]; 1747 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ]; 1748 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ]; 1749 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ]; 1750 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ]; 1751 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ]; 1752 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ]; 1753 1754 /* DMSP */ 1755 bool supp_phymode_switch; 1756 1757 /* DulMac */ 1758 struct fast_ant_training fat_table; 1759 1760 u8 resp_tx_path; 1761 u8 path_sel; 1762 u32 patha_sum; 1763 u32 pathb_sum; 1764 u32 patha_cnt; 1765 u32 pathb_cnt; 1766 1767 u8 pre_channel; 1768 u8 *p_channel; 1769 u8 linked_interval; 1770 1771 u64 last_tx_ok_cnt; 1772 u64 last_rx_ok_cnt; 1773 }; 1774 1775 #define EFUSE_MAX_LOGICAL_SIZE 512 1776 1777 struct rtl_efuse { 1778 bool autoLoad_ok; 1779 bool bootfromefuse; 1780 u16 max_physical_size; 1781 1782 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1783 u16 efuse_usedbytes; 1784 u8 efuse_usedpercentage; 1785 #ifdef EFUSE_REPG_WORKAROUND 1786 bool efuse_re_pg_sec1flag; 1787 u8 efuse_re_pg_data[8]; 1788 #endif 1789 1790 u8 autoload_failflag; 1791 u8 autoload_status; 1792 1793 short epromtype; 1794 u16 eeprom_vid; 1795 u16 eeprom_did; 1796 u16 eeprom_svid; 1797 u16 eeprom_smid; 1798 u8 eeprom_oemid; 1799 u16 eeprom_channelplan; 1800 u8 eeprom_version; 1801 u8 board_type; 1802 u8 external_pa; 1803 1804 u8 dev_addr[6]; 1805 u8 wowlan_enable; 1806 u8 antenna_div_cfg; 1807 u8 antenna_div_type; 1808 1809 bool txpwr_fromeprom; 1810 u8 eeprom_crystalcap; 1811 u8 eeprom_tssi[2]; 1812 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1813 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1814 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1815 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1816 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1817 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1818 1819 u8 internal_pa_5g[2]; /* pathA / pathB */ 1820 u8 eeprom_c9; 1821 u8 eeprom_cc; 1822 1823 /*For power group */ 1824 u8 eeprom_pwrgroup[2][3]; 1825 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1826 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1827 1828 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1829 /*For HT 40MHZ pwr */ 1830 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1831 /*For HT 40MHZ pwr */ 1832 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1833 1834 /*--------------------------------------------------------* 1835 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1836 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1837 * define new arrays in Windows code. 1838 * BUT, in linux code, we use the same array for all ICs. 1839 * 1840 * The Correspondance relation between two arrays is: 1841 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1842 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1843 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1844 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1845 * 1846 * Sizes of these arrays are decided by the larger ones. 1847 */ 1848 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1849 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1850 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1851 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1852 1853 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1854 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1855 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1856 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1857 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1858 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1859 1860 u8 txpwr_safetyflag; /* Band edge enable flag */ 1861 u16 eeprom_txpowerdiff; 1862 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1863 u8 antenna_txpwdiff[3]; 1864 1865 u8 eeprom_regulatory; 1866 u8 eeprom_thermalmeter; 1867 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1868 u16 tssi_13dbm; 1869 u8 crystalcap; /* CrystalCap. */ 1870 u8 delta_iqk; 1871 u8 delta_lck; 1872 1873 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1874 bool apk_thermalmeterignore; 1875 1876 bool b1x1_recvcombine; 1877 bool b1ss_support; 1878 1879 /*channel plan */ 1880 u8 channel_plan; 1881 }; 1882 1883 struct rtl_tx_report { 1884 atomic_t sn; 1885 u16 last_sent_sn; 1886 unsigned long last_sent_time; 1887 u16 last_recv_sn; 1888 }; 1889 1890 struct rtl_ps_ctl { 1891 bool pwrdomain_protect; 1892 bool in_powersavemode; 1893 bool rfchange_inprogress; 1894 bool swrf_processing; 1895 bool hwradiooff; 1896 /* 1897 * just for PCIE ASPM 1898 * If it supports ASPM, Offset[560h] = 0x40, 1899 * otherwise Offset[560h] = 0x00. 1900 * */ 1901 bool support_aspm; 1902 bool support_backdoor; 1903 1904 /*for LPS */ 1905 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1906 bool swctrl_lps; 1907 bool leisure_ps; 1908 bool fwctrl_lps; 1909 u8 fwctrl_psmode; 1910 /*For Fw control LPS mode */ 1911 u8 reg_fwctrl_lps; 1912 /*Record Fw PS mode status. */ 1913 bool fw_current_inpsmode; 1914 u8 reg_max_lps_awakeintvl; 1915 bool report_linked; 1916 bool low_power_enable;/*for 32k*/ 1917 1918 /*for IPS */ 1919 bool inactiveps; 1920 1921 u32 rfoff_reason; 1922 1923 /*RF OFF Level */ 1924 u32 cur_ps_level; 1925 u32 reg_rfps_level; 1926 1927 /*just for PCIE ASPM */ 1928 u8 const_amdpci_aspm; 1929 bool pwrdown_mode; 1930 1931 enum rf_pwrstate inactive_pwrstate; 1932 enum rf_pwrstate rfpwr_state; /*cur power state */ 1933 1934 /* for SW LPS*/ 1935 bool sw_ps_enabled; 1936 bool state; 1937 bool state_inap; 1938 bool multi_buffered; 1939 u16 nullfunc_seq; 1940 unsigned int dtim_counter; 1941 unsigned int sleep_ms; 1942 unsigned long last_sleep_jiffies; 1943 unsigned long last_awake_jiffies; 1944 unsigned long last_delaylps_stamp_jiffies; 1945 unsigned long last_dtim; 1946 unsigned long last_beacon; 1947 unsigned long last_action; 1948 unsigned long last_slept; 1949 1950 /*For P2P PS */ 1951 struct rtl_p2p_ps_info p2p_ps_info; 1952 u8 pwr_mode; 1953 u8 smart_ps; 1954 1955 /* wake up on line */ 1956 u8 wo_wlan_mode; 1957 u8 arp_offload_enable; 1958 u8 gtk_offload_enable; 1959 /* Used for WOL, indicates the reason for waking event.*/ 1960 u32 wakeup_reason; 1961 /* Record the last waking time for comparison with setting key. */ 1962 u64 last_wakeup_time; 1963 }; 1964 1965 struct rtl_stats { 1966 u8 psaddr[ETH_ALEN]; 1967 u32 mac_time[2]; 1968 s8 rssi; 1969 u8 signal; 1970 u8 noise; 1971 u8 rate; /* hw desc rate */ 1972 u8 received_channel; 1973 u8 control; 1974 u8 mask; 1975 u8 freq; 1976 u16 len; 1977 u64 tsf; 1978 u32 beacon_time; 1979 u8 nic_type; 1980 u16 length; 1981 u8 signalquality; /*in 0-100 index. */ 1982 /* 1983 * Real power in dBm for this packet, 1984 * no beautification and aggregation. 1985 * */ 1986 s32 recvsignalpower; 1987 s8 rxpower; /*in dBm Translate from PWdB */ 1988 u8 signalstrength; /*in 0-100 index. */ 1989 u16 hwerror:1; 1990 u16 crc:1; 1991 u16 icv:1; 1992 u16 shortpreamble:1; 1993 u16 antenna:1; 1994 u16 decrypted:1; 1995 u16 wakeup:1; 1996 u32 timestamp_low; 1997 u32 timestamp_high; 1998 bool shift; 1999 2000 u8 rx_drvinfo_size; 2001 u8 rx_bufshift; 2002 bool isampdu; 2003 bool isfirst_ampdu; 2004 bool rx_is40Mhzpacket; 2005 u8 rx_packet_bw; 2006 u32 rx_pwdb_all; 2007 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2008 s8 rx_mimo_signalquality[4]; 2009 u8 rx_mimo_evm_dbm[4]; 2010 u16 cfo_short[4]; /* per-path's Cfo_short */ 2011 u16 cfo_tail[4]; 2012 2013 s8 rx_mimo_sig_qual[4]; 2014 u8 rx_pwr[4]; /* per-path's pwdb */ 2015 u8 rx_snr[4]; /* per-path's SNR */ 2016 u8 bandwidth; 2017 u8 bt_coex_pwr_adjust; 2018 bool packet_matchbssid; 2019 bool is_cck; 2020 bool is_ht; 2021 bool packet_toself; 2022 bool packet_beacon; /*for rssi */ 2023 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2024 2025 bool is_vht; 2026 bool is_short_gi; 2027 u8 vht_nss; 2028 2029 u8 packet_report_type; 2030 2031 u32 macid; 2032 u8 wake_match; 2033 u32 bt_rx_rssi_percentage; 2034 u32 macid_valid_entry[2]; 2035 }; 2036 2037 2038 struct rt_link_detect { 2039 /* count for roaming */ 2040 u32 bcn_rx_inperiod; 2041 u32 roam_times; 2042 2043 u32 num_tx_in4period[4]; 2044 u32 num_rx_in4period[4]; 2045 2046 u32 num_tx_inperiod; 2047 u32 num_rx_inperiod; 2048 2049 bool busytraffic; 2050 bool tx_busy_traffic; 2051 bool rx_busy_traffic; 2052 bool higher_busytraffic; 2053 bool higher_busyrxtraffic; 2054 2055 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2056 u32 tidtx_inperiod[MAX_TID_COUNT]; 2057 bool higher_busytxtraffic[MAX_TID_COUNT]; 2058 }; 2059 2060 struct rtl_tcb_desc { 2061 u8 packet_bw:2; 2062 u8 multicast:1; 2063 u8 broadcast:1; 2064 2065 u8 rts_stbc:1; 2066 u8 rts_enable:1; 2067 u8 cts_enable:1; 2068 u8 rts_use_shortpreamble:1; 2069 u8 rts_use_shortgi:1; 2070 u8 rts_sc:1; 2071 u8 rts_bw:1; 2072 u8 rts_rate; 2073 2074 u8 use_shortgi:1; 2075 u8 use_shortpreamble:1; 2076 u8 use_driver_rate:1; 2077 u8 disable_ratefallback:1; 2078 2079 u8 use_spe_rpt:1; 2080 2081 u8 ratr_index; 2082 u8 mac_id; 2083 u8 hw_rate; 2084 2085 u8 last_inipkt:1; 2086 u8 cmd_or_init:1; 2087 u8 queue_index; 2088 2089 /* early mode */ 2090 u8 empkt_num; 2091 /* The max value by HW */ 2092 u32 empkt_len[10]; 2093 bool tx_enable_sw_calc_duration; 2094 }; 2095 2096 struct rtl_wow_pattern { 2097 u8 type; 2098 u16 crc; 2099 u32 mask[4]; 2100 }; 2101 2102 struct rtl_hal_ops { 2103 int (*init_sw_vars) (struct ieee80211_hw *hw); 2104 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2105 void (*read_chip_version)(struct ieee80211_hw *hw); 2106 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2107 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2108 u32 *p_inta, u32 *p_intb); 2109 int (*hw_init) (struct ieee80211_hw *hw); 2110 void (*hw_disable) (struct ieee80211_hw *hw); 2111 void (*hw_suspend) (struct ieee80211_hw *hw); 2112 void (*hw_resume) (struct ieee80211_hw *hw); 2113 void (*enable_interrupt) (struct ieee80211_hw *hw); 2114 void (*disable_interrupt) (struct ieee80211_hw *hw); 2115 int (*set_network_type) (struct ieee80211_hw *hw, 2116 enum nl80211_iftype type); 2117 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2118 bool check_bssid); 2119 void (*set_bw_mode) (struct ieee80211_hw *hw, 2120 enum nl80211_channel_type ch_type); 2121 u8(*switch_channel) (struct ieee80211_hw *hw); 2122 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2123 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2124 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2125 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2126 u32 add_msr, u32 rm_msr); 2127 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2128 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2129 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2130 struct ieee80211_sta *sta, u8 rssi_level); 2131 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2132 u8 *desc, u8 queue_index, 2133 struct sk_buff *skb, dma_addr_t addr); 2134 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2135 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2136 u8 queue_index); 2137 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2138 u8 queue_index); 2139 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2140 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2141 u8 *pbd_desc_tx, 2142 struct ieee80211_tx_info *info, 2143 struct ieee80211_sta *sta, 2144 struct sk_buff *skb, u8 hw_queue, 2145 struct rtl_tcb_desc *ptcb_desc); 2146 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2147 u32 buffer_len, bool bIsPsPoll); 2148 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2149 bool firstseg, bool lastseg, 2150 struct sk_buff *skb); 2151 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2152 struct rtl_stats *stats, 2153 struct ieee80211_rx_status *rx_status, 2154 u8 *pdesc, struct sk_buff *skb); 2155 void (*set_channel_access) (struct ieee80211_hw *hw); 2156 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2157 void (*dm_watchdog) (struct ieee80211_hw *hw); 2158 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2159 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2160 enum rf_pwrstate rfpwr_state); 2161 void (*led_control) (struct ieee80211_hw *hw, 2162 enum led_ctl_mode ledaction); 2163 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2164 u8 desc_name, u8 *val); 2165 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); 2166 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2167 u8 hw_queue, u16 index); 2168 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2169 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2170 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2171 u8 *macaddr, bool is_group, u8 enc_algo, 2172 bool is_wepkey, bool clear_all); 2173 void (*init_sw_leds) (struct ieee80211_hw *hw); 2174 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2175 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2176 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2177 u32 data); 2178 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2179 u32 regaddr, u32 bitmask); 2180 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2181 u32 regaddr, u32 bitmask, u32 data); 2182 void (*linked_set_reg) (struct ieee80211_hw *hw); 2183 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2184 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2185 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2186 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2187 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2188 u8 *powerlevel); 2189 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2190 u8 *ppowerlevel, u8 channel); 2191 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2192 u8 configtype); 2193 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2194 u8 configtype); 2195 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2196 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2197 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2198 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2199 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2200 bool mstate); 2201 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2202 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2203 u32 cmd_len, u8 *p_cmdbuffer); 2204 bool (*get_btc_status) (void); 2205 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2206 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2207 const struct rtl_stats *status, struct sk_buff *skb); 2208 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2209 struct rtl_wow_pattern *rtl_pattern, 2210 u8 index); 2211 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2212 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len, 2213 u8 *val); 2214 }; 2215 2216 struct rtl_intf_ops { 2217 /*com */ 2218 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2219 int (*adapter_start) (struct ieee80211_hw *hw); 2220 void (*adapter_stop) (struct ieee80211_hw *hw); 2221 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2222 struct rtl_priv **buddy_priv); 2223 2224 int (*adapter_tx) (struct ieee80211_hw *hw, 2225 struct ieee80211_sta *sta, 2226 struct sk_buff *skb, 2227 struct rtl_tcb_desc *ptcb_desc); 2228 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2229 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2230 bool (*waitq_insert) (struct ieee80211_hw *hw, 2231 struct ieee80211_sta *sta, 2232 struct sk_buff *skb); 2233 2234 /*pci */ 2235 void (*disable_aspm) (struct ieee80211_hw *hw); 2236 void (*enable_aspm) (struct ieee80211_hw *hw); 2237 2238 /*usb */ 2239 }; 2240 2241 struct rtl_mod_params { 2242 /* default: 0,0 */ 2243 u64 debug_mask; 2244 /* default: 0 = using hardware encryption */ 2245 bool sw_crypto; 2246 2247 /* default: 0 = DBG_EMERG (0)*/ 2248 int debug_level; 2249 2250 /* default: 1 = using no linked power save */ 2251 bool inactiveps; 2252 2253 /* default: 1 = using linked sw power save */ 2254 bool swctrl_lps; 2255 2256 /* default: 1 = using linked fw power save */ 2257 bool fwctrl_lps; 2258 2259 /* default: 0 = not using MSI interrupts mode 2260 * submodules should set their own default value 2261 */ 2262 bool msi_support; 2263 2264 /* default 0: 1 means disable */ 2265 bool disable_watchdog; 2266 2267 /* default 0: 1 means do not disable interrupts */ 2268 bool int_clear; 2269 2270 /* select antenna */ 2271 int ant_sel; 2272 }; 2273 2274 struct rtl_hal_usbint_cfg { 2275 /* data - rx */ 2276 u32 in_ep_num; 2277 u32 rx_urb_num; 2278 u32 rx_max_size; 2279 2280 /* op - rx */ 2281 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2282 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2283 struct sk_buff_head *); 2284 2285 /* tx */ 2286 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2287 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2288 struct sk_buff *); 2289 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2290 struct sk_buff_head *); 2291 2292 /* endpoint mapping */ 2293 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2294 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2295 }; 2296 2297 struct rtl_hal_cfg { 2298 u8 bar_id; 2299 bool write_readback; 2300 char *name; 2301 char *alt_fw_name; 2302 struct rtl_hal_ops *ops; 2303 struct rtl_mod_params *mod_params; 2304 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2305 2306 /*this map used for some registers or vars 2307 defined int HAL but used in MAIN */ 2308 u32 maps[RTL_VAR_MAP_MAX]; 2309 2310 }; 2311 2312 struct rtl_locks { 2313 /* mutex */ 2314 struct mutex conf_mutex; 2315 struct mutex ps_mutex; 2316 2317 /*spin lock */ 2318 spinlock_t ips_lock; 2319 spinlock_t irq_th_lock; 2320 spinlock_t irq_pci_lock; 2321 spinlock_t tx_lock; 2322 spinlock_t h2c_lock; 2323 spinlock_t rf_ps_lock; 2324 spinlock_t rf_lock; 2325 spinlock_t lps_lock; 2326 spinlock_t waitq_lock; 2327 spinlock_t entry_list_lock; 2328 spinlock_t usb_lock; 2329 spinlock_t c2hcmd_lock; 2330 spinlock_t scan_list_lock; /* lock for the scan list */ 2331 2332 /*FW clock change */ 2333 spinlock_t fw_ps_lock; 2334 2335 /*Dual mac*/ 2336 spinlock_t cck_and_rw_pagea_lock; 2337 2338 /*Easy concurrent*/ 2339 spinlock_t check_sendpkt_lock; 2340 2341 spinlock_t iqk_lock; 2342 }; 2343 2344 struct rtl_works { 2345 struct ieee80211_hw *hw; 2346 2347 /*timer */ 2348 struct timer_list watchdog_timer; 2349 struct timer_list dualmac_easyconcurrent_retrytimer; 2350 struct timer_list fw_clockoff_timer; 2351 struct timer_list fast_antenna_training_timer; 2352 /*task */ 2353 struct tasklet_struct irq_tasklet; 2354 struct tasklet_struct irq_prepare_bcn_tasklet; 2355 2356 /*work queue */ 2357 struct workqueue_struct *rtl_wq; 2358 struct delayed_work watchdog_wq; 2359 struct delayed_work ips_nic_off_wq; 2360 struct delayed_work c2hcmd_wq; 2361 2362 /* For SW LPS */ 2363 struct delayed_work ps_work; 2364 struct delayed_work ps_rfon_wq; 2365 struct delayed_work fwevt_wq; 2366 2367 struct work_struct lps_change_work; 2368 struct work_struct fill_h2c_cmd; 2369 }; 2370 2371 #define MIMO_PS_STATIC 0 2372 #define MIMO_PS_DYNAMIC 1 2373 #define MIMO_PS_NOLIMIT 3 2374 2375 struct rtl_dualmac_easy_concurrent_ctl { 2376 enum band_type currentbandtype_backfordmdp; 2377 bool close_bbandrf_for_dmsp; 2378 bool change_to_dmdp; 2379 bool change_to_dmsp; 2380 bool switch_in_process; 2381 }; 2382 2383 struct rtl_dmsp_ctl { 2384 bool activescan_for_slaveofdmsp; 2385 bool scan_for_anothermac_fordmsp; 2386 bool scan_for_itself_fordmsp; 2387 bool writedig_for_anothermacofdmsp; 2388 u32 curdigvalue_for_anothermacofdmsp; 2389 bool changecckpdstate_for_anothermacofdmsp; 2390 u8 curcckpdstate_for_anothermacofdmsp; 2391 bool changetxhighpowerlvl_for_anothermacofdmsp; 2392 u8 curtxhighlvl_for_anothermacofdmsp; 2393 long rssivalmin_for_anothermacofdmsp; 2394 }; 2395 2396 struct ps_t { 2397 u8 pre_ccastate; 2398 u8 cur_ccasate; 2399 u8 pre_rfstate; 2400 u8 cur_rfstate; 2401 u8 initialize; 2402 long rssi_val_min; 2403 }; 2404 2405 struct dig_t { 2406 u32 rssi_lowthresh; 2407 u32 rssi_highthresh; 2408 u32 fa_lowthresh; 2409 u32 fa_highthresh; 2410 long last_min_undec_pwdb_for_dm; 2411 long rssi_highpower_lowthresh; 2412 long rssi_highpower_highthresh; 2413 u32 recover_cnt; 2414 u32 pre_igvalue; 2415 u32 cur_igvalue; 2416 long rssi_val; 2417 u8 dig_enable_flag; 2418 u8 dig_ext_port_stage; 2419 u8 dig_algorithm; 2420 u8 dig_twoport_algorithm; 2421 u8 dig_dbgmode; 2422 u8 dig_slgorithm_switch; 2423 u8 cursta_cstate; 2424 u8 presta_cstate; 2425 u8 curmultista_cstate; 2426 u8 stop_dig; 2427 s8 back_val; 2428 s8 back_range_max; 2429 s8 back_range_min; 2430 u8 rx_gain_max; 2431 u8 rx_gain_min; 2432 u8 min_undec_pwdb_for_dm; 2433 u8 rssi_val_min; 2434 u8 pre_cck_cca_thres; 2435 u8 cur_cck_cca_thres; 2436 u8 pre_cck_pd_state; 2437 u8 cur_cck_pd_state; 2438 u8 pre_cck_fa_state; 2439 u8 cur_cck_fa_state; 2440 u8 pre_ccastate; 2441 u8 cur_ccasate; 2442 u8 large_fa_hit; 2443 u8 forbidden_igi; 2444 u8 dig_state; 2445 u8 dig_highpwrstate; 2446 u8 cur_sta_cstate; 2447 u8 pre_sta_cstate; 2448 u8 cur_ap_cstate; 2449 u8 pre_ap_cstate; 2450 u8 cur_pd_thstate; 2451 u8 pre_pd_thstate; 2452 u8 cur_cs_ratiostate; 2453 u8 pre_cs_ratiostate; 2454 u8 backoff_enable_flag; 2455 s8 backoffval_range_max; 2456 s8 backoffval_range_min; 2457 u8 dig_min_0; 2458 u8 dig_min_1; 2459 u8 bt30_cur_igi; 2460 bool media_connect_0; 2461 bool media_connect_1; 2462 2463 u32 antdiv_rssi_max; 2464 u32 rssi_max; 2465 }; 2466 2467 struct rtl_global_var { 2468 /* from this list we can get 2469 * other adapter's rtl_priv */ 2470 struct list_head glb_priv_list; 2471 spinlock_t glb_list_lock; 2472 }; 2473 2474 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */ 2475 2476 struct rtl_btc_info { 2477 u8 bt_type; 2478 u8 btcoexist; 2479 u8 ant_num; 2480 u8 single_ant_path; 2481 2482 u8 ap_num; 2483 bool in_4way; 2484 unsigned long in_4way_ts; 2485 }; 2486 2487 struct bt_coexist_info { 2488 struct rtl_btc_ops *btc_ops; 2489 struct rtl_btc_info btc_info; 2490 /* EEPROM BT info. */ 2491 u8 eeprom_bt_coexist; 2492 u8 eeprom_bt_type; 2493 u8 eeprom_bt_ant_num; 2494 u8 eeprom_bt_ant_isol; 2495 u8 eeprom_bt_radio_shared; 2496 2497 u8 bt_coexistence; 2498 u8 bt_ant_num; 2499 u8 bt_coexist_type; 2500 u8 bt_state; 2501 u8 bt_cur_state; /* 0:on, 1:off */ 2502 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2503 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2504 u8 bt_service; 2505 u8 bt_radio_shared_type; 2506 u8 bt_rfreg_origin_1e; 2507 u8 bt_rfreg_origin_1f; 2508 u8 bt_rssi_state; 2509 u32 ratio_tx; 2510 u32 ratio_pri; 2511 u32 bt_edca_ul; 2512 u32 bt_edca_dl; 2513 2514 bool init_set; 2515 bool bt_busy_traffic; 2516 bool bt_traffic_mode_set; 2517 bool bt_non_traffic_mode_set; 2518 2519 bool fw_coexist_all_off; 2520 bool sw_coexist_all_off; 2521 bool hw_coexist_all_off; 2522 u32 cstate; 2523 u32 previous_state; 2524 u32 cstate_h; 2525 u32 previous_state_h; 2526 2527 u8 bt_pre_rssi_state; 2528 u8 bt_pre_rssi_state1; 2529 2530 u8 reg_bt_iso; 2531 u8 reg_bt_sco; 2532 bool balance_on; 2533 u8 bt_active_zero_cnt; 2534 bool cur_bt_disabled; 2535 bool pre_bt_disabled; 2536 2537 u8 bt_profile_case; 2538 u8 bt_profile_action; 2539 bool bt_busy; 2540 bool hold_for_bt_operation; 2541 u8 lps_counter; 2542 }; 2543 2544 struct rtl_btc_ops { 2545 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2546 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2547 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2548 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2549 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2550 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2551 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2552 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2553 enum rt_media_status mstatus); 2554 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2555 void (*btc_halt_notify) (void); 2556 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2557 u8 *tmp_buf, u8 length); 2558 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv, 2559 u8 *tmp_buf, u8 length); 2560 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2561 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2562 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2563 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2564 u8 pkt_type); 2565 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len); 2566 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv); 2567 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv); 2568 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv); 2569 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg, 2570 u8 *ctrl_agg_size, u8 *agg_size); 2571 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv); 2572 }; 2573 2574 struct proxim { 2575 bool proxim_on; 2576 2577 void *proximity_priv; 2578 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2579 struct sk_buff *skb); 2580 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2581 }; 2582 2583 struct rtl_c2hcmd { 2584 struct list_head list; 2585 u8 tag; 2586 u8 len; 2587 u8 *val; 2588 }; 2589 2590 struct rtl_bssid_entry { 2591 struct list_head list; 2592 u8 bssid[ETH_ALEN]; 2593 u32 age; 2594 }; 2595 2596 struct rtl_scan_list { 2597 int num; 2598 struct list_head list; /* sort by age */ 2599 }; 2600 2601 struct rtl_priv { 2602 struct ieee80211_hw *hw; 2603 struct completion firmware_loading_complete; 2604 struct list_head list; 2605 struct rtl_priv *buddy_priv; 2606 struct rtl_global_var *glb_var; 2607 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2608 struct rtl_dmsp_ctl dmsp_ctl; 2609 struct rtl_locks locks; 2610 struct rtl_works works; 2611 struct rtl_mac mac80211; 2612 struct rtl_hal rtlhal; 2613 struct rtl_regulatory regd; 2614 struct rtl_rfkill rfkill; 2615 struct rtl_io io; 2616 struct rtl_phy phy; 2617 struct rtl_dm dm; 2618 struct rtl_security sec; 2619 struct rtl_efuse efuse; 2620 struct rtl_led_ctl ledctl; 2621 struct rtl_tx_report tx_report; 2622 struct rtl_scan_list scan_list; 2623 2624 struct rtl_ps_ctl psc; 2625 struct rate_adaptive ra; 2626 struct dynamic_primary_cca primarycca; 2627 struct wireless_stats stats; 2628 struct rt_link_detect link_info; 2629 struct false_alarm_statistics falsealm_cnt; 2630 2631 struct rtl_rate_priv *rate_priv; 2632 2633 /* sta entry list for ap adhoc or mesh */ 2634 struct list_head entry_list; 2635 2636 /* c2hcmd list for kthread level access */ 2637 struct list_head c2hcmd_list; 2638 2639 int max_fw_size; 2640 2641 /* 2642 *hal_cfg : for diff cards 2643 *intf_ops : for diff interrface usb/pcie 2644 */ 2645 struct rtl_hal_cfg *cfg; 2646 const struct rtl_intf_ops *intf_ops; 2647 2648 /*this var will be set by set_bit, 2649 and was used to indicate status of 2650 interface or hardware */ 2651 unsigned long status; 2652 2653 /* tables for dm */ 2654 struct dig_t dm_digtable; 2655 struct ps_t dm_pstable; 2656 2657 u32 reg_874; 2658 u32 reg_c70; 2659 u32 reg_85c; 2660 u32 reg_a74; 2661 bool reg_init; /* true if regs saved */ 2662 bool bt_operation_on; 2663 __le32 *usb_data; 2664 int usb_data_index; 2665 bool initialized; 2666 bool enter_ps; /* true when entering PS */ 2667 u8 rate_mask[5]; 2668 2669 /* intel Proximity, should be alloc mem 2670 * in intel Proximity module and can only 2671 * be used in intel Proximity mode 2672 */ 2673 struct proxim proximity; 2674 2675 /*for bt coexist use*/ 2676 struct bt_coexist_info btcoexist; 2677 2678 /* separate 92ee from other ICs, 2679 * 92ee use new trx flow. 2680 */ 2681 bool use_new_trx_flow; 2682 2683 #ifdef CONFIG_PM 2684 struct wiphy_wowlan_support wowlan; 2685 #endif 2686 /*This must be the last item so 2687 that it points to the data allocated 2688 beyond this structure like: 2689 rtl_pci_priv or rtl_usb_priv */ 2690 u8 priv[0] __aligned(sizeof(void *)); 2691 }; 2692 2693 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2694 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2695 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2696 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2697 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2698 2699 2700 /*************************************** 2701 Bluetooth Co-existence Related 2702 ****************************************/ 2703 2704 enum bt_ant_num { 2705 ANT_X2 = 0, 2706 ANT_X1 = 1, 2707 }; 2708 2709 enum bt_co_type { 2710 BT_2WIRE = 0, 2711 BT_ISSC_3WIRE = 1, 2712 BT_ACCEL = 2, 2713 BT_CSR_BC4 = 3, 2714 BT_CSR_BC8 = 4, 2715 BT_RTL8756 = 5, 2716 BT_RTL8723A = 6, 2717 BT_RTL8821A = 7, 2718 BT_RTL8723B = 8, 2719 BT_RTL8192E = 9, 2720 BT_RTL8812A = 11, 2721 }; 2722 2723 enum bt_total_ant_num { 2724 ANT_TOTAL_X2 = 0, 2725 ANT_TOTAL_X1 = 1 2726 }; 2727 2728 enum bt_cur_state { 2729 BT_OFF = 0, 2730 BT_ON = 1, 2731 }; 2732 2733 enum bt_service_type { 2734 BT_SCO = 0, 2735 BT_A2DP = 1, 2736 BT_HID = 2, 2737 BT_HID_IDLE = 3, 2738 BT_SCAN = 4, 2739 BT_IDLE = 5, 2740 BT_OTHER_ACTION = 6, 2741 BT_BUSY = 7, 2742 BT_OTHERBUSY = 8, 2743 BT_PAN = 9, 2744 }; 2745 2746 enum bt_radio_shared { 2747 BT_RADIO_SHARED = 0, 2748 BT_RADIO_INDIVIDUAL = 1, 2749 }; 2750 2751 2752 /**************************************** 2753 mem access macro define start 2754 Call endian free function when 2755 1. Read/write packet content. 2756 2. Before write integer to IO. 2757 3. After read integer from IO. 2758 ****************************************/ 2759 /* Convert little data endian to host ordering */ 2760 #define EF1BYTE(_val) \ 2761 ((u8)(_val)) 2762 #define EF2BYTE(_val) \ 2763 (le16_to_cpu(_val)) 2764 #define EF4BYTE(_val) \ 2765 (le32_to_cpu(_val)) 2766 2767 /* Read data from memory */ 2768 #define READEF1BYTE(_ptr) \ 2769 EF1BYTE(*((u8 *)(_ptr))) 2770 /* Read le16 data from memory and convert to host ordering */ 2771 #define READEF2BYTE(_ptr) \ 2772 EF2BYTE(*(_ptr)) 2773 #define READEF4BYTE(_ptr) \ 2774 EF4BYTE(*(_ptr)) 2775 2776 /* Create a bit mask 2777 * Examples: 2778 * BIT_LEN_MASK_32(0) => 0x00000000 2779 * BIT_LEN_MASK_32(1) => 0x00000001 2780 * BIT_LEN_MASK_32(2) => 0x00000003 2781 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2782 */ 2783 #define BIT_LEN_MASK_32(__bitlen) \ 2784 (0xFFFFFFFF >> (32 - (__bitlen))) 2785 #define BIT_LEN_MASK_16(__bitlen) \ 2786 (0xFFFF >> (16 - (__bitlen))) 2787 #define BIT_LEN_MASK_8(__bitlen) \ 2788 (0xFF >> (8 - (__bitlen))) 2789 2790 /* Create an offset bit mask 2791 * Examples: 2792 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2793 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2794 */ 2795 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2796 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2797 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2798 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2799 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2800 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2801 2802 /*Description: 2803 * Return 4-byte value in host byte ordering from 2804 * 4-byte pointer in little-endian system. 2805 */ 2806 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2807 (EF4BYTE(*((__le32 *)(__pstart)))) 2808 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2809 (EF2BYTE(*((__le16 *)(__pstart)))) 2810 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2811 (EF1BYTE(*((u8 *)(__pstart)))) 2812 2813 /*Description: 2814 Translate subfield (continuous bits in little-endian) of 4-byte 2815 value to host byte ordering.*/ 2816 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2817 ( \ 2818 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2819 BIT_LEN_MASK_32(__bitlen) \ 2820 ) 2821 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2822 ( \ 2823 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2824 BIT_LEN_MASK_16(__bitlen) \ 2825 ) 2826 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2827 ( \ 2828 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2829 BIT_LEN_MASK_8(__bitlen) \ 2830 ) 2831 2832 /* Description: 2833 * Mask subfield (continuous bits in little-endian) of 4-byte value 2834 * and return the result in 4-byte value in host byte ordering. 2835 */ 2836 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2837 ( \ 2838 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2839 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2840 ) 2841 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2842 ( \ 2843 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2844 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2845 ) 2846 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2847 ( \ 2848 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2849 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2850 ) 2851 2852 /* Description: 2853 * Set subfield of little-endian 4-byte value to specified value. 2854 */ 2855 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2856 *((__le32 *)(__pstart)) = \ 2857 cpu_to_le32( \ 2858 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2859 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2860 ); 2861 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2862 *((__le16 *)(__pstart)) = \ 2863 cpu_to_le16( \ 2864 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2865 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2866 ); 2867 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2868 *((u8 *)(__pstart)) = EF1BYTE \ 2869 ( \ 2870 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2871 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2872 ); 2873 2874 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2875 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2876 2877 /**************************************** 2878 mem access macro define end 2879 ****************************************/ 2880 2881 #define byte(x, n) ((x >> (8 * n)) & 0xff) 2882 2883 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 2884 #define RTL_WATCH_DOG_TIME 2000 2885 #define MSECS(t) msecs_to_jiffies(t) 2886 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 2887 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 2888 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 2889 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 2890 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 2891 2892 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 2893 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 2894 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 2895 /*NIC halt, re-initialize hw parameters*/ 2896 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 2897 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 2898 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 2899 /*Always enable ASPM and Clock Req in initialization.*/ 2900 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 2901 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 2902 #define RT_PS_LEVEL_ASPM BIT(7) 2903 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 2904 #define RT_RF_LPS_DISALBE_2R BIT(30) 2905 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 2906 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 2907 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 2908 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 2909 (ppsc->cur_ps_level &= (~(_ps_flg))) 2910 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 2911 (ppsc->cur_ps_level |= _ps_flg) 2912 2913 #define container_of_dwork_rtl(x, y, z) \ 2914 container_of(to_delayed_work(x), y, z) 2915 2916 #define FILL_OCTET_STRING(_os, _octet, _len) \ 2917 (_os).octet = (u8 *)(_octet); \ 2918 (_os).length = (_len); 2919 2920 #define CP_MACADDR(des, src) \ 2921 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 2922 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2923 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2924 2925 #define LDPC_HT_ENABLE_RX BIT(0) 2926 #define LDPC_HT_ENABLE_TX BIT(1) 2927 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 2928 #define LDPC_HT_CAP_TX BIT(3) 2929 2930 #define STBC_HT_ENABLE_RX BIT(0) 2931 #define STBC_HT_ENABLE_TX BIT(1) 2932 #define STBC_HT_TEST_TX_ENABLE BIT(2) 2933 #define STBC_HT_CAP_TX BIT(3) 2934 2935 #define LDPC_VHT_ENABLE_RX BIT(0) 2936 #define LDPC_VHT_ENABLE_TX BIT(1) 2937 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 2938 #define LDPC_VHT_CAP_TX BIT(3) 2939 2940 #define STBC_VHT_ENABLE_RX BIT(0) 2941 #define STBC_VHT_ENABLE_TX BIT(1) 2942 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 2943 #define STBC_VHT_CAP_TX BIT(3) 2944 2945 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 2946 2947 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 2948 2949 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 2950 { 2951 return rtlpriv->io.read8_sync(rtlpriv, addr); 2952 } 2953 2954 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 2955 { 2956 return rtlpriv->io.read16_sync(rtlpriv, addr); 2957 } 2958 2959 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 2960 { 2961 return rtlpriv->io.read32_sync(rtlpriv, addr); 2962 } 2963 2964 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 2965 { 2966 rtlpriv->io.write8_async(rtlpriv, addr, val8); 2967 2968 if (rtlpriv->cfg->write_readback) 2969 rtlpriv->io.read8_sync(rtlpriv, addr); 2970 } 2971 2972 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw, 2973 u32 addr, u32 val8) 2974 { 2975 struct rtl_priv *rtlpriv = rtl_priv(hw); 2976 2977 rtl_write_byte(rtlpriv, addr, (u8)val8); 2978 } 2979 2980 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 2981 { 2982 rtlpriv->io.write16_async(rtlpriv, addr, val16); 2983 2984 if (rtlpriv->cfg->write_readback) 2985 rtlpriv->io.read16_sync(rtlpriv, addr); 2986 } 2987 2988 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 2989 u32 addr, u32 val32) 2990 { 2991 rtlpriv->io.write32_async(rtlpriv, addr, val32); 2992 2993 if (rtlpriv->cfg->write_readback) 2994 rtlpriv->io.read32_sync(rtlpriv, addr); 2995 } 2996 2997 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 2998 u32 regaddr, u32 bitmask) 2999 { 3000 struct rtl_priv *rtlpriv = hw->priv; 3001 3002 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 3003 } 3004 3005 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 3006 u32 bitmask, u32 data) 3007 { 3008 struct rtl_priv *rtlpriv = hw->priv; 3009 3010 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 3011 } 3012 3013 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw, 3014 u32 regaddr, u32 data) 3015 { 3016 rtl_set_bbreg(hw, regaddr, 0xffffffff, data); 3017 } 3018 3019 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 3020 enum radio_path rfpath, u32 regaddr, 3021 u32 bitmask) 3022 { 3023 struct rtl_priv *rtlpriv = hw->priv; 3024 3025 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 3026 } 3027 3028 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 3029 enum radio_path rfpath, u32 regaddr, 3030 u32 bitmask, u32 data) 3031 { 3032 struct rtl_priv *rtlpriv = hw->priv; 3033 3034 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 3035 } 3036 3037 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 3038 { 3039 return (_HAL_STATE_STOP == rtlhal->state); 3040 } 3041 3042 static inline void set_hal_start(struct rtl_hal *rtlhal) 3043 { 3044 rtlhal->state = _HAL_STATE_START; 3045 } 3046 3047 static inline void set_hal_stop(struct rtl_hal *rtlhal) 3048 { 3049 rtlhal->state = _HAL_STATE_STOP; 3050 } 3051 3052 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3053 { 3054 return rtlphy->rf_type; 3055 } 3056 3057 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3058 { 3059 return (struct ieee80211_hdr *)(skb->data); 3060 } 3061 3062 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3063 { 3064 return rtl_get_hdr(skb)->frame_control; 3065 } 3066 3067 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3068 { 3069 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3070 } 3071 3072 static inline u16 rtl_get_tid(struct sk_buff *skb) 3073 { 3074 return rtl_get_tid_h(rtl_get_hdr(skb)); 3075 } 3076 3077 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3078 struct ieee80211_vif *vif, 3079 const u8 *bssid) 3080 { 3081 return ieee80211_find_sta(vif, bssid); 3082 } 3083 3084 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3085 u8 *mac_addr) 3086 { 3087 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3088 return ieee80211_find_sta(mac->vif, mac_addr); 3089 } 3090 3091 #endif 3092