1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL_WIFI_H__ 27 #define __RTL_WIFI_H__ 28 29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 30 31 #include <linux/sched.h> 32 #include <linux/firmware.h> 33 #include <linux/etherdevice.h> 34 #include <linux/vmalloc.h> 35 #include <linux/usb.h> 36 #include <net/mac80211.h> 37 #include <linux/completion.h> 38 #include "debug.h" 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKHWORD 0xffff0000 45 #define MASKLWORD 0x0000ffff 46 #define MASKDWORD 0xffffffff 47 #define MASK12BITS 0xfff 48 #define MASKH4BITS 0xf0000000 49 #define MASKOFDM_D 0xffc00000 50 #define MASKCCK 0x3f3f3f3f 51 52 #define MASK4BITS 0x0f 53 #define MASK20BITS 0xfffff 54 #define RFREG_OFFSET_MASK 0xfffff 55 56 #define MASKBYTE0 0xff 57 #define MASKBYTE1 0xff00 58 #define MASKBYTE2 0xff0000 59 #define MASKBYTE3 0xff000000 60 #define MASKHWORD 0xffff0000 61 #define MASKLWORD 0x0000ffff 62 #define MASKDWORD 0xffffffff 63 #define MASK12BITS 0xfff 64 #define MASKH4BITS 0xf0000000 65 #define MASKOFDM_D 0xffc00000 66 #define MASKCCK 0x3f3f3f3f 67 68 #define MASK4BITS 0x0f 69 #define MASK20BITS 0xfffff 70 #define RFREG_OFFSET_MASK 0xfffff 71 72 #define RF_CHANGE_BY_INIT 0 73 #define RF_CHANGE_BY_IPS BIT(28) 74 #define RF_CHANGE_BY_PS BIT(29) 75 #define RF_CHANGE_BY_HW BIT(30) 76 #define RF_CHANGE_BY_SW BIT(31) 77 78 #define IQK_ADDA_REG_NUM 16 79 #define IQK_MAC_REG_NUM 4 80 #define IQK_THRESHOLD 8 81 82 #define MAX_KEY_LEN 61 83 #define KEY_BUF_SIZE 5 84 85 /* QoS related. */ 86 /*aci: 0x00 Best Effort*/ 87 /*aci: 0x01 Background*/ 88 /*aci: 0x10 Video*/ 89 /*aci: 0x11 Voice*/ 90 /*Max: define total number.*/ 91 #define AC0_BE 0 92 #define AC1_BK 1 93 #define AC2_VI 2 94 #define AC3_VO 3 95 #define AC_MAX 4 96 #define QOS_QUEUE_NUM 4 97 #define RTL_MAC80211_NUM_QUEUE 5 98 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 99 #define RTL_USB_MAX_RX_COUNT 100 100 #define QBSS_LOAD_SIZE 5 101 #define MAX_WMMELE_LENGTH 64 102 103 #define TOTAL_CAM_ENTRY 32 104 105 /*slot time for 11g. */ 106 #define RTL_SLOT_TIME_9 9 107 #define RTL_SLOT_TIME_20 20 108 109 /*related to tcp/ip. */ 110 #define SNAP_SIZE 6 111 #define PROTOC_TYPE_SIZE 2 112 113 /*related with 802.11 frame*/ 114 #define MAC80211_3ADDR_LEN 24 115 #define MAC80211_4ADDR_LEN 30 116 117 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ 118 #define CHANNEL_MAX_NUMBER_2G 14 119 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to 120 *"phy_GetChnlGroup8812A" and 121 * "Hal_ReadTxPowerInfo8812A" 122 */ 123 #define CHANNEL_MAX_NUMBER_5G_80M 7 124 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ 125 #define MAX_PG_GROUP 13 126 #define CHANNEL_GROUP_MAX_2G 3 127 #define CHANNEL_GROUP_IDX_5GL 3 128 #define CHANNEL_GROUP_IDX_5GM 6 129 #define CHANNEL_GROUP_IDX_5GH 9 130 #define CHANNEL_GROUP_MAX_5G 9 131 #define CHANNEL_MAX_NUMBER_2G 14 132 #define AVG_THERMAL_NUM 8 133 #define AVG_THERMAL_NUM_88E 4 134 #define AVG_THERMAL_NUM_8723BE 4 135 #define MAX_TID_COUNT 9 136 137 /* for early mode */ 138 #define FCS_LEN 4 139 #define EM_HDR_LEN 8 140 141 enum rtl8192c_h2c_cmd { 142 H2C_AP_OFFLOAD = 0, 143 H2C_SETPWRMODE = 1, 144 H2C_JOINBSSRPT = 2, 145 H2C_RSVDPAGE = 3, 146 H2C_RSSI_REPORT = 5, 147 H2C_RA_MASK = 6, 148 H2C_MACID_PS_MODE = 7, 149 H2C_P2P_PS_OFFLOAD = 8, 150 H2C_MAC_MODE_SEL = 9, 151 H2C_PWRM = 15, 152 H2C_P2P_PS_CTW_CMD = 24, 153 MAX_H2CCMD 154 }; 155 156 #define MAX_TX_COUNT 4 157 #define MAX_REGULATION_NUM 4 158 #define MAX_RF_PATH_NUM 4 159 #define MAX_RATE_SECTION_NUM 6 160 #define MAX_2_4G_BANDWIDTH_NUM 4 161 #define MAX_5G_BANDWIDTH_NUM 4 162 #define MAX_RF_PATH 4 163 #define MAX_CHNL_GROUP_24G 6 164 #define MAX_CHNL_GROUP_5G 14 165 166 #define TX_PWR_BY_RATE_NUM_BAND 2 167 #define TX_PWR_BY_RATE_NUM_RF 4 168 #define TX_PWR_BY_RATE_NUM_SECTION 12 169 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 170 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 171 172 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 173 174 #define DEL_SW_IDX_SZ 30 175 #define BAND_NUM 3 176 177 /* For now, it's just for 8192ee 178 * but not OK yet, keep it 0 179 */ 180 #define DMA_IS_64BIT 0 181 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ 182 183 enum rf_tx_num { 184 RF_1TX = 0, 185 RF_2TX, 186 RF_MAX_TX_NUM, 187 RF_TX_NUM_NONIMPLEMENT, 188 }; 189 190 #define PACKET_NORMAL 0 191 #define PACKET_DHCP 1 192 #define PACKET_ARP 2 193 #define PACKET_EAPOL 3 194 195 #define MAX_SUPPORT_WOL_PATTERN_NUM 16 196 #define RSVD_WOL_PATTERN_NUM 1 197 #define WKFMCAM_ADDR_NUM 6 198 #define WKFMCAM_SIZE 24 199 200 #define MAX_WOL_BIT_MASK_SIZE 16 201 /* MIN LEN keeps 13 here */ 202 #define MIN_WOL_PATTERN_SIZE 13 203 #define MAX_WOL_PATTERN_SIZE 128 204 205 #define WAKE_ON_MAGIC_PACKET BIT(0) 206 #define WAKE_ON_PATTERN_MATCH BIT(1) 207 208 #define WOL_REASON_PTK_UPDATE BIT(0) 209 #define WOL_REASON_GTK_UPDATE BIT(1) 210 #define WOL_REASON_DISASSOC BIT(2) 211 #define WOL_REASON_DEAUTH BIT(3) 212 #define WOL_REASON_AP_LOST BIT(4) 213 #define WOL_REASON_MAGIC_PKT BIT(5) 214 #define WOL_REASON_UNICAST_PKT BIT(6) 215 #define WOL_REASON_PATTERN_PKT BIT(7) 216 #define WOL_REASON_RTD3_SSID_MATCH BIT(8) 217 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9) 218 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10) 219 220 struct rtlwifi_firmware_header { 221 __le16 signature; 222 u8 category; 223 u8 function; 224 __le16 version; 225 u8 subversion; 226 u8 rsvd1; 227 u8 month; 228 u8 date; 229 u8 hour; 230 u8 minute; 231 __le16 ramcodeSize; 232 __le16 rsvd2; 233 __le32 svnindex; 234 __le32 rsvd3; 235 __le32 rsvd4; 236 __le32 rsvd5; 237 }; 238 239 struct txpower_info_2g { 240 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 241 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 242 /*If only one tx, only BW20 and OFDM are used.*/ 243 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 245 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 246 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 247 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 248 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 249 }; 250 251 struct txpower_info_5g { 252 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; 253 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ 254 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; 255 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; 256 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; 257 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; 258 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; 259 }; 260 261 enum rate_section { 262 CCK = 0, 263 OFDM, 264 HT_MCS0_MCS7, 265 HT_MCS8_MCS15, 266 VHT_1SSMCS0_1SSMCS9, 267 VHT_2SSMCS0_2SSMCS9, 268 }; 269 270 enum intf_type { 271 INTF_PCI = 0, 272 INTF_USB = 1, 273 }; 274 275 enum radio_path { 276 RF90_PATH_A = 0, 277 RF90_PATH_B = 1, 278 RF90_PATH_C = 2, 279 RF90_PATH_D = 3, 280 }; 281 282 enum regulation_txpwr_lmt { 283 TXPWR_LMT_FCC = 0, 284 TXPWR_LMT_MKK = 1, 285 TXPWR_LMT_ETSI = 2, 286 TXPWR_LMT_WW = 3, 287 288 TXPWR_LMT_MAX_REGULATION_NUM = 4 289 }; 290 291 enum rt_eeprom_type { 292 EEPROM_93C46, 293 EEPROM_93C56, 294 EEPROM_BOOT_EFUSE, 295 }; 296 297 enum ttl_status { 298 RTL_STATUS_INTERFACE_START = 0, 299 }; 300 301 enum hardware_type { 302 HARDWARE_TYPE_RTL8192E, 303 HARDWARE_TYPE_RTL8192U, 304 HARDWARE_TYPE_RTL8192SE, 305 HARDWARE_TYPE_RTL8192SU, 306 HARDWARE_TYPE_RTL8192CE, 307 HARDWARE_TYPE_RTL8192CU, 308 HARDWARE_TYPE_RTL8192DE, 309 HARDWARE_TYPE_RTL8192DU, 310 HARDWARE_TYPE_RTL8723AE, 311 HARDWARE_TYPE_RTL8723U, 312 HARDWARE_TYPE_RTL8188EE, 313 HARDWARE_TYPE_RTL8723BE, 314 HARDWARE_TYPE_RTL8192EE, 315 HARDWARE_TYPE_RTL8821AE, 316 HARDWARE_TYPE_RTL8812AE, 317 318 /* keep it last */ 319 HARDWARE_TYPE_NUM 320 }; 321 322 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \ 323 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) 324 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \ 325 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 326 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \ 327 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) 328 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \ 329 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) 330 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \ 331 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) 332 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \ 333 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) 334 #define IS_HARDWARE_TYPE_8723E(rtlhal) \ 335 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) 336 #define IS_HARDWARE_TYPE_8723U(rtlhal) \ 337 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) 338 #define IS_HARDWARE_TYPE_8192S(rtlhal) \ 339 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) 340 #define IS_HARDWARE_TYPE_8192C(rtlhal) \ 341 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) 342 #define IS_HARDWARE_TYPE_8192D(rtlhal) \ 343 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) 344 #define IS_HARDWARE_TYPE_8723(rtlhal) \ 345 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) 346 347 #define RX_HAL_IS_CCK_RATE(rxmcs) \ 348 ((rxmcs) == DESC_RATE1M || \ 349 (rxmcs) == DESC_RATE2M || \ 350 (rxmcs) == DESC_RATE5_5M || \ 351 (rxmcs) == DESC_RATE11M) 352 353 enum scan_operation_backup_opt { 354 SCAN_OPT_BACKUP = 0, 355 SCAN_OPT_BACKUP_BAND0 = 0, 356 SCAN_OPT_BACKUP_BAND1, 357 SCAN_OPT_RESTORE, 358 SCAN_OPT_MAX 359 }; 360 361 /*RF state.*/ 362 enum rf_pwrstate { 363 ERFON, 364 ERFSLEEP, 365 ERFOFF 366 }; 367 368 struct bb_reg_def { 369 u32 rfintfs; 370 u32 rfintfi; 371 u32 rfintfo; 372 u32 rfintfe; 373 u32 rf3wire_offset; 374 u32 rflssi_select; 375 u32 rftxgain_stage; 376 u32 rfhssi_para1; 377 u32 rfhssi_para2; 378 u32 rfsw_ctrl; 379 u32 rfagc_control1; 380 u32 rfagc_control2; 381 u32 rfrxiq_imbal; 382 u32 rfrx_afe; 383 u32 rftxiq_imbal; 384 u32 rftx_afe; 385 u32 rf_rb; /* rflssi_readback */ 386 u32 rf_rbpi; /* rflssi_readbackpi */ 387 }; 388 389 enum io_type { 390 IO_CMD_PAUSE_DM_BY_SCAN = 0, 391 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, 392 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, 393 IO_CMD_RESUME_DM_BY_SCAN = 2, 394 }; 395 396 enum hw_variables { 397 HW_VAR_ETHER_ADDR = 0x0, 398 HW_VAR_MULTICAST_REG = 0x1, 399 HW_VAR_BASIC_RATE = 0x2, 400 HW_VAR_BSSID = 0x3, 401 HW_VAR_MEDIA_STATUS= 0x4, 402 HW_VAR_SECURITY_CONF= 0x5, 403 HW_VAR_BEACON_INTERVAL = 0x6, 404 HW_VAR_ATIM_WINDOW = 0x7, 405 HW_VAR_LISTEN_INTERVAL = 0x8, 406 HW_VAR_CS_COUNTER = 0x9, 407 HW_VAR_DEFAULTKEY0 = 0xa, 408 HW_VAR_DEFAULTKEY1 = 0xb, 409 HW_VAR_DEFAULTKEY2 = 0xc, 410 HW_VAR_DEFAULTKEY3 = 0xd, 411 HW_VAR_SIFS = 0xe, 412 HW_VAR_R2T_SIFS = 0xf, 413 HW_VAR_DIFS = 0x10, 414 HW_VAR_EIFS = 0x11, 415 HW_VAR_SLOT_TIME = 0x12, 416 HW_VAR_ACK_PREAMBLE = 0x13, 417 HW_VAR_CW_CONFIG = 0x14, 418 HW_VAR_CW_VALUES = 0x15, 419 HW_VAR_RATE_FALLBACK_CONTROL= 0x16, 420 HW_VAR_CONTENTION_WINDOW = 0x17, 421 HW_VAR_RETRY_COUNT = 0x18, 422 HW_VAR_TR_SWITCH = 0x19, 423 HW_VAR_COMMAND = 0x1a, 424 HW_VAR_WPA_CONFIG = 0x1b, 425 HW_VAR_AMPDU_MIN_SPACE = 0x1c, 426 HW_VAR_SHORTGI_DENSITY = 0x1d, 427 HW_VAR_AMPDU_FACTOR = 0x1e, 428 HW_VAR_MCS_RATE_AVAILABLE = 0x1f, 429 HW_VAR_AC_PARAM = 0x20, 430 HW_VAR_ACM_CTRL = 0x21, 431 HW_VAR_DIS_Req_Qsize = 0x22, 432 HW_VAR_CCX_CHNL_LOAD = 0x23, 433 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24, 434 HW_VAR_CCX_CLM_NHM = 0x25, 435 HW_VAR_TxOPLimit = 0x26, 436 HW_VAR_TURBO_MODE = 0x27, 437 HW_VAR_RF_STATE = 0x28, 438 HW_VAR_RF_OFF_BY_HW = 0x29, 439 HW_VAR_BUS_SPEED = 0x2a, 440 HW_VAR_SET_DEV_POWER = 0x2b, 441 442 HW_VAR_RCR = 0x2c, 443 HW_VAR_RATR_0 = 0x2d, 444 HW_VAR_RRSR = 0x2e, 445 HW_VAR_CPU_RST = 0x2f, 446 HW_VAR_CHECK_BSSID = 0x30, 447 HW_VAR_LBK_MODE = 0x31, 448 HW_VAR_AES_11N_FIX = 0x32, 449 HW_VAR_USB_RX_AGGR = 0x33, 450 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34, 451 HW_VAR_RETRY_LIMIT = 0x35, 452 HW_VAR_INIT_TX_RATE = 0x36, 453 HW_VAR_TX_RATE_REG = 0x37, 454 HW_VAR_EFUSE_USAGE = 0x38, 455 HW_VAR_EFUSE_BYTES = 0x39, 456 HW_VAR_AUTOLOAD_STATUS = 0x3a, 457 HW_VAR_RF_2R_DISABLE = 0x3b, 458 HW_VAR_SET_RPWM = 0x3c, 459 HW_VAR_H2C_FW_PWRMODE = 0x3d, 460 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e, 461 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f, 462 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40, 463 HW_VAR_FW_PSMODE_STATUS = 0x41, 464 HW_VAR_INIT_RTS_RATE = 0x42, 465 HW_VAR_RESUME_CLK_ON = 0x43, 466 HW_VAR_FW_LPS_ACTION = 0x44, 467 HW_VAR_1X1_RECV_COMBINE = 0x45, 468 HW_VAR_STOP_SEND_BEACON = 0x46, 469 HW_VAR_TSF_TIMER = 0x47, 470 HW_VAR_IO_CMD = 0x48, 471 472 HW_VAR_RF_RECOVERY = 0x49, 473 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a, 474 HW_VAR_WF_MASK = 0x4b, 475 HW_VAR_WF_CRC = 0x4c, 476 HW_VAR_WF_IS_MAC_ADDR = 0x4d, 477 HW_VAR_H2C_FW_OFFLOAD = 0x4e, 478 HW_VAR_RESET_WFCRC = 0x4f, 479 480 HW_VAR_HANDLE_FW_C2H = 0x50, 481 HW_VAR_DL_FW_RSVD_PAGE = 0x51, 482 HW_VAR_AID = 0x52, 483 HW_VAR_HW_SEQ_ENABLE = 0x53, 484 HW_VAR_CORRECT_TSF = 0x54, 485 HW_VAR_BCN_VALID = 0x55, 486 HW_VAR_FWLPS_RF_ON = 0x56, 487 HW_VAR_DUAL_TSF_RST = 0x57, 488 HW_VAR_SWITCH_EPHY_WoWLAN = 0x58, 489 HW_VAR_INT_MIGRATION = 0x59, 490 HW_VAR_INT_AC = 0x5a, 491 HW_VAR_RF_TIMING = 0x5b, 492 493 HAL_DEF_WOWLAN = 0x5c, 494 HW_VAR_MRC = 0x5d, 495 HW_VAR_KEEP_ALIVE = 0x5e, 496 HW_VAR_NAV_UPPER = 0x5f, 497 498 HW_VAR_MGT_FILTER = 0x60, 499 HW_VAR_CTRL_FILTER = 0x61, 500 HW_VAR_DATA_FILTER = 0x62, 501 }; 502 503 enum rt_media_status { 504 RT_MEDIA_DISCONNECT = 0, 505 RT_MEDIA_CONNECT = 1 506 }; 507 508 enum rt_oem_id { 509 RT_CID_DEFAULT = 0, 510 RT_CID_8187_ALPHA0 = 1, 511 RT_CID_8187_SERCOMM_PS = 2, 512 RT_CID_8187_HW_LED = 3, 513 RT_CID_8187_NETGEAR = 4, 514 RT_CID_WHQL = 5, 515 RT_CID_819X_CAMEO = 6, 516 RT_CID_819X_RUNTOP = 7, 517 RT_CID_819X_SENAO = 8, 518 RT_CID_TOSHIBA = 9, 519 RT_CID_819X_NETCORE = 10, 520 RT_CID_NETTRONIX = 11, 521 RT_CID_DLINK = 12, 522 RT_CID_PRONET = 13, 523 RT_CID_COREGA = 14, 524 RT_CID_819X_ALPHA = 15, 525 RT_CID_819X_SITECOM = 16, 526 RT_CID_CCX = 17, 527 RT_CID_819X_LENOVO = 18, 528 RT_CID_819X_QMI = 19, 529 RT_CID_819X_EDIMAX_BELKIN = 20, 530 RT_CID_819X_SERCOMM_BELKIN = 21, 531 RT_CID_819X_CAMEO1 = 22, 532 RT_CID_819X_MSI = 23, 533 RT_CID_819X_ACER = 24, 534 RT_CID_819X_HP = 27, 535 RT_CID_819X_CLEVO = 28, 536 RT_CID_819X_ARCADYAN_BELKIN = 29, 537 RT_CID_819X_SAMSUNG = 30, 538 RT_CID_819X_WNC_COREGA = 31, 539 RT_CID_819X_FOXCOON = 32, 540 RT_CID_819X_DELL = 33, 541 RT_CID_819X_PRONETS = 34, 542 RT_CID_819X_EDIMAX_ASUS = 35, 543 RT_CID_NETGEAR = 36, 544 RT_CID_PLANEX = 37, 545 RT_CID_CC_C = 38, 546 }; 547 548 enum hw_descs { 549 HW_DESC_OWN, 550 HW_DESC_RXOWN, 551 HW_DESC_TX_NEXTDESC_ADDR, 552 HW_DESC_TXBUFF_ADDR, 553 HW_DESC_RXBUFF_ADDR, 554 HW_DESC_RXPKT_LEN, 555 HW_DESC_RXERO, 556 HW_DESC_RX_PREPARE, 557 }; 558 559 enum prime_sc { 560 PRIME_CHNL_OFFSET_DONT_CARE = 0, 561 PRIME_CHNL_OFFSET_LOWER = 1, 562 PRIME_CHNL_OFFSET_UPPER = 2, 563 }; 564 565 enum rf_type { 566 RF_1T1R = 0, 567 RF_1T2R = 1, 568 RF_2T2R = 2, 569 RF_2T2R_GREEN = 3, 570 }; 571 572 enum ht_channel_width { 573 HT_CHANNEL_WIDTH_20 = 0, 574 HT_CHANNEL_WIDTH_20_40 = 1, 575 HT_CHANNEL_WIDTH_80 = 2, 576 }; 577 578 /* Ref: 802.11i sepc D10.0 7.3.2.25.1 579 Cipher Suites Encryption Algorithms */ 580 enum rt_enc_alg { 581 NO_ENCRYPTION = 0, 582 WEP40_ENCRYPTION = 1, 583 TKIP_ENCRYPTION = 2, 584 RSERVED_ENCRYPTION = 3, 585 AESCCMP_ENCRYPTION = 4, 586 WEP104_ENCRYPTION = 5, 587 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ 588 }; 589 590 enum rtl_hal_state { 591 _HAL_STATE_STOP = 0, 592 _HAL_STATE_START = 1, 593 }; 594 595 enum rtl_desc92_rate { 596 DESC_RATE1M = 0x00, 597 DESC_RATE2M = 0x01, 598 DESC_RATE5_5M = 0x02, 599 DESC_RATE11M = 0x03, 600 601 DESC_RATE6M = 0x04, 602 DESC_RATE9M = 0x05, 603 DESC_RATE12M = 0x06, 604 DESC_RATE18M = 0x07, 605 DESC_RATE24M = 0x08, 606 DESC_RATE36M = 0x09, 607 DESC_RATE48M = 0x0a, 608 DESC_RATE54M = 0x0b, 609 610 DESC_RATEMCS0 = 0x0c, 611 DESC_RATEMCS1 = 0x0d, 612 DESC_RATEMCS2 = 0x0e, 613 DESC_RATEMCS3 = 0x0f, 614 DESC_RATEMCS4 = 0x10, 615 DESC_RATEMCS5 = 0x11, 616 DESC_RATEMCS6 = 0x12, 617 DESC_RATEMCS7 = 0x13, 618 DESC_RATEMCS8 = 0x14, 619 DESC_RATEMCS9 = 0x15, 620 DESC_RATEMCS10 = 0x16, 621 DESC_RATEMCS11 = 0x17, 622 DESC_RATEMCS12 = 0x18, 623 DESC_RATEMCS13 = 0x19, 624 DESC_RATEMCS14 = 0x1a, 625 DESC_RATEMCS15 = 0x1b, 626 DESC_RATEMCS15_SG = 0x1c, 627 DESC_RATEMCS32 = 0x20, 628 629 DESC_RATEVHT1SS_MCS0 = 0x2c, 630 DESC_RATEVHT1SS_MCS1 = 0x2d, 631 DESC_RATEVHT1SS_MCS2 = 0x2e, 632 DESC_RATEVHT1SS_MCS3 = 0x2f, 633 DESC_RATEVHT1SS_MCS4 = 0x30, 634 DESC_RATEVHT1SS_MCS5 = 0x31, 635 DESC_RATEVHT1SS_MCS6 = 0x32, 636 DESC_RATEVHT1SS_MCS7 = 0x33, 637 DESC_RATEVHT1SS_MCS8 = 0x34, 638 DESC_RATEVHT1SS_MCS9 = 0x35, 639 DESC_RATEVHT2SS_MCS0 = 0x36, 640 DESC_RATEVHT2SS_MCS1 = 0x37, 641 DESC_RATEVHT2SS_MCS2 = 0x38, 642 DESC_RATEVHT2SS_MCS3 = 0x39, 643 DESC_RATEVHT2SS_MCS4 = 0x3a, 644 DESC_RATEVHT2SS_MCS5 = 0x3b, 645 DESC_RATEVHT2SS_MCS6 = 0x3c, 646 DESC_RATEVHT2SS_MCS7 = 0x3d, 647 DESC_RATEVHT2SS_MCS8 = 0x3e, 648 DESC_RATEVHT2SS_MCS9 = 0x3f, 649 }; 650 651 enum rtl_var_map { 652 /*reg map */ 653 SYS_ISO_CTRL = 0, 654 SYS_FUNC_EN, 655 SYS_CLK, 656 MAC_RCR_AM, 657 MAC_RCR_AB, 658 MAC_RCR_ACRC32, 659 MAC_RCR_ACF, 660 MAC_RCR_AAP, 661 MAC_HIMR, 662 MAC_HIMRE, 663 MAC_HSISR, 664 665 /*efuse map */ 666 EFUSE_TEST, 667 EFUSE_CTRL, 668 EFUSE_CLK, 669 EFUSE_CLK_CTRL, 670 EFUSE_PWC_EV12V, 671 EFUSE_FEN_ELDR, 672 EFUSE_LOADER_CLK_EN, 673 EFUSE_ANA8M, 674 EFUSE_HWSET_MAX_SIZE, 675 EFUSE_MAX_SECTION_MAP, 676 EFUSE_REAL_CONTENT_SIZE, 677 EFUSE_OOB_PROTECT_BYTES_LEN, 678 EFUSE_ACCESS, 679 680 /*CAM map */ 681 RWCAM, 682 WCAMI, 683 RCAMO, 684 CAMDBG, 685 SECR, 686 SEC_CAM_NONE, 687 SEC_CAM_WEP40, 688 SEC_CAM_TKIP, 689 SEC_CAM_AES, 690 SEC_CAM_WEP104, 691 692 /*IMR map */ 693 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ 694 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ 695 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ 696 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ 697 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ 698 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ 699 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ 700 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ 701 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ 702 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ 703 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ 704 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ 705 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ 706 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ 707 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ 708 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ 709 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ 710 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ 711 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ 712 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ 713 RTL_IMR_RDU, /*Receive Descriptor Unavailable */ 714 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 715 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 716 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 717 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ 718 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 719 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 720 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 721 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ 722 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ 723 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 724 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 725 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 726 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/ 727 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | 728 * RTL_IMR_TBDER) */ 729 RTL_IMR_C2HCMD, /*fw interrupt*/ 730 731 /*CCK Rates, TxHT = 0 */ 732 RTL_RC_CCK_RATE1M, 733 RTL_RC_CCK_RATE2M, 734 RTL_RC_CCK_RATE5_5M, 735 RTL_RC_CCK_RATE11M, 736 737 /*OFDM Rates, TxHT = 0 */ 738 RTL_RC_OFDM_RATE6M, 739 RTL_RC_OFDM_RATE9M, 740 RTL_RC_OFDM_RATE12M, 741 RTL_RC_OFDM_RATE18M, 742 RTL_RC_OFDM_RATE24M, 743 RTL_RC_OFDM_RATE36M, 744 RTL_RC_OFDM_RATE48M, 745 RTL_RC_OFDM_RATE54M, 746 747 RTL_RC_HT_RATEMCS7, 748 RTL_RC_HT_RATEMCS15, 749 750 RTL_RC_VHT_RATE_1SS_MCS7, 751 RTL_RC_VHT_RATE_1SS_MCS8, 752 RTL_RC_VHT_RATE_1SS_MCS9, 753 RTL_RC_VHT_RATE_2SS_MCS7, 754 RTL_RC_VHT_RATE_2SS_MCS8, 755 RTL_RC_VHT_RATE_2SS_MCS9, 756 757 /*keep it last */ 758 RTL_VAR_MAP_MAX, 759 }; 760 761 /*Firmware PS mode for control LPS.*/ 762 enum _fw_ps_mode { 763 FW_PS_ACTIVE_MODE = 0, 764 FW_PS_MIN_MODE = 1, 765 FW_PS_MAX_MODE = 2, 766 FW_PS_DTIM_MODE = 3, 767 FW_PS_VOIP_MODE = 4, 768 FW_PS_UAPSD_WMM_MODE = 5, 769 FW_PS_UAPSD_MODE = 6, 770 FW_PS_IBSS_MODE = 7, 771 FW_PS_WWLAN_MODE = 8, 772 FW_PS_PM_Radio_Off = 9, 773 FW_PS_PM_Card_Disable = 10, 774 }; 775 776 enum rt_psmode { 777 EACTIVE, /*Active/Continuous access. */ 778 EMAXPS, /*Max power save mode. */ 779 EFASTPS, /*Fast power save mode. */ 780 EAUTOPS, /*Auto power save mode. */ 781 }; 782 783 /*LED related.*/ 784 enum led_ctl_mode { 785 LED_CTL_POWER_ON = 1, 786 LED_CTL_LINK = 2, 787 LED_CTL_NO_LINK = 3, 788 LED_CTL_TX = 4, 789 LED_CTL_RX = 5, 790 LED_CTL_SITE_SURVEY = 6, 791 LED_CTL_POWER_OFF = 7, 792 LED_CTL_START_TO_LINK = 8, 793 LED_CTL_START_WPS = 9, 794 LED_CTL_STOP_WPS = 10, 795 }; 796 797 enum rtl_led_pin { 798 LED_PIN_GPIO0, 799 LED_PIN_LED0, 800 LED_PIN_LED1, 801 LED_PIN_LED2 802 }; 803 804 /*QoS related.*/ 805 /*acm implementation method.*/ 806 enum acm_method { 807 eAcmWay0_SwAndHw = 0, 808 eAcmWay1_HW = 1, 809 EACMWAY2_SW = 2, 810 }; 811 812 enum macphy_mode { 813 SINGLEMAC_SINGLEPHY = 0, 814 DUALMAC_DUALPHY, 815 DUALMAC_SINGLEPHY, 816 }; 817 818 enum band_type { 819 BAND_ON_2_4G = 0, 820 BAND_ON_5G, 821 BAND_ON_BOTH, 822 BANDMAX 823 }; 824 825 /*aci/aifsn Field. 826 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 827 union aci_aifsn { 828 u8 char_data; 829 830 struct { 831 u8 aifsn:4; 832 u8 acm:1; 833 u8 aci:2; 834 u8 reserved:1; 835 } f; /* Field */ 836 }; 837 838 /*mlme related.*/ 839 enum wireless_mode { 840 WIRELESS_MODE_UNKNOWN = 0x00, 841 WIRELESS_MODE_A = 0x01, 842 WIRELESS_MODE_B = 0x02, 843 WIRELESS_MODE_G = 0x04, 844 WIRELESS_MODE_AUTO = 0x08, 845 WIRELESS_MODE_N_24G = 0x10, 846 WIRELESS_MODE_N_5G = 0x20, 847 WIRELESS_MODE_AC_5G = 0x40, 848 WIRELESS_MODE_AC_24G = 0x80, 849 WIRELESS_MODE_AC_ONLY = 0x100, 850 WIRELESS_MODE_MAX = 0x800 851 }; 852 853 #define IS_WIRELESS_MODE_A(wirelessmode) \ 854 (wirelessmode == WIRELESS_MODE_A) 855 #define IS_WIRELESS_MODE_B(wirelessmode) \ 856 (wirelessmode == WIRELESS_MODE_B) 857 #define IS_WIRELESS_MODE_G(wirelessmode) \ 858 (wirelessmode == WIRELESS_MODE_G) 859 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ 860 (wirelessmode == WIRELESS_MODE_N_24G) 861 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ 862 (wirelessmode == WIRELESS_MODE_N_5G) 863 864 enum ratr_table_mode { 865 RATR_INX_WIRELESS_NGB = 0, 866 RATR_INX_WIRELESS_NG = 1, 867 RATR_INX_WIRELESS_NB = 2, 868 RATR_INX_WIRELESS_N = 3, 869 RATR_INX_WIRELESS_GB = 4, 870 RATR_INX_WIRELESS_G = 5, 871 RATR_INX_WIRELESS_B = 6, 872 RATR_INX_WIRELESS_MC = 7, 873 RATR_INX_WIRELESS_A = 8, 874 RATR_INX_WIRELESS_AC_5N = 8, 875 RATR_INX_WIRELESS_AC_24N = 9, 876 }; 877 878 enum rtl_link_state { 879 MAC80211_NOLINK = 0, 880 MAC80211_LINKING = 1, 881 MAC80211_LINKED = 2, 882 MAC80211_LINKED_SCANNING = 3, 883 }; 884 885 enum act_category { 886 ACT_CAT_QOS = 1, 887 ACT_CAT_DLS = 2, 888 ACT_CAT_BA = 3, 889 ACT_CAT_HT = 7, 890 ACT_CAT_WMM = 17, 891 }; 892 893 enum ba_action { 894 ACT_ADDBAREQ = 0, 895 ACT_ADDBARSP = 1, 896 ACT_DELBA = 2, 897 }; 898 899 enum rt_polarity_ctl { 900 RT_POLARITY_LOW_ACT = 0, 901 RT_POLARITY_HIGH_ACT = 1, 902 }; 903 904 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */ 905 enum fw_wow_reason_v2 { 906 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01, 907 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02, 908 FW_WOW_V2_DISASSOC_EVENT = 0x04, 909 FW_WOW_V2_DEAUTH_EVENT = 0x08, 910 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10, 911 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21, 912 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22, 913 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23, 914 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24, 915 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30, 916 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31, 917 FW_WOW_V2_REASON_MAX = 0xff, 918 }; 919 920 enum wolpattern_type { 921 UNICAST_PATTERN = 0, 922 MULTICAST_PATTERN = 1, 923 BROADCAST_PATTERN = 2, 924 DONT_CARE_DA = 3, 925 UNKNOWN_TYPE = 4, 926 }; 927 928 enum package_type { 929 PACKAGE_DEFAULT, 930 PACKAGE_QFN68, 931 PACKAGE_TFBGA90, 932 PACKAGE_TFBGA80, 933 PACKAGE_TFBGA79 934 }; 935 936 struct octet_string { 937 u8 *octet; 938 u16 length; 939 }; 940 941 struct rtl_hdr_3addr { 942 __le16 frame_ctl; 943 __le16 duration_id; 944 u8 addr1[ETH_ALEN]; 945 u8 addr2[ETH_ALEN]; 946 u8 addr3[ETH_ALEN]; 947 __le16 seq_ctl; 948 u8 payload[0]; 949 } __packed; 950 951 struct rtl_info_element { 952 u8 id; 953 u8 len; 954 u8 data[0]; 955 } __packed; 956 957 struct rtl_probe_rsp { 958 struct rtl_hdr_3addr header; 959 u32 time_stamp[2]; 960 __le16 beacon_interval; 961 __le16 capability; 962 /*SSID, supported rates, FH params, DS params, 963 CF params, IBSS params, TIM (if beacon), RSN */ 964 struct rtl_info_element info_element[0]; 965 } __packed; 966 967 /*LED related.*/ 968 /*ledpin Identify how to implement this SW led.*/ 969 struct rtl_led { 970 void *hw; 971 enum rtl_led_pin ledpin; 972 bool ledon; 973 }; 974 975 struct rtl_led_ctl { 976 bool led_opendrain; 977 struct rtl_led sw_led0; 978 struct rtl_led sw_led1; 979 }; 980 981 struct rtl_qos_parameters { 982 __le16 cw_min; 983 __le16 cw_max; 984 u8 aifs; 985 u8 flag; 986 __le16 tx_op; 987 } __packed; 988 989 struct rt_smooth_data { 990 u32 elements[100]; /*array to store values */ 991 u32 index; /*index to current array to store */ 992 u32 total_num; /*num of valid elements */ 993 u32 total_val; /*sum of valid elements */ 994 }; 995 996 struct false_alarm_statistics { 997 u32 cnt_parity_fail; 998 u32 cnt_rate_illegal; 999 u32 cnt_crc8_fail; 1000 u32 cnt_mcs_fail; 1001 u32 cnt_fast_fsync_fail; 1002 u32 cnt_sb_search_fail; 1003 u32 cnt_ofdm_fail; 1004 u32 cnt_cck_fail; 1005 u32 cnt_all; 1006 u32 cnt_ofdm_cca; 1007 u32 cnt_cck_cca; 1008 u32 cnt_cca_all; 1009 u32 cnt_bw_usc; 1010 u32 cnt_bw_lsc; 1011 }; 1012 1013 struct init_gain { 1014 u8 xaagccore1; 1015 u8 xbagccore1; 1016 u8 xcagccore1; 1017 u8 xdagccore1; 1018 u8 cca; 1019 1020 }; 1021 1022 struct wireless_stats { 1023 unsigned long txbytesunicast; 1024 unsigned long txbytesmulticast; 1025 unsigned long txbytesbroadcast; 1026 unsigned long rxbytesunicast; 1027 1028 long rx_snr_db[4]; 1029 /*Correct smoothed ss in Dbm, only used 1030 in driver to report real power now. */ 1031 long recv_signal_power; 1032 long signal_quality; 1033 long last_sigstrength_inpercent; 1034 1035 u32 rssi_calculate_cnt; 1036 u32 pwdb_all_cnt; 1037 1038 /*Transformed, in dbm. Beautified signal 1039 strength for UI, not correct. */ 1040 long signal_strength; 1041 1042 u8 rx_rssi_percentage[4]; 1043 u8 rx_evm_dbm[4]; 1044 u8 rx_evm_percentage[2]; 1045 1046 u16 rx_cfo_short[4]; 1047 u16 rx_cfo_tail[4]; 1048 1049 struct rt_smooth_data ui_rssi; 1050 struct rt_smooth_data ui_link_quality; 1051 }; 1052 1053 struct rate_adaptive { 1054 u8 rate_adaptive_disabled; 1055 u8 ratr_state; 1056 u16 reserve; 1057 1058 u32 high_rssi_thresh_for_ra; 1059 u32 high2low_rssi_thresh_for_ra; 1060 u8 low2high_rssi_thresh_for_ra40m; 1061 u32 low_rssi_thresh_for_ra40m; 1062 u8 low2high_rssi_thresh_for_ra20m; 1063 u32 low_rssi_thresh_for_ra20m; 1064 u32 upper_rssi_threshold_ratr; 1065 u32 middleupper_rssi_threshold_ratr; 1066 u32 middle_rssi_threshold_ratr; 1067 u32 middlelow_rssi_threshold_ratr; 1068 u32 low_rssi_threshold_ratr; 1069 u32 ultralow_rssi_threshold_ratr; 1070 u32 low_rssi_threshold_ratr_40m; 1071 u32 low_rssi_threshold_ratr_20m; 1072 u8 ping_rssi_enable; 1073 u32 ping_rssi_ratr; 1074 u32 ping_rssi_thresh_for_ra; 1075 u32 last_ratr; 1076 u8 pre_ratr_state; 1077 u8 ldpc_thres; 1078 bool use_ldpc; 1079 bool lower_rts_rate; 1080 bool is_special_data; 1081 }; 1082 1083 struct regd_pair_mapping { 1084 u16 reg_dmnenum; 1085 u16 reg_5ghz_ctl; 1086 u16 reg_2ghz_ctl; 1087 }; 1088 1089 struct dynamic_primary_cca { 1090 u8 pricca_flag; 1091 u8 intf_flag; 1092 u8 intf_type; 1093 u8 dup_rts_flag; 1094 u8 monitor_flag; 1095 u8 ch_offset; 1096 u8 mf_state; 1097 }; 1098 1099 struct rtl_regulatory { 1100 s8 alpha2[2]; 1101 u16 country_code; 1102 u16 max_power_level; 1103 u32 tp_scale; 1104 u16 current_rd; 1105 u16 current_rd_ext; 1106 int16_t power_limit; 1107 struct regd_pair_mapping *regpair; 1108 }; 1109 1110 struct rtl_rfkill { 1111 bool rfkill_state; /*0 is off, 1 is on */ 1112 }; 1113 1114 /*for P2P PS**/ 1115 #define P2P_MAX_NOA_NUM 2 1116 1117 enum p2p_role { 1118 P2P_ROLE_DISABLE = 0, 1119 P2P_ROLE_DEVICE = 1, 1120 P2P_ROLE_CLIENT = 2, 1121 P2P_ROLE_GO = 3 1122 }; 1123 1124 enum p2p_ps_state { 1125 P2P_PS_DISABLE = 0, 1126 P2P_PS_ENABLE = 1, 1127 P2P_PS_SCAN = 2, 1128 P2P_PS_SCAN_DONE = 3, 1129 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ 1130 }; 1131 1132 enum p2p_ps_mode { 1133 P2P_PS_NONE = 0, 1134 P2P_PS_CTWINDOW = 1, 1135 P2P_PS_NOA = 2, 1136 P2P_PS_MIX = 3, /* CTWindow and NoA */ 1137 }; 1138 1139 struct rtl_p2p_ps_info { 1140 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ 1141 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ 1142 u8 noa_index; /* Identifies instance of Notice of Absence timing. */ 1143 /* Client traffic window. A period of time in TU after TBTT. */ 1144 u8 ctwindow; 1145 u8 opp_ps; /* opportunistic power save. */ 1146 u8 noa_num; /* number of NoA descriptor in P2P IE. */ 1147 /* Count for owner, Type of client. */ 1148 u8 noa_count_type[P2P_MAX_NOA_NUM]; 1149 /* Max duration for owner, preferred or min acceptable duration 1150 * for client. 1151 */ 1152 u32 noa_duration[P2P_MAX_NOA_NUM]; 1153 /* Length of interval for owner, preferred or max acceptable intervali 1154 * of client. 1155 */ 1156 u32 noa_interval[P2P_MAX_NOA_NUM]; 1157 /* schedule in terms of the lower 4 bytes of the TSF timer. */ 1158 u32 noa_start_time[P2P_MAX_NOA_NUM]; 1159 }; 1160 1161 struct p2p_ps_offload_t { 1162 u8 offload_en:1; 1163 u8 role:1; /* 1: Owner, 0: Client */ 1164 u8 ctwindow_en:1; 1165 u8 noa0_en:1; 1166 u8 noa1_en:1; 1167 u8 allstasleep:1; 1168 u8 discovery:1; 1169 u8 reserved:1; 1170 }; 1171 1172 #define IQK_MATRIX_REG_NUM 8 1173 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) 1174 1175 struct iqk_matrix_regs { 1176 bool iqk_done; 1177 long value[1][IQK_MATRIX_REG_NUM]; 1178 }; 1179 1180 struct phy_parameters { 1181 u16 length; 1182 u32 *pdata; 1183 }; 1184 1185 enum hw_param_tab_index { 1186 PHY_REG_2T, 1187 PHY_REG_1T, 1188 PHY_REG_PG, 1189 RADIOA_2T, 1190 RADIOB_2T, 1191 RADIOA_1T, 1192 RADIOB_1T, 1193 MAC_REG, 1194 AGCTAB_2T, 1195 AGCTAB_1T, 1196 MAX_TAB 1197 }; 1198 1199 struct rtl_phy { 1200 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 1201 struct init_gain initgain_backup; 1202 enum io_type current_io_type; 1203 1204 u8 rf_mode; 1205 u8 rf_type; 1206 u8 current_chan_bw; 1207 u8 set_bwmode_inprogress; 1208 u8 sw_chnl_inprogress; 1209 u8 sw_chnl_stage; 1210 u8 sw_chnl_step; 1211 u8 current_channel; 1212 u8 h2c_box_num; 1213 u8 set_io_inprogress; 1214 u8 lck_inprogress; 1215 1216 /* record for power tracking */ 1217 s32 reg_e94; 1218 s32 reg_e9c; 1219 s32 reg_ea4; 1220 s32 reg_eac; 1221 s32 reg_eb4; 1222 s32 reg_ebc; 1223 s32 reg_ec4; 1224 s32 reg_ecc; 1225 u8 rfpienable; 1226 u8 reserve_0; 1227 u16 reserve_1; 1228 u32 reg_c04, reg_c08, reg_874; 1229 u32 adda_backup[16]; 1230 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 1231 u32 iqk_bb_backup[10]; 1232 bool iqk_initialized; 1233 1234 bool rfpath_rx_enable[MAX_RF_PATH]; 1235 u8 reg_837; 1236 /* Dual mac */ 1237 bool need_iqk; 1238 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; 1239 1240 bool rfpi_enable; 1241 bool iqk_in_progress; 1242 1243 u8 pwrgroup_cnt; 1244 u8 cck_high_power; 1245 /* this is for 88E & 8723A */ 1246 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16]; 1247 /* MAX_PG_GROUP groups of pwr diff by rates */ 1248 u32 mcs_offset[MAX_PG_GROUP][16]; 1249 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] 1250 [TX_PWR_BY_RATE_NUM_RF] 1251 [TX_PWR_BY_RATE_NUM_RF] 1252 [TX_PWR_BY_RATE_NUM_SECTION]; 1253 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] 1254 [TX_PWR_BY_RATE_NUM_RF] 1255 [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; 1256 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] 1257 [TX_PWR_BY_RATE_NUM_RF] 1258 [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; 1259 u8 default_initialgain[4]; 1260 1261 /* the current Tx power level */ 1262 u8 cur_cck_txpwridx; 1263 u8 cur_ofdm24g_txpwridx; 1264 u8 cur_bw20_txpwridx; 1265 u8 cur_bw40_txpwridx; 1266 1267 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM] 1268 [MAX_2_4G_BANDWIDTH_NUM] 1269 [MAX_RATE_SECTION_NUM] 1270 [CHANNEL_MAX_NUMBER_2G] 1271 [MAX_RF_PATH_NUM]; 1272 s8 txpwr_limit_5g[MAX_REGULATION_NUM] 1273 [MAX_5G_BANDWIDTH_NUM] 1274 [MAX_RATE_SECTION_NUM] 1275 [CHANNEL_MAX_NUMBER_5G] 1276 [MAX_RF_PATH_NUM]; 1277 1278 u32 rfreg_chnlval[2]; 1279 bool apk_done; 1280 u32 reg_rf3c[2]; /* pathA / pathB */ 1281 1282 u32 backup_rf_0x1a;/*92ee*/ 1283 /* bfsync */ 1284 u8 framesync; 1285 u32 framesync_c34; 1286 1287 u8 num_total_rfpath; 1288 struct phy_parameters hwparam_tables[MAX_TAB]; 1289 u16 rf_pathmap; 1290 1291 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1292 enum rt_polarity_ctl polarity_ctl; 1293 }; 1294 1295 #define MAX_TID_COUNT 9 1296 #define RTL_AGG_STOP 0 1297 #define RTL_AGG_PROGRESS 1 1298 #define RTL_AGG_START 2 1299 #define RTL_AGG_OPERATIONAL 3 1300 #define RTL_AGG_OFF 0 1301 #define RTL_AGG_ON 1 1302 #define RTL_RX_AGG_START 1 1303 #define RTL_RX_AGG_STOP 0 1304 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 1305 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 1306 1307 struct rtl_ht_agg { 1308 u16 txq_id; 1309 u16 wait_for_ba; 1310 u16 start_idx; 1311 u64 bitmap; 1312 u32 rate_n_flags; 1313 u8 agg_state; 1314 u8 rx_agg_state; 1315 }; 1316 1317 struct rssi_sta { 1318 long undec_sm_pwdb; 1319 long undec_sm_cck; 1320 }; 1321 1322 struct rtl_tid_data { 1323 u16 seq_number; 1324 struct rtl_ht_agg agg; 1325 }; 1326 1327 struct rtl_sta_info { 1328 struct list_head list; 1329 struct rtl_tid_data tids[MAX_TID_COUNT]; 1330 /* just used for ap adhoc or mesh*/ 1331 struct rssi_sta rssi_stat; 1332 u16 wireless_mode; 1333 u8 ratr_index; 1334 u8 mimo_ps; 1335 u8 mac_addr[ETH_ALEN]; 1336 } __packed; 1337 1338 struct rtl_priv; 1339 struct rtl_io { 1340 struct device *dev; 1341 struct mutex bb_mutex; 1342 1343 /*PCI MEM map */ 1344 unsigned long pci_mem_end; /*shared mem end */ 1345 unsigned long pci_mem_start; /*shared mem start */ 1346 1347 /*PCI IO map */ 1348 unsigned long pci_base_addr; /*device I/O address */ 1349 1350 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 1351 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 1352 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 1353 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, 1354 u16 len); 1355 1356 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 1357 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 1358 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 1359 1360 }; 1361 1362 struct rtl_mac { 1363 u8 mac_addr[ETH_ALEN]; 1364 u8 mac80211_registered; 1365 u8 beacon_enabled; 1366 1367 u32 tx_ss_num; 1368 u32 rx_ss_num; 1369 1370 struct ieee80211_supported_band bands[NUM_NL80211_BANDS]; 1371 struct ieee80211_hw *hw; 1372 struct ieee80211_vif *vif; 1373 enum nl80211_iftype opmode; 1374 1375 /*Probe Beacon management */ 1376 struct rtl_tid_data tids[MAX_TID_COUNT]; 1377 enum rtl_link_state link_state; 1378 1379 int n_channels; 1380 int n_bitrates; 1381 1382 bool offchan_delay; 1383 u8 p2p; /*using p2p role*/ 1384 bool p2p_in_use; 1385 1386 /*filters */ 1387 u32 rx_conf; 1388 u16 rx_mgt_filter; 1389 u16 rx_ctrl_filter; 1390 u16 rx_data_filter; 1391 1392 bool act_scanning; 1393 u8 cnt_after_linked; 1394 bool skip_scan; 1395 1396 /* early mode */ 1397 /* skb wait queue */ 1398 struct sk_buff_head skb_waitq[MAX_TID_COUNT]; 1399 1400 u8 ht_stbc_cap; 1401 u8 ht_cur_stbc; 1402 1403 /*vht support*/ 1404 u8 vht_enable; 1405 u8 bw_80; 1406 u8 vht_cur_ldpc; 1407 u8 vht_cur_stbc; 1408 u8 vht_stbc_cap; 1409 u8 vht_ldpc_cap; 1410 1411 /*RDG*/ 1412 bool rdg_en; 1413 1414 /*AP*/ 1415 u8 bssid[ETH_ALEN] __aligned(2); 1416 u32 vendor; 1417 u8 mcs[16]; /* 16 bytes mcs for HT rates. */ 1418 u32 basic_rates; /* b/g rates */ 1419 u8 ht_enable; 1420 u8 sgi_40; 1421 u8 sgi_20; 1422 u8 bw_40; 1423 u16 mode; /* wireless mode */ 1424 u8 slot_time; 1425 u8 short_preamble; 1426 u8 use_cts_protect; 1427 u8 cur_40_prime_sc; 1428 u8 cur_40_prime_sc_bk; 1429 u8 cur_80_prime_sc; 1430 u64 tsf; 1431 u8 retry_short; 1432 u8 retry_long; 1433 u16 assoc_id; 1434 bool hiddenssid; 1435 1436 /*IBSS*/ 1437 int beacon_interval; 1438 1439 /*AMPDU*/ 1440 u8 min_space_cfg; /*For Min spacing configurations */ 1441 u8 max_mss_density; 1442 u8 current_ampdu_factor; 1443 u8 current_ampdu_density; 1444 1445 /*QOS & EDCA */ 1446 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; 1447 struct rtl_qos_parameters ac[AC_MAX]; 1448 1449 /* counters */ 1450 u64 last_txok_cnt; 1451 u64 last_rxok_cnt; 1452 u32 last_bt_edca_ul; 1453 u32 last_bt_edca_dl; 1454 }; 1455 1456 struct btdm_8723 { 1457 bool all_off; 1458 bool agc_table_en; 1459 bool adc_back_off_on; 1460 bool b2_ant_hid_en; 1461 bool low_penalty_rate_adaptive; 1462 bool rf_rx_lpf_shrink; 1463 bool reject_aggre_pkt; 1464 bool tra_tdma_on; 1465 u8 tra_tdma_nav; 1466 u8 tra_tdma_ant; 1467 bool tdma_on; 1468 u8 tdma_ant; 1469 u8 tdma_nav; 1470 u8 tdma_dac_swing; 1471 u8 fw_dac_swing_lvl; 1472 bool ps_tdma_on; 1473 u8 ps_tdma_byte[5]; 1474 bool pta_on; 1475 u32 val_0x6c0; 1476 u32 val_0x6c8; 1477 u32 val_0x6cc; 1478 bool sw_dac_swing_on; 1479 u32 sw_dac_swing_lvl; 1480 u32 wlan_act_hi; 1481 u32 wlan_act_lo; 1482 u32 bt_retry_index; 1483 bool dec_bt_pwr; 1484 bool ignore_wlan_act; 1485 }; 1486 1487 struct bt_coexist_8723 { 1488 u32 high_priority_tx; 1489 u32 high_priority_rx; 1490 u32 low_priority_tx; 1491 u32 low_priority_rx; 1492 u8 c2h_bt_info; 1493 bool c2h_bt_info_req_sent; 1494 bool c2h_bt_inquiry_page; 1495 u32 bt_inq_page_start_time; 1496 u8 bt_retry_cnt; 1497 u8 c2h_bt_info_original; 1498 u8 bt_inquiry_page_cnt; 1499 struct btdm_8723 btdm; 1500 }; 1501 1502 struct rtl_hal { 1503 struct ieee80211_hw *hw; 1504 bool driver_is_goingto_unload; 1505 bool up_first_time; 1506 bool first_init; 1507 bool being_init_adapter; 1508 bool bbrf_ready; 1509 bool mac_func_enable; 1510 bool pre_edcca_enable; 1511 struct bt_coexist_8723 hal_coex_8723; 1512 1513 enum intf_type interface; 1514 u16 hw_type; /*92c or 92d or 92s and so on */ 1515 u8 ic_class; 1516 u8 oem_id; 1517 u32 version; /*version of chip */ 1518 u8 state; /*stop 0, start 1 */ 1519 u8 board_type; 1520 u8 package_type; 1521 u8 external_pa; 1522 1523 u8 pa_mode; 1524 u8 pa_type_2g; 1525 u8 pa_type_5g; 1526 u8 lna_type_2g; 1527 u8 lna_type_5g; 1528 u8 external_pa_2g; 1529 u8 external_lna_2g; 1530 u8 external_pa_5g; 1531 u8 external_lna_5g; 1532 u8 rfe_type; 1533 1534 /*firmware */ 1535 u32 fwsize; 1536 u8 *pfirmware; 1537 u16 fw_version; 1538 u16 fw_subversion; 1539 bool h2c_setinprogress; 1540 u8 last_hmeboxnum; 1541 bool fw_ready; 1542 /*Reserve page start offset except beacon in TxQ. */ 1543 u8 fw_rsvdpage_startoffset; 1544 u8 h2c_txcmd_seq; 1545 u8 current_ra_rate; 1546 1547 /* FW Cmd IO related */ 1548 u16 fwcmd_iomap; 1549 u32 fwcmd_ioparam; 1550 bool set_fwcmd_inprogress; 1551 u8 current_fwcmd_io; 1552 1553 struct p2p_ps_offload_t p2p_ps_offload; 1554 bool fw_clk_change_in_progress; 1555 bool allow_sw_to_change_hwclc; 1556 u8 fw_ps_state; 1557 /**/ 1558 bool driver_going2unload; 1559 1560 /*AMPDU init min space*/ 1561 u8 minspace_cfg; /*For Min spacing configurations */ 1562 1563 /* Dual mac */ 1564 enum macphy_mode macphymode; 1565 enum band_type current_bandtype; /* 0:2.4G, 1:5G */ 1566 enum band_type current_bandtypebackup; 1567 enum band_type bandset; 1568 /* dual MAC 0--Mac0 1--Mac1 */ 1569 u32 interfaceindex; 1570 /* just for DualMac S3S4 */ 1571 u8 macphyctl_reg; 1572 bool earlymode_enable; 1573 u8 max_earlymode_num; 1574 /* Dual mac*/ 1575 bool during_mac0init_radiob; 1576 bool during_mac1init_radioa; 1577 bool reloadtxpowerindex; 1578 /* True if IMR or IQK have done 1579 for 2.4G in scan progress */ 1580 bool load_imrandiqk_setting_for2g; 1581 1582 bool disable_amsdu_8k; 1583 bool master_of_dmsp; 1584 bool slave_of_dmsp; 1585 1586 u16 rx_tag;/*for 92ee*/ 1587 u8 rts_en; 1588 1589 /*for wowlan*/ 1590 bool wow_enable; 1591 bool enter_pnp_sleep; 1592 bool wake_from_pnp_sleep; 1593 bool wow_enabled; 1594 __kernel_time_t last_suspend_sec; 1595 u32 wowlan_fwsize; 1596 u8 *wowlan_firmware; 1597 1598 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ 1599 1600 bool real_wow_v2_enable; 1601 bool re_init_llt_table; 1602 }; 1603 1604 struct rtl_security { 1605 /*default 0 */ 1606 bool use_sw_sec; 1607 1608 bool being_setkey; 1609 bool use_defaultkey; 1610 /*Encryption Algorithm for Unicast Packet */ 1611 enum rt_enc_alg pairwise_enc_algorithm; 1612 /*Encryption Algorithm for Brocast/Multicast */ 1613 enum rt_enc_alg group_enc_algorithm; 1614 /*Cam Entry Bitmap */ 1615 u32 hwsec_cam_bitmap; 1616 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; 1617 /*local Key buffer, indx 0 is for 1618 pairwise key 1-4 is for agoup key. */ 1619 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; 1620 u8 key_len[KEY_BUF_SIZE]; 1621 1622 /*The pointer of Pairwise Key, 1623 it always points to KeyBuf[4] */ 1624 u8 *pairwise_key; 1625 }; 1626 1627 #define ASSOCIATE_ENTRY_NUM 33 1628 1629 struct fast_ant_training { 1630 u8 bssid[6]; 1631 u8 antsel_rx_keep_0; 1632 u8 antsel_rx_keep_1; 1633 u8 antsel_rx_keep_2; 1634 u32 ant_sum[7]; 1635 u32 ant_cnt[7]; 1636 u32 ant_ave[7]; 1637 u8 fat_state; 1638 u32 train_idx; 1639 u8 antsel_a[ASSOCIATE_ENTRY_NUM]; 1640 u8 antsel_b[ASSOCIATE_ENTRY_NUM]; 1641 u8 antsel_c[ASSOCIATE_ENTRY_NUM]; 1642 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; 1643 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; 1644 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1645 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; 1646 u8 rx_idle_ant; 1647 bool becomelinked; 1648 }; 1649 1650 struct dm_phy_dbg_info { 1651 s8 rx_snrdb[4]; 1652 u64 num_qry_phy_status; 1653 u64 num_qry_phy_status_cck; 1654 u64 num_qry_phy_status_ofdm; 1655 u16 num_qry_beacon_pkt; 1656 u16 num_non_be_pkt; 1657 s32 rx_evm[4]; 1658 }; 1659 1660 struct rtl_dm { 1661 /*PHY status for Dynamic Management */ 1662 long entry_min_undec_sm_pwdb; 1663 long undec_sm_cck; 1664 long undec_sm_pwdb; /*out dm */ 1665 long entry_max_undec_sm_pwdb; 1666 s32 ofdm_pkt_cnt; 1667 bool dm_initialgain_enable; 1668 bool dynamic_txpower_enable; 1669 bool current_turbo_edca; 1670 bool is_any_nonbepkts; /*out dm */ 1671 bool is_cur_rdlstate; 1672 bool txpower_trackinginit; 1673 bool disable_framebursting; 1674 bool cck_inch14; 1675 bool txpower_tracking; 1676 bool useramask; 1677 bool rfpath_rxenable[4]; 1678 bool inform_fw_driverctrldm; 1679 bool current_mrc_switch; 1680 u8 txpowercount; 1681 u8 powerindex_backup[6]; 1682 1683 u8 thermalvalue_rxgain; 1684 u8 thermalvalue_iqk; 1685 u8 thermalvalue_lck; 1686 u8 thermalvalue; 1687 u8 last_dtp_lvl; 1688 u8 thermalvalue_avg[AVG_THERMAL_NUM]; 1689 u8 thermalvalue_avg_index; 1690 u8 tm_trigger; 1691 bool done_txpower; 1692 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1693 u8 dm_flag; /*Indicate each dynamic mechanism's status. */ 1694 u8 dm_flag_tmp; 1695 u8 dm_type; 1696 u8 dm_rssi_sel; 1697 u8 txpower_track_control; 1698 bool interrupt_migration; 1699 bool disable_tx_int; 1700 s8 ofdm_index[MAX_RF_PATH]; 1701 u8 default_ofdm_index; 1702 u8 default_cck_index; 1703 s8 cck_index; 1704 s8 delta_power_index[MAX_RF_PATH]; 1705 s8 delta_power_index_last[MAX_RF_PATH]; 1706 s8 power_index_offset[MAX_RF_PATH]; 1707 s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; 1708 s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; 1709 s8 remnant_cck_idx; 1710 bool modify_txagc_flag_path_a; 1711 bool modify_txagc_flag_path_b; 1712 1713 bool one_entry_only; 1714 struct dm_phy_dbg_info dbginfo; 1715 1716 /* Dynamic ATC switch */ 1717 bool atc_status; 1718 bool large_cfo_hit; 1719 bool is_freeze; 1720 int cfo_tail[2]; 1721 int cfo_ave_pre; 1722 int crystal_cap; 1723 u8 cfo_threshold; 1724 u32 packet_count; 1725 u32 packet_count_pre; 1726 u8 tx_rate; 1727 1728 /*88e tx power tracking*/ 1729 u8 swing_idx_ofdm[MAX_RF_PATH]; 1730 u8 swing_idx_ofdm_cur; 1731 u8 swing_idx_ofdm_base[MAX_RF_PATH]; 1732 bool swing_flag_ofdm; 1733 u8 swing_idx_cck; 1734 u8 swing_idx_cck_cur; 1735 u8 swing_idx_cck_base; 1736 bool swing_flag_cck; 1737 1738 s8 swing_diff_2g; 1739 s8 swing_diff_5g; 1740 1741 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ]; 1742 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ]; 1743 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ]; 1744 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ]; 1745 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ]; 1746 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ]; 1747 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ]; 1748 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ]; 1749 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ]; 1750 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ]; 1751 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ]; 1752 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ]; 1753 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ]; 1754 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ]; 1755 1756 /* DMSP */ 1757 bool supp_phymode_switch; 1758 1759 /* DulMac */ 1760 struct fast_ant_training fat_table; 1761 1762 u8 resp_tx_path; 1763 u8 path_sel; 1764 u32 patha_sum; 1765 u32 pathb_sum; 1766 u32 patha_cnt; 1767 u32 pathb_cnt; 1768 1769 u8 pre_channel; 1770 u8 *p_channel; 1771 u8 linked_interval; 1772 1773 u64 last_tx_ok_cnt; 1774 u64 last_rx_ok_cnt; 1775 }; 1776 1777 #define EFUSE_MAX_LOGICAL_SIZE 512 1778 1779 struct rtl_efuse { 1780 bool autoLoad_ok; 1781 bool bootfromefuse; 1782 u16 max_physical_size; 1783 1784 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1785 u16 efuse_usedbytes; 1786 u8 efuse_usedpercentage; 1787 #ifdef EFUSE_REPG_WORKAROUND 1788 bool efuse_re_pg_sec1flag; 1789 u8 efuse_re_pg_data[8]; 1790 #endif 1791 1792 u8 autoload_failflag; 1793 u8 autoload_status; 1794 1795 short epromtype; 1796 u16 eeprom_vid; 1797 u16 eeprom_did; 1798 u16 eeprom_svid; 1799 u16 eeprom_smid; 1800 u8 eeprom_oemid; 1801 u16 eeprom_channelplan; 1802 u8 eeprom_version; 1803 u8 board_type; 1804 u8 external_pa; 1805 1806 u8 dev_addr[6]; 1807 u8 wowlan_enable; 1808 u8 antenna_div_cfg; 1809 u8 antenna_div_type; 1810 1811 bool txpwr_fromeprom; 1812 u8 eeprom_crystalcap; 1813 u8 eeprom_tssi[2]; 1814 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ 1815 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; 1816 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; 1817 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; 1818 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1819 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; 1820 1821 u8 internal_pa_5g[2]; /* pathA / pathB */ 1822 u8 eeprom_c9; 1823 u8 eeprom_cc; 1824 1825 /*For power group */ 1826 u8 eeprom_pwrgroup[2][3]; 1827 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; 1828 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; 1829 1830 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; 1831 /*For HT 40MHZ pwr */ 1832 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1833 /*For HT 40MHZ pwr */ 1834 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1835 1836 /*--------------------------------------------------------* 1837 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, 1838 * other ICs (8188EE\8723BE\8192EE\8812AE...) 1839 * define new arrays in Windows code. 1840 * BUT, in linux code, we use the same array for all ICs. 1841 * 1842 * The Correspondance relation between two arrays is: 1843 * txpwr_cckdiff[][] == CCK_24G_Diff[][] 1844 * txpwr_ht20diff[][] == BW20_24G_Diff[][] 1845 * txpwr_ht40diff[][] == BW40_24G_Diff[][] 1846 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] 1847 * 1848 * Sizes of these arrays are decided by the larger ones. 1849 */ 1850 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1851 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1852 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1853 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1854 1855 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 1856 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; 1857 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; 1858 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; 1859 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; 1860 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; 1861 1862 u8 txpwr_safetyflag; /* Band edge enable flag */ 1863 u16 eeprom_txpowerdiff; 1864 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ 1865 u8 antenna_txpwdiff[3]; 1866 1867 u8 eeprom_regulatory; 1868 u8 eeprom_thermalmeter; 1869 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ 1870 u16 tssi_13dbm; 1871 u8 crystalcap; /* CrystalCap. */ 1872 u8 delta_iqk; 1873 u8 delta_lck; 1874 1875 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1876 bool apk_thermalmeterignore; 1877 1878 bool b1x1_recvcombine; 1879 bool b1ss_support; 1880 1881 /*channel plan */ 1882 u8 channel_plan; 1883 }; 1884 1885 struct rtl_ps_ctl { 1886 bool pwrdomain_protect; 1887 bool in_powersavemode; 1888 bool rfchange_inprogress; 1889 bool swrf_processing; 1890 bool hwradiooff; 1891 /* 1892 * just for PCIE ASPM 1893 * If it supports ASPM, Offset[560h] = 0x40, 1894 * otherwise Offset[560h] = 0x00. 1895 * */ 1896 bool support_aspm; 1897 bool support_backdoor; 1898 1899 /*for LPS */ 1900 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1901 bool swctrl_lps; 1902 bool leisure_ps; 1903 bool fwctrl_lps; 1904 u8 fwctrl_psmode; 1905 /*For Fw control LPS mode */ 1906 u8 reg_fwctrl_lps; 1907 /*Record Fw PS mode status. */ 1908 bool fw_current_inpsmode; 1909 u8 reg_max_lps_awakeintvl; 1910 bool report_linked; 1911 bool low_power_enable;/*for 32k*/ 1912 1913 /*for IPS */ 1914 bool inactiveps; 1915 1916 u32 rfoff_reason; 1917 1918 /*RF OFF Level */ 1919 u32 cur_ps_level; 1920 u32 reg_rfps_level; 1921 1922 /*just for PCIE ASPM */ 1923 u8 const_amdpci_aspm; 1924 bool pwrdown_mode; 1925 1926 enum rf_pwrstate inactive_pwrstate; 1927 enum rf_pwrstate rfpwr_state; /*cur power state */ 1928 1929 /* for SW LPS*/ 1930 bool sw_ps_enabled; 1931 bool state; 1932 bool state_inap; 1933 bool multi_buffered; 1934 u16 nullfunc_seq; 1935 unsigned int dtim_counter; 1936 unsigned int sleep_ms; 1937 unsigned long last_sleep_jiffies; 1938 unsigned long last_awake_jiffies; 1939 unsigned long last_delaylps_stamp_jiffies; 1940 unsigned long last_dtim; 1941 unsigned long last_beacon; 1942 unsigned long last_action; 1943 unsigned long last_slept; 1944 1945 /*For P2P PS */ 1946 struct rtl_p2p_ps_info p2p_ps_info; 1947 u8 pwr_mode; 1948 u8 smart_ps; 1949 1950 /* wake up on line */ 1951 u8 wo_wlan_mode; 1952 u8 arp_offload_enable; 1953 u8 gtk_offload_enable; 1954 /* Used for WOL, indicates the reason for waking event.*/ 1955 u32 wakeup_reason; 1956 /* Record the last waking time for comparison with setting key. */ 1957 u64 last_wakeup_time; 1958 }; 1959 1960 struct rtl_stats { 1961 u8 psaddr[ETH_ALEN]; 1962 u32 mac_time[2]; 1963 s8 rssi; 1964 u8 signal; 1965 u8 noise; 1966 u8 rate; /* hw desc rate */ 1967 u8 received_channel; 1968 u8 control; 1969 u8 mask; 1970 u8 freq; 1971 u16 len; 1972 u64 tsf; 1973 u32 beacon_time; 1974 u8 nic_type; 1975 u16 length; 1976 u8 signalquality; /*in 0-100 index. */ 1977 /* 1978 * Real power in dBm for this packet, 1979 * no beautification and aggregation. 1980 * */ 1981 s32 recvsignalpower; 1982 s8 rxpower; /*in dBm Translate from PWdB */ 1983 u8 signalstrength; /*in 0-100 index. */ 1984 u16 hwerror:1; 1985 u16 crc:1; 1986 u16 icv:1; 1987 u16 shortpreamble:1; 1988 u16 antenna:1; 1989 u16 decrypted:1; 1990 u16 wakeup:1; 1991 u32 timestamp_low; 1992 u32 timestamp_high; 1993 bool shift; 1994 1995 u8 rx_drvinfo_size; 1996 u8 rx_bufshift; 1997 bool isampdu; 1998 bool isfirst_ampdu; 1999 bool rx_is40Mhzpacket; 2000 u8 rx_packet_bw; 2001 u32 rx_pwdb_all; 2002 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 2003 s8 rx_mimo_signalquality[4]; 2004 u8 rx_mimo_evm_dbm[4]; 2005 u16 cfo_short[4]; /* per-path's Cfo_short */ 2006 u16 cfo_tail[4]; 2007 2008 s8 rx_mimo_sig_qual[4]; 2009 u8 rx_pwr[4]; /* per-path's pwdb */ 2010 u8 rx_snr[4]; /* per-path's SNR */ 2011 u8 bandwidth; 2012 u8 bt_coex_pwr_adjust; 2013 bool packet_matchbssid; 2014 bool is_cck; 2015 bool is_ht; 2016 bool packet_toself; 2017 bool packet_beacon; /*for rssi */ 2018 s8 cck_adc_pwdb[4]; /*for rx path selection */ 2019 2020 bool is_vht; 2021 bool is_short_gi; 2022 u8 vht_nss; 2023 2024 u8 packet_report_type; 2025 2026 u32 macid; 2027 u8 wake_match; 2028 u32 bt_rx_rssi_percentage; 2029 u32 macid_valid_entry[2]; 2030 }; 2031 2032 2033 struct rt_link_detect { 2034 /* count for roaming */ 2035 u32 bcn_rx_inperiod; 2036 u32 roam_times; 2037 2038 u32 num_tx_in4period[4]; 2039 u32 num_rx_in4period[4]; 2040 2041 u32 num_tx_inperiod; 2042 u32 num_rx_inperiod; 2043 2044 bool busytraffic; 2045 bool tx_busy_traffic; 2046 bool rx_busy_traffic; 2047 bool higher_busytraffic; 2048 bool higher_busyrxtraffic; 2049 2050 u32 tidtx_in4period[MAX_TID_COUNT][4]; 2051 u32 tidtx_inperiod[MAX_TID_COUNT]; 2052 bool higher_busytxtraffic[MAX_TID_COUNT]; 2053 }; 2054 2055 struct rtl_tcb_desc { 2056 u8 packet_bw:2; 2057 u8 multicast:1; 2058 u8 broadcast:1; 2059 2060 u8 rts_stbc:1; 2061 u8 rts_enable:1; 2062 u8 cts_enable:1; 2063 u8 rts_use_shortpreamble:1; 2064 u8 rts_use_shortgi:1; 2065 u8 rts_sc:1; 2066 u8 rts_bw:1; 2067 u8 rts_rate; 2068 2069 u8 use_shortgi:1; 2070 u8 use_shortpreamble:1; 2071 u8 use_driver_rate:1; 2072 u8 disable_ratefallback:1; 2073 2074 u8 ratr_index; 2075 u8 mac_id; 2076 u8 hw_rate; 2077 2078 u8 last_inipkt:1; 2079 u8 cmd_or_init:1; 2080 u8 queue_index; 2081 2082 /* early mode */ 2083 u8 empkt_num; 2084 /* The max value by HW */ 2085 u32 empkt_len[10]; 2086 bool tx_enable_sw_calc_duration; 2087 }; 2088 2089 struct rtl_wow_pattern { 2090 u8 type; 2091 u16 crc; 2092 u32 mask[4]; 2093 }; 2094 2095 struct rtl_hal_ops { 2096 int (*init_sw_vars) (struct ieee80211_hw *hw); 2097 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 2098 void (*read_chip_version)(struct ieee80211_hw *hw); 2099 void (*read_eeprom_info) (struct ieee80211_hw *hw); 2100 void (*interrupt_recognized) (struct ieee80211_hw *hw, 2101 u32 *p_inta, u32 *p_intb); 2102 int (*hw_init) (struct ieee80211_hw *hw); 2103 void (*hw_disable) (struct ieee80211_hw *hw); 2104 void (*hw_suspend) (struct ieee80211_hw *hw); 2105 void (*hw_resume) (struct ieee80211_hw *hw); 2106 void (*enable_interrupt) (struct ieee80211_hw *hw); 2107 void (*disable_interrupt) (struct ieee80211_hw *hw); 2108 int (*set_network_type) (struct ieee80211_hw *hw, 2109 enum nl80211_iftype type); 2110 void (*set_chk_bssid)(struct ieee80211_hw *hw, 2111 bool check_bssid); 2112 void (*set_bw_mode) (struct ieee80211_hw *hw, 2113 enum nl80211_channel_type ch_type); 2114 u8(*switch_channel) (struct ieee80211_hw *hw); 2115 void (*set_qos) (struct ieee80211_hw *hw, int aci); 2116 void (*set_bcn_reg) (struct ieee80211_hw *hw); 2117 void (*set_bcn_intv) (struct ieee80211_hw *hw); 2118 void (*update_interrupt_mask) (struct ieee80211_hw *hw, 2119 u32 add_msr, u32 rm_msr); 2120 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2121 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); 2122 void (*update_rate_tbl) (struct ieee80211_hw *hw, 2123 struct ieee80211_sta *sta, u8 rssi_level); 2124 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, 2125 u8 *desc, u8 queue_index, 2126 struct sk_buff *skb, dma_addr_t addr); 2127 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); 2128 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, 2129 u8 queue_index); 2130 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, 2131 u8 queue_index); 2132 void (*fill_tx_desc) (struct ieee80211_hw *hw, 2133 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 2134 u8 *pbd_desc_tx, 2135 struct ieee80211_tx_info *info, 2136 struct ieee80211_sta *sta, 2137 struct sk_buff *skb, u8 hw_queue, 2138 struct rtl_tcb_desc *ptcb_desc); 2139 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, 2140 u32 buffer_len, bool bIsPsPoll); 2141 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 2142 bool firstseg, bool lastseg, 2143 struct sk_buff *skb); 2144 bool (*query_rx_desc) (struct ieee80211_hw *hw, 2145 struct rtl_stats *stats, 2146 struct ieee80211_rx_status *rx_status, 2147 u8 *pdesc, struct sk_buff *skb); 2148 void (*set_channel_access) (struct ieee80211_hw *hw); 2149 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 2150 void (*dm_watchdog) (struct ieee80211_hw *hw); 2151 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 2152 bool (*set_rf_power_state) (struct ieee80211_hw *hw, 2153 enum rf_pwrstate rfpwr_state); 2154 void (*led_control) (struct ieee80211_hw *hw, 2155 enum led_ctl_mode ledaction); 2156 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 2157 u8 desc_name, u8 *val); 2158 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); 2159 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, 2160 u8 hw_queue, u16 index); 2161 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); 2162 void (*enable_hw_sec) (struct ieee80211_hw *hw); 2163 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 2164 u8 *macaddr, bool is_group, u8 enc_algo, 2165 bool is_wepkey, bool clear_all); 2166 void (*init_sw_leds) (struct ieee80211_hw *hw); 2167 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 2168 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 2169 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 2170 u32 data); 2171 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2172 u32 regaddr, u32 bitmask); 2173 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 2174 u32 regaddr, u32 bitmask, u32 data); 2175 void (*linked_set_reg) (struct ieee80211_hw *hw); 2176 void (*chk_switch_dmdp) (struct ieee80211_hw *hw); 2177 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); 2178 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); 2179 bool (*phy_rf6052_config) (struct ieee80211_hw *hw); 2180 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, 2181 u8 *powerlevel); 2182 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, 2183 u8 *ppowerlevel, u8 channel); 2184 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, 2185 u8 configtype); 2186 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, 2187 u8 configtype); 2188 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); 2189 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); 2190 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); 2191 void (*c2h_command_handle) (struct ieee80211_hw *hw); 2192 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, 2193 bool mstate); 2194 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); 2195 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, 2196 u32 cmd_len, u8 *p_cmdbuffer); 2197 bool (*get_btc_status) (void); 2198 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr); 2199 u32 (*rx_command_packet)(struct ieee80211_hw *hw, 2200 const struct rtl_stats *status, struct sk_buff *skb); 2201 void (*add_wowlan_pattern)(struct ieee80211_hw *hw, 2202 struct rtl_wow_pattern *rtl_pattern, 2203 u8 index); 2204 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx); 2205 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len, 2206 u8 *val); 2207 }; 2208 2209 struct rtl_intf_ops { 2210 /*com */ 2211 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); 2212 int (*adapter_start) (struct ieee80211_hw *hw); 2213 void (*adapter_stop) (struct ieee80211_hw *hw); 2214 bool (*check_buddy_priv)(struct ieee80211_hw *hw, 2215 struct rtl_priv **buddy_priv); 2216 2217 int (*adapter_tx) (struct ieee80211_hw *hw, 2218 struct ieee80211_sta *sta, 2219 struct sk_buff *skb, 2220 struct rtl_tcb_desc *ptcb_desc); 2221 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop); 2222 int (*reset_trx_ring) (struct ieee80211_hw *hw); 2223 bool (*waitq_insert) (struct ieee80211_hw *hw, 2224 struct ieee80211_sta *sta, 2225 struct sk_buff *skb); 2226 2227 /*pci */ 2228 void (*disable_aspm) (struct ieee80211_hw *hw); 2229 void (*enable_aspm) (struct ieee80211_hw *hw); 2230 2231 /*usb */ 2232 }; 2233 2234 struct rtl_mod_params { 2235 /* default: 0,0 */ 2236 u64 debug_mask; 2237 /* default: 0 = using hardware encryption */ 2238 bool sw_crypto; 2239 2240 /* default: 0 = DBG_EMERG (0)*/ 2241 int debug_level; 2242 2243 /* default: 1 = using no linked power save */ 2244 bool inactiveps; 2245 2246 /* default: 1 = using linked sw power save */ 2247 bool swctrl_lps; 2248 2249 /* default: 1 = using linked fw power save */ 2250 bool fwctrl_lps; 2251 2252 /* default: 0 = not using MSI interrupts mode 2253 * submodules should set their own default value 2254 */ 2255 bool msi_support; 2256 2257 /* default 0: 1 means disable */ 2258 bool disable_watchdog; 2259 2260 /* default 0: 1 means do not disable interrupts */ 2261 bool int_clear; 2262 2263 /* select antenna */ 2264 int ant_sel; 2265 }; 2266 2267 struct rtl_hal_usbint_cfg { 2268 /* data - rx */ 2269 u32 in_ep_num; 2270 u32 rx_urb_num; 2271 u32 rx_max_size; 2272 2273 /* op - rx */ 2274 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); 2275 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, 2276 struct sk_buff_head *); 2277 2278 /* tx */ 2279 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); 2280 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, 2281 struct sk_buff *); 2282 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, 2283 struct sk_buff_head *); 2284 2285 /* endpoint mapping */ 2286 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); 2287 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); 2288 }; 2289 2290 struct rtl_hal_cfg { 2291 u8 bar_id; 2292 bool write_readback; 2293 char *name; 2294 char *alt_fw_name; 2295 struct rtl_hal_ops *ops; 2296 struct rtl_mod_params *mod_params; 2297 struct rtl_hal_usbint_cfg *usb_interface_cfg; 2298 2299 /*this map used for some registers or vars 2300 defined int HAL but used in MAIN */ 2301 u32 maps[RTL_VAR_MAP_MAX]; 2302 2303 }; 2304 2305 struct rtl_locks { 2306 /* mutex */ 2307 struct mutex conf_mutex; 2308 struct mutex ps_mutex; 2309 2310 /*spin lock */ 2311 spinlock_t ips_lock; 2312 spinlock_t irq_th_lock; 2313 spinlock_t irq_pci_lock; 2314 spinlock_t tx_lock; 2315 spinlock_t h2c_lock; 2316 spinlock_t rf_ps_lock; 2317 spinlock_t rf_lock; 2318 spinlock_t lps_lock; 2319 spinlock_t waitq_lock; 2320 spinlock_t entry_list_lock; 2321 spinlock_t usb_lock; 2322 spinlock_t c2hcmd_lock; 2323 2324 /*FW clock change */ 2325 spinlock_t fw_ps_lock; 2326 2327 /*Dual mac*/ 2328 spinlock_t cck_and_rw_pagea_lock; 2329 2330 /*Easy concurrent*/ 2331 spinlock_t check_sendpkt_lock; 2332 2333 spinlock_t iqk_lock; 2334 }; 2335 2336 struct rtl_works { 2337 struct ieee80211_hw *hw; 2338 2339 /*timer */ 2340 struct timer_list watchdog_timer; 2341 struct timer_list dualmac_easyconcurrent_retrytimer; 2342 struct timer_list fw_clockoff_timer; 2343 struct timer_list fast_antenna_training_timer; 2344 /*task */ 2345 struct tasklet_struct irq_tasklet; 2346 struct tasklet_struct irq_prepare_bcn_tasklet; 2347 2348 /*work queue */ 2349 struct workqueue_struct *rtl_wq; 2350 struct delayed_work watchdog_wq; 2351 struct delayed_work ips_nic_off_wq; 2352 struct delayed_work c2hcmd_wq; 2353 2354 /* For SW LPS */ 2355 struct delayed_work ps_work; 2356 struct delayed_work ps_rfon_wq; 2357 struct delayed_work fwevt_wq; 2358 2359 struct work_struct lps_change_work; 2360 struct work_struct fill_h2c_cmd; 2361 }; 2362 2363 #define MIMO_PS_STATIC 0 2364 #define MIMO_PS_DYNAMIC 1 2365 #define MIMO_PS_NOLIMIT 3 2366 2367 struct rtl_dualmac_easy_concurrent_ctl { 2368 enum band_type currentbandtype_backfordmdp; 2369 bool close_bbandrf_for_dmsp; 2370 bool change_to_dmdp; 2371 bool change_to_dmsp; 2372 bool switch_in_process; 2373 }; 2374 2375 struct rtl_dmsp_ctl { 2376 bool activescan_for_slaveofdmsp; 2377 bool scan_for_anothermac_fordmsp; 2378 bool scan_for_itself_fordmsp; 2379 bool writedig_for_anothermacofdmsp; 2380 u32 curdigvalue_for_anothermacofdmsp; 2381 bool changecckpdstate_for_anothermacofdmsp; 2382 u8 curcckpdstate_for_anothermacofdmsp; 2383 bool changetxhighpowerlvl_for_anothermacofdmsp; 2384 u8 curtxhighlvl_for_anothermacofdmsp; 2385 long rssivalmin_for_anothermacofdmsp; 2386 }; 2387 2388 struct ps_t { 2389 u8 pre_ccastate; 2390 u8 cur_ccasate; 2391 u8 pre_rfstate; 2392 u8 cur_rfstate; 2393 u8 initialize; 2394 long rssi_val_min; 2395 }; 2396 2397 struct dig_t { 2398 u32 rssi_lowthresh; 2399 u32 rssi_highthresh; 2400 u32 fa_lowthresh; 2401 u32 fa_highthresh; 2402 long last_min_undec_pwdb_for_dm; 2403 long rssi_highpower_lowthresh; 2404 long rssi_highpower_highthresh; 2405 u32 recover_cnt; 2406 u32 pre_igvalue; 2407 u32 cur_igvalue; 2408 long rssi_val; 2409 u8 dig_enable_flag; 2410 u8 dig_ext_port_stage; 2411 u8 dig_algorithm; 2412 u8 dig_twoport_algorithm; 2413 u8 dig_dbgmode; 2414 u8 dig_slgorithm_switch; 2415 u8 cursta_cstate; 2416 u8 presta_cstate; 2417 u8 curmultista_cstate; 2418 u8 stop_dig; 2419 s8 back_val; 2420 s8 back_range_max; 2421 s8 back_range_min; 2422 u8 rx_gain_max; 2423 u8 rx_gain_min; 2424 u8 min_undec_pwdb_for_dm; 2425 u8 rssi_val_min; 2426 u8 pre_cck_cca_thres; 2427 u8 cur_cck_cca_thres; 2428 u8 pre_cck_pd_state; 2429 u8 cur_cck_pd_state; 2430 u8 pre_cck_fa_state; 2431 u8 cur_cck_fa_state; 2432 u8 pre_ccastate; 2433 u8 cur_ccasate; 2434 u8 large_fa_hit; 2435 u8 forbidden_igi; 2436 u8 dig_state; 2437 u8 dig_highpwrstate; 2438 u8 cur_sta_cstate; 2439 u8 pre_sta_cstate; 2440 u8 cur_ap_cstate; 2441 u8 pre_ap_cstate; 2442 u8 cur_pd_thstate; 2443 u8 pre_pd_thstate; 2444 u8 cur_cs_ratiostate; 2445 u8 pre_cs_ratiostate; 2446 u8 backoff_enable_flag; 2447 s8 backoffval_range_max; 2448 s8 backoffval_range_min; 2449 u8 dig_min_0; 2450 u8 dig_min_1; 2451 u8 bt30_cur_igi; 2452 bool media_connect_0; 2453 bool media_connect_1; 2454 2455 u32 antdiv_rssi_max; 2456 u32 rssi_max; 2457 }; 2458 2459 struct rtl_global_var { 2460 /* from this list we can get 2461 * other adapter's rtl_priv */ 2462 struct list_head glb_priv_list; 2463 spinlock_t glb_list_lock; 2464 }; 2465 2466 struct rtl_btc_info { 2467 u8 bt_type; 2468 u8 btcoexist; 2469 u8 ant_num; 2470 u8 single_ant_path; 2471 }; 2472 2473 struct bt_coexist_info { 2474 struct rtl_btc_ops *btc_ops; 2475 struct rtl_btc_info btc_info; 2476 /* EEPROM BT info. */ 2477 u8 eeprom_bt_coexist; 2478 u8 eeprom_bt_type; 2479 u8 eeprom_bt_ant_num; 2480 u8 eeprom_bt_ant_isol; 2481 u8 eeprom_bt_radio_shared; 2482 2483 u8 bt_coexistence; 2484 u8 bt_ant_num; 2485 u8 bt_coexist_type; 2486 u8 bt_state; 2487 u8 bt_cur_state; /* 0:on, 1:off */ 2488 u8 bt_ant_isolation; /* 0:good, 1:bad */ 2489 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ 2490 u8 bt_service; 2491 u8 bt_radio_shared_type; 2492 u8 bt_rfreg_origin_1e; 2493 u8 bt_rfreg_origin_1f; 2494 u8 bt_rssi_state; 2495 u32 ratio_tx; 2496 u32 ratio_pri; 2497 u32 bt_edca_ul; 2498 u32 bt_edca_dl; 2499 2500 bool init_set; 2501 bool bt_busy_traffic; 2502 bool bt_traffic_mode_set; 2503 bool bt_non_traffic_mode_set; 2504 2505 bool fw_coexist_all_off; 2506 bool sw_coexist_all_off; 2507 bool hw_coexist_all_off; 2508 u32 cstate; 2509 u32 previous_state; 2510 u32 cstate_h; 2511 u32 previous_state_h; 2512 2513 u8 bt_pre_rssi_state; 2514 u8 bt_pre_rssi_state1; 2515 2516 u8 reg_bt_iso; 2517 u8 reg_bt_sco; 2518 bool balance_on; 2519 u8 bt_active_zero_cnt; 2520 bool cur_bt_disabled; 2521 bool pre_bt_disabled; 2522 2523 u8 bt_profile_case; 2524 u8 bt_profile_action; 2525 bool bt_busy; 2526 bool hold_for_bt_operation; 2527 u8 lps_counter; 2528 }; 2529 2530 struct rtl_btc_ops { 2531 void (*btc_init_variables) (struct rtl_priv *rtlpriv); 2532 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); 2533 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); 2534 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); 2535 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type); 2536 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); 2537 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); 2538 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, 2539 enum rt_media_status mstatus); 2540 void (*btc_periodical) (struct rtl_priv *rtlpriv); 2541 void (*btc_halt_notify) (void); 2542 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, 2543 u8 *tmp_buf, u8 length); 2544 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); 2545 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); 2546 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); 2547 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv, 2548 u8 pkt_type); 2549 }; 2550 2551 struct proxim { 2552 bool proxim_on; 2553 2554 void *proximity_priv; 2555 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, 2556 struct sk_buff *skb); 2557 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); 2558 }; 2559 2560 struct rtl_c2hcmd { 2561 struct list_head list; 2562 u8 tag; 2563 u8 len; 2564 u8 *val; 2565 }; 2566 2567 struct rtl_priv { 2568 struct ieee80211_hw *hw; 2569 struct completion firmware_loading_complete; 2570 struct list_head list; 2571 struct rtl_priv *buddy_priv; 2572 struct rtl_global_var *glb_var; 2573 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; 2574 struct rtl_dmsp_ctl dmsp_ctl; 2575 struct rtl_locks locks; 2576 struct rtl_works works; 2577 struct rtl_mac mac80211; 2578 struct rtl_hal rtlhal; 2579 struct rtl_regulatory regd; 2580 struct rtl_rfkill rfkill; 2581 struct rtl_io io; 2582 struct rtl_phy phy; 2583 struct rtl_dm dm; 2584 struct rtl_security sec; 2585 struct rtl_efuse efuse; 2586 struct rtl_led_ctl ledctl; 2587 2588 struct rtl_ps_ctl psc; 2589 struct rate_adaptive ra; 2590 struct dynamic_primary_cca primarycca; 2591 struct wireless_stats stats; 2592 struct rt_link_detect link_info; 2593 struct false_alarm_statistics falsealm_cnt; 2594 2595 struct rtl_rate_priv *rate_priv; 2596 2597 /* sta entry list for ap adhoc or mesh */ 2598 struct list_head entry_list; 2599 2600 /* c2hcmd list for kthread level access */ 2601 struct list_head c2hcmd_list; 2602 2603 int max_fw_size; 2604 2605 /* 2606 *hal_cfg : for diff cards 2607 *intf_ops : for diff interrface usb/pcie 2608 */ 2609 struct rtl_hal_cfg *cfg; 2610 const struct rtl_intf_ops *intf_ops; 2611 2612 /*this var will be set by set_bit, 2613 and was used to indicate status of 2614 interface or hardware */ 2615 unsigned long status; 2616 2617 /* tables for dm */ 2618 struct dig_t dm_digtable; 2619 struct ps_t dm_pstable; 2620 2621 u32 reg_874; 2622 u32 reg_c70; 2623 u32 reg_85c; 2624 u32 reg_a74; 2625 bool reg_init; /* true if regs saved */ 2626 bool bt_operation_on; 2627 __le32 *usb_data; 2628 int usb_data_index; 2629 bool initialized; 2630 bool enter_ps; /* true when entering PS */ 2631 u8 rate_mask[5]; 2632 2633 /* intel Proximity, should be alloc mem 2634 * in intel Proximity module and can only 2635 * be used in intel Proximity mode 2636 */ 2637 struct proxim proximity; 2638 2639 /*for bt coexist use*/ 2640 struct bt_coexist_info btcoexist; 2641 2642 /* separate 92ee from other ICs, 2643 * 92ee use new trx flow. 2644 */ 2645 bool use_new_trx_flow; 2646 2647 #ifdef CONFIG_PM 2648 struct wiphy_wowlan_support wowlan; 2649 #endif 2650 /*This must be the last item so 2651 that it points to the data allocated 2652 beyond this structure like: 2653 rtl_pci_priv or rtl_usb_priv */ 2654 u8 priv[0] __aligned(sizeof(void *)); 2655 }; 2656 2657 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) 2658 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) 2659 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) 2660 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 2661 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 2662 2663 2664 /*************************************** 2665 Bluetooth Co-existence Related 2666 ****************************************/ 2667 2668 enum bt_ant_num { 2669 ANT_X2 = 0, 2670 ANT_X1 = 1, 2671 }; 2672 2673 enum bt_co_type { 2674 BT_2WIRE = 0, 2675 BT_ISSC_3WIRE = 1, 2676 BT_ACCEL = 2, 2677 BT_CSR_BC4 = 3, 2678 BT_CSR_BC8 = 4, 2679 BT_RTL8756 = 5, 2680 BT_RTL8723A = 6, 2681 BT_RTL8821A = 7, 2682 BT_RTL8723B = 8, 2683 BT_RTL8192E = 9, 2684 BT_RTL8812A = 11, 2685 }; 2686 2687 enum bt_total_ant_num { 2688 ANT_TOTAL_X2 = 0, 2689 ANT_TOTAL_X1 = 1 2690 }; 2691 2692 enum bt_cur_state { 2693 BT_OFF = 0, 2694 BT_ON = 1, 2695 }; 2696 2697 enum bt_service_type { 2698 BT_SCO = 0, 2699 BT_A2DP = 1, 2700 BT_HID = 2, 2701 BT_HID_IDLE = 3, 2702 BT_SCAN = 4, 2703 BT_IDLE = 5, 2704 BT_OTHER_ACTION = 6, 2705 BT_BUSY = 7, 2706 BT_OTHERBUSY = 8, 2707 BT_PAN = 9, 2708 }; 2709 2710 enum bt_radio_shared { 2711 BT_RADIO_SHARED = 0, 2712 BT_RADIO_INDIVIDUAL = 1, 2713 }; 2714 2715 2716 /**************************************** 2717 mem access macro define start 2718 Call endian free function when 2719 1. Read/write packet content. 2720 2. Before write integer to IO. 2721 3. After read integer from IO. 2722 ****************************************/ 2723 /* Convert little data endian to host ordering */ 2724 #define EF1BYTE(_val) \ 2725 ((u8)(_val)) 2726 #define EF2BYTE(_val) \ 2727 (le16_to_cpu(_val)) 2728 #define EF4BYTE(_val) \ 2729 (le32_to_cpu(_val)) 2730 2731 /* Read data from memory */ 2732 #define READEF1BYTE(_ptr) \ 2733 EF1BYTE(*((u8 *)(_ptr))) 2734 /* Read le16 data from memory and convert to host ordering */ 2735 #define READEF2BYTE(_ptr) \ 2736 EF2BYTE(*(_ptr)) 2737 #define READEF4BYTE(_ptr) \ 2738 EF4BYTE(*(_ptr)) 2739 2740 /* Create a bit mask 2741 * Examples: 2742 * BIT_LEN_MASK_32(0) => 0x00000000 2743 * BIT_LEN_MASK_32(1) => 0x00000001 2744 * BIT_LEN_MASK_32(2) => 0x00000003 2745 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF 2746 */ 2747 #define BIT_LEN_MASK_32(__bitlen) \ 2748 (0xFFFFFFFF >> (32 - (__bitlen))) 2749 #define BIT_LEN_MASK_16(__bitlen) \ 2750 (0xFFFF >> (16 - (__bitlen))) 2751 #define BIT_LEN_MASK_8(__bitlen) \ 2752 (0xFF >> (8 - (__bitlen))) 2753 2754 /* Create an offset bit mask 2755 * Examples: 2756 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 2757 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 2758 */ 2759 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 2760 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 2761 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 2762 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) 2763 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ 2764 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 2765 2766 /*Description: 2767 * Return 4-byte value in host byte ordering from 2768 * 4-byte pointer in little-endian system. 2769 */ 2770 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 2771 (EF4BYTE(*((__le32 *)(__pstart)))) 2772 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 2773 (EF2BYTE(*((__le16 *)(__pstart)))) 2774 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 2775 (EF1BYTE(*((u8 *)(__pstart)))) 2776 2777 /*Description: 2778 Translate subfield (continuous bits in little-endian) of 4-byte 2779 value to host byte ordering.*/ 2780 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2781 ( \ 2782 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ 2783 BIT_LEN_MASK_32(__bitlen) \ 2784 ) 2785 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2786 ( \ 2787 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ 2788 BIT_LEN_MASK_16(__bitlen) \ 2789 ) 2790 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2791 ( \ 2792 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ 2793 BIT_LEN_MASK_8(__bitlen) \ 2794 ) 2795 2796 /* Description: 2797 * Mask subfield (continuous bits in little-endian) of 4-byte value 2798 * and return the result in 4-byte value in host byte ordering. 2799 */ 2800 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 2801 ( \ 2802 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 2803 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ 2804 ) 2805 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ 2806 ( \ 2807 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ 2808 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ 2809 ) 2810 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ 2811 ( \ 2812 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ 2813 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 2814 ) 2815 2816 /* Description: 2817 * Set subfield of little-endian 4-byte value to specified value. 2818 */ 2819 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2820 *((__le32 *)(__pstart)) = \ 2821 cpu_to_le32( \ 2822 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ 2823 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ 2824 ); 2825 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2826 *((__le16 *)(__pstart)) = \ 2827 cpu_to_le16( \ 2828 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ 2829 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ 2830 ); 2831 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 2832 *((u8 *)(__pstart)) = EF1BYTE \ 2833 ( \ 2834 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ 2835 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ 2836 ); 2837 2838 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ 2839 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) 2840 2841 /**************************************** 2842 mem access macro define end 2843 ****************************************/ 2844 2845 #define byte(x, n) ((x >> (8 * n)) & 0xff) 2846 2847 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 2848 #define RTL_WATCH_DOG_TIME 2000 2849 #define MSECS(t) msecs_to_jiffies(t) 2850 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) 2851 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) 2852 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) 2853 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) 2854 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) 2855 2856 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ 2857 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ 2858 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ 2859 /*NIC halt, re-initialize hw parameters*/ 2860 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) 2861 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ 2862 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 2863 /*Always enable ASPM and Clock Req in initialization.*/ 2864 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 2865 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ 2866 #define RT_PS_LEVEL_ASPM BIT(7) 2867 /*When LPS is on, disable 2R if no packet is received or transmittd.*/ 2868 #define RT_RF_LPS_DISALBE_2R BIT(30) 2869 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 2870 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ 2871 ((ppsc->cur_ps_level & _ps_flg) ? true : false) 2872 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ 2873 (ppsc->cur_ps_level &= (~(_ps_flg))) 2874 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ 2875 (ppsc->cur_ps_level |= _ps_flg) 2876 2877 #define container_of_dwork_rtl(x, y, z) \ 2878 container_of(to_delayed_work(x), y, z) 2879 2880 #define FILL_OCTET_STRING(_os, _octet, _len) \ 2881 (_os).octet = (u8 *)(_octet); \ 2882 (_os).length = (_len); 2883 2884 #define CP_MACADDR(des, src) \ 2885 ((des)[0] = (src)[0], (des)[1] = (src)[1],\ 2886 (des)[2] = (src)[2], (des)[3] = (src)[3],\ 2887 (des)[4] = (src)[4], (des)[5] = (src)[5]) 2888 2889 #define LDPC_HT_ENABLE_RX BIT(0) 2890 #define LDPC_HT_ENABLE_TX BIT(1) 2891 #define LDPC_HT_TEST_TX_ENABLE BIT(2) 2892 #define LDPC_HT_CAP_TX BIT(3) 2893 2894 #define STBC_HT_ENABLE_RX BIT(0) 2895 #define STBC_HT_ENABLE_TX BIT(1) 2896 #define STBC_HT_TEST_TX_ENABLE BIT(2) 2897 #define STBC_HT_CAP_TX BIT(3) 2898 2899 #define LDPC_VHT_ENABLE_RX BIT(0) 2900 #define LDPC_VHT_ENABLE_TX BIT(1) 2901 #define LDPC_VHT_TEST_TX_ENABLE BIT(2) 2902 #define LDPC_VHT_CAP_TX BIT(3) 2903 2904 #define STBC_VHT_ENABLE_RX BIT(0) 2905 #define STBC_VHT_ENABLE_TX BIT(1) 2906 #define STBC_VHT_TEST_TX_ENABLE BIT(2) 2907 #define STBC_VHT_CAP_TX BIT(3) 2908 2909 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G]; 2910 2911 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M]; 2912 2913 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 2914 { 2915 return rtlpriv->io.read8_sync(rtlpriv, addr); 2916 } 2917 2918 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) 2919 { 2920 return rtlpriv->io.read16_sync(rtlpriv, addr); 2921 } 2922 2923 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) 2924 { 2925 return rtlpriv->io.read32_sync(rtlpriv, addr); 2926 } 2927 2928 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) 2929 { 2930 rtlpriv->io.write8_async(rtlpriv, addr, val8); 2931 2932 if (rtlpriv->cfg->write_readback) 2933 rtlpriv->io.read8_sync(rtlpriv, addr); 2934 } 2935 2936 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) 2937 { 2938 rtlpriv->io.write16_async(rtlpriv, addr, val16); 2939 2940 if (rtlpriv->cfg->write_readback) 2941 rtlpriv->io.read16_sync(rtlpriv, addr); 2942 } 2943 2944 static inline void rtl_write_dword(struct rtl_priv *rtlpriv, 2945 u32 addr, u32 val32) 2946 { 2947 rtlpriv->io.write32_async(rtlpriv, addr, val32); 2948 2949 if (rtlpriv->cfg->write_readback) 2950 rtlpriv->io.read32_sync(rtlpriv, addr); 2951 } 2952 2953 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, 2954 u32 regaddr, u32 bitmask) 2955 { 2956 struct rtl_priv *rtlpriv = hw->priv; 2957 2958 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); 2959 } 2960 2961 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, 2962 u32 bitmask, u32 data) 2963 { 2964 struct rtl_priv *rtlpriv = hw->priv; 2965 2966 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); 2967 } 2968 2969 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, 2970 enum radio_path rfpath, u32 regaddr, 2971 u32 bitmask) 2972 { 2973 struct rtl_priv *rtlpriv = hw->priv; 2974 2975 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); 2976 } 2977 2978 static inline void rtl_set_rfreg(struct ieee80211_hw *hw, 2979 enum radio_path rfpath, u32 regaddr, 2980 u32 bitmask, u32 data) 2981 { 2982 struct rtl_priv *rtlpriv = hw->priv; 2983 2984 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); 2985 } 2986 2987 static inline bool is_hal_stop(struct rtl_hal *rtlhal) 2988 { 2989 return (_HAL_STATE_STOP == rtlhal->state); 2990 } 2991 2992 static inline void set_hal_start(struct rtl_hal *rtlhal) 2993 { 2994 rtlhal->state = _HAL_STATE_START; 2995 } 2996 2997 static inline void set_hal_stop(struct rtl_hal *rtlhal) 2998 { 2999 rtlhal->state = _HAL_STATE_STOP; 3000 } 3001 3002 static inline u8 get_rf_type(struct rtl_phy *rtlphy) 3003 { 3004 return rtlphy->rf_type; 3005 } 3006 3007 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) 3008 { 3009 return (struct ieee80211_hdr *)(skb->data); 3010 } 3011 3012 static inline __le16 rtl_get_fc(struct sk_buff *skb) 3013 { 3014 return rtl_get_hdr(skb)->frame_control; 3015 } 3016 3017 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) 3018 { 3019 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; 3020 } 3021 3022 static inline u16 rtl_get_tid(struct sk_buff *skb) 3023 { 3024 return rtl_get_tid_h(rtl_get_hdr(skb)); 3025 } 3026 3027 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 3028 struct ieee80211_vif *vif, 3029 const u8 *bssid) 3030 { 3031 return ieee80211_find_sta(vif, bssid); 3032 } 3033 3034 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, 3035 u8 *mac_addr) 3036 { 3037 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3038 return ieee80211_find_sta(mac->vif, mac_addr); 3039 } 3040 3041 #endif 3042