1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL8821AE_PWRSEQ_H__ 27 #define __RTL8821AE_PWRSEQ_H__ 28 29 #include "../pwrseqcmd.h" 30 #include "../btcoexist/halbt_precomp.h" 31 32 #define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15 33 #define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15 34 #define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15 35 #define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15 36 #define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 25 37 #define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15 38 #define RTL8812_TRANS_ACT_TO_LPS_STEPS 15 39 #define RTL8812_TRANS_LPS_TO_ACT_STEPS 15 40 #define RTL8812_TRANS_END_STEPS 1 41 42 /* The following macros have the following format: 43 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value 44 * comments }, 45 */ 46 #define RTL8812_TRANS_CARDEMU_TO_ACT \ 47 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 48 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ 49 /* disable SW LPS 0x04[10]=0*/}, \ 50 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 51 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \ 52 /* wait till 0x04[17] = 1 power ready*/}, \ 53 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 54 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 55 /* disable HWPDN 0x04[15]=0*/}, \ 56 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 58 /* disable WL suspend*/}, \ 59 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 60 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 61 /* polling until return 0*/}, \ 62 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, 64 65 #define RTL8812_TRANS_ACT_TO_CARDEMU \ 66 {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 67 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \ 68 /* 0xc00[7:0] = 4 turn off 3-wire */}, \ 69 {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \ 71 /* 0xe00[7:0] = 4 turn off 3-wire */}, \ 72 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 74 /* 0x2[0] = 0 RESET BB, CLOSE RF */}, \ 75 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 76 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \ 77 /*Delay 1us*/}, \ 78 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 80 /* Whole BB is reset*/}, \ 81 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \ 83 /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/}, \ 84 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \ 86 /*0x8[1] = 0 ANA clk =500k */}, \ 87 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 89 /*0x04[9] = 1 turn off MAC by HW state machine*/}, \ 90 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \ 92 /*wait till 0x04[9] = 0 polling until return 0 to disable*/}, 93 94 #define RTL8812_TRANS_CARDEMU_TO_SUS \ 95 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xc0}, \ 97 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xE0}, \ 99 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 100 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \ 101 /* gpio11 input mode, gpio10~8 output mode */}, \ 102 {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 104 /* gpio 0~7 output same value as input ?? */}, \ 105 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \ 107 /* gpio0~7 output mode */}, \ 108 {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 110 /* 0x47[7:0] = 00 gpio mode */}, \ 111 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 113 /* suspend option all off */}, \ 114 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \ 116 /*0x14[7] = 1 turn on ZCD */}, \ 117 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \ 119 /* 0x15[0] =1 trun on ZCD */}, \ 120 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \ 122 /*0x23[4] = 1 hpon LDO sleep mode */}, \ 123 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \ 125 /*0x8[1] = 0 ANA clk =500k */}, \ 126 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ 128 /*0x04[11] = 2b'11 enable WL suspend for PCIe*/}, 129 130 #define RTL8812_TRANS_SUS_TO_CARDEMU \ 131 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 133 /*0x04[11] = 2b'01enable WL suspend*/}, \ 134 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 135 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \ 136 /*0x23[4] = 0 hpon LDO sleep mode leave */}, \ 137 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \ 139 /* 0x15[0] =0 trun off ZCD */}, \ 140 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 141 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \ 142 /*0x14[7] = 0 turn off ZCD */}, \ 143 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 144 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 145 /* gpio0~7 input mode */}, \ 146 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 147 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 148 /* gpio11 input mode, gpio10~8 input mode */}, 149 150 #define RTL8812_TRANS_CARDEMU_TO_CARDDIS \ 151 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ 153 /*0x03[2] = 0, reset 8051*/}, \ 154 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \ 156 /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/}, \ 157 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \ 159 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 160 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \ 161 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 162 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \ 163 /* gpio11 input mode, gpio10~8 output mode */}, \ 164 {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 165 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 166 /* gpio 0~7 output same value as input ?? */}, \ 167 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 168 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \ 169 /* gpio0~7 output mode */}, \ 170 {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 172 /* 0x47[7:0] = 00 gpio mode */}, \ 173 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \ 175 /*0x14[7] = 1 turn on ZCD */}, \ 176 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \ 178 /* 0x15[0] =1 trun on ZCD */}, \ 179 {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \ 181 /*0x12[0] = 0 force PFM mode */}, \ 182 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \ 184 /*0x23[4] = 1 hpon LDO sleep mode */}, \ 185 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 186 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \ 187 /*0x8[1] = 0 ANA clk =500k */}, \ 188 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 189 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \ 190 /*0x07=0x20 , SOP option to disable BG/MB*/}, \ 191 {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 192 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 193 /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */}, \ 194 {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 196 /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */}, \ 197 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 198 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \ 199 /*0x04[11] = 2b'01 enable WL suspend*/}, 200 201 #define RTL8812_TRANS_CARDDIS_TO_CARDEMU \ 202 {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 203 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 204 /*0x12[0] = 1 force PWM mode */}, \ 205 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \ 207 /*0x14[7] = 0 turn off ZCD */}, \ 208 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \ 210 /* 0x15[0] =0 trun off ZCD */}, \ 211 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 212 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \ 213 /*0x23[4] = 0 hpon LDO leave sleep mode */}, \ 214 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 215 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 216 /* gpio0~7 input mode */}, \ 217 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 219 /* gpio11 input mode, gpio10~8 input mode */}, \ 220 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ 222 /*0x04[10] = 0, enable SW LPS PCIE only*/}, \ 223 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \ 225 /*0x04[11] = 2b'01enable WL suspend*/}, \ 226 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \ 228 /*0x03[2] = 1, enable 8051*/}, \ 229 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 231 /*PCIe DMA start*/}, 232 233 #define RTL8812_TRANS_CARDEMU_TO_PDN \ 234 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \ 236 /* 0x04[15] = 1*/}, 237 238 #define RTL8812_TRANS_PDN_TO_CARDEMU \ 239 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 241 /* 0x04[15] = 0*/}, 242 243 #define RTL8812_TRANS_ACT_TO_LPS \ 244 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 245 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \ 246 /*PCIe DMA stop*/}, \ 247 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \ 249 /*Tx Pause*/}, \ 250 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 251 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 252 /*Should be zero if no packet is transmitting*/}, \ 253 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 254 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 255 /*Should be zero if no packet is transmitting*/}, \ 256 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 257 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 258 /*Should be zero if no packet is transmitting*/}, \ 259 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 260 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 261 /*Should be zero if no packet is transmitting*/}, \ 262 {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 263 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \ 264 /* 0xc00[7:0] = 4 turn off 3-wire */}, \ 265 {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \ 267 /* 0xe00[7:0] = 4 turn off 3-wire */}, \ 268 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 270 /*CCK and OFDM are disabled,and clock are gated,and RF closed*/}, \ 271 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 272 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \ 273 /*Delay 1us*/}, \ 274 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 275 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 276 /* Whole BB is reset*/}, \ 277 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 278 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \ 279 /*Reset MAC TRX*/}, \ 280 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 281 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 282 /*check if removed later*/}, \ 283 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 284 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \ 285 /*Respond TxOK to scheduler*/}, 286 287 #define RTL8812_TRANS_LPS_TO_ACT \ 288 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 289 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \ 290 /*SDIO RPWM*/}, \ 291 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \ 293 /*USB RPWM*/}, \ 294 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 295 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \ 296 /*PCIe RPWM*/}, \ 297 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 298 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \ 299 /*Delay*/}, \ 300 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ 302 /*. 0x08[4] = 0 switch TSF to 40M*/}, \ 303 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 304 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \ 305 /*Polling 0x109[7]=0 TSF in 40M*/}, \ 306 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ 308 /*. 0x29[7:6] = 2b'00 enable BB clock*/}, \ 309 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 311 /*. 0x101[1] = 1*/}, \ 312 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 313 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \ 314 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/}, \ 315 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ 317 /*. 0x02[1:0] = 2b'11 enable BB macro*/}, \ 318 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 319 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 320 /*. 0x522 = 0*/}, 321 322 #define RTL8812_TRANS_END \ 323 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 324 0, PWR_CMD_END, 0, 0}, 325 326 extern struct wlan_pwr_cfg rtl8812_power_on_flow 327 [RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + 328 RTL8812_TRANS_END_STEPS]; 329 extern struct wlan_pwr_cfg rtl8812_radio_off_flow 330 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + 331 RTL8812_TRANS_END_STEPS]; 332 extern struct wlan_pwr_cfg rtl8812_card_disable_flow 333 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + 334 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + 335 RTL8812_TRANS_END_STEPS]; 336 extern struct wlan_pwr_cfg rtl8812_card_enable_flow 337 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + 338 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + 339 RTL8812_TRANS_END_STEPS]; 340 extern struct wlan_pwr_cfg rtl8812_suspend_flow 341 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + 342 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + 343 RTL8812_TRANS_END_STEPS]; 344 extern struct wlan_pwr_cfg rtl8812_resume_flow 345 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + 346 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + 347 RTL8812_TRANS_END_STEPS]; 348 extern struct wlan_pwr_cfg rtl8812_hwpdn_flow 349 [RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + 350 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + 351 RTL8812_TRANS_END_STEPS]; 352 extern struct wlan_pwr_cfg rtl8812_enter_lps_flow 353 [RTL8812_TRANS_ACT_TO_LPS_STEPS + 354 RTL8812_TRANS_END_STEPS]; 355 extern struct wlan_pwr_cfg rtl8812_leave_lps_flow 356 [RTL8812_TRANS_LPS_TO_ACT_STEPS + 357 RTL8812_TRANS_END_STEPS]; 358 359 /* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd 360 * There are 6 HW Power States: 361 * 0: POFF--Power Off 362 * 1: PDN--Power Down 363 * 2: CARDEMU--Card Emulation 364 * 3: ACT--Active Mode 365 * 4: LPS--Low Power State 366 * 5: SUS--Suspend 367 * 368 * The transision from different states are defined below 369 * TRANS_CARDEMU_TO_ACT 370 * TRANS_ACT_TO_CARDEMU 371 * TRANS_CARDEMU_TO_SUS 372 * TRANS_SUS_TO_CARDEMU 373 * TRANS_CARDEMU_TO_PDN 374 * TRANS_ACT_TO_LPS 375 * TRANS_LPS_TO_ACT 376 * 377 * TRANS_END 378 */ 379 #define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25 380 #define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15 381 #define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15 382 #define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15 383 #define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15 384 #define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15 385 #define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15 386 #define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15 387 #define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15 388 #define RTL8821A_TRANS_END_STEPS 1 389 390 #define RTL8821A_TRANS_CARDEMU_TO_ACT \ 391 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 392 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 393 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 394 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/}, \ 395 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 396 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ 398 /*0x67[0] = 0 to disable BT_GPS_SEL pins*/}, \ 399 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 400 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 401 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \ 402 /*Delay 1ms*/}, \ 403 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 404 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 405 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \ 406 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/}, \ 407 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ 409 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/}, \ 410 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 411 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \ 412 /* Disable USB suspend */}, \ 413 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 414 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \ 415 /* wait till 0x04[17] = 1 power ready*/}, \ 416 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 417 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \ 418 /* Enable USB suspend */}, \ 419 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 421 /* release WLON reset 0x04[16]=1*/}, \ 422 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 424 /* disable HWPDN 0x04[15]=0*/}, \ 425 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \ 427 /* disable WL suspend*/}, \ 428 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 429 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 430 /* polling until return 0*/}, \ 431 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 432 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \ 433 /**/}, \ 434 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 435 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 436 /*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */},\ 437 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \ 439 /*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A \ 440 from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */},\ 441 {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 442 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \ 443 /*anapar_mac<118> , 0x25[6]=0 by wlan single function*/},\ 444 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 445 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 446 /*Enable falling edge triggering interrupt*/},\ 447 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 448 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 449 /*Enable GPIO9 interrupt mode*/},\ 450 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 451 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 452 /*Enable GPIO9 input mode*/},\ 453 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 454 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \ 455 /*Enable HSISR GPIO[C:0] interrupt*/},\ 456 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 457 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 458 /*Enable HSISR GPIO9 interrupt*/},\ 459 {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 460 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \ 461 /*0x7A = 0x3A start BT*/},\ 462 {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 463 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 \ 464 /* 0x2C[23:12]=0x820 ; XTAL trim */}, \ 465 {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \ 467 /* 0x10[6]=1 */}, 468 469 #define RTL8821A_TRANS_ACT_TO_CARDEMU \ 470 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 471 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 472 /*0x1F[7:0] = 0 turn off RF*/}, \ 473 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 474 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 475 /*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from \ 476 register 0x65[2] */},\ 477 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 478 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 479 /*Enable rising edge triggering interrupt*/}, \ 480 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 481 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 482 /*0x04[9] = 1 turn off MAC by HW state machine*/}, \ 483 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 484 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \ 485 /*wait till 0x04[9] = 0 polling until return 0 to disable*/}, \ 486 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 487 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \ 489 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/}, \ 490 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 491 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 492 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 493 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/}, 494 495 #define RTL8821A_TRANS_CARDEMU_TO_SUS \ 496 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \ 498 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/}, \ 499 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 500 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 501 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \ 502 /*0x04[12:11] = 2b'01 enable WL suspend*/}, \ 503 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 504 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \ 505 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \ 506 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 507 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \ 508 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/}, \ 509 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 510 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \ 511 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/}, \ 512 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 513 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \ 514 /*Set SDIO suspend local register*/}, \ 515 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 516 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \ 517 /*wait power state to suspend*/}, 518 519 #define RTL8821A_TRANS_SUS_TO_CARDEMU \ 520 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 521 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \ 522 /*clear suspend enable and power down enable*/}, \ 523 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 524 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \ 525 /*Set SDIO suspend local register*/}, \ 526 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 527 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \ 528 /*wait power state to suspend*/},\ 529 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 530 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ 531 /*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \ 532 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 533 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \ 534 /*0x04[12:11] = 2b'01enable WL suspend*/}, 535 536 #define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \ 537 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 538 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \ 539 /*0x07=0x20 , SOP option to disable BG/MB*/}, \ 540 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 541 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\ 542 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \ 543 /*0x04[12:11] = 2b'01 enable WL suspend*/}, \ 544 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 545 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \ 546 /*0x04[10] = 1, enable SW LPS*/}, \ 547 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 548 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \ 549 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/}, \ 550 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 551 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \ 552 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \ 553 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 554 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \ 555 /*Set SDIO suspend local register*/}, \ 556 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 557 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \ 558 /*wait power state to suspend*/}, 559 560 #define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \ 561 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 562 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \ 563 /*clear suspend enable and power down enable*/}, \ 564 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 565 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \ 566 /*Set SDIO suspend local register*/}, \ 567 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 568 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \ 569 /*wait power state to suspend*/},\ 570 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 571 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 572 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/}, \ 573 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 574 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \ 575 /*0x04[12:11] = 2b'01enable WL suspend*/},\ 576 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 577 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ 578 /*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \ 579 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 580 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 581 /*PCIe DMA start*/}, 582 583 #define RTL8821A_TRANS_CARDEMU_TO_PDN \ 584 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 585 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \ 586 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/}, \ 587 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 588 PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,\ 589 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \ 590 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/}, \ 591 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 592 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 593 /* 0x04[16] = 0*/},\ 594 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 595 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \ 596 /* 0x04[15] = 1*/}, 597 598 #define RTL8821A_TRANS_PDN_TO_CARDEMU \ 599 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 600 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \ 601 /* 0x04[15] = 0*/}, 602 603 #define RTL8821A_TRANS_ACT_TO_LPS \ 604 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 605 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \ 606 /*PCIe DMA stop*/}, \ 607 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 608 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \ 609 /*Tx Pause*/}, \ 610 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 611 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 612 /*Should be zero if no packet is transmitting*/}, \ 613 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 614 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 615 /*Should be zero if no packet is transmitting*/}, \ 616 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 617 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 618 /*Should be zero if no packet is transmitting*/}, \ 619 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 620 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \ 621 /*Should be zero if no packet is transmitting*/}, \ 622 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 623 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \ 624 /*CCK and OFDM are disabled,and clock are gated*/}, \ 625 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 626 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \ 627 /*Delay 1us*/}, \ 628 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 629 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 630 /*Whole BB is reset*/}, \ 631 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 632 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \ 633 /*Reset MAC TRX*/}, \ 634 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 635 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 636 /*check if removed later*/}, \ 637 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 638 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \ 639 /*When driver enter Sus/ Disable, enable LOP for BT*/}, \ 640 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 641 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \ 642 /*Respond TxOK to scheduler*/}, 643 644 #define RTL8821A_TRANS_LPS_TO_ACT \ 645 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 646 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \ 647 /*SDIO RPWM*/},\ 648 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\ 649 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \ 650 /*USB RPWM*/},\ 651 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 652 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \ 653 /*PCIe RPWM*/},\ 654 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 655 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \ 656 /*Delay*/},\ 657 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 658 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \ 659 /*. 0x08[4] = 0 switch TSF to 40M*/},\ 660 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 661 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \ 662 /*Polling 0x109[7]=0 TSF in 40M*/},\ 663 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \ 665 /*. 0x29[7:6] = 2b'00 enable BB clock*/},\ 666 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 667 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 668 /*. 0x101[1] = 1*/},\ 669 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 670 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \ 671 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/},\ 672 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 673 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ 674 /*. 0x02[1:0] = 2b'11 enable BB macro*/},\ 675 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 676 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \ 677 /*. 0x522 = 0*/}, 678 679 #define RTL8821A_TRANS_END \ 680 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 681 0, PWR_CMD_END, 0, 0}, 682 683 extern struct wlan_pwr_cfg rtl8821A_power_on_flow 684 [RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + 685 RTL8821A_TRANS_END_STEPS]; 686 extern struct wlan_pwr_cfg rtl8821A_radio_off_flow 687 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + 688 RTL8821A_TRANS_END_STEPS]; 689 extern struct wlan_pwr_cfg rtl8821A_card_disable_flow 690 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + 691 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + 692 RTL8821A_TRANS_END_STEPS]; 693 extern struct wlan_pwr_cfg rtl8821A_card_enable_flow 694 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + 695 RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + 696 RTL8821A_TRANS_END_STEPS]; 697 extern struct wlan_pwr_cfg rtl8821A_suspend_flow 698 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + 699 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + 700 RTL8821A_TRANS_END_STEPS]; 701 extern struct wlan_pwr_cfg rtl8821A_resume_flow 702 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + 703 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + 704 RTL8821A_TRANS_END_STEPS]; 705 extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow 706 [RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + 707 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + 708 RTL8821A_TRANS_END_STEPS]; 709 extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow 710 [RTL8821A_TRANS_ACT_TO_LPS_STEPS + 711 RTL8821A_TRANS_END_STEPS]; 712 extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow 713 [RTL8821A_TRANS_LPS_TO_ACT_STEPS + 714 RTL8821A_TRANS_END_STEPS]; 715 716 /*RTL8812 Power Configuration CMDs for PCIe interface*/ 717 #define RTL8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow 718 #define RTL8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow 719 #define RTL8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow 720 #define RTL8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow 721 #define RTL8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow 722 #define RTL8812_NIC_RESUME_FLOW rtl8812_resume_flow 723 #define RTL8812_NIC_PDN_FLOW rtl8812_hwpdn_flow 724 #define RTL8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow 725 #define RTL8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow 726 727 /* RTL8821 Power Configuration CMDs for PCIe interface */ 728 #define RTL8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow 729 #define RTL8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow 730 #define RTL8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow 731 #define RTL8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow 732 #define RTL8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow 733 #define RTL8821A_NIC_RESUME_FLOW rtl8821A_resume_flow 734 #define RTL8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow 735 #define RTL8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow 736 #define RTL8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow 737 738 #endif 739