1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "rf.h"
11 #include "dm.h"
12 #include "table.h"
13 #include "trx.h"
14 #include "../btcoexist/halbt_precomp.h"
15 #include "hw.h"
16 #include "../efuse.h"
17 
18 #define READ_NEXT_PAIR(array_table, v1, v2, i) \
19 	do { \
20 		i += 2; \
21 		v1 = array_table[i]; \
22 		v2 = array_table[i+1]; \
23 	} while (0)
24 
25 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
26 					 enum radio_path rfpath, u32 offset);
27 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
28 					   enum radio_path rfpath, u32 offset,
29 					   u32 data);
30 static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask)
31 {
32 	u32 i = ffs(bitmask);
33 
34 	return i ? i - 1 : 32;
35 }
36 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
37 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/
38 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
39 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
40 						     u8 configtype);
41 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
42 						       u8 configtype);
43 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
44 
45 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
46 					    enum wireless_mode wirelessmode,
47 					    u8 txpwridx);
48 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
49 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
50 
51 static void rtl8812ae_fixspur(struct ieee80211_hw *hw,
52 			      enum ht_channel_width band_width, u8 channel)
53 {
54 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
55 
56 	/*C cut Item12 ADC FIFO CLOCK*/
57 	if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) {
58 		if (band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11)
59 			rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3);
60 			/* 0x8AC[11:10] = 2'b11*/
61 		else
62 			rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
63 			/* 0x8AC[11:10] = 2'b10*/
64 
65 		/* <20120914, Kordan> A workarould to resolve
66 		 * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)
67 		 */
68 		if (band_width == HT_CHANNEL_WIDTH_20 &&
69 		    (channel == 13 || channel == 14)) {
70 			rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
71 			/*0x8AC[9:8] = 2'b11*/
72 			rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
73 			/* 0x8C4[30] = 1*/
74 		} else if (band_width == HT_CHANNEL_WIDTH_20_40 &&
75 			   channel == 11) {
76 			rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
77 			/*0x8C4[30] = 1*/
78 		} else if (band_width != HT_CHANNEL_WIDTH_80) {
79 			rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
80 			/*0x8AC[9:8] = 2'b10*/
81 			rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
82 			/*0x8C4[30] = 0*/
83 		}
84 	} else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
85 		/* <20120914, Kordan> A workarould to resolve
86 		 * 2480Mhz spur by setting ADC clock as 160M.
87 		 */
88 		if (band_width == HT_CHANNEL_WIDTH_20 &&
89 		    (channel == 13 || channel == 14))
90 			rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
91 			/*0x8AC[9:8] = 11*/
92 		else if (channel  <= 14) /*2.4G only*/
93 			rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
94 			/*0x8AC[9:8] = 10*/
95 	}
96 }
97 
98 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
99 			       u32 bitmask)
100 {
101 	struct rtl_priv *rtlpriv = rtl_priv(hw);
102 	u32 returnvalue, originalvalue, bitshift;
103 
104 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
105 		"regaddr(%#x), bitmask(%#x)\n",
106 		regaddr, bitmask);
107 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
108 	bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
109 	returnvalue = (originalvalue & bitmask) >> bitshift;
110 
111 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
112 		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
113 		bitmask, regaddr, originalvalue);
114 	return returnvalue;
115 }
116 
117 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
118 			      u32 regaddr, u32 bitmask, u32 data)
119 {
120 	struct rtl_priv *rtlpriv = rtl_priv(hw);
121 	u32 originalvalue, bitshift;
122 
123 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
124 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
125 		regaddr, bitmask, data);
126 
127 	if (bitmask != MASKDWORD) {
128 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
129 		bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
130 		data = ((originalvalue & (~bitmask)) |
131 			((data << bitshift) & bitmask));
132 	}
133 
134 	rtl_write_dword(rtlpriv, regaddr, data);
135 
136 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
137 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
138 		regaddr, bitmask, data);
139 }
140 
141 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
142 			       enum radio_path rfpath, u32 regaddr,
143 			       u32 bitmask)
144 {
145 	struct rtl_priv *rtlpriv = rtl_priv(hw);
146 	u32 original_value, readback_value, bitshift;
147 
148 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
149 		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
150 		regaddr, rfpath, bitmask);
151 
152 	spin_lock(&rtlpriv->locks.rf_lock);
153 
154 	original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
155 	bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
156 	readback_value = (original_value & bitmask) >> bitshift;
157 
158 	spin_unlock(&rtlpriv->locks.rf_lock);
159 
160 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
161 		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
162 		regaddr, rfpath, bitmask, original_value);
163 
164 	return readback_value;
165 }
166 
167 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
168 			   enum radio_path rfpath,
169 			   u32 regaddr, u32 bitmask, u32 data)
170 {
171 	struct rtl_priv *rtlpriv = rtl_priv(hw);
172 	u32 original_value, bitshift;
173 
174 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
175 		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
176 		regaddr, bitmask, data, rfpath);
177 
178 	spin_lock(&rtlpriv->locks.rf_lock);
179 
180 	if (bitmask != RFREG_OFFSET_MASK) {
181 		original_value =
182 		   _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr);
183 		bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
184 		data = ((original_value & (~bitmask)) | (data << bitshift));
185 	}
186 
187 	_rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data);
188 
189 	spin_unlock(&rtlpriv->locks.rf_lock);
190 
191 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
192 		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
193 		 regaddr, bitmask, data, rfpath);
194 }
195 
196 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
197 					 enum radio_path rfpath, u32 offset)
198 {
199 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200 	bool is_pi_mode = false;
201 	u32 retvalue = 0;
202 
203 	/* 2009/06/17 MH We can not execute IO for power
204 	save or other accident mode.*/
205 	if (RT_CANNOT_IO(hw)) {
206 		pr_err("return all one\n");
207 		return 0xFFFFFFFF;
208 	}
209 	/* <20120809, Kordan> CCA OFF(when entering),
210 		asked by James to avoid reading the wrong value.
211 	    <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
212 	if (offset != 0x0 &&
213 	    !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
214 	    (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
215 		rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
216 	offset &= 0xff;
217 
218 	if (rfpath == RF90_PATH_A)
219 		is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4);
220 	else if (rfpath == RF90_PATH_B)
221 		is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4);
222 
223 	rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
224 
225 	if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
226 	    (IS_VENDOR_8812A_C_CUT(rtlhal->version)))
227 		udelay(20);
228 
229 	if (is_pi_mode) {
230 		if (rfpath == RF90_PATH_A)
231 			retvalue =
232 			  rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA);
233 		else if (rfpath == RF90_PATH_B)
234 			retvalue =
235 			  rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA);
236 	} else {
237 		if (rfpath == RF90_PATH_A)
238 			retvalue =
239 			  rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA);
240 		else if (rfpath == RF90_PATH_B)
241 			retvalue =
242 			  rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA);
243 	}
244 
245 	/*<20120809, Kordan> CCA ON(when exiting),
246 	 * asked by James to avoid reading the wrong value.
247 	 *   <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!
248 	 */
249 	if (offset != 0x0 &&
250 	    !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
251 	    (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
252 		rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
253 	return retvalue;
254 }
255 
256 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
257 					   enum radio_path rfpath, u32 offset,
258 					   u32 data)
259 {
260 	struct rtl_priv *rtlpriv = rtl_priv(hw);
261 	struct rtl_phy *rtlphy = &rtlpriv->phy;
262 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
263 	u32 data_and_addr;
264 	u32 newoffset;
265 
266 	if (RT_CANNOT_IO(hw)) {
267 		pr_err("stop\n");
268 		return;
269 	}
270 	offset &= 0xff;
271 	newoffset = offset;
272 	data_and_addr = ((newoffset << 20) |
273 			 (data & 0x000fffff)) & 0x0fffffff;
274 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
275 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
276 		"RFW-%d Addr[0x%x]=0x%x\n",
277 		rfpath, pphyreg->rf3wire_offset, data_and_addr);
278 }
279 
280 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw)
281 {
282 	bool rtstatus = 0;
283 
284 	rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw);
285 
286 	return rtstatus;
287 }
288 
289 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw)
290 {
291 	bool rtstatus = true;
292 	struct rtl_priv *rtlpriv = rtl_priv(hw);
293 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
294 	struct rtl_phy *rtlphy = &rtlpriv->phy;
295 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
296 	u8 regval;
297 	u8 crystal_cap;
298 
299 	phy_init_bb_rf_register_definition(hw);
300 
301 	regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
302 	regval |= FEN_PCIEA;
303 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);
304 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
305 		       regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);
306 
307 	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7);
308 	rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7);
309 
310 	rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw);
311 
312 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
313 		crystal_cap = rtlefuse->crystalcap & 0x3F;
314 		rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000,
315 			      (crystal_cap | (crystal_cap << 6)));
316 	} else {
317 		crystal_cap = rtlefuse->crystalcap & 0x3F;
318 		rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
319 			      (crystal_cap | (crystal_cap << 6)));
320 	}
321 	rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);
322 
323 	return rtstatus;
324 }
325 
326 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw)
327 {
328 	return rtl8821ae_phy_rf6052_config(hw);
329 }
330 
331 static void _rtl8812ae_phy_set_rfe_reg_24g(struct ieee80211_hw *hw)
332 {
333 	struct rtl_priv *rtlpriv = rtl_priv(hw);
334 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
335 	u8 tmp;
336 
337 	switch (rtlhal->rfe_type) {
338 	case 3:
339 		rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337770);
340 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337770);
341 		rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
342 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
343 		rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
344 		break;
345 	case 4:
346 		rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
347 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
348 		rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x001);
349 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x001);
350 		break;
351 	case 5:
352 		rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x77);
353 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
354 		tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3);
355 		rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp & ~0x1);
356 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
357 		break;
358 	case 1:
359 		if (rtlpriv->btcoexist.bt_coexistence) {
360 			rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x777777);
361 			rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
362 				      0x77777777);
363 			rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
364 			rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
365 			break;
366 		}
367 		fallthrough;
368 	case 0:
369 	case 2:
370 	default:
371 		rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
372 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
373 		rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
374 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
375 		break;
376 	}
377 }
378 
379 static void _rtl8812ae_phy_set_rfe_reg_5g(struct ieee80211_hw *hw)
380 {
381 	struct rtl_priv *rtlpriv = rtl_priv(hw);
382 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
383 	u8 tmp;
384 
385 	switch (rtlhal->rfe_type) {
386 	case 0:
387 		rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337717);
388 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337717);
389 		rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
390 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
391 		break;
392 	case 1:
393 		if (rtlpriv->btcoexist.bt_coexistence) {
394 			rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x337717);
395 			rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
396 				      0x77337717);
397 			rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000);
398 			rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
399 		} else {
400 			rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD,
401 				      0x77337717);
402 			rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD,
403 				      0x77337717);
404 			rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000);
405 			rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000);
406 		}
407 		break;
408 	case 3:
409 		rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337717);
410 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337717);
411 		rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
412 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
413 		rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1);
414 		break;
415 	case 5:
416 		rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x33);
417 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
418 		tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3);
419 		rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp | 0x1);
420 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
421 		break;
422 	case 2:
423 	case 4:
424 	default:
425 		rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777);
426 		rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
427 		rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010);
428 		rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010);
429 		break;
430 	}
431 }
432 
433 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8	band,
434 			   u8 rf_path)
435 {
436 	struct rtl_priv *rtlpriv = rtl_priv(hw);
437 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 	struct rtl_dm *rtldm = rtl_dm(rtlpriv);
439 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
440 	s8 reg_swing_2g = -1;/* 0xff; */
441 	s8 reg_swing_5g = -1;/* 0xff; */
442 	s8 swing_2g = -1 * reg_swing_2g;
443 	s8 swing_5g = -1 * reg_swing_5g;
444 	u32  out = 0x200;
445 	const s8 auto_temp = -1;
446 
447 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
448 		"===> PHY_GetTXBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n",
449 		(int)swing_2g, (int)swing_5g,
450 		(int)rtlefuse->autoload_failflag);
451 
452 	if (rtlefuse->autoload_failflag) {
453 		if (band == BAND_ON_2_4G) {
454 			rtldm->swing_diff_2g = swing_2g;
455 			if (swing_2g == 0) {
456 				out = 0x200; /* 0 dB */
457 			} else if (swing_2g == -3) {
458 				out = 0x16A; /* -3 dB */
459 			} else if (swing_2g == -6) {
460 				out = 0x101; /* -6 dB */
461 			} else if (swing_2g == -9) {
462 				out = 0x0B6; /* -9 dB */
463 			} else {
464 				rtldm->swing_diff_2g = 0;
465 				out = 0x200;
466 			}
467 		} else if (band == BAND_ON_5G) {
468 			rtldm->swing_diff_5g = swing_5g;
469 			if (swing_5g == 0) {
470 				out = 0x200; /* 0 dB */
471 			} else if (swing_5g == -3) {
472 				out = 0x16A; /* -3 dB */
473 			} else if (swing_5g == -6) {
474 				out = 0x101; /* -6 dB */
475 			} else if (swing_5g == -9) {
476 				out = 0x0B6; /* -9 dB */
477 			} else {
478 				if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
479 					rtldm->swing_diff_5g = -3;
480 					out = 0x16A;
481 				} else {
482 					rtldm->swing_diff_5g = 0;
483 					out = 0x200;
484 				}
485 			}
486 		} else {
487 			rtldm->swing_diff_2g = -3;
488 			rtldm->swing_diff_5g = -3;
489 			out = 0x16A; /* -3 dB */
490 		}
491 	} else {
492 		u32 swing = 0, swing_a = 0, swing_b = 0;
493 
494 		if (band == BAND_ON_2_4G) {
495 			if (reg_swing_2g == auto_temp) {
496 				efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing);
497 				swing = (swing == 0xFF) ? 0x00 : swing;
498 			} else if (swing_2g ==  0) {
499 				swing = 0x00; /* 0 dB */
500 			} else if (swing_2g == -3) {
501 				swing = 0x05; /* -3 dB */
502 			} else if (swing_2g == -6) {
503 				swing = 0x0A; /* -6 dB */
504 			} else if (swing_2g == -9) {
505 				swing = 0xFF; /* -9 dB */
506 			} else {
507 				swing = 0x00;
508 			}
509 		} else {
510 			if (reg_swing_5g == auto_temp) {
511 				efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing);
512 				swing = (swing == 0xFF) ? 0x00 : swing;
513 			} else if (swing_5g ==  0) {
514 				swing = 0x00; /* 0 dB */
515 			} else if (swing_5g == -3) {
516 				swing = 0x05; /* -3 dB */
517 			} else if (swing_5g == -6) {
518 				swing = 0x0A; /* -6 dB */
519 			} else if (swing_5g == -9) {
520 				swing = 0xFF; /* -9 dB */
521 			} else {
522 				swing = 0x00;
523 			}
524 		}
525 
526 		swing_a = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */
527 		swing_b = (swing & 0xC) >> 2; /* 0xC6/C7[3:2] */
528 		rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
529 			"===> PHY_GetTXBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
530 			swing_a, swing_b);
531 
532 		/* 3 Path-A */
533 		if (swing_a == 0x0) {
534 			if (band == BAND_ON_2_4G)
535 				rtldm->swing_diff_2g = 0;
536 			else
537 				rtldm->swing_diff_5g = 0;
538 			out = 0x200; /* 0 dB */
539 		} else if (swing_a == 0x1) {
540 			if (band == BAND_ON_2_4G)
541 				rtldm->swing_diff_2g = -3;
542 			else
543 				rtldm->swing_diff_5g = -3;
544 			out = 0x16A; /* -3 dB */
545 		} else if (swing_a == 0x2) {
546 			if (band == BAND_ON_2_4G)
547 				rtldm->swing_diff_2g = -6;
548 			else
549 				rtldm->swing_diff_5g = -6;
550 			out = 0x101; /* -6 dB */
551 		} else if (swing_a == 0x3) {
552 			if (band == BAND_ON_2_4G)
553 				rtldm->swing_diff_2g = -9;
554 			else
555 				rtldm->swing_diff_5g = -9;
556 			out = 0x0B6; /* -9 dB */
557 		}
558 		/* 3 Path-B */
559 		if (swing_b == 0x0) {
560 			if (band == BAND_ON_2_4G)
561 				rtldm->swing_diff_2g = 0;
562 			else
563 				rtldm->swing_diff_5g = 0;
564 			out = 0x200; /* 0 dB */
565 		} else if (swing_b == 0x1) {
566 			if (band == BAND_ON_2_4G)
567 				rtldm->swing_diff_2g = -3;
568 			else
569 				rtldm->swing_diff_5g = -3;
570 			out = 0x16A; /* -3 dB */
571 		} else if (swing_b == 0x2) {
572 			if (band == BAND_ON_2_4G)
573 				rtldm->swing_diff_2g = -6;
574 			else
575 				rtldm->swing_diff_5g = -6;
576 			out = 0x101; /* -6 dB */
577 		} else if (swing_b == 0x3) {
578 			if (band == BAND_ON_2_4G)
579 				rtldm->swing_diff_2g = -9;
580 			else
581 				rtldm->swing_diff_5g = -9;
582 			out = 0x0B6; /* -9 dB */
583 		}
584 	}
585 
586 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
587 		"<=== PHY_GetTXBBSwing_8812A, out = 0x%X\n", out);
588 	return out;
589 }
590 
591 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
592 {
593 	struct rtl_priv *rtlpriv = rtl_priv(hw);
594 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
595 	struct rtl_dm *rtldm = rtl_dm(rtlpriv);
596 	u8 current_band = rtlhal->current_bandtype;
597 	u32 txpath, rxpath;
598 	s8 bb_diff_between_band;
599 
600 	txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0);
601 	rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000);
602 	rtlhal->current_bandtype = (enum band_type) band;
603 	/* reconfig BB/RF according to wireless mode */
604 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
605 		/* BB & RF Config */
606 		rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
607 
608 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
609 			/* 0xCB0[15:12] = 0x7 (LNA_On)*/
610 			rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
611 			/* 0xCB0[7:4] = 0x7 (PAPE_A)*/
612 			rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
613 		}
614 
615 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
616 			/*0x834[1:0] = 0x1*/
617 			rtl_set_bbreg(hw, 0x834, 0x3, 0x1);
618 		}
619 
620 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
621 			/* 0xC1C[11:8] = 0 */
622 			rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0);
623 		} else {
624 			/* 0x82C[1:0] = 2b'00 */
625 			rtl_set_bbreg(hw, 0x82c, 0x3, 0);
626 		}
627 
628 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
629 			_rtl8812ae_phy_set_rfe_reg_24g(hw);
630 
631 		rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1);
632 		rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1);
633 
634 		rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0);
635 	} else {/* 5G band */
636 		u16 count, reg_41a;
637 
638 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
639 			/*0xCB0[15:12] = 0x5 (LNA_On)*/
640 			rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
641 			/*0xCB0[7:4] = 0x4 (PAPE_A)*/
642 			rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
643 		}
644 		/*CCK_CHECK_en*/
645 		rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80);
646 
647 		count = 0;
648 		reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
649 		rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
650 			"Reg41A value %d\n", reg_41a);
651 		reg_41a &= 0x30;
652 		while ((reg_41a != 0x30) && (count < 50)) {
653 			udelay(50);
654 			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "Delay 50us\n");
655 
656 			reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
657 			reg_41a &= 0x30;
658 			count++;
659 			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
660 				"Reg41A value %d\n", reg_41a);
661 		}
662 		if (count != 0)
663 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
664 				"PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n",
665 				count, reg_41a);
666 
667 		/* 2012/02/01, Sinda add registry to switch workaround
668 		without long-run verification for scan issue. */
669 		rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
670 
671 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
672 			/*0x834[1:0] = 0x2*/
673 			rtl_set_bbreg(hw, 0x834, 0x3, 0x2);
674 		}
675 
676 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
677 			/* AGC table select */
678 			/* 0xC1C[11:8] = 1*/
679 			rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1);
680 		} else
681 			/* 0x82C[1:0] = 2'b00 */
682 			rtl_set_bbreg(hw, 0x82c, 0x3, 1);
683 
684 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
685 			_rtl8812ae_phy_set_rfe_reg_5g(hw);
686 
687 		rtl_set_bbreg(hw, RTXPATH, 0xf0, 0);
688 		rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf);
689 
690 		rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
691 			"==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
692 			rtlpriv->dm.ofdm_index[RF90_PATH_A]);
693 	}
694 
695 	if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
696 	    (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) {
697 		/* 0xC1C[31:21] */
698 		rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
699 			      phy_get_tx_swing_8812A(hw, band, RF90_PATH_A));
700 		/* 0xE1C[31:21] */
701 		rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
702 			      phy_get_tx_swing_8812A(hw, band, RF90_PATH_B));
703 
704 		/* <20121005, Kordan> When TxPowerTrack is ON,
705 		 *	we should take care of the change of BB swing.
706 		 *   That is, reset all info to trigger Tx power tracking.
707 		 */
708 		if (band != current_band) {
709 			bb_diff_between_band =
710 				(rtldm->swing_diff_2g - rtldm->swing_diff_5g);
711 			bb_diff_between_band = (band == BAND_ON_2_4G) ?
712 						bb_diff_between_band :
713 						(-1 * bb_diff_between_band);
714 			rtldm->default_ofdm_index += bb_diff_between_band * 2;
715 		}
716 		rtl8821ae_dm_clear_txpower_tracking_state(hw);
717 	}
718 
719 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
720 		"<==%s():Switch Band OK.\n", __func__);
721 	return;
722 }
723 
724 static bool _rtl8821ae_check_positive(struct ieee80211_hw *hw,
725 				      const u32 condition1,
726 				      const u32 condition2)
727 {
728 	struct rtl_priv *rtlpriv = rtl_priv(hw);
729 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
730 	u32 cut_ver = ((rtlhal->version & CHIP_VER_RTL_MASK)
731 					>> CHIP_VER_RTL_SHIFT);
732 	u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0));
733 
734 	u8  board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */
735 			 ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA  */
736 			 ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */
737 			 ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA  */
738 			 ((rtlhal->board_type & BIT(2)) >> 2) << 4;  /* _BT   */
739 
740 	u32 cond1 = condition1, cond2 = condition2;
741 	u32 driver1 = cut_ver << 24 |	/* CUT ver */
742 		      0 << 20 |			/* interface 2/2 */
743 		      0x04 << 16 |		/* platform */
744 		      rtlhal->package_type << 12 |
745 		      intf << 8 |			/* interface 1/2 */
746 		      board_type;
747 
748 	u32 driver2 = rtlhal->type_glna <<  0 |
749 		      rtlhal->type_gpa  <<  8 |
750 		      rtlhal->type_alna << 16 |
751 		      rtlhal->type_apa  << 24;
752 
753 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
754 		"===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
755 		cond1, cond2);
756 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
757 		"===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
758 		driver1, driver2);
759 
760 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
761 		"	(Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf);
762 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
763 		"	(Board, Package) = (0x%X, 0x%X)\n",
764 		rtlhal->board_type, rtlhal->package_type);
765 
766 	/*============== Value Defined Check ===============*/
767 	/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
768 
769 	if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) !=
770 		(driver1 & 0x0000F000)))
771 		return false;
772 	if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) !=
773 		(driver1 & 0x0F000000)))
774 		return false;
775 
776 	/*=============== Bit Defined Check ================*/
777 	/* We don't care [31:28] */
778 
779 	cond1   &= 0x00FF0FFF;
780 	driver1 &= 0x00FF0FFF;
781 
782 	if ((cond1 & driver1) == cond1) {
783 		u32 mask = 0;
784 
785 		if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
786 			return true;
787 
788 		if ((cond1 & BIT(0)) != 0) /*GLNA*/
789 			mask |= 0x000000FF;
790 		if ((cond1 & BIT(1)) != 0) /*GPA*/
791 			mask |= 0x0000FF00;
792 		if ((cond1 & BIT(2)) != 0) /*ALNA*/
793 			mask |= 0x00FF0000;
794 		if ((cond1 & BIT(3)) != 0) /*APA*/
795 			mask |= 0xFF000000;
796 
797 		/* BoardType of each RF path is matched*/
798 		if ((cond2 & mask) == (driver2 & mask))
799 			return true;
800 		else
801 			return false;
802 	} else
803 		return false;
804 }
805 
806 static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw,
807 				       const u32 condition)
808 {
809 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
810 	u32 _board = rtlefuse->board_type; /*need efuse define*/
811 	u32 _interface = 0x01; /* ODM_ITRF_PCIE */
812 	u32 _platform = 0x08;/* ODM_WIN */
813 	u32 cond = condition;
814 
815 	if (condition == 0xCDCDCDCD)
816 		return true;
817 
818 	cond = condition & 0xFF;
819 	if ((_board != cond) && cond != 0xFF)
820 		return false;
821 
822 	cond = condition & 0xFF00;
823 	cond = cond >> 8;
824 	if ((_interface & cond) == 0 && cond != 0x07)
825 		return false;
826 
827 	cond = condition & 0xFF0000;
828 	cond = cond >> 16;
829 	if ((_platform & cond) == 0 && cond != 0x0F)
830 		return false;
831 	return true;
832 }
833 
834 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw,
835 				     u32 addr, u32 data,
836 				     enum radio_path rfpath, u32 regaddr)
837 {
838 	if (addr == 0xfe || addr == 0xffe) {
839 		/* In order not to disturb BT music when
840 		 * wifi init.(1ant NIC only)
841 		 */
842 		mdelay(50);
843 	} else {
844 		rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
845 		udelay(1);
846 	}
847 }
848 
849 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw,
850 					 u32 addr, u32 data)
851 {
852 	u32 content = 0x1000; /*RF Content: radio_a_txt*/
853 	u32 maskforphyset = (u32)(content & 0xE000);
854 
855 	_rtl8821ae_config_rf_reg(hw, addr, data,
856 				 RF90_PATH_A, addr | maskforphyset);
857 }
858 
859 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw,
860 					 u32 addr, u32 data)
861 {
862 	u32 content = 0x1001; /*RF Content: radio_b_txt*/
863 	u32 maskforphyset = (u32)(content & 0xE000);
864 
865 	_rtl8821ae_config_rf_reg(hw, addr, data,
866 				 RF90_PATH_B, addr | maskforphyset);
867 }
868 
869 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw,
870 				     u32 addr, u32 data)
871 {
872 	if (addr == 0xfe)
873 		mdelay(50);
874 	else if (addr == 0xfd)
875 		mdelay(5);
876 	else if (addr == 0xfc)
877 		mdelay(1);
878 	else if (addr == 0xfb)
879 		udelay(50);
880 	else if (addr == 0xfa)
881 		udelay(5);
882 	else if (addr == 0xf9)
883 		udelay(1);
884 	else
885 		rtl_set_bbreg(hw, addr, MASKDWORD, data);
886 
887 	udelay(1);
888 }
889 
890 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
891 {
892 	struct rtl_priv *rtlpriv = rtl_priv(hw);
893 	struct rtl_phy *rtlphy = &rtlpriv->phy;
894 	u8 band, rfpath, txnum, rate_section;
895 
896 	for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
897 		for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath)
898 			for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
899 				for (rate_section = 0;
900 				     rate_section < TX_PWR_BY_RATE_NUM_SECTION;
901 				     ++rate_section)
902 					rtlphy->tx_power_by_rate_offset[band]
903 					    [rfpath][txnum][rate_section] = 0;
904 }
905 
906 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
907 					  u8 band, u8 path,
908 					  u8 rate_section,
909 					  u8 txnum, u8 value)
910 {
911 	struct rtl_priv *rtlpriv = rtl_priv(hw);
912 	struct rtl_phy *rtlphy = &rtlpriv->phy;
913 
914 	if (path > RF90_PATH_D) {
915 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
916 			"Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path);
917 		return;
918 	}
919 
920 	if (band == BAND_ON_2_4G) {
921 		switch (rate_section) {
922 		case CCK:
923 			rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
924 			break;
925 		case OFDM:
926 			rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
927 			break;
928 		case HT_MCS0_MCS7:
929 			rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
930 			break;
931 		case HT_MCS8_MCS15:
932 			rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
933 			break;
934 		case VHT_1SSMCS0_1SSMCS9:
935 			rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value;
936 			break;
937 		case VHT_2SSMCS0_2SSMCS9:
938 			rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value;
939 			break;
940 		default:
941 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
942 				"Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
943 				rate_section, path, txnum);
944 			break;
945 		}
946 	} else if (band == BAND_ON_5G) {
947 		switch (rate_section) {
948 		case OFDM:
949 			rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value;
950 			break;
951 		case HT_MCS0_MCS7:
952 			rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value;
953 			break;
954 		case HT_MCS8_MCS15:
955 			rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value;
956 			break;
957 		case VHT_1SSMCS0_1SSMCS9:
958 			rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value;
959 			break;
960 		case VHT_2SSMCS0_2SSMCS9:
961 			rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value;
962 			break;
963 		default:
964 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
965 				"Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
966 				rate_section, path, txnum);
967 			break;
968 		}
969 	} else {
970 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
971 			"Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band);
972 	}
973 }
974 
975 static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
976 						  u8 band, u8 path,
977 						  u8 txnum, u8 rate_section)
978 {
979 	struct rtl_priv *rtlpriv = rtl_priv(hw);
980 	struct rtl_phy *rtlphy = &rtlpriv->phy;
981 	u8 value = 0;
982 
983 	if (path > RF90_PATH_D) {
984 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
985 			"Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
986 			path);
987 		return 0;
988 	}
989 
990 	if (band == BAND_ON_2_4G) {
991 		switch (rate_section) {
992 		case CCK:
993 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
994 			break;
995 		case OFDM:
996 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
997 			break;
998 		case HT_MCS0_MCS7:
999 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
1000 			break;
1001 		case HT_MCS8_MCS15:
1002 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
1003 			break;
1004 		case VHT_1SSMCS0_1SSMCS9:
1005 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4];
1006 			break;
1007 		case VHT_2SSMCS0_2SSMCS9:
1008 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5];
1009 			break;
1010 		default:
1011 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1012 				"Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
1013 				rate_section, path, txnum);
1014 			break;
1015 		}
1016 	} else if (band == BAND_ON_5G) {
1017 		switch (rate_section) {
1018 		case OFDM:
1019 			value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0];
1020 			break;
1021 		case HT_MCS0_MCS7:
1022 			value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1];
1023 			break;
1024 		case HT_MCS8_MCS15:
1025 			value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2];
1026 			break;
1027 		case VHT_1SSMCS0_1SSMCS9:
1028 			value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3];
1029 			break;
1030 		case VHT_2SSMCS0_2SSMCS9:
1031 			value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4];
1032 			break;
1033 		default:
1034 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1035 				"Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
1036 				rate_section, path, txnum);
1037 			break;
1038 		}
1039 	} else {
1040 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1041 			"Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band);
1042 	}
1043 
1044 	return value;
1045 }
1046 
1047 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
1048 {
1049 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1050 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1051 	u16 rawvalue = 0;
1052 	u8 base = 0, path = 0;
1053 
1054 	for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
1055 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF;
1056 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1057 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base);
1058 
1059 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF;
1060 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1061 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base);
1062 
1063 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF;
1064 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1065 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base);
1066 
1067 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF;
1068 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1069 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base);
1070 
1071 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF;
1072 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1073 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
1074 
1075 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF;
1076 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1077 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
1078 
1079 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF;
1080 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1081 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base);
1082 
1083 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF;
1084 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1085 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base);
1086 
1087 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF;
1088 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1089 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base);
1090 
1091 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF;
1092 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1093 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
1094 
1095 		rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF;
1096 		base = (rawvalue >> 4) * 10 + (rawvalue & 0xF);
1097 		_rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
1098 	}
1099 }
1100 
1101 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
1102 						u8 end, u8 base_val)
1103 {
1104 	int i;
1105 	u8 temp_value = 0;
1106 	u32 temp_data = 0;
1107 
1108 	for (i = 3; i >= 0; --i) {
1109 		if (i >= start && i <= end) {
1110 			/* Get the exact value */
1111 			temp_value = (u8)(*data >> (i * 8)) & 0xF;
1112 			temp_value += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
1113 
1114 			/* Change the value to a relative value */
1115 			temp_value = (temp_value > base_val) ? temp_value -
1116 					base_val : base_val - temp_value;
1117 		} else {
1118 			temp_value = (u8)(*data >> (i * 8)) & 0xFF;
1119 		}
1120 		temp_data <<= 8;
1121 		temp_data |= temp_value;
1122 	}
1123 	*data = temp_data;
1124 }
1125 
1126 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw)
1127 {
1128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1130 	u8 regulation, bw, channel, rate_section;
1131 	s8 temp_pwrlmt = 0;
1132 
1133 	for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1134 		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1135 			for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1136 				for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1137 					temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1138 						[bw][rate_section][channel][RF90_PATH_A];
1139 					if (temp_pwrlmt == MAX_POWER_INDEX) {
1140 						if (bw == 0 || bw == 1) { /*5G 20M 40M VHT and HT can cross reference*/
1141 							rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1142 								"No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n",
1143 								1, bw, rate_section, channel, RF90_PATH_A);
1144 							if (rate_section == 2) {
1145 								rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A] =
1146 									rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A];
1147 							} else if (rate_section == 4) {
1148 								rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A] =
1149 									rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A];
1150 							} else if (rate_section == 3) {
1151 								rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A] =
1152 									rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A];
1153 							} else if (rate_section == 5) {
1154 								rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A] =
1155 									rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A];
1156 							}
1157 
1158 							rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1159 								"use other value %d\n",
1160 								temp_pwrlmt);
1161 						}
1162 					}
1163 				}
1164 			}
1165 		}
1166 	}
1167 }
1168 
1169 static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw,
1170 						   enum band_type band, u8 rate)
1171 {
1172 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1173 	u8 index = 0;
1174 	if (band == BAND_ON_2_4G) {
1175 		switch (rate) {
1176 		case MGN_1M:
1177 		case MGN_2M:
1178 		case MGN_5_5M:
1179 		case MGN_11M:
1180 			index = 0;
1181 			break;
1182 
1183 		case MGN_6M:
1184 		case MGN_9M:
1185 		case MGN_12M:
1186 		case MGN_18M:
1187 		case MGN_24M:
1188 		case MGN_36M:
1189 		case MGN_48M:
1190 		case MGN_54M:
1191 			index = 1;
1192 			break;
1193 
1194 		case MGN_MCS0:
1195 		case MGN_MCS1:
1196 		case MGN_MCS2:
1197 		case MGN_MCS3:
1198 		case MGN_MCS4:
1199 		case MGN_MCS5:
1200 		case MGN_MCS6:
1201 		case MGN_MCS7:
1202 			index = 2;
1203 			break;
1204 
1205 		case MGN_MCS8:
1206 		case MGN_MCS9:
1207 		case MGN_MCS10:
1208 		case MGN_MCS11:
1209 		case MGN_MCS12:
1210 		case MGN_MCS13:
1211 		case MGN_MCS14:
1212 		case MGN_MCS15:
1213 			index = 3;
1214 			break;
1215 
1216 		default:
1217 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1218 				"Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n",
1219 				rate);
1220 			break;
1221 		}
1222 	} else if (band == BAND_ON_5G) {
1223 		switch (rate) {
1224 		case MGN_6M:
1225 		case MGN_9M:
1226 		case MGN_12M:
1227 		case MGN_18M:
1228 		case MGN_24M:
1229 		case MGN_36M:
1230 		case MGN_48M:
1231 		case MGN_54M:
1232 			index = 0;
1233 			break;
1234 
1235 		case MGN_MCS0:
1236 		case MGN_MCS1:
1237 		case MGN_MCS2:
1238 		case MGN_MCS3:
1239 		case MGN_MCS4:
1240 		case MGN_MCS5:
1241 		case MGN_MCS6:
1242 		case MGN_MCS7:
1243 			index = 1;
1244 			break;
1245 
1246 		case MGN_MCS8:
1247 		case MGN_MCS9:
1248 		case MGN_MCS10:
1249 		case MGN_MCS11:
1250 		case MGN_MCS12:
1251 		case MGN_MCS13:
1252 		case MGN_MCS14:
1253 		case MGN_MCS15:
1254 			index = 2;
1255 			break;
1256 
1257 		case MGN_VHT1SS_MCS0:
1258 		case MGN_VHT1SS_MCS1:
1259 		case MGN_VHT1SS_MCS2:
1260 		case MGN_VHT1SS_MCS3:
1261 		case MGN_VHT1SS_MCS4:
1262 		case MGN_VHT1SS_MCS5:
1263 		case MGN_VHT1SS_MCS6:
1264 		case MGN_VHT1SS_MCS7:
1265 		case MGN_VHT1SS_MCS8:
1266 		case MGN_VHT1SS_MCS9:
1267 			index = 3;
1268 			break;
1269 
1270 		case MGN_VHT2SS_MCS0:
1271 		case MGN_VHT2SS_MCS1:
1272 		case MGN_VHT2SS_MCS2:
1273 		case MGN_VHT2SS_MCS3:
1274 		case MGN_VHT2SS_MCS4:
1275 		case MGN_VHT2SS_MCS5:
1276 		case MGN_VHT2SS_MCS6:
1277 		case MGN_VHT2SS_MCS7:
1278 		case MGN_VHT2SS_MCS8:
1279 		case MGN_VHT2SS_MCS9:
1280 			index = 4;
1281 			break;
1282 
1283 		default:
1284 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1285 				"Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n",
1286 				rate);
1287 			break;
1288 		}
1289 	}
1290 
1291 	return index;
1292 }
1293 
1294 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw)
1295 {
1296 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1297 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1298 	u8 bw40_pwr_base_dbm2_4G, bw40_pwr_base_dbm5G;
1299 	u8 regulation, bw, channel, rate_section;
1300 	u8 base_index2_4G = 0;
1301 	u8 base_index5G = 0;
1302 	s8 temp_value = 0, temp_pwrlmt = 0;
1303 	u8 rf_path = 0;
1304 
1305 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1306 		"=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n");
1307 
1308 	_rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw);
1309 
1310 	for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1311 		for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
1312 			for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
1313 				for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1314 					/* obtain the base dBm values in 2.4G band
1315 					 CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/
1316 					if (rate_section == 0) { /*CCK*/
1317 						base_index2_4G =
1318 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1319 							BAND_ON_2_4G, MGN_11M);
1320 					} else if (rate_section == 1) { /*OFDM*/
1321 						base_index2_4G =
1322 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1323 							BAND_ON_2_4G, MGN_54M);
1324 					} else if (rate_section == 2) { /*HT IT*/
1325 						base_index2_4G =
1326 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1327 							BAND_ON_2_4G, MGN_MCS7);
1328 					} else if (rate_section == 3) { /*HT 2T*/
1329 						base_index2_4G =
1330 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1331 							BAND_ON_2_4G, MGN_MCS15);
1332 					}
1333 
1334 					temp_pwrlmt = rtlphy->txpwr_limit_2_4g[regulation]
1335 						[bw][rate_section][channel][RF90_PATH_A];
1336 
1337 					for (rf_path = RF90_PATH_A;
1338 						rf_path < MAX_RF_PATH_NUM;
1339 						++rf_path) {
1340 						if (rate_section == 3)
1341 							bw40_pwr_base_dbm2_4G =
1342 							rtlphy->txpwr_by_rate_base_24g[rf_path][RF_2TX][base_index2_4G];
1343 						else
1344 							bw40_pwr_base_dbm2_4G =
1345 							rtlphy->txpwr_by_rate_base_24g[rf_path][RF_1TX][base_index2_4G];
1346 
1347 						if (temp_pwrlmt != MAX_POWER_INDEX) {
1348 							temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G;
1349 							rtlphy->txpwr_limit_2_4g[regulation]
1350 								[bw][rate_section][channel][rf_path] =
1351 								temp_value;
1352 						}
1353 
1354 						rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1355 							"TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfpath %d] %d)\n",
1356 							regulation, bw, rate_section, channel,
1357 							rtlphy->txpwr_limit_2_4g[regulation][bw]
1358 							[rate_section][channel][rf_path], (temp_pwrlmt == 63)
1359 							? 0 : temp_pwrlmt/2, channel, rf_path,
1360 							bw40_pwr_base_dbm2_4G);
1361 					}
1362 				}
1363 			}
1364 		}
1365 	}
1366 	for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1367 		for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1368 			for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1369 				for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) {
1370 					/* obtain the base dBm values in 5G band
1371 					 OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15,
1372 					VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/
1373 					if (rate_section == 1) { /*OFDM*/
1374 						base_index5G =
1375 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1376 							BAND_ON_5G, MGN_54M);
1377 					} else if (rate_section == 2) { /*HT 1T*/
1378 						base_index5G =
1379 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1380 							BAND_ON_5G, MGN_MCS7);
1381 					} else if (rate_section == 3) { /*HT 2T*/
1382 						base_index5G =
1383 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1384 							BAND_ON_5G, MGN_MCS15);
1385 					} else if (rate_section == 4) { /*VHT 1T*/
1386 						base_index5G =
1387 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1388 							BAND_ON_5G, MGN_VHT1SS_MCS7);
1389 					} else if (rate_section == 5) { /*VHT 2T*/
1390 						base_index5G =
1391 							_rtl8812ae_phy_get_txpower_by_rate_base_index(hw,
1392 							BAND_ON_5G, MGN_VHT2SS_MCS7);
1393 					}
1394 
1395 					temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation]
1396 						[bw][rate_section][channel]
1397 						[RF90_PATH_A];
1398 
1399 					for (rf_path = RF90_PATH_A;
1400 					     rf_path < MAX_RF_PATH_NUM;
1401 					     ++rf_path) {
1402 						if (rate_section == 3 || rate_section == 5)
1403 							bw40_pwr_base_dbm5G =
1404 							rtlphy->txpwr_by_rate_base_5g[rf_path]
1405 							[RF_2TX][base_index5G];
1406 						else
1407 							bw40_pwr_base_dbm5G =
1408 							rtlphy->txpwr_by_rate_base_5g[rf_path]
1409 							[RF_1TX][base_index5G];
1410 
1411 						if (temp_pwrlmt != MAX_POWER_INDEX) {
1412 							temp_value =
1413 								temp_pwrlmt - bw40_pwr_base_dbm5G;
1414 							rtlphy->txpwr_limit_5g[regulation]
1415 								[bw][rate_section][channel]
1416 								[rf_path] = temp_value;
1417 						}
1418 
1419 						rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1420 							"TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfpath %d] %d)\n",
1421 							regulation, bw, rate_section,
1422 							channel, rtlphy->txpwr_limit_5g[regulation]
1423 							[bw][rate_section][channel][rf_path],
1424 							temp_pwrlmt, channel, rf_path, bw40_pwr_base_dbm5G);
1425 					}
1426 				}
1427 			}
1428 		}
1429 	}
1430 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1431 		"<===== %s()\n", __func__);
1432 }
1433 
1434 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw)
1435 {
1436 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1437 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1438 	u8 i, j, k, l, m;
1439 
1440 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1441 		"=====>`%s()!\n", __func__);
1442 
1443 	for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1444 		for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
1445 			for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1446 				for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
1447 					for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1448 						rtlphy->txpwr_limit_2_4g
1449 								[i][j][k][m][l]
1450 							= MAX_POWER_INDEX;
1451 	}
1452 	for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1453 		for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
1454 			for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1455 				for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)
1456 					for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1457 						rtlphy->txpwr_limit_5g
1458 								[i][j][k][m][l]
1459 							= MAX_POWER_INDEX;
1460 	}
1461 
1462 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1463 		"<===== %s()!\n", __func__);
1464 }
1465 
1466 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
1467 {
1468 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1469 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1470 	u8 base = 0, rfpath = 0;
1471 
1472 	for (rfpath = RF90_PATH_A; rfpath <= RF90_PATH_B; ++rfpath) {
1473 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, CCK);
1474 		_phy_convert_txpower_dbm_to_relative_value(
1475 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0],
1476 			0, 3, base);
1477 
1478 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, OFDM);
1479 		_phy_convert_txpower_dbm_to_relative_value(
1480 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1],
1481 			0, 3, base);
1482 		_phy_convert_txpower_dbm_to_relative_value(
1483 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2],
1484 			0, 3, base);
1485 
1486 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, HT_MCS0_MCS7);
1487 		_phy_convert_txpower_dbm_to_relative_value(
1488 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3],
1489 			0, 3, base);
1490 		_phy_convert_txpower_dbm_to_relative_value(
1491 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4],
1492 			0, 3, base);
1493 
1494 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, HT_MCS8_MCS15);
1495 
1496 		_phy_convert_txpower_dbm_to_relative_value(
1497 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][5],
1498 			0, 3, base);
1499 
1500 		_phy_convert_txpower_dbm_to_relative_value(
1501 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6],
1502 			0, 3, base);
1503 
1504 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1505 		_phy_convert_txpower_dbm_to_relative_value(
1506 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][7],
1507 			0, 3, base);
1508 		_phy_convert_txpower_dbm_to_relative_value(
1509 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][8],
1510 			0, 3, base);
1511 		_phy_convert_txpower_dbm_to_relative_value(
1512 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9],
1513 			0, 1, base);
1514 
1515 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1516 		_phy_convert_txpower_dbm_to_relative_value(
1517 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9],
1518 			2, 3, base);
1519 		_phy_convert_txpower_dbm_to_relative_value(
1520 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][10],
1521 			0, 3, base);
1522 		_phy_convert_txpower_dbm_to_relative_value(
1523 			&rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][11],
1524 			0, 3, base);
1525 
1526 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, OFDM);
1527 		_phy_convert_txpower_dbm_to_relative_value(
1528 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][1],
1529 			0, 3, base);
1530 		_phy_convert_txpower_dbm_to_relative_value(
1531 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][2],
1532 			0, 3, base);
1533 
1534 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, HT_MCS0_MCS7);
1535 		_phy_convert_txpower_dbm_to_relative_value(
1536 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][3],
1537 			0, 3, base);
1538 		_phy_convert_txpower_dbm_to_relative_value(
1539 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][4],
1540 			0, 3, base);
1541 
1542 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, HT_MCS8_MCS15);
1543 		_phy_convert_txpower_dbm_to_relative_value(
1544 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][5],
1545 			0, 3, base);
1546 		_phy_convert_txpower_dbm_to_relative_value(
1547 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][6],
1548 			0, 3, base);
1549 
1550 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9);
1551 		_phy_convert_txpower_dbm_to_relative_value(
1552 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][7],
1553 			0, 3, base);
1554 		_phy_convert_txpower_dbm_to_relative_value(
1555 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][8],
1556 			0, 3, base);
1557 		_phy_convert_txpower_dbm_to_relative_value(
1558 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9],
1559 			0, 1, base);
1560 
1561 		base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9);
1562 		_phy_convert_txpower_dbm_to_relative_value(
1563 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9],
1564 			2, 3, base);
1565 		_phy_convert_txpower_dbm_to_relative_value(
1566 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][10],
1567 			0, 3, base);
1568 		_phy_convert_txpower_dbm_to_relative_value(
1569 			&rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][11],
1570 			0, 3, base);
1571 	}
1572 
1573 	rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1574 		"<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n");
1575 }
1576 
1577 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
1578 {
1579 	_rtl8821ae_phy_store_txpower_by_rate_base(hw);
1580 	_rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw);
1581 }
1582 
1583 /* string is in decimal */
1584 static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint)
1585 {
1586 	u16 i = 0;
1587 	*pint = 0;
1588 
1589 	while (str[i] != '\0') {
1590 		if (str[i] >= '0' && str[i] <= '9') {
1591 			*pint *= 10;
1592 			*pint += (str[i] - '0');
1593 		} else {
1594 			return false;
1595 		}
1596 		++i;
1597 	}
1598 
1599 	return true;
1600 }
1601 
1602 static bool _rtl8812ae_eq_n_byte(u8 *str1, u8 *str2, u32 num)
1603 {
1604 	if (num == 0)
1605 		return false;
1606 	while (num > 0) {
1607 		num--;
1608 		if (str1[num] != str2[num])
1609 			return false;
1610 	}
1611 	return true;
1612 }
1613 
1614 static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw,
1615 					      u8 band, u8 channel)
1616 {
1617 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1618 	s8 channel_index = -1;
1619 	u8  i = 0;
1620 
1621 	if (band == BAND_ON_2_4G)
1622 		channel_index = channel - 1;
1623 	else if (band == BAND_ON_5G) {
1624 		for (i = 0; i < sizeof(channel5g)/sizeof(u8); ++i) {
1625 			if (channel5g[i] == channel)
1626 				channel_index = i;
1627 		}
1628 	} else
1629 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s\n",
1630 			band,  __func__);
1631 
1632 	if (channel_index == -1)
1633 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1634 			"Invalid Channel %d of Band %d in %s\n", channel,
1635 			band, __func__);
1636 
1637 	return channel_index;
1638 }
1639 
1640 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation,
1641 				      u8 *pband, u8 *pbandwidth,
1642 				      u8 *prate_section, u8 *prf_path,
1643 				      u8 *pchannel, u8 *ppower_limit)
1644 {
1645 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1646 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1647 	u8 regulation = 0, bandwidth = 0, rate_section = 0, channel;
1648 	u8 channel_index;
1649 	s8 power_limit = 0, prev_power_limit, ret;
1650 
1651 	if (!_rtl8812ae_get_integer_from_string((char *)pchannel, &channel) ||
1652 	    !_rtl8812ae_get_integer_from_string((char *)ppower_limit,
1653 						&power_limit)) {
1654 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1655 			"Illegal index of pwr_lmt table [chnl %d][val %d]\n",
1656 			channel, power_limit);
1657 	}
1658 
1659 	power_limit = power_limit > MAX_POWER_INDEX ?
1660 		      MAX_POWER_INDEX : power_limit;
1661 
1662 	if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("FCC"), 3))
1663 		regulation = 0;
1664 	else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("MKK"), 3))
1665 		regulation = 1;
1666 	else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("ETSI"), 4))
1667 		regulation = 2;
1668 	else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("WW13"), 4))
1669 		regulation = 3;
1670 
1671 	if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("CCK"), 3))
1672 		rate_section = 0;
1673 	else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("OFDM"), 4))
1674 		rate_section = 1;
1675 	else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
1676 		 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2))
1677 		rate_section = 2;
1678 	else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) &&
1679 		 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2))
1680 		rate_section = 3;
1681 	else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
1682 		 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2))
1683 		rate_section = 4;
1684 	else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) &&
1685 		 _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2))
1686 		rate_section = 5;
1687 
1688 	if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("20M"), 3))
1689 		bandwidth = 0;
1690 	else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("40M"), 3))
1691 		bandwidth = 1;
1692 	else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("80M"), 3))
1693 		bandwidth = 2;
1694 	else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("160M"), 4))
1695 		bandwidth = 3;
1696 
1697 	if (_rtl8812ae_eq_n_byte(pband, (u8 *)("2.4G"), 4)) {
1698 		ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1699 							       BAND_ON_2_4G,
1700 							       channel);
1701 
1702 		if (ret == -1)
1703 			return;
1704 
1705 		channel_index = ret;
1706 
1707 		prev_power_limit = rtlphy->txpwr_limit_2_4g[regulation]
1708 						[bandwidth][rate_section]
1709 						[channel_index][RF90_PATH_A];
1710 
1711 		if (power_limit < prev_power_limit)
1712 			rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1713 				[rate_section][channel_index][RF90_PATH_A] =
1714 								   power_limit;
1715 
1716 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1717 			"2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n",
1718 			regulation, bandwidth, rate_section, channel_index,
1719 			rtlphy->txpwr_limit_2_4g[regulation][bandwidth]
1720 				[rate_section][channel_index][RF90_PATH_A]);
1721 	} else if (_rtl8812ae_eq_n_byte(pband, (u8 *)("5G"), 2)) {
1722 		ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
1723 							       BAND_ON_5G,
1724 							       channel);
1725 
1726 		if (ret == -1)
1727 			return;
1728 
1729 		channel_index = ret;
1730 
1731 		prev_power_limit = rtlphy->txpwr_limit_5g[regulation][bandwidth]
1732 						[rate_section][channel_index]
1733 						[RF90_PATH_A];
1734 
1735 		if (power_limit < prev_power_limit)
1736 			rtlphy->txpwr_limit_5g[regulation][bandwidth]
1737 			[rate_section][channel_index][RF90_PATH_A] = power_limit;
1738 
1739 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1740 			"5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n",
1741 			regulation, bandwidth, rate_section, channel,
1742 			rtlphy->txpwr_limit_5g[regulation][bandwidth]
1743 				[rate_section][channel_index][RF90_PATH_A]);
1744 	} else {
1745 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1746 			"Cannot recognize the band info in %s\n", pband);
1747 		return;
1748 	}
1749 }
1750 
1751 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw,
1752 					  u8 *regulation, u8 *band,
1753 					  u8 *bandwidth, u8 *rate_section,
1754 					  u8 *rf_path, u8 *channel,
1755 					  u8 *power_limit)
1756 {
1757 	_rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth,
1758 					 rate_section, rf_path, channel,
1759 					 power_limit);
1760 }
1761 
1762 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw)
1763 {
1764 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1765 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1766 	u32 i = 0;
1767 	u32 array_len;
1768 	u8 **array;
1769 
1770 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1771 		array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN;
1772 		array = RTL8812AE_TXPWR_LMT;
1773 	} else {
1774 		array_len = RTL8821AE_TXPWR_LMT_ARRAY_LEN;
1775 		array = RTL8821AE_TXPWR_LMT;
1776 	}
1777 
1778 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
1779 
1780 	for (i = 0; i < array_len; i += 7) {
1781 		u8 *regulation = array[i];
1782 		u8 *band = array[i+1];
1783 		u8 *bandwidth = array[i+2];
1784 		u8 *rate = array[i+3];
1785 		u8 *rf_path = array[i+4];
1786 		u8 *chnl = array[i+5];
1787 		u8 *val = array[i+6];
1788 
1789 		_rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band,
1790 						   bandwidth, rate, rf_path,
1791 						   chnl, val);
1792 	}
1793 }
1794 
1795 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw)
1796 {
1797 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1798 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1799 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1800 	bool rtstatus;
1801 
1802 	_rtl8821ae_phy_init_txpower_limit(hw);
1803 
1804 	/* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1805 	if (rtlefuse->eeprom_regulatory != 2)
1806 		_rtl8821ae_phy_read_and_config_txpwr_lmt(hw);
1807 
1808 	rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1809 						       BASEBAND_CONFIG_PHY_REG);
1810 	if (!rtstatus) {
1811 		pr_err("Write BB Reg Fail!!\n");
1812 		return false;
1813 	}
1814 	_rtl8821ae_phy_init_tx_power_by_rate(hw);
1815 	if (rtlefuse->autoload_failflag == false) {
1816 		rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw,
1817 						    BASEBAND_CONFIG_PHY_REG);
1818 	}
1819 	if (!rtstatus) {
1820 		pr_err("BB_PG Reg Fail!!\n");
1821 		return false;
1822 	}
1823 
1824 	_rtl8821ae_phy_txpower_by_rate_configuration(hw);
1825 
1826 	/* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
1827 	if (rtlefuse->eeprom_regulatory != 2)
1828 		_rtl8812ae_phy_convert_txpower_limit_to_power_index(hw);
1829 
1830 	rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1831 						BASEBAND_CONFIG_AGC_TAB);
1832 
1833 	if (!rtstatus) {
1834 		pr_err("AGC Table Fail\n");
1835 		return false;
1836 	}
1837 	rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
1838 			RFPGA0_XA_HSSIPARAMETER2, 0x200));
1839 	return true;
1840 }
1841 
1842 static bool
1843 __rtl8821ae_phy_config_with_headerfile(struct ieee80211_hw *hw,
1844 				       u32 *array_table, u16 arraylen,
1845 				       void (*set_reg)(struct ieee80211_hw *hw,
1846 						       u32 regaddr, u32 data))
1847 {
1848 	#define COND_ELSE  2
1849 	#define COND_ENDIF 3
1850 
1851 	int i = 0;
1852 	u8 cond;
1853 	bool matched = true, skipped = false;
1854 
1855 	while ((i + 1) < arraylen) {
1856 		u32 v1 = array_table[i];
1857 		u32 v2 = array_table[i + 1];
1858 
1859 		if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
1860 			if (v1 & BIT(31)) {/* positive condition*/
1861 				cond  = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
1862 				if (cond == COND_ENDIF) {/*end*/
1863 					matched = true;
1864 					skipped = false;
1865 				} else if (cond == COND_ELSE) /*else*/
1866 					matched = skipped ? false : true;
1867 				else {/*if , else if*/
1868 					if (skipped) {
1869 						matched = false;
1870 					} else {
1871 						if (_rtl8821ae_check_positive(
1872 								hw, v1, v2)) {
1873 							matched = true;
1874 							skipped = true;
1875 						} else {
1876 							matched = false;
1877 							skipped = false;
1878 						}
1879 					}
1880 				}
1881 			} else if (v1 & BIT(30)) { /*negative condition*/
1882 			/*do nothing*/
1883 			}
1884 		} else {
1885 			if (matched)
1886 				set_reg(hw, v1, v2);
1887 		}
1888 		i = i + 2;
1889 	}
1890 
1891 	return true;
1892 }
1893 
1894 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1895 {
1896 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1897 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1898 	u32 arraylength;
1899 	u32 *ptrarray;
1900 
1901 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read MAC_REG_Array\n");
1902 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1903 		arraylength = RTL8821AE_MAC_1T_ARRAYLEN;
1904 		ptrarray = RTL8821AE_MAC_REG_ARRAY;
1905 	} else {
1906 		arraylength = RTL8812AE_MAC_1T_ARRAYLEN;
1907 		ptrarray = RTL8812AE_MAC_REG_ARRAY;
1908 	}
1909 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1910 		"Img: MAC_REG_ARRAY LEN %d\n", arraylength);
1911 
1912 	return __rtl8821ae_phy_config_with_headerfile(hw,
1913 			ptrarray, arraylength, rtl_write_byte_with_val32);
1914 }
1915 
1916 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1917 						     u8 configtype)
1918 {
1919 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1920 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1921 	u32 *array_table;
1922 	u16 arraylen;
1923 
1924 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
1925 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1926 			arraylen = RTL8812AE_PHY_REG_1TARRAYLEN;
1927 			array_table = RTL8812AE_PHY_REG_ARRAY;
1928 		} else {
1929 			arraylen = RTL8821AE_PHY_REG_1TARRAYLEN;
1930 			array_table = RTL8821AE_PHY_REG_ARRAY;
1931 		}
1932 
1933 		return __rtl8821ae_phy_config_with_headerfile(hw,
1934 				array_table, arraylen,
1935 				_rtl8821ae_config_bb_reg);
1936 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1937 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1938 			arraylen = RTL8812AE_AGC_TAB_1TARRAYLEN;
1939 			array_table = RTL8812AE_AGC_TAB_ARRAY;
1940 		} else {
1941 			arraylen = RTL8821AE_AGC_TAB_1TARRAYLEN;
1942 			array_table = RTL8821AE_AGC_TAB_ARRAY;
1943 		}
1944 
1945 		return __rtl8821ae_phy_config_with_headerfile(hw,
1946 				array_table, arraylen,
1947 				rtl_set_bbreg_with_dwmask);
1948 	}
1949 	return true;
1950 }
1951 
1952 static u8 _rtl8821ae_get_rate_section_index(u32 regaddr)
1953 {
1954 	u8 index = 0;
1955 	regaddr &= 0xFFF;
1956 	if (regaddr >= 0xC20 && regaddr <= 0xC4C)
1957 		index = (u8)((regaddr - 0xC20) / 4);
1958 	else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
1959 		index = (u8)((regaddr - 0xE20) / 4);
1960 	else
1961 		WARN_ONCE(true,
1962 			  "rtl8821ae: Invalid RegAddr 0x%x\n", regaddr);
1963 	return index;
1964 }
1965 
1966 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw,
1967 					      u32 band, u32 rfpath,
1968 					      u32 txnum, u32 regaddr,
1969 					      u32 bitmask, u32 data)
1970 {
1971 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1972 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1973 	u8 rate_section = _rtl8821ae_get_rate_section_index(regaddr);
1974 
1975 	if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
1976 		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n", band);
1977 		band = BAND_ON_2_4G;
1978 	}
1979 	if (rfpath >= MAX_RF_PATH) {
1980 		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n", rfpath);
1981 		rfpath = MAX_RF_PATH - 1;
1982 	}
1983 	if (txnum >= MAX_RF_PATH) {
1984 		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n", txnum);
1985 		txnum = MAX_RF_PATH - 1;
1986 	}
1987 	rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data;
1988 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1989 		"TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1990 		band, rfpath, txnum, rate_section,
1991 		rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]);
1992 }
1993 
1994 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1995 							u8 configtype)
1996 {
1997 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1998 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1999 	int i;
2000 	u32 *array;
2001 	u16 arraylen;
2002 	u32 v1, v2, v3, v4, v5, v6;
2003 
2004 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2005 		arraylen = RTL8812AE_PHY_REG_ARRAY_PGLEN;
2006 		array = RTL8812AE_PHY_REG_ARRAY_PG;
2007 	} else {
2008 		arraylen = RTL8821AE_PHY_REG_ARRAY_PGLEN;
2009 		array = RTL8821AE_PHY_REG_ARRAY_PG;
2010 	}
2011 
2012 	if (configtype != BASEBAND_CONFIG_PHY_REG) {
2013 		rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
2014 			"configtype != BaseBand_Config_PHY_REG\n");
2015 		return true;
2016 	}
2017 	for (i = 0; i < arraylen; i += 6) {
2018 		v1 = array[i];
2019 		v2 = array[i+1];
2020 		v3 = array[i+2];
2021 		v4 = array[i+3];
2022 		v5 = array[i+4];
2023 		v6 = array[i+5];
2024 
2025 		if (v1 < 0xCDCDCDCD) {
2026 			if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
2027 				(v4 == 0xfe || v4 == 0xffe)) {
2028 				msleep(50);
2029 				continue;
2030 			}
2031 
2032 			if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2033 				if (v4 == 0xfe)
2034 					msleep(50);
2035 				else if (v4 == 0xfd)
2036 					mdelay(5);
2037 				else if (v4 == 0xfc)
2038 					mdelay(1);
2039 				else if (v4 == 0xfb)
2040 					udelay(50);
2041 				else if (v4 == 0xfa)
2042 					udelay(5);
2043 				else if (v4 == 0xf9)
2044 					udelay(1);
2045 			}
2046 			_rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3,
2047 							  v4, v5, v6);
2048 			continue;
2049 		} else {
2050 			 /*don't need the hw_body*/
2051 			if (!_rtl8821ae_check_condition(hw, v1)) {
2052 				i += 2; /* skip the pair of expression*/
2053 				v1 = array[i];
2054 				v2 = array[i+1];
2055 				v3 = array[i+2];
2056 				while (v2 != 0xDEAD) {
2057 					i += 3;
2058 					v1 = array[i];
2059 					v2 = array[i+1];
2060 					v3 = array[i+2];
2061 				}
2062 			}
2063 		}
2064 	}
2065 
2066 	return true;
2067 }
2068 
2069 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2070 					     enum radio_path rfpath)
2071 {
2072 	u32 *radioa_array_table_a, *radioa_array_table_b;
2073 	u16 radioa_arraylen_a, radioa_arraylen_b;
2074 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2075 
2076 	radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN;
2077 	radioa_array_table_a = RTL8812AE_RADIOA_ARRAY;
2078 	radioa_arraylen_b = RTL8812AE_RADIOB_1TARRAYLEN;
2079 	radioa_array_table_b = RTL8812AE_RADIOB_ARRAY;
2080 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2081 		"Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a);
2082 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2083 	switch (rfpath) {
2084 	case RF90_PATH_A:
2085 		return __rtl8821ae_phy_config_with_headerfile(hw,
2086 				radioa_array_table_a, radioa_arraylen_a,
2087 				_rtl8821ae_config_rf_radio_a);
2088 		break;
2089 	case RF90_PATH_B:
2090 		return __rtl8821ae_phy_config_with_headerfile(hw,
2091 				radioa_array_table_b, radioa_arraylen_b,
2092 				_rtl8821ae_config_rf_radio_b);
2093 		break;
2094 	case RF90_PATH_C:
2095 	case RF90_PATH_D:
2096 		pr_err("switch case %#x not processed\n", rfpath);
2097 		break;
2098 	}
2099 	return true;
2100 }
2101 
2102 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
2103 						enum radio_path rfpath)
2104 {
2105 	u32 *radioa_array_table;
2106 	u16 radioa_arraylen;
2107 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2108 
2109 	radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN;
2110 	radioa_array_table = RTL8821AE_RADIOA_ARRAY;
2111 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2112 		"Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen);
2113 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
2114 	switch (rfpath) {
2115 	case RF90_PATH_A:
2116 		return __rtl8821ae_phy_config_with_headerfile(hw,
2117 			radioa_array_table, radioa_arraylen,
2118 			_rtl8821ae_config_rf_radio_a);
2119 		break;
2120 
2121 	case RF90_PATH_B:
2122 	case RF90_PATH_C:
2123 	case RF90_PATH_D:
2124 		pr_err("switch case %#x not processed\n", rfpath);
2125 		break;
2126 	}
2127 	return true;
2128 }
2129 
2130 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
2131 {
2132 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2133 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2134 
2135 	rtlphy->default_initialgain[0] =
2136 	    (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
2137 	rtlphy->default_initialgain[1] =
2138 	    (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
2139 	rtlphy->default_initialgain[2] =
2140 	    (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
2141 	rtlphy->default_initialgain[3] =
2142 	    (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
2143 
2144 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2145 		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
2146 		rtlphy->default_initialgain[0],
2147 		rtlphy->default_initialgain[1],
2148 		rtlphy->default_initialgain[2],
2149 		rtlphy->default_initialgain[3]);
2150 
2151 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,
2152 					       ROFDM0_RXDETECTOR3, MASKBYTE0);
2153 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,
2154 					      ROFDM0_RXDETECTOR2, MASKDWORD);
2155 
2156 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2157 		"Default framesync (0x%x) = 0x%x\n",
2158 		ROFDM0_RXDETECTOR3, rtlphy->framesync);
2159 }
2160 
2161 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
2162 {
2163 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2164 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2165 
2166 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2167 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
2168 
2169 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
2170 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
2171 
2172 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
2173 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
2174 
2175 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;
2176 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;
2177 
2178 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;
2179 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;
2180 
2181 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A;
2182 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A;
2183 
2184 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A;
2185 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A;
2186 }
2187 
2188 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
2189 {
2190 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2191 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2192 	u8 txpwr_level;
2193 	long txpwr_dbm;
2194 
2195 	txpwr_level = rtlphy->cur_cck_txpwridx;
2196 	txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2197 						 WIRELESS_MODE_B, txpwr_level);
2198 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2199 	if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2200 					 WIRELESS_MODE_G,
2201 					 txpwr_level) > txpwr_dbm)
2202 		txpwr_dbm =
2203 		    _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
2204 						 txpwr_level);
2205 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
2206 	if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
2207 					 WIRELESS_MODE_N_24G,
2208 					 txpwr_level) > txpwr_dbm)
2209 		txpwr_dbm =
2210 		    _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
2211 						 txpwr_level);
2212 	*powerlevel = txpwr_dbm;
2213 }
2214 
2215 static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index)
2216 {
2217 	u8 i = 0;
2218 	bool in_24g = true;
2219 
2220 	if (channel <= 14) {
2221 		in_24g = true;
2222 		*chnl_index = channel - 1;
2223 	} else {
2224 		in_24g = false;
2225 
2226 		for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) {
2227 			if (channel5g[i] == channel) {
2228 				*chnl_index = i;
2229 				return in_24g;
2230 			}
2231 		}
2232 	}
2233 	return in_24g;
2234 }
2235 
2236 static s8 _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate)
2237 {
2238 	s8 rate_section = 0;
2239 	switch (rate) {
2240 	case DESC_RATE1M:
2241 	case DESC_RATE2M:
2242 	case DESC_RATE5_5M:
2243 	case DESC_RATE11M:
2244 		rate_section = 0;
2245 		break;
2246 	case DESC_RATE6M:
2247 	case DESC_RATE9M:
2248 	case DESC_RATE12M:
2249 	case DESC_RATE18M:
2250 		rate_section = 1;
2251 		break;
2252 	case DESC_RATE24M:
2253 	case DESC_RATE36M:
2254 	case DESC_RATE48M:
2255 	case DESC_RATE54M:
2256 		rate_section = 2;
2257 		break;
2258 	case DESC_RATEMCS0:
2259 	case DESC_RATEMCS1:
2260 	case DESC_RATEMCS2:
2261 	case DESC_RATEMCS3:
2262 		rate_section = 3;
2263 		break;
2264 	case DESC_RATEMCS4:
2265 	case DESC_RATEMCS5:
2266 	case DESC_RATEMCS6:
2267 	case DESC_RATEMCS7:
2268 		rate_section = 4;
2269 		break;
2270 	case DESC_RATEMCS8:
2271 	case DESC_RATEMCS9:
2272 	case DESC_RATEMCS10:
2273 	case DESC_RATEMCS11:
2274 		rate_section = 5;
2275 		break;
2276 	case DESC_RATEMCS12:
2277 	case DESC_RATEMCS13:
2278 	case DESC_RATEMCS14:
2279 	case DESC_RATEMCS15:
2280 		rate_section = 6;
2281 		break;
2282 	case DESC_RATEVHT1SS_MCS0:
2283 	case DESC_RATEVHT1SS_MCS1:
2284 	case DESC_RATEVHT1SS_MCS2:
2285 	case DESC_RATEVHT1SS_MCS3:
2286 		rate_section = 7;
2287 		break;
2288 	case DESC_RATEVHT1SS_MCS4:
2289 	case DESC_RATEVHT1SS_MCS5:
2290 	case DESC_RATEVHT1SS_MCS6:
2291 	case DESC_RATEVHT1SS_MCS7:
2292 		rate_section = 8;
2293 		break;
2294 	case DESC_RATEVHT1SS_MCS8:
2295 	case DESC_RATEVHT1SS_MCS9:
2296 	case DESC_RATEVHT2SS_MCS0:
2297 	case DESC_RATEVHT2SS_MCS1:
2298 		rate_section = 9;
2299 		break;
2300 	case DESC_RATEVHT2SS_MCS2:
2301 	case DESC_RATEVHT2SS_MCS3:
2302 	case DESC_RATEVHT2SS_MCS4:
2303 	case DESC_RATEVHT2SS_MCS5:
2304 		rate_section = 10;
2305 		break;
2306 	case DESC_RATEVHT2SS_MCS6:
2307 	case DESC_RATEVHT2SS_MCS7:
2308 	case DESC_RATEVHT2SS_MCS8:
2309 	case DESC_RATEVHT2SS_MCS9:
2310 		rate_section = 11;
2311 		break;
2312 	default:
2313 		WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n");
2314 		break;
2315 	}
2316 
2317 	return rate_section;
2318 }
2319 
2320 static s8 _rtl8812ae_phy_get_world_wide_limit(s8  *limit_table)
2321 {
2322 	s8 min = limit_table[0];
2323 	u8 i = 0;
2324 
2325 	for (i = 0; i < MAX_REGULATION_NUM; ++i) {
2326 		if (limit_table[i] < min)
2327 			min = limit_table[i];
2328 	}
2329 	return min;
2330 }
2331 
2332 static s8 _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw,
2333 					     u8 band,
2334 					     enum ht_channel_width bandwidth,
2335 					     enum radio_path rf_path,
2336 					     u8 rate, u8 channel)
2337 {
2338 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2339 	struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
2340 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2341 	short band_temp = -1, regulation = -1, bandwidth_temp = -1,
2342 		 rate_section = -1, channel_temp = -1;
2343 	u16 regu, bdwidth, sec, chnl;
2344 	s8 power_limit = MAX_POWER_INDEX;
2345 
2346 	if (rtlefuse->eeprom_regulatory == 2)
2347 		return MAX_POWER_INDEX;
2348 
2349 	regulation = TXPWR_LMT_WW;
2350 
2351 	if (band == BAND_ON_2_4G)
2352 		band_temp = 0;
2353 	else if (band == BAND_ON_5G)
2354 		band_temp = 1;
2355 
2356 	if (bandwidth == HT_CHANNEL_WIDTH_20)
2357 		bandwidth_temp = 0;
2358 	else if (bandwidth == HT_CHANNEL_WIDTH_20_40)
2359 		bandwidth_temp = 1;
2360 	else if (bandwidth == HT_CHANNEL_WIDTH_80)
2361 		bandwidth_temp = 2;
2362 
2363 	switch (rate) {
2364 	case DESC_RATE1M:
2365 	case DESC_RATE2M:
2366 	case DESC_RATE5_5M:
2367 	case DESC_RATE11M:
2368 		rate_section = 0;
2369 		break;
2370 	case DESC_RATE6M:
2371 	case DESC_RATE9M:
2372 	case DESC_RATE12M:
2373 	case DESC_RATE18M:
2374 	case DESC_RATE24M:
2375 	case DESC_RATE36M:
2376 	case DESC_RATE48M:
2377 	case DESC_RATE54M:
2378 		rate_section = 1;
2379 		break;
2380 	case DESC_RATEMCS0:
2381 	case DESC_RATEMCS1:
2382 	case DESC_RATEMCS2:
2383 	case DESC_RATEMCS3:
2384 	case DESC_RATEMCS4:
2385 	case DESC_RATEMCS5:
2386 	case DESC_RATEMCS6:
2387 	case DESC_RATEMCS7:
2388 		rate_section = 2;
2389 		break;
2390 	case DESC_RATEMCS8:
2391 	case DESC_RATEMCS9:
2392 	case DESC_RATEMCS10:
2393 	case DESC_RATEMCS11:
2394 	case DESC_RATEMCS12:
2395 	case DESC_RATEMCS13:
2396 	case DESC_RATEMCS14:
2397 	case DESC_RATEMCS15:
2398 		rate_section = 3;
2399 		break;
2400 	case DESC_RATEVHT1SS_MCS0:
2401 	case DESC_RATEVHT1SS_MCS1:
2402 	case DESC_RATEVHT1SS_MCS2:
2403 	case DESC_RATEVHT1SS_MCS3:
2404 	case DESC_RATEVHT1SS_MCS4:
2405 	case DESC_RATEVHT1SS_MCS5:
2406 	case DESC_RATEVHT1SS_MCS6:
2407 	case DESC_RATEVHT1SS_MCS7:
2408 	case DESC_RATEVHT1SS_MCS8:
2409 	case DESC_RATEVHT1SS_MCS9:
2410 		rate_section = 4;
2411 		break;
2412 	case DESC_RATEVHT2SS_MCS0:
2413 	case DESC_RATEVHT2SS_MCS1:
2414 	case DESC_RATEVHT2SS_MCS2:
2415 	case DESC_RATEVHT2SS_MCS3:
2416 	case DESC_RATEVHT2SS_MCS4:
2417 	case DESC_RATEVHT2SS_MCS5:
2418 	case DESC_RATEVHT2SS_MCS6:
2419 	case DESC_RATEVHT2SS_MCS7:
2420 	case DESC_RATEVHT2SS_MCS8:
2421 	case DESC_RATEVHT2SS_MCS9:
2422 		rate_section = 5;
2423 		break;
2424 	default:
2425 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2426 			"Wrong rate 0x%x\n", rate);
2427 		break;
2428 	}
2429 
2430 	if (band_temp == BAND_ON_5G  && rate_section == 0)
2431 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2432 			"Wrong rate 0x%x: No CCK in 5G Band\n", rate);
2433 
2434 	/*workaround for wrong index combination to obtain tx power limit,
2435 	  OFDM only exists in BW 20M*/
2436 	if (rate_section == 1)
2437 		bandwidth_temp = 0;
2438 
2439 	/*workaround for wrong index combination to obtain tx power limit,
2440 	 *HT on 80M will reference to HT on 40M
2441 	 */
2442 	if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G &&
2443 	    bandwidth_temp == 2)
2444 		bandwidth_temp = 1;
2445 
2446 	if (band == BAND_ON_2_4G)
2447 		channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2448 		BAND_ON_2_4G, channel);
2449 	else if (band == BAND_ON_5G)
2450 		channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw,
2451 		BAND_ON_5G, channel);
2452 	else if (band == BAND_ON_BOTH)
2453 		;/* BAND_ON_BOTH don't care temporarily */
2454 
2455 	if (band_temp == -1 || regulation == -1 || bandwidth_temp == -1 ||
2456 		rate_section == -1 || channel_temp == -1) {
2457 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2458 			"Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n",
2459 			band_temp, regulation, bandwidth_temp, rf_path,
2460 			rate_section, channel_temp);
2461 		return MAX_POWER_INDEX;
2462 	}
2463 
2464 	regu = regulation;
2465 	bdwidth = bandwidth_temp;
2466 	sec = rate_section;
2467 	chnl = channel_temp;
2468 
2469 	if (band == BAND_ON_2_4G) {
2470 		s8 limits[10] = {0};
2471 		u8 i;
2472 
2473 		for (i = 0; i < 4; ++i)
2474 			limits[i] = rtlphy->txpwr_limit_2_4g[i][bdwidth]
2475 			[sec][chnl][rf_path];
2476 
2477 		power_limit = (regulation == TXPWR_LMT_WW) ?
2478 			_rtl8812ae_phy_get_world_wide_limit(limits) :
2479 			rtlphy->txpwr_limit_2_4g[regu][bdwidth]
2480 					[sec][chnl][rf_path];
2481 	} else if (band == BAND_ON_5G) {
2482 		s8 limits[10] = {0};
2483 		u8 i;
2484 
2485 		for (i = 0; i < MAX_REGULATION_NUM; ++i)
2486 			limits[i] = rtlphy->txpwr_limit_5g[i][bdwidth]
2487 			[sec][chnl][rf_path];
2488 
2489 		power_limit = (regulation == TXPWR_LMT_WW) ?
2490 			_rtl8812ae_phy_get_world_wide_limit(limits) :
2491 			rtlphy->txpwr_limit_5g[regu][chnl]
2492 			[sec][chnl][rf_path];
2493 	} else {
2494 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2495 			"No power limit table of the specified band\n");
2496 	}
2497 	return power_limit;
2498 }
2499 
2500 static s8 _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw,
2501 					u8 band, u8 path, u8 rate)
2502 {
2503 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2504 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2505 	u8 shift = 0, rate_section, tx_num;
2506 	s8 tx_pwr_diff = 0;
2507 	s8 limit = 0;
2508 
2509 	rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate);
2510 	tx_num = RF_TX_NUM_NONIMPLEMENT;
2511 
2512 	if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
2513 		if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
2514 			(rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9))
2515 			tx_num = RF_2TX;
2516 		else
2517 			tx_num = RF_1TX;
2518 	}
2519 
2520 	switch (rate) {
2521 	case DESC_RATE1M:
2522 	case DESC_RATE6M:
2523 	case DESC_RATE24M:
2524 	case DESC_RATEMCS0:
2525 	case DESC_RATEMCS4:
2526 	case DESC_RATEMCS8:
2527 	case DESC_RATEMCS12:
2528 	case DESC_RATEVHT1SS_MCS0:
2529 	case DESC_RATEVHT1SS_MCS4:
2530 	case DESC_RATEVHT1SS_MCS8:
2531 	case DESC_RATEVHT2SS_MCS2:
2532 	case DESC_RATEVHT2SS_MCS6:
2533 		shift = 0;
2534 		break;
2535 	case DESC_RATE2M:
2536 	case DESC_RATE9M:
2537 	case DESC_RATE36M:
2538 	case DESC_RATEMCS1:
2539 	case DESC_RATEMCS5:
2540 	case DESC_RATEMCS9:
2541 	case DESC_RATEMCS13:
2542 	case DESC_RATEVHT1SS_MCS1:
2543 	case DESC_RATEVHT1SS_MCS5:
2544 	case DESC_RATEVHT1SS_MCS9:
2545 	case DESC_RATEVHT2SS_MCS3:
2546 	case DESC_RATEVHT2SS_MCS7:
2547 		shift = 8;
2548 		break;
2549 	case DESC_RATE5_5M:
2550 	case DESC_RATE12M:
2551 	case DESC_RATE48M:
2552 	case DESC_RATEMCS2:
2553 	case DESC_RATEMCS6:
2554 	case DESC_RATEMCS10:
2555 	case DESC_RATEMCS14:
2556 	case DESC_RATEVHT1SS_MCS2:
2557 	case DESC_RATEVHT1SS_MCS6:
2558 	case DESC_RATEVHT2SS_MCS0:
2559 	case DESC_RATEVHT2SS_MCS4:
2560 	case DESC_RATEVHT2SS_MCS8:
2561 		shift = 16;
2562 		break;
2563 	case DESC_RATE11M:
2564 	case DESC_RATE18M:
2565 	case DESC_RATE54M:
2566 	case DESC_RATEMCS3:
2567 	case DESC_RATEMCS7:
2568 	case DESC_RATEMCS11:
2569 	case DESC_RATEMCS15:
2570 	case DESC_RATEVHT1SS_MCS3:
2571 	case DESC_RATEVHT1SS_MCS7:
2572 	case DESC_RATEVHT2SS_MCS1:
2573 	case DESC_RATEVHT2SS_MCS5:
2574 	case DESC_RATEVHT2SS_MCS9:
2575 		shift = 24;
2576 		break;
2577 	default:
2578 		WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n");
2579 		break;
2580 	}
2581 
2582 	tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][path]
2583 		[tx_num][rate_section] >> shift) & 0xff;
2584 
2585 	/* RegEnableTxPowerLimit == 1 for 8812a & 8821a */
2586 	if (rtlpriv->efuse.eeprom_regulatory != 2) {
2587 		limit = _rtl8812ae_phy_get_txpower_limit(hw, band,
2588 			rtlphy->current_chan_bw, path, rate,
2589 			rtlphy->current_channel);
2590 
2591 		if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9  ||
2592 			 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) {
2593 			if (limit < 0) {
2594 				if (tx_pwr_diff < (-limit))
2595 					tx_pwr_diff = -limit;
2596 			}
2597 		} else {
2598 			if (limit < 0)
2599 				tx_pwr_diff = limit;
2600 			else
2601 				tx_pwr_diff = tx_pwr_diff > limit ? limit : tx_pwr_diff;
2602 		}
2603 		rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2604 			"Maximum power by rate %d, final power by rate %d\n",
2605 			limit, tx_pwr_diff);
2606 	}
2607 
2608 	return	tx_pwr_diff;
2609 }
2610 
2611 static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path,
2612 					u8 rate, u8 bandwidth, u8 channel)
2613 {
2614 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2615 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2616 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2617 	u8 index = (channel - 1);
2618 	u8 txpower = 0;
2619 	bool in_24g = false;
2620 	s8 powerdiff_byrate = 0;
2621 
2622 	if (((rtlhal->current_bandtype == BAND_ON_2_4G) &&
2623 	    (channel > 14 || channel < 1)) ||
2624 	    ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) {
2625 		index = 0;
2626 		rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
2627 			"Illegal channel!!\n");
2628 	}
2629 
2630 	in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index);
2631 	if (in_24g) {
2632 		if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2633 			txpower = rtlefuse->txpwrlevel_cck[path][index];
2634 		else if (DESC_RATE6M <= rate)
2635 			txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
2636 		else
2637 			rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "invalid rate\n");
2638 
2639 		if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2640 		    !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2641 			txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
2642 
2643 		if (bandwidth == HT_CHANNEL_WIDTH_20) {
2644 			if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2645 				(DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2646 				txpower += rtlefuse->txpwr_ht20diff[path][TX_1S];
2647 			if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2648 				(DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2649 				txpower += rtlefuse->txpwr_ht20diff[path][TX_2S];
2650 		} else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2651 			if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2652 				(DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2653 				txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2654 			if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2655 				(DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2656 				txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2657 		} else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2658 			if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2659 			    (DESC_RATEVHT1SS_MCS0 <= rate &&
2660 			     rate <= DESC_RATEVHT2SS_MCS9))
2661 				txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2662 			if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2663 			    (DESC_RATEVHT2SS_MCS0 <= rate &&
2664 			     rate <= DESC_RATEVHT2SS_MCS9))
2665 				txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2666 		}
2667 	} else {
2668 		if (DESC_RATE6M <= rate)
2669 			txpower = rtlefuse->txpwr_5g_bw40base[path][index];
2670 		else
2671 			rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING,
2672 				"INVALID Rate.\n");
2673 
2674 		if (DESC_RATE6M <= rate && rate <= DESC_RATE54M &&
2675 		    !RTL8821AE_RX_HAL_IS_CCK_RATE(rate))
2676 			txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
2677 
2678 		if (bandwidth == HT_CHANNEL_WIDTH_20) {
2679 			if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2680 			    (DESC_RATEVHT1SS_MCS0 <= rate &&
2681 			     rate <= DESC_RATEVHT2SS_MCS9))
2682 				txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S];
2683 			if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2684 			    (DESC_RATEVHT2SS_MCS0 <= rate &&
2685 			     rate <= DESC_RATEVHT2SS_MCS9))
2686 				txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S];
2687 		} else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2688 			if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2689 			    (DESC_RATEVHT1SS_MCS0 <= rate &&
2690 			     rate <= DESC_RATEVHT2SS_MCS9))
2691 				txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S];
2692 			if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2693 			    (DESC_RATEVHT2SS_MCS0 <= rate &&
2694 			     rate <= DESC_RATEVHT2SS_MCS9))
2695 				txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S];
2696 		} else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2697 			u8 i;
2698 
2699 			for (i = 0; i < sizeof(channel5g_80m) / sizeof(u8); ++i)
2700 				if (channel5g_80m[i] == channel)
2701 					index = i;
2702 
2703 			if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2704 			    (DESC_RATEVHT1SS_MCS0 <= rate &&
2705 			     rate <= DESC_RATEVHT2SS_MCS9))
2706 				txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2707 					+ rtlefuse->txpwr_5g_bw80diff[path][TX_1S];
2708 			if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2709 			    (DESC_RATEVHT2SS_MCS0 <= rate &&
2710 			     rate <= DESC_RATEVHT2SS_MCS9))
2711 				txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2712 					+ rtlefuse->txpwr_5g_bw80diff[path][TX_1S]
2713 					+ rtlefuse->txpwr_5g_bw80diff[path][TX_2S];
2714 		    }
2715 	}
2716 	if (rtlefuse->eeprom_regulatory != 2)
2717 		powerdiff_byrate =
2718 		  _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g),
2719 						     path, rate);
2720 
2721 	if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2722 	    rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9)
2723 		txpower -= powerdiff_byrate;
2724 	else
2725 		txpower += powerdiff_byrate;
2726 
2727 	if (rate > DESC_RATE11M)
2728 		txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path];
2729 	else
2730 		txpower += rtlpriv->dm.remnant_cck_idx;
2731 
2732 	if (txpower > MAX_POWER_INDEX)
2733 		txpower = MAX_POWER_INDEX;
2734 
2735 	return txpower;
2736 }
2737 
2738 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
2739 					     u8 power_index, u8 path, u8 rate)
2740 {
2741 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2742 
2743 	if (path == RF90_PATH_A) {
2744 		switch (rate) {
2745 		case DESC_RATE1M:
2746 			rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2747 				      MASKBYTE0, power_index);
2748 			break;
2749 		case DESC_RATE2M:
2750 			rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2751 				      MASKBYTE1, power_index);
2752 			break;
2753 		case DESC_RATE5_5M:
2754 			rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2755 				      MASKBYTE2, power_index);
2756 			break;
2757 		case DESC_RATE11M:
2758 			rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1,
2759 				      MASKBYTE3, power_index);
2760 			break;
2761 		case DESC_RATE6M:
2762 			rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2763 				      MASKBYTE0, power_index);
2764 			break;
2765 		case DESC_RATE9M:
2766 			rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2767 				      MASKBYTE1, power_index);
2768 			break;
2769 		case DESC_RATE12M:
2770 			rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2771 				      MASKBYTE2, power_index);
2772 			break;
2773 		case DESC_RATE18M:
2774 			rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6,
2775 				      MASKBYTE3, power_index);
2776 			break;
2777 		case DESC_RATE24M:
2778 			rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2779 				      MASKBYTE0, power_index);
2780 			break;
2781 		case DESC_RATE36M:
2782 			rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2783 				      MASKBYTE1, power_index);
2784 			break;
2785 		case DESC_RATE48M:
2786 			rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2787 				      MASKBYTE2, power_index);
2788 			break;
2789 		case DESC_RATE54M:
2790 			rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24,
2791 				      MASKBYTE3, power_index);
2792 			break;
2793 		case DESC_RATEMCS0:
2794 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2795 				      MASKBYTE0, power_index);
2796 			break;
2797 		case DESC_RATEMCS1:
2798 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2799 				      MASKBYTE1, power_index);
2800 			break;
2801 		case DESC_RATEMCS2:
2802 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2803 				      MASKBYTE2, power_index);
2804 			break;
2805 		case DESC_RATEMCS3:
2806 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00,
2807 				      MASKBYTE3, power_index);
2808 			break;
2809 		case DESC_RATEMCS4:
2810 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2811 				      MASKBYTE0, power_index);
2812 			break;
2813 		case DESC_RATEMCS5:
2814 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2815 				      MASKBYTE1, power_index);
2816 			break;
2817 		case DESC_RATEMCS6:
2818 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2819 				      MASKBYTE2, power_index);
2820 			break;
2821 		case DESC_RATEMCS7:
2822 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
2823 				      MASKBYTE3, power_index);
2824 			break;
2825 		case DESC_RATEMCS8:
2826 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2827 				      MASKBYTE0, power_index);
2828 			break;
2829 		case DESC_RATEMCS9:
2830 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2831 				      MASKBYTE1, power_index);
2832 			break;
2833 		case DESC_RATEMCS10:
2834 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2835 				      MASKBYTE2, power_index);
2836 			break;
2837 		case DESC_RATEMCS11:
2838 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08,
2839 				      MASKBYTE3, power_index);
2840 			break;
2841 		case DESC_RATEMCS12:
2842 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2843 				      MASKBYTE0, power_index);
2844 			break;
2845 		case DESC_RATEMCS13:
2846 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2847 				      MASKBYTE1, power_index);
2848 			break;
2849 		case DESC_RATEMCS14:
2850 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2851 				      MASKBYTE2, power_index);
2852 			break;
2853 		case DESC_RATEMCS15:
2854 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12,
2855 				      MASKBYTE3, power_index);
2856 			break;
2857 		case DESC_RATEVHT1SS_MCS0:
2858 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2859 				      MASKBYTE0, power_index);
2860 			break;
2861 		case DESC_RATEVHT1SS_MCS1:
2862 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2863 				      MASKBYTE1, power_index);
2864 			break;
2865 		case DESC_RATEVHT1SS_MCS2:
2866 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2867 				      MASKBYTE2, power_index);
2868 			break;
2869 		case DESC_RATEVHT1SS_MCS3:
2870 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0,
2871 				      MASKBYTE3, power_index);
2872 			break;
2873 		case DESC_RATEVHT1SS_MCS4:
2874 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2875 				      MASKBYTE0, power_index);
2876 			break;
2877 		case DESC_RATEVHT1SS_MCS5:
2878 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2879 				      MASKBYTE1, power_index);
2880 			break;
2881 		case DESC_RATEVHT1SS_MCS6:
2882 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2883 				      MASKBYTE2, power_index);
2884 			break;
2885 		case DESC_RATEVHT1SS_MCS7:
2886 			rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4,
2887 				      MASKBYTE3, power_index);
2888 			break;
2889 		case DESC_RATEVHT1SS_MCS8:
2890 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2891 				      MASKBYTE0, power_index);
2892 			break;
2893 		case DESC_RATEVHT1SS_MCS9:
2894 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2895 				      MASKBYTE1, power_index);
2896 			break;
2897 		case DESC_RATEVHT2SS_MCS0:
2898 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2899 				      MASKBYTE2, power_index);
2900 			break;
2901 		case DESC_RATEVHT2SS_MCS1:
2902 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8,
2903 				      MASKBYTE3, power_index);
2904 			break;
2905 		case DESC_RATEVHT2SS_MCS2:
2906 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2907 				      MASKBYTE0, power_index);
2908 			break;
2909 		case DESC_RATEVHT2SS_MCS3:
2910 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2911 				      MASKBYTE1, power_index);
2912 			break;
2913 		case DESC_RATEVHT2SS_MCS4:
2914 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2915 				      MASKBYTE2, power_index);
2916 			break;
2917 		case DESC_RATEVHT2SS_MCS5:
2918 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2,
2919 				      MASKBYTE3, power_index);
2920 			break;
2921 		case DESC_RATEVHT2SS_MCS6:
2922 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2923 				      MASKBYTE0, power_index);
2924 			break;
2925 		case DESC_RATEVHT2SS_MCS7:
2926 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2927 				      MASKBYTE1, power_index);
2928 			break;
2929 		case DESC_RATEVHT2SS_MCS8:
2930 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2931 				      MASKBYTE2, power_index);
2932 			break;
2933 		case DESC_RATEVHT2SS_MCS9:
2934 			rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6,
2935 				      MASKBYTE3, power_index);
2936 			break;
2937 		default:
2938 			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
2939 				"Invalid Rate!!\n");
2940 			break;
2941 		}
2942 	} else if (path == RF90_PATH_B) {
2943 		switch (rate) {
2944 		case DESC_RATE1M:
2945 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2946 				      MASKBYTE0, power_index);
2947 			break;
2948 		case DESC_RATE2M:
2949 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2950 				      MASKBYTE1, power_index);
2951 			break;
2952 		case DESC_RATE5_5M:
2953 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2954 				      MASKBYTE2, power_index);
2955 			break;
2956 		case DESC_RATE11M:
2957 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1,
2958 				      MASKBYTE3, power_index);
2959 			break;
2960 		case DESC_RATE6M:
2961 			rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2962 				      MASKBYTE0, power_index);
2963 			break;
2964 		case DESC_RATE9M:
2965 			rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2966 				      MASKBYTE1, power_index);
2967 			break;
2968 		case DESC_RATE12M:
2969 			rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2970 				      MASKBYTE2, power_index);
2971 			break;
2972 		case DESC_RATE18M:
2973 			rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6,
2974 				      MASKBYTE3, power_index);
2975 			break;
2976 		case DESC_RATE24M:
2977 			rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2978 				      MASKBYTE0, power_index);
2979 			break;
2980 		case DESC_RATE36M:
2981 			rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2982 				      MASKBYTE1, power_index);
2983 			break;
2984 		case DESC_RATE48M:
2985 			rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2986 				      MASKBYTE2, power_index);
2987 			break;
2988 		case DESC_RATE54M:
2989 			rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24,
2990 				      MASKBYTE3, power_index);
2991 			break;
2992 		case DESC_RATEMCS0:
2993 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2994 				      MASKBYTE0, power_index);
2995 			break;
2996 		case DESC_RATEMCS1:
2997 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
2998 				      MASKBYTE1, power_index);
2999 			break;
3000 		case DESC_RATEMCS2:
3001 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3002 				      MASKBYTE2, power_index);
3003 			break;
3004 		case DESC_RATEMCS3:
3005 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00,
3006 				      MASKBYTE3, power_index);
3007 			break;
3008 		case DESC_RATEMCS4:
3009 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3010 				      MASKBYTE0, power_index);
3011 			break;
3012 		case DESC_RATEMCS5:
3013 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3014 				      MASKBYTE1, power_index);
3015 			break;
3016 		case DESC_RATEMCS6:
3017 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3018 				      MASKBYTE2, power_index);
3019 			break;
3020 		case DESC_RATEMCS7:
3021 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04,
3022 				      MASKBYTE3, power_index);
3023 			break;
3024 		case DESC_RATEMCS8:
3025 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3026 				      MASKBYTE0, power_index);
3027 			break;
3028 		case DESC_RATEMCS9:
3029 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3030 				      MASKBYTE1, power_index);
3031 			break;
3032 		case DESC_RATEMCS10:
3033 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3034 				      MASKBYTE2, power_index);
3035 			break;
3036 		case DESC_RATEMCS11:
3037 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08,
3038 				      MASKBYTE3, power_index);
3039 			break;
3040 		case DESC_RATEMCS12:
3041 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3042 				      MASKBYTE0, power_index);
3043 			break;
3044 		case DESC_RATEMCS13:
3045 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3046 				      MASKBYTE1, power_index);
3047 			break;
3048 		case DESC_RATEMCS14:
3049 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3050 				      MASKBYTE2, power_index);
3051 			break;
3052 		case DESC_RATEMCS15:
3053 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12,
3054 				      MASKBYTE3, power_index);
3055 			break;
3056 		case DESC_RATEVHT1SS_MCS0:
3057 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3058 				      MASKBYTE0, power_index);
3059 			break;
3060 		case DESC_RATEVHT1SS_MCS1:
3061 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3062 				      MASKBYTE1, power_index);
3063 			break;
3064 		case DESC_RATEVHT1SS_MCS2:
3065 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3066 				      MASKBYTE2, power_index);
3067 			break;
3068 		case DESC_RATEVHT1SS_MCS3:
3069 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0,
3070 				      MASKBYTE3, power_index);
3071 			break;
3072 		case DESC_RATEVHT1SS_MCS4:
3073 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3074 				      MASKBYTE0, power_index);
3075 			break;
3076 		case DESC_RATEVHT1SS_MCS5:
3077 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3078 				      MASKBYTE1, power_index);
3079 			break;
3080 		case DESC_RATEVHT1SS_MCS6:
3081 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3082 				      MASKBYTE2, power_index);
3083 			break;
3084 		case DESC_RATEVHT1SS_MCS7:
3085 			rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4,
3086 				      MASKBYTE3, power_index);
3087 			break;
3088 		case DESC_RATEVHT1SS_MCS8:
3089 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3090 				      MASKBYTE0, power_index);
3091 			break;
3092 		case DESC_RATEVHT1SS_MCS9:
3093 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3094 				      MASKBYTE1, power_index);
3095 			break;
3096 		case DESC_RATEVHT2SS_MCS0:
3097 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3098 				      MASKBYTE2, power_index);
3099 			break;
3100 		case DESC_RATEVHT2SS_MCS1:
3101 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8,
3102 				      MASKBYTE3, power_index);
3103 			break;
3104 		case DESC_RATEVHT2SS_MCS2:
3105 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3106 				      MASKBYTE0, power_index);
3107 			break;
3108 		case DESC_RATEVHT2SS_MCS3:
3109 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3110 				      MASKBYTE1, power_index);
3111 			break;
3112 		case DESC_RATEVHT2SS_MCS4:
3113 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3114 				      MASKBYTE2, power_index);
3115 			break;
3116 		case DESC_RATEVHT2SS_MCS5:
3117 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2,
3118 				      MASKBYTE3, power_index);
3119 			break;
3120 		case DESC_RATEVHT2SS_MCS6:
3121 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3122 				      MASKBYTE0, power_index);
3123 			break;
3124 		case DESC_RATEVHT2SS_MCS7:
3125 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3126 				      MASKBYTE1, power_index);
3127 			break;
3128 		case DESC_RATEVHT2SS_MCS8:
3129 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3130 				      MASKBYTE2, power_index);
3131 			break;
3132 		case DESC_RATEVHT2SS_MCS9:
3133 			rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6,
3134 				      MASKBYTE3, power_index);
3135 			break;
3136 		default:
3137 			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3138 				"Invalid Rate!!\n");
3139 			break;
3140 		}
3141 	} else {
3142 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3143 			"Invalid RFPath!!\n");
3144 	}
3145 }
3146 
3147 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3148 						     u8 *array, u8 path,
3149 						     u8 channel, u8 size)
3150 {
3151 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3152 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3153 	u8 i;
3154 	u8 power_index;
3155 
3156 	for (i = 0; i < size; i++) {
3157 		power_index =
3158 		  _rtl8821ae_get_txpower_index(hw, path, array[i],
3159 					       rtlphy->current_chan_bw,
3160 					       channel);
3161 		_rtl8821ae_phy_set_txpower_index(hw, power_index, path,
3162 						 array[i]);
3163 	}
3164 }
3165 
3166 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw,
3167 						    u8 bw, u8 channel, u8 path)
3168 {
3169 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3170 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3171 
3172 	u8 i;
3173 	u32 power_level, data, offset;
3174 
3175 	if (path >= rtlphy->num_total_rfpath)
3176 		return;
3177 
3178 	data = 0;
3179 	if (path == RF90_PATH_A) {
3180 		power_level =
3181 			_rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
3182 			DESC_RATEMCS7, bw, channel);
3183 		offset =  RA_TXPWRTRAING;
3184 	} else {
3185 		power_level =
3186 			_rtl8821ae_get_txpower_index(hw, RF90_PATH_B,
3187 			DESC_RATEMCS7, bw, channel);
3188 		offset =  RB_TXPWRTRAING;
3189 	}
3190 
3191 	for (i = 0; i < 3; i++) {
3192 		if (i == 0)
3193 			power_level = power_level - 10;
3194 		else if (i == 1)
3195 			power_level = power_level - 8;
3196 		else
3197 			power_level = power_level - 6;
3198 
3199 		data |= (((power_level > 2) ? (power_level) : 2) << (i * 8));
3200 	}
3201 	rtl_set_bbreg(hw, offset, 0xffffff, data);
3202 }
3203 
3204 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
3205 					     u8 channel, u8 path)
3206 {
3207 	/* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
3208 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3209 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3210 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3211 	u8 cck_rates[]  = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M,
3212 			      DESC_RATE11M};
3213 	u8 sizes_of_cck_retes = 4;
3214 	u8 ofdm_rates[]  = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
3215 				DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
3216 				DESC_RATE48M, DESC_RATE54M};
3217 	u8 sizes_of_ofdm_retes = 8;
3218 	u8 ht_rates_1t[]  = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
3219 				DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
3220 				DESC_RATEMCS6, DESC_RATEMCS7};
3221 	u8 sizes_of_ht_retes_1t = 8;
3222 	u8 ht_rates_2t[]  = {DESC_RATEMCS8, DESC_RATEMCS9,
3223 				DESC_RATEMCS10, DESC_RATEMCS11,
3224 				DESC_RATEMCS12, DESC_RATEMCS13,
3225 				DESC_RATEMCS14, DESC_RATEMCS15};
3226 	u8 sizes_of_ht_retes_2t = 8;
3227 	u8 vht_rates_1t[]  = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
3228 				DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
3229 				DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
3230 				DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
3231 			     DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
3232 	u8 vht_rates_2t[]  = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
3233 				DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
3234 				DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
3235 				DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
3236 				DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
3237 	u8 sizes_of_vht_retes = 10;
3238 
3239 	if (rtlhal->current_bandtype == BAND_ON_2_4G)
3240 		_rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel,
3241 							 sizes_of_cck_retes);
3242 
3243 	_rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel,
3244 						 sizes_of_ofdm_retes);
3245 	_rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel,
3246 						 sizes_of_ht_retes_1t);
3247 	_rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel,
3248 						 sizes_of_vht_retes);
3249 
3250 	if (rtlphy->num_total_rfpath >= 2) {
3251 		_rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path,
3252 							 channel,
3253 							 sizes_of_ht_retes_2t);
3254 		_rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path,
3255 							 channel,
3256 							 sizes_of_vht_retes);
3257 	}
3258 
3259 	_rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw,
3260 						channel, path);
3261 }
3262 
3263 /*just in case, write txpower in DW, to reduce time*/
3264 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
3265 {
3266 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3267 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3268 	u8 path = 0;
3269 
3270 	for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path)
3271 		rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path);
3272 }
3273 
3274 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
3275 					    enum wireless_mode wirelessmode,
3276 					    u8 txpwridx)
3277 {
3278 	long offset;
3279 	long pwrout_dbm;
3280 
3281 	switch (wirelessmode) {
3282 	case WIRELESS_MODE_B:
3283 		offset = -7;
3284 		break;
3285 	case WIRELESS_MODE_G:
3286 	case WIRELESS_MODE_N_24G:
3287 		offset = -8;
3288 		break;
3289 	default:
3290 		offset = -8;
3291 		break;
3292 	}
3293 	pwrout_dbm = txpwridx / 2 + offset;
3294 	return pwrout_dbm;
3295 }
3296 
3297 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
3298 {
3299 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3300 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3301 	enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3302 
3303 	if (!is_hal_stop(rtlhal)) {
3304 		switch (operation) {
3305 		case SCAN_OPT_BACKUP_BAND0:
3306 			iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
3307 			rtlpriv->cfg->ops->set_hw_reg(hw,
3308 						      HW_VAR_IO_CMD,
3309 						      (u8 *)&iotype);
3310 
3311 			break;
3312 		case SCAN_OPT_BACKUP_BAND1:
3313 			iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
3314 			rtlpriv->cfg->ops->set_hw_reg(hw,
3315 						      HW_VAR_IO_CMD,
3316 						      (u8 *)&iotype);
3317 
3318 			break;
3319 		case SCAN_OPT_RESTORE:
3320 			iotype = IO_CMD_RESUME_DM_BY_SCAN;
3321 			rtlpriv->cfg->ops->set_hw_reg(hw,
3322 						      HW_VAR_IO_CMD,
3323 						      (u8 *)&iotype);
3324 			break;
3325 		default:
3326 			pr_err("Unknown Scan Backup operation.\n");
3327 			break;
3328 		}
3329 	}
3330 }
3331 
3332 static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv *rtlpriv, u8 bw)
3333 {
3334 	u16 reg_rf_mode_bw, tmp = 0;
3335 
3336 	reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL);
3337 	switch (bw) {
3338 	case HT_CHANNEL_WIDTH_20:
3339 		rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F);
3340 		break;
3341 	case HT_CHANNEL_WIDTH_20_40:
3342 		tmp = reg_rf_mode_bw | BIT(7);
3343 		rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF);
3344 		break;
3345 	case HT_CHANNEL_WIDTH_80:
3346 		tmp = reg_rf_mode_bw | BIT(8);
3347 		rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F);
3348 		break;
3349 	default:
3350 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "unknown Bandwidth: 0x%x\n", bw);
3351 		break;
3352 	}
3353 }
3354 
3355 static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv *rtlpriv)
3356 {
3357 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3358 	struct rtl_mac *mac = rtl_mac(rtlpriv);
3359 	u8 sc_set_40 = 0, sc_set_20 = 0;
3360 
3361 	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3362 		if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3363 			sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
3364 		else if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3365 			sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
3366 		else
3367 			pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3368 
3369 		if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3370 			(mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3371 			sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
3372 		else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3373 			(mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
3374 			sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3375 		else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
3376 			(mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3377 			sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3378 		else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
3379 			(mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
3380 			sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
3381 		else
3382 			pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3383 	} else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
3384 		if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER)
3385 			sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3386 		else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER)
3387 			sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3388 		else
3389 			pr_err("SCMapping: Not Correct Primary40MHz Setting\n");
3390 	}
3391 	return (sc_set_40 << 4) | sc_set_20;
3392 }
3393 
3394 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
3395 {
3396 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3397 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3398 	u8 sub_chnl = 0;
3399 	u8 l1pk_val = 0;
3400 
3401 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3402 		"Switch to %s bandwidth\n",
3403 		(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
3404 		 "20MHz" :
3405 		 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ?
3406 		  "40MHz" : "80MHz")));
3407 
3408 	_rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw);
3409 	sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv);
3410 	rtl_write_byte(rtlpriv, 0x0483, sub_chnl);
3411 
3412 	switch (rtlphy->current_chan_bw) {
3413 	case HT_CHANNEL_WIDTH_20:
3414 		rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
3415 		rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3416 
3417 		if (rtlphy->rf_type == RF_2T2R)
3418 			rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
3419 		else
3420 			rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
3421 		break;
3422 	case HT_CHANNEL_WIDTH_20_40:
3423 		rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
3424 		rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
3425 		rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3426 		rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3427 
3428 		if (rtlphy->reg_837 & BIT(2))
3429 			l1pk_val = 6;
3430 		else {
3431 			if (rtlphy->rf_type == RF_2T2R)
3432 				l1pk_val = 7;
3433 			else
3434 				l1pk_val = 8;
3435 		}
3436 		/* 0x848[25:22] = 0x6 */
3437 		rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3438 
3439 		if (sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ)
3440 			rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
3441 		else
3442 			rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
3443 		break;
3444 
3445 	case HT_CHANNEL_WIDTH_80:
3446 		 /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */
3447 		rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202);
3448 		/* 0x8c4[30] = 1 */
3449 		rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
3450 		rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
3451 		rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
3452 
3453 		if (rtlphy->reg_837 & BIT(2))
3454 			l1pk_val = 5;
3455 		else {
3456 			if (rtlphy->rf_type == RF_2T2R)
3457 				l1pk_val = 6;
3458 			else
3459 				l1pk_val = 7;
3460 		}
3461 		rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
3462 
3463 		break;
3464 	default:
3465 		pr_err("unknown bandwidth: %#X\n",
3466 		       rtlphy->current_chan_bw);
3467 		break;
3468 	}
3469 
3470 	rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel);
3471 
3472 	rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
3473 	rtlphy->set_bwmode_inprogress = false;
3474 
3475 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
3476 }
3477 
3478 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
3479 			    enum nl80211_channel_type ch_type)
3480 {
3481 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3482 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3483 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3484 	u8 tmp_bw = rtlphy->current_chan_bw;
3485 
3486 	if (rtlphy->set_bwmode_inprogress)
3487 		return;
3488 	rtlphy->set_bwmode_inprogress = true;
3489 	if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
3490 		rtl8821ae_phy_set_bw_mode_callback(hw);
3491 	else {
3492 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3493 			"FALSE driver sleep or unload\n");
3494 		rtlphy->set_bwmode_inprogress = false;
3495 		rtlphy->current_chan_bw = tmp_bw;
3496 	}
3497 }
3498 
3499 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
3500 {
3501 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3502 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3503 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3504 	u8 channel = rtlphy->current_channel;
3505 	u8 path;
3506 	u32 data;
3507 
3508 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3509 		"switch to channel%d\n", rtlphy->current_channel);
3510 	if (is_hal_stop(rtlhal))
3511 		return;
3512 
3513 	if (36 <= channel && channel <= 48)
3514 		data = 0x494;
3515 	else if (50 <= channel && channel <= 64)
3516 		data = 0x453;
3517 	else if (100 <= channel && channel <= 116)
3518 		data = 0x452;
3519 	else if (118 <= channel)
3520 		data = 0x412;
3521 	else
3522 		data = 0x96a;
3523 	rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3524 
3525 	for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++) {
3526 		if (36 <= channel && channel <= 64)
3527 			data = 0x101;
3528 		else if (100 <= channel && channel <= 140)
3529 			data = 0x301;
3530 		else if (140 < channel)
3531 			data = 0x501;
3532 		else
3533 			data = 0x000;
3534 		rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3535 			BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data);
3536 
3537 		rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3538 			BMASKBYTE0, channel);
3539 
3540 		if (channel > 14) {
3541 			if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
3542 				if (36 <= channel && channel <= 64)
3543 					data = 0x114E9;
3544 				else
3545 					data = 0x110E9;
3546 				rtl8821ae_phy_set_rf_reg(hw, path, RF_APK,
3547 					BRFREGOFFSETMASK, data);
3548 			}
3549 		}
3550 	}
3551 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3552 }
3553 
3554 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw)
3555 {
3556 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3557 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3558 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3559 	u32 timeout = 1000, timecount = 0;
3560 	u8 channel = rtlphy->current_channel;
3561 
3562 	if (rtlphy->sw_chnl_inprogress)
3563 		return 0;
3564 	if (rtlphy->set_bwmode_inprogress)
3565 		return 0;
3566 
3567 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3568 		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
3569 			"sw_chnl_inprogress false driver sleep or unload\n");
3570 		return 0;
3571 	}
3572 	while (rtlphy->lck_inprogress && timecount < timeout) {
3573 		mdelay(50);
3574 		timecount += 50;
3575 	}
3576 
3577 	if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G)
3578 		rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G);
3579 	else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G)
3580 		rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3581 
3582 	rtlphy->sw_chnl_inprogress = true;
3583 	if (channel == 0)
3584 		channel = 1;
3585 
3586 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
3587 		"switch to channel%d, band type is %d\n",
3588 		rtlphy->current_channel, rtlhal->current_bandtype);
3589 
3590 	rtl8821ae_phy_sw_chnl_callback(hw);
3591 
3592 	rtl8821ae_dm_clear_txpower_tracking_state(hw);
3593 	rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel);
3594 
3595 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
3596 	rtlphy->sw_chnl_inprogress = false;
3597 	return 1;
3598 }
3599 
3600 u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)
3601 {
3602 	static const u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] = {
3603 		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
3604 		14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
3605 		56, 58, 60, 62, 64, 100, 102, 104, 106, 108,
3606 		110, 112, 114, 116, 118, 120, 122, 124, 126,
3607 		128, 130, 132, 134, 136, 138, 140, 149, 151,
3608 		153, 155, 157, 159, 161, 163, 165};
3609 	u8 place;
3610 
3611 	if (chnl > 14) {
3612 		for (place = 14; place < sizeof(channel_all); place++)
3613 			if (channel_all[place] == chnl)
3614 				return place-13;
3615 	}
3616 
3617 	return 0;
3618 }
3619 
3620 #define MACBB_REG_NUM 10
3621 #define AFE_REG_NUM 14
3622 #define RF_REG_NUM 3
3623 
3624 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw,
3625 					u32 *macbb_backup,
3626 					u32 *backup_macbb_reg, u32 mac_bb_num)
3627 {
3628 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3629 	u32 i;
3630 
3631 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3632 	/*save MACBB default value*/
3633 	for (i = 0; i < mac_bb_num; i++)
3634 		macbb_backup[i] = rtl_read_dword(rtlpriv, backup_macbb_reg[i]);
3635 
3636 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupMacBB Success!!!!\n");
3637 }
3638 
3639 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup,
3640 				      u32 *backup_afe_REG, u32 afe_num)
3641 {
3642 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3643 	u32 i;
3644 
3645 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3646 	/*Save AFE Parameters */
3647 	for (i = 0; i < afe_num; i++)
3648 		afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
3649 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupAFE Success!!!!\n");
3650 }
3651 
3652 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup,
3653 				     u32 *rfb_backup, u32 *backup_rf_reg,
3654 				     u32 rf_num)
3655 {
3656 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3657 	u32 i;
3658 
3659 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3660 	/*Save RF Parameters*/
3661 	for (i = 0; i < rf_num; i++) {
3662 		rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i],
3663 					      BMASKDWORD);
3664 		rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i],
3665 					      BMASKDWORD);
3666 	}
3667 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupRF Success!!!!\n");
3668 }
3669 
3670 static void _rtl8821ae_iqk_configure_mac(
3671 		struct ieee80211_hw *hw
3672 		)
3673 {
3674 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3675 	/* ========MAC register setting========*/
3676 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3677 	rtl_write_byte(rtlpriv, 0x522, 0x3f);
3678 	rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3679 	rtl_write_byte(rtlpriv, 0x808, 0x00);		/*RX ante off*/
3680 	rtl_set_bbreg(hw, 0x838, 0xf, 0xc);		/*CCA off*/
3681 }
3682 
3683 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw,
3684 				       enum radio_path path, u32 tx_x, u32 tx_y)
3685 {
3686 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3687 	switch (path) {
3688 	case RF90_PATH_A:
3689 		/* [31] = 1 --> Page C1 */
3690 		rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1);
3691 		rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3692 		rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
3693 		rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
3694 		rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3695 		rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3696 		rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3697 			"TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3698 			tx_x, tx_y);
3699 		rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3700 			"0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3701 			rtl_get_bbreg(hw, 0xcd4, 0x000007ff),
3702 			rtl_get_bbreg(hw, 0xccc, 0x000007ff));
3703 		break;
3704 	default:
3705 		break;
3706 	}
3707 }
3708 
3709 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw,
3710 				       enum radio_path path, u32 rx_x, u32 rx_y)
3711 {
3712 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3713 	switch (path) {
3714 	case RF90_PATH_A:
3715 		rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3716 		rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
3717 		rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
3718 		rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3719 			"rx_x = %x;;rx_y = %x ====>fill to IQC\n",
3720 			rx_x >> 1, rx_y >> 1);
3721 		rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3722 			"0xc10 = %x ====>fill to IQC\n",
3723 			rtl_read_dword(rtlpriv, 0xc10));
3724 		break;
3725 	default:
3726 		break;
3727 	}
3728 }
3729 
3730 #define cal_num 10
3731 
3732 static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path)
3733 {
3734 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3735 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3736 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3737 
3738 	u32	tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65;
3739 	int	tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0;
3740 	int	tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num],
3741 		tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num],
3742 		tx_dt[cal_num], rx_dt[cal_num];
3743 	bool	tx0iqkok = false, rx0iqkok = false;
3744 	bool	vdf_enable = false;
3745 	int	i, k, vdf_y[3], vdf_x[3],
3746 		ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0;
3747 
3748 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3749 		"BandWidth = %d.\n",
3750 		rtlphy->current_chan_bw);
3751 	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3752 		vdf_enable = true;
3753 
3754 	while (cal < cal_num) {
3755 		switch (path) {
3756 		case RF90_PATH_A:
3757 			temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff);
3758 			/* Path-A LOK */
3759 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3760 			/*========Path-A AFE all on========*/
3761 			/*Port 0 DAC/ADC on*/
3762 			rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
3763 			rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
3764 			rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
3765 			rtl_write_dword(rtlpriv, 0xc6c, 0x19791979);
3766 			rtl_write_dword(rtlpriv, 0xc70, 0x19791979);
3767 			rtl_write_dword(rtlpriv, 0xc74, 0x19791979);
3768 			rtl_write_dword(rtlpriv, 0xc78, 0x19791979);
3769 			rtl_write_dword(rtlpriv, 0xc7c, 0x19791979);
3770 			rtl_write_dword(rtlpriv, 0xc80, 0x19791979);
3771 			rtl_write_dword(rtlpriv, 0xc84, 0x19791979);
3772 
3773 			rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
3774 
3775 			/* LOK Setting */
3776 			/* ====== LOK ====== */
3777 			/*DAC/ADC sampling rate (160 MHz)*/
3778 			rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3779 
3780 			/* 2. LoK RF Setting (at BW = 20M) */
3781 			rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002);
3782 			rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3);     /* BW 20M */
3783 			rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3784 			rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3785 			rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3786 			rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3787 			rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3788 			rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
3789 			rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3790 			rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3791 			rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3792 			rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3793 			rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3794 			rtl_write_dword(rtlpriv, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
3795 
3796 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3797 			rtl_write_dword(rtlpriv, 0xc88, 0x821403f4);
3798 
3799 			if (rtlhal->current_bandtype)
3800 				rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
3801 			else
3802 				rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
3803 
3804 			rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3805 			rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3806 			rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3807 			rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3808 			rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3809 
3810 			mdelay(10); /* Delay 10ms */
3811 			rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3812 
3813 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3814 			rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */
3815 
3816 			switch (rtlphy->current_chan_bw) {
3817 			case 1:
3818 				rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1);
3819 				break;
3820 			case 2:
3821 				rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0);
3822 				break;
3823 			default:
3824 				break;
3825 			}
3826 
3827 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3828 
3829 			/* 3. TX RF Setting */
3830 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3831 			rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
3832 			rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
3833 			rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
3834 			rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
3835 			rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
3836 			rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
3837 			rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
3838 			/* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */
3839 			rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3840 			rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3841 			rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3842 			rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
3843 			rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
3844 			rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
3845 
3846 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
3847 			rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
3848 			if (rtlhal->current_bandtype)
3849 				rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96);
3850 			else
3851 				rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96);
3852 
3853 			if (vdf_enable == 1) {
3854 				rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "VDF_enable\n");
3855 				for (k = 0; k <= 2; k++) {
3856 					switch (k) {
3857 					case 0:
3858 						rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3859 						rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3860 						rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3861 						break;
3862 					case 1:
3863 						rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
3864 						rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
3865 						rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
3866 						break;
3867 					case 2:
3868 						rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3869 							"vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff);
3870 						rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
3871 							"vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff);
3872 						tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
3873 						tx_dt[cal] = ((16*tx_dt[cal])*10000/15708);
3874 						tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0));
3875 						rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3876 						rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3877 						rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
3878 						rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
3879 						break;
3880 					default:
3881 						break;
3882 					}
3883 					rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3884 					cal_retry = 0;
3885 					while (1) {
3886 						/* one shot */
3887 						rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3888 						rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3889 
3890 						mdelay(10); /* Delay 10ms */
3891 						rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3892 						delay_count = 0;
3893 						while (1) {
3894 							iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3895 							if ((~iqk_ready) || (delay_count > 20))
3896 								break;
3897 							else{
3898 								mdelay(1);
3899 								delay_count++;
3900 							}
3901 						}
3902 
3903 						if (delay_count < 20) {							/* If 20ms No Result, then cal_retry++ */
3904 							/* ============TXIQK Check============== */
3905 							tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3906 
3907 							if (~tx_fail) {
3908 								rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3909 								vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3910 								rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3911 								vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3912 								tx0iqkok = true;
3913 								break;
3914 							} else {
3915 								rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3916 								rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3917 								tx0iqkok = false;
3918 								cal_retry++;
3919 								if (cal_retry == 10)
3920 									break;
3921 							}
3922 						} else {
3923 							tx0iqkok = false;
3924 							cal_retry++;
3925 							if (cal_retry == 10)
3926 								break;
3927 						}
3928 					}
3929 				}
3930 				if (k == 3) {
3931 					tx_x0[cal] = vdf_x[k-1];
3932 					tx_y0[cal] = vdf_y[k-1];
3933 				}
3934 			} else {
3935 				rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
3936 				rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
3937 				rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
3938 				cal_retry = 0;
3939 				while (1) {
3940 					/* one shot */
3941 					rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3942 					rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3943 
3944 					mdelay(10); /* Delay 10ms */
3945 					rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3946 					delay_count = 0;
3947 					while (1) {
3948 						iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
3949 						if ((~iqk_ready) || (delay_count > 20))
3950 							break;
3951 						else{
3952 							mdelay(1);
3953 							delay_count++;
3954 						}
3955 					}
3956 
3957 					if (delay_count < 20) {							/* If 20ms No Result, then cal_retry++ */
3958 						/* ============TXIQK Check============== */
3959 						tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
3960 
3961 						if (~tx_fail) {
3962 							rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3963 							tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3964 							rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3965 							tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
3966 							tx0iqkok = true;
3967 							break;
3968 						} else {
3969 							rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
3970 							rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
3971 							tx0iqkok = false;
3972 							cal_retry++;
3973 							if (cal_retry == 10)
3974 								break;
3975 						}
3976 					} else {
3977 						tx0iqkok = false;
3978 						cal_retry++;
3979 						if (cal_retry == 10)
3980 							break;
3981 					}
3982 				}
3983 			}
3984 
3985 			if (tx0iqkok == false)
3986 				break;				/* TXK fail, Don't do RXK */
3987 
3988 			if (vdf_enable == 1) {
3989 				rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);    /* TX VDF Disable */
3990 				rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RXVDF Start\n");
3991 				for (k = 0; k <= 2; k++) {
3992 					/* ====== RX mode TXK (RXK Step 1) ====== */
3993 					rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
3994 					/* 1. TX RF Setting */
3995 					rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
3996 					rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
3997 					rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
3998 					rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
3999 					rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4000 					rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4001 					rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4002 
4003 					rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4004 					rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */
4005 					rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */
4006 					rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4007 					rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4008 					rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4009 					rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4010 					switch (k) {
4011 					case 0:
4012 						{
4013 							rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4014 							rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4015 							rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4016 						}
4017 						break;
4018 					case 1:
4019 						{
4020 							rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4021 							rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4022 							rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4023 						}
4024 						break;
4025 					case 2:
4026 						{
4027 							rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4028 								"VDF_Y[1] = %x;;;VDF_Y[0] = %x\n",
4029 								vdf_y[1] >> 21 & 0x00007ff,
4030 								vdf_y[0] >> 21 & 0x00007ff);
4031 							rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4032 								"VDF_X[1] = %x;;;VDF_X[0] = %x\n",
4033 								vdf_x[1] >> 21 & 0x00007ff,
4034 								vdf_x[0] >> 21 & 0x00007ff);
4035 							rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4036 							rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "Rx_dt = %d\n",
4037 								rx_dt[cal]);
4038 							rx_dt[cal] = ((16*rx_dt[cal])*10000/13823);
4039 							rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0));
4040 							rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4041 							rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4042 							rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4043 						}
4044 						break;
4045 					default:
4046 						break;
4047 					}
4048 					rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4049 					rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4050 					rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4051 					cal_retry = 0;
4052 					while (1) {
4053 						/* one shot */
4054 						rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4055 						rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4056 
4057 						mdelay(10); /* Delay 10ms */
4058 						rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4059 						delay_count = 0;
4060 						while (1) {
4061 							iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4062 							if ((~iqk_ready) || (delay_count > 20))
4063 								break;
4064 							else{
4065 								mdelay(1);
4066 								delay_count++;
4067 							}
4068 						}
4069 
4070 						if (delay_count < 20) {							/* If 20ms No Result, then cal_retry++ */
4071 							/* ============TXIQK Check============== */
4072 							tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4073 
4074 							if (~tx_fail) {
4075 								rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4076 								tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4077 								rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4078 								tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4079 								tx0iqkok = true;
4080 								break;
4081 							} else{
4082 								tx0iqkok = false;
4083 								cal_retry++;
4084 								if (cal_retry == 10)
4085 									break;
4086 							}
4087 						} else {
4088 							tx0iqkok = false;
4089 							cal_retry++;
4090 							if (cal_retry == 10)
4091 								break;
4092 						}
4093 					}
4094 
4095 					if (tx0iqkok == false) {   /* If RX mode TXK fail, then take TXK Result */
4096 						tx_x0_rxk[cal] = tx_x0[cal];
4097 						tx_y0_rxk[cal] = tx_y0[cal];
4098 						tx0iqkok = true;
4099 						rtl_dbg(rtlpriv,
4100 							COMP_IQK,
4101 							DBG_LOUD,
4102 							"RXK Step 1 fail\n");
4103 					}
4104 
4105 					/* ====== RX IQK ====== */
4106 					rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4107 					/* 1. RX RF Setting */
4108 					rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4109 					rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4110 					rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4111 					rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4112 					rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4113 					rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4114 					rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4115 
4116 					rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4117 					rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4118 					rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4119 					rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4120 					rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4121 					rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4122 					rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4123 
4124 					rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4125 					rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4126 					rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4127 					rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4128 
4129 					rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4130 
4131 					if (k == 2)
4132 						rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1);  /* RX VDF Enable */
4133 					rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4134 
4135 					cal_retry = 0;
4136 					while (1) {
4137 						/* one shot */
4138 						rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4139 						rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4140 
4141 						mdelay(10); /* Delay 10ms */
4142 						rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4143 						delay_count = 0;
4144 						while (1) {
4145 							iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4146 							if ((~iqk_ready) || (delay_count > 20))
4147 								break;
4148 							else{
4149 								mdelay(1);
4150 								delay_count++;
4151 							}
4152 						}
4153 
4154 						if (delay_count < 20) {	/* If 20ms No Result, then cal_retry++ */
4155 							/* ============RXIQK Check============== */
4156 							rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4157 							if (rx_fail == 0) {
4158 								rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4159 								vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4160 								rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4161 								vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4162 								rx0iqkok = true;
4163 								break;
4164 							} else {
4165 								rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4166 								rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4167 								rx0iqkok = false;
4168 								cal_retry++;
4169 								if (cal_retry == 10)
4170 									break;
4171 
4172 							}
4173 						} else{
4174 							rx0iqkok = false;
4175 							cal_retry++;
4176 							if (cal_retry == 10)
4177 								break;
4178 						}
4179 					}
4180 
4181 				}
4182 				if (k == 3) {
4183 					rx_x0[cal] = vdf_x[k-1];
4184 					rx_y0[cal] = vdf_y[k-1];
4185 				}
4186 				rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);    /* TX VDF Enable */
4187 			}
4188 
4189 			else{
4190 				/* ====== RX mode TXK (RXK Step 1) ====== */
4191 				rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4192 				/* 1. TX RF Setting */
4193 				rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4194 				rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4195 				rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4196 				rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4197 				rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4198 				rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4199 				rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4200 				rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4201 				rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4202 				rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
4203 
4204 				rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4205 				rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4206 				rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4207 				rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4208 				/* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */
4209 				rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4210 				cal_retry = 0;
4211 				while (1) {
4212 					/* one shot */
4213 					rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4214 					rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4215 
4216 					mdelay(10); /* Delay 10ms */
4217 					rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4218 					delay_count = 0;
4219 					while (1) {
4220 						iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4221 						if ((~iqk_ready) || (delay_count > 20))
4222 							break;
4223 						else{
4224 							mdelay(1);
4225 							delay_count++;
4226 						}
4227 					}
4228 
4229 					if (delay_count < 20) {							/* If 20ms No Result, then cal_retry++ */
4230 						/* ============TXIQK Check============== */
4231 						tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4232 
4233 						if (~tx_fail) {
4234 							rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4235 							tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4236 							rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4237 							tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4238 							tx0iqkok = true;
4239 							break;
4240 						} else {
4241 							tx0iqkok = false;
4242 							cal_retry++;
4243 							if (cal_retry == 10)
4244 								break;
4245 						}
4246 					} else{
4247 						tx0iqkok = false;
4248 						cal_retry++;
4249 						if (cal_retry == 10)
4250 							break;
4251 					}
4252 				}
4253 
4254 				if (tx0iqkok == false) {   /* If RX mode TXK fail, then take TXK Result */
4255 					tx_x0_rxk[cal] = tx_x0[cal];
4256 					tx_y0_rxk[cal] = tx_y0[cal];
4257 					tx0iqkok = true;
4258 					rtl_dbg(rtlpriv, COMP_IQK,
4259 						DBG_LOUD, "1");
4260 				}
4261 
4262 				/* ====== RX IQK ====== */
4263 				rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4264 				/* 1. RX RF Setting */
4265 				rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4266 				rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4267 				rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4268 				rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4269 				rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4270 				rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4271 				rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4272 
4273 				rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4274 				rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4275 				rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4276 				rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4277 				/* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */
4278 				rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4279 				rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4280 
4281 				rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4282 				rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
4283 				rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */
4284 				rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4285 
4286 				rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4287 
4288 				rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */
4289 
4290 				cal_retry = 0;
4291 				while (1) {
4292 					/* one shot */
4293 					rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4294 					rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4295 
4296 					mdelay(10); /* Delay 10ms */
4297 					rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4298 					delay_count = 0;
4299 					while (1) {
4300 						iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4301 						if ((~iqk_ready) || (delay_count > 20))
4302 							break;
4303 						else{
4304 							mdelay(1);
4305 							delay_count++;
4306 						}
4307 					}
4308 
4309 					if (delay_count < 20) {	/* If 20ms No Result, then cal_retry++ */
4310 						/* ============RXIQK Check============== */
4311 						rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4312 						if (rx_fail == 0) {
4313 							rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4314 							rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4315 							rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4316 							rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4317 							rx0iqkok = true;
4318 							break;
4319 						} else{
4320 							rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4321 							rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4322 							rx0iqkok = false;
4323 							cal_retry++;
4324 							if (cal_retry == 10)
4325 								break;
4326 
4327 						}
4328 					} else{
4329 						rx0iqkok = false;
4330 						cal_retry++;
4331 						if (cal_retry == 10)
4332 							break;
4333 					}
4334 				}
4335 			}
4336 
4337 			if (tx0iqkok)
4338 				tx_average++;
4339 			if (rx0iqkok)
4340 				rx_average++;
4341 			rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4342 			rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4343 			break;
4344 		default:
4345 			break;
4346 		}
4347 		cal++;
4348 	}
4349 
4350 	/* FillIQK Result */
4351 	switch (path) {
4352 	case RF90_PATH_A:
4353 		rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4354 			"========Path_A =======\n");
4355 		if (tx_average == 0)
4356 			break;
4357 
4358 		for (i = 0; i < tx_average; i++) {
4359 			rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4360 				"TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i,
4361 				(tx_x0_rxk[i]) >> 21 & 0x000007ff, i,
4362 				(tx_y0_rxk[i]) >> 21 & 0x000007ff);
4363 			rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4364 				"TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i,
4365 				(tx_x0[i]) >> 21 & 0x000007ff, i,
4366 				(tx_y0[i]) >> 21 & 0x000007ff);
4367 		}
4368 		for (i = 0; i < tx_average; i++) {
4369 			for (ii = i+1; ii < tx_average; ii++) {
4370 				dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21);
4371 				if (dx < 3 && dx > -3) {
4372 					dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
4373 					if (dy < 3 && dy > -3) {
4374 						tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2;
4375 						tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2;
4376 						tx_finish = 1;
4377 						break;
4378 					}
4379 				}
4380 			}
4381 			if (tx_finish == 1)
4382 				break;
4383 		}
4384 
4385 		if (tx_finish == 1)
4386 			_rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */
4387 		else
4388 			_rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0);
4389 
4390 		if (rx_average == 0)
4391 			break;
4392 
4393 		for (i = 0; i < rx_average; i++)
4394 			rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4395 				"RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i,
4396 				(rx_x0[i])>>21&0x000007ff, i,
4397 				(rx_y0[i])>>21&0x000007ff);
4398 		for (i = 0; i < rx_average; i++) {
4399 			for (ii = i+1; ii < rx_average; ii++) {
4400 				dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21);
4401 				if (dx < 4 && dx > -4) {
4402 					dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21);
4403 					if (dy < 4 && dy > -4) {
4404 						rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2;
4405 						rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2;
4406 						rx_finish = 1;
4407 						break;
4408 					}
4409 				}
4410 			}
4411 			if (rx_finish == 1)
4412 				break;
4413 		}
4414 
4415 		if (rx_finish == 1)
4416 			_rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y);
4417 		else
4418 			_rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0);
4419 		break;
4420 	default:
4421 		break;
4422 	}
4423 }
4424 
4425 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw,
4426 				      enum radio_path path,
4427 				      u32 *backup_rf_reg,
4428 				      u32 *rf_backup, u32 rf_reg_num)
4429 {
4430 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4431 	u32 i;
4432 
4433 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4434 	for (i = 0; i < RF_REG_NUM; i++)
4435 		rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK,
4436 			      rf_backup[i]);
4437 
4438 	switch (path) {
4439 	case RF90_PATH_A:
4440 		rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4441 			"RestoreRF Path A Success!!!!\n");
4442 		break;
4443 	default:
4444 			break;
4445 	}
4446 }
4447 
4448 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw,
4449 				       u32 *afe_backup, u32 *backup_afe_reg,
4450 				       u32 afe_num)
4451 {
4452 	u32 i;
4453 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4454 
4455 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4456 	/* Reload AFE Parameters */
4457 	for (i = 0; i < afe_num; i++)
4458 		rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
4459 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
4460 	rtl_write_dword(rtlpriv, 0xc80, 0x0);
4461 	rtl_write_dword(rtlpriv, 0xc84, 0x0);
4462 	rtl_write_dword(rtlpriv, 0xc88, 0x0);
4463 	rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
4464 	rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4465 	rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4466 	rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4467 	rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4468 	rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4469 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreAFE Success!!!!\n");
4470 }
4471 
4472 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw,
4473 					 u32 *macbb_backup,
4474 					 u32 *backup_macbb_reg,
4475 					 u32 macbb_num)
4476 {
4477 	u32 i;
4478 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4479 
4480 	rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
4481 	/* Reload MacBB Parameters */
4482 	for (i = 0; i < macbb_num; i++)
4483 		rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
4484 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreMacBB Success!!!!\n");
4485 }
4486 
4487 #undef MACBB_REG_NUM
4488 #undef AFE_REG_NUM
4489 #undef RF_REG_NUM
4490 
4491 #define MACBB_REG_NUM 11
4492 #define AFE_REG_NUM 12
4493 #define RF_REG_NUM 3
4494 
4495 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw)
4496 {
4497 	u32	macbb_backup[MACBB_REG_NUM];
4498 	u32 afe_backup[AFE_REG_NUM];
4499 	u32 rfa_backup[RF_REG_NUM];
4500 	u32 rfb_backup[RF_REG_NUM];
4501 	u32 backup_macbb_reg[MACBB_REG_NUM] = {
4502 		0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
4503 		0xe00, 0xe50, 0x838, 0x82c
4504 	};
4505 	u32 backup_afe_reg[AFE_REG_NUM] = {
4506 		0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
4507 		0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8
4508 	};
4509 	u32	backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
4510 
4511 	_rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg,
4512 				    MACBB_REG_NUM);
4513 	_rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4514 	_rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg,
4515 				 RF_REG_NUM);
4516 
4517 	_rtl8821ae_iqk_configure_mac(hw);
4518 	_rtl8821ae_iqk_tx(hw, RF90_PATH_A);
4519 	_rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup,
4520 				  RF_REG_NUM);
4521 
4522 	_rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4523 	_rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg,
4524 				     MACBB_REG_NUM);
4525 }
4526 
4527 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main)
4528 {
4529 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4530 	/* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */
4531 	/* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */
4532 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
4533 
4534 	if (main)
4535 		rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
4536 	else
4537 		rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);
4538 }
4539 
4540 #undef IQK_ADDA_REG_NUM
4541 #undef IQK_DELAY_TIME
4542 
4543 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4544 {
4545 }
4546 
4547 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4548 		      u8 thermal_value, u8 threshold)
4549 {
4550 	struct rtl_dm	*rtldm = rtl_dm(rtl_priv(hw));
4551 
4552 	rtldm->thermalvalue_iqk = thermal_value;
4553 	rtl8812ae_phy_iq_calibrate(hw, false);
4554 }
4555 
4556 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
4557 {
4558 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4559 	struct rtl_phy *rtlphy = &rtlpriv->phy;
4560 
4561 	if (!rtlphy->lck_inprogress) {
4562 		spin_lock(&rtlpriv->locks.iqk_lock);
4563 		rtlphy->lck_inprogress = true;
4564 		spin_unlock(&rtlpriv->locks.iqk_lock);
4565 
4566 		_rtl8821ae_phy_iq_calibrate(hw);
4567 
4568 		spin_lock(&rtlpriv->locks.iqk_lock);
4569 		rtlphy->lck_inprogress = false;
4570 		spin_unlock(&rtlpriv->locks.iqk_lock);
4571 	}
4572 }
4573 
4574 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw)
4575 {
4576 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4577 	struct rtl_phy *rtlphy = &rtlpriv->phy;
4578 	u8 i;
4579 
4580 	rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD,
4581 		"rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
4582 		(int)(sizeof(rtlphy->iqk_matrix) /
4583 		sizeof(struct iqk_matrix_regs)),
4584 		IQK_MATRIX_SETTINGS_NUM);
4585 
4586 	for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
4587 		rtlphy->iqk_matrix[i].value[0][0] = 0x100;
4588 		rtlphy->iqk_matrix[i].value[0][2] = 0x100;
4589 		rtlphy->iqk_matrix[i].value[0][4] = 0x100;
4590 		rtlphy->iqk_matrix[i].value[0][6] = 0x100;
4591 
4592 		rtlphy->iqk_matrix[i].value[0][1] = 0x0;
4593 		rtlphy->iqk_matrix[i].value[0][3] = 0x0;
4594 		rtlphy->iqk_matrix[i].value[0][5] = 0x0;
4595 		rtlphy->iqk_matrix[i].value[0][7] = 0x0;
4596 
4597 		rtlphy->iqk_matrix[i].iqk_done = false;
4598 	}
4599 }
4600 
4601 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index,
4602 		      u8 thermal_value, u8 threshold)
4603 {
4604 	struct rtl_dm	*rtldm = rtl_dm(rtl_priv(hw));
4605 
4606 	rtl8821ae_reset_iqk_result(hw);
4607 
4608 	rtldm->thermalvalue_iqk = thermal_value;
4609 	rtl8821ae_phy_iq_calibrate(hw, false);
4610 }
4611 
4612 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw)
4613 {
4614 }
4615 
4616 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
4617 {
4618 }
4619 
4620 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
4621 {
4622 	_rtl8821ae_phy_set_rfpath_switch(hw, bmain);
4623 }
4624 
4625 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
4626 {
4627 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4628 	struct rtl_phy *rtlphy = &rtlpriv->phy;
4629 	bool postprocessing = false;
4630 
4631 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4632 		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
4633 		iotype, rtlphy->set_io_inprogress);
4634 	do {
4635 		switch (iotype) {
4636 		case IO_CMD_RESUME_DM_BY_SCAN:
4637 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4638 				"[IO CMD] Resume DM after scan.\n");
4639 			postprocessing = true;
4640 			break;
4641 		case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4642 		case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4643 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4644 				"[IO CMD] Pause DM before scan.\n");
4645 			postprocessing = true;
4646 			break;
4647 		default:
4648 			pr_err("switch case %#x not processed\n",
4649 			       iotype);
4650 			break;
4651 		}
4652 	} while (false);
4653 	if (postprocessing && !rtlphy->set_io_inprogress) {
4654 		rtlphy->set_io_inprogress = true;
4655 		rtlphy->current_io_type = iotype;
4656 	} else {
4657 		return false;
4658 	}
4659 	rtl8821ae_phy_set_io(hw);
4660 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
4661 	return true;
4662 }
4663 
4664 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw)
4665 {
4666 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4667 	struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
4668 	struct rtl_phy *rtlphy = &rtlpriv->phy;
4669 
4670 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4671 		"--->Cmd(%#x), set_io_inprogress(%d)\n",
4672 		rtlphy->current_io_type, rtlphy->set_io_inprogress);
4673 	switch (rtlphy->current_io_type) {
4674 	case IO_CMD_RESUME_DM_BY_SCAN:
4675 		if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4676 			_rtl8821ae_resume_tx_beacon(hw);
4677 		rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
4678 		rtl8821ae_dm_write_cck_cca_thres(hw,
4679 						 rtlphy->initgain_backup.cca);
4680 		break;
4681 	case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
4682 		if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
4683 			_rtl8821ae_stop_tx_beacon(hw);
4684 		rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
4685 		rtl8821ae_dm_write_dig(hw, 0x17);
4686 		rtlphy->initgain_backup.cca = dm_digtable->cur_cck_cca_thres;
4687 		rtl8821ae_dm_write_cck_cca_thres(hw, 0x40);
4688 		break;
4689 	case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
4690 		break;
4691 	default:
4692 		pr_err("switch case %#x not processed\n",
4693 		       rtlphy->current_io_type);
4694 		break;
4695 	}
4696 	rtlphy->set_io_inprogress = false;
4697 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
4698 		"(%#x)\n", rtlphy->current_io_type);
4699 }
4700 
4701 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw)
4702 {
4703 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4704 
4705 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
4706 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4707 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
4708 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
4709 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
4710 }
4711 
4712 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4713 					      enum rf_pwrstate rfpwr_state)
4714 {
4715 	struct rtl_priv *rtlpriv = rtl_priv(hw);
4716 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
4717 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
4718 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4719 	bool bresult = true;
4720 	u8 i, queue_id;
4721 	struct rtl8192_tx_ring *ring = NULL;
4722 
4723 	switch (rfpwr_state) {
4724 	case ERFON:
4725 		if ((ppsc->rfpwr_state == ERFOFF) &&
4726 		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
4727 			bool rtstatus = false;
4728 			u32 initializecount = 0;
4729 
4730 			do {
4731 				initializecount++;
4732 				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4733 					"IPS Set eRf nic enable\n");
4734 				rtstatus = rtl_ps_enable_nic(hw);
4735 			} while (!rtstatus && (initializecount < 10));
4736 			RT_CLEAR_PS_LEVEL(ppsc,
4737 					  RT_RF_OFF_LEVL_HALT_NIC);
4738 		} else {
4739 			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4740 				"Set ERFON slept:%d ms\n",
4741 				jiffies_to_msecs(jiffies -
4742 						 ppsc->last_sleep_jiffies));
4743 			ppsc->last_awake_jiffies = jiffies;
4744 			rtl8821ae_phy_set_rf_on(hw);
4745 		}
4746 		if (mac->link_state == MAC80211_LINKED) {
4747 			rtlpriv->cfg->ops->led_control(hw,
4748 						       LED_CTL_LINK);
4749 		} else {
4750 			rtlpriv->cfg->ops->led_control(hw,
4751 						       LED_CTL_NO_LINK);
4752 		}
4753 		break;
4754 	case ERFOFF:
4755 		for (queue_id = 0, i = 0;
4756 		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
4757 			ring = &pcipriv->dev.tx_ring[queue_id];
4758 			if (queue_id == BEACON_QUEUE ||
4759 			    skb_queue_len(&ring->queue) == 0) {
4760 				queue_id++;
4761 				continue;
4762 			} else {
4763 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
4764 					"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
4765 					(i + 1), queue_id,
4766 					skb_queue_len(&ring->queue));
4767 
4768 				udelay(10);
4769 				i++;
4770 			}
4771 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
4772 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
4773 					"\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
4774 					MAX_DOZE_WAITING_TIMES_9x,
4775 					queue_id,
4776 					skb_queue_len(&ring->queue));
4777 				break;
4778 			}
4779 		}
4780 
4781 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
4782 			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
4783 				"IPS Set eRf nic disable\n");
4784 			rtl_ps_disable_nic(hw);
4785 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
4786 		} else {
4787 			if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
4788 				rtlpriv->cfg->ops->led_control(hw,
4789 							       LED_CTL_NO_LINK);
4790 			} else {
4791 				rtlpriv->cfg->ops->led_control(hw,
4792 							       LED_CTL_POWER_OFF);
4793 			}
4794 		}
4795 		break;
4796 	default:
4797 		pr_err("switch case %#x not processed\n",
4798 		       rfpwr_state);
4799 		bresult = false;
4800 		break;
4801 	}
4802 	if (bresult)
4803 		ppsc->rfpwr_state = rfpwr_state;
4804 	return bresult;
4805 }
4806 
4807 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
4808 				      enum rf_pwrstate rfpwr_state)
4809 {
4810 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
4811 
4812 	bool bresult = false;
4813 
4814 	if (rfpwr_state == ppsc->rfpwr_state)
4815 		return bresult;
4816 	bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state);
4817 	return bresult;
4818 }
4819