1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2010 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../pci.h" 6 #include "../ps.h" 7 #include "reg.h" 8 #include "def.h" 9 #include "phy.h" 10 #include "rf.h" 11 #include "dm.h" 12 #include "table.h" 13 #include "trx.h" 14 #include "../btcoexist/halbt_precomp.h" 15 #include "hw.h" 16 #include "../efuse.h" 17 18 #define READ_NEXT_PAIR(array_table, v1, v2, i) \ 19 do { \ 20 i += 2; \ 21 v1 = array_table[i]; \ 22 v2 = array_table[i+1]; \ 23 } while (0) 24 25 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw, 26 enum radio_path rfpath, u32 offset); 27 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw, 28 enum radio_path rfpath, u32 offset, 29 u32 data); 30 static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask) 31 { 32 u32 i = ffs(bitmask); 33 34 return i ? i - 1 : 32; 35 } 36 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw); 37 /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/ 38 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 39 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 40 u8 configtype); 41 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 42 u8 configtype); 43 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 44 45 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 46 enum wireless_mode wirelessmode, 47 u8 txpwridx); 48 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw); 49 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw); 50 51 static void rtl8812ae_fixspur(struct ieee80211_hw *hw, 52 enum ht_channel_width band_width, u8 channel) 53 { 54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 55 56 /*C cut Item12 ADC FIFO CLOCK*/ 57 if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) { 58 if (band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11) 59 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3); 60 /* 0x8AC[11:10] = 2'b11*/ 61 else 62 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2); 63 /* 0x8AC[11:10] = 2'b10*/ 64 65 /* <20120914, Kordan> A workarould to resolve 66 * 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson) 67 */ 68 if (band_width == HT_CHANNEL_WIDTH_20 && 69 (channel == 13 || channel == 14)) { 70 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); 71 /*0x8AC[9:8] = 2'b11*/ 72 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); 73 /* 0x8C4[30] = 1*/ 74 } else if (band_width == HT_CHANNEL_WIDTH_20_40 && 75 channel == 11) { 76 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); 77 /*0x8C4[30] = 1*/ 78 } else if (band_width != HT_CHANNEL_WIDTH_80) { 79 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2); 80 /*0x8AC[9:8] = 2'b10*/ 81 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); 82 /*0x8C4[30] = 0*/ 83 } 84 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 85 /* <20120914, Kordan> A workarould to resolve 86 * 2480Mhz spur by setting ADC clock as 160M. 87 */ 88 if (band_width == HT_CHANNEL_WIDTH_20 && 89 (channel == 13 || channel == 14)) 90 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3); 91 /*0x8AC[9:8] = 11*/ 92 else if (channel <= 14) /*2.4G only*/ 93 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2); 94 /*0x8AC[9:8] = 10*/ 95 } 96 } 97 98 u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, 99 u32 bitmask) 100 { 101 struct rtl_priv *rtlpriv = rtl_priv(hw); 102 u32 returnvalue, originalvalue, bitshift; 103 104 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 105 "regaddr(%#x), bitmask(%#x)\n", 106 regaddr, bitmask); 107 originalvalue = rtl_read_dword(rtlpriv, regaddr); 108 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 109 returnvalue = (originalvalue & bitmask) >> bitshift; 110 111 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 112 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 113 bitmask, regaddr, originalvalue); 114 return returnvalue; 115 } 116 117 void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw, 118 u32 regaddr, u32 bitmask, u32 data) 119 { 120 struct rtl_priv *rtlpriv = rtl_priv(hw); 121 u32 originalvalue, bitshift; 122 123 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 124 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 125 regaddr, bitmask, data); 126 127 if (bitmask != MASKDWORD) { 128 originalvalue = rtl_read_dword(rtlpriv, regaddr); 129 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 130 data = ((originalvalue & (~bitmask)) | 131 ((data << bitshift) & bitmask)); 132 } 133 134 rtl_write_dword(rtlpriv, regaddr, data); 135 136 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 137 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 138 regaddr, bitmask, data); 139 } 140 141 u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw, 142 enum radio_path rfpath, u32 regaddr, 143 u32 bitmask) 144 { 145 struct rtl_priv *rtlpriv = rtl_priv(hw); 146 u32 original_value, readback_value, bitshift; 147 148 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 149 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 150 regaddr, rfpath, bitmask); 151 152 spin_lock(&rtlpriv->locks.rf_lock); 153 154 original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); 155 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 156 readback_value = (original_value & bitmask) >> bitshift; 157 158 spin_unlock(&rtlpriv->locks.rf_lock); 159 160 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 161 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 162 regaddr, rfpath, bitmask, original_value); 163 164 return readback_value; 165 } 166 167 void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw, 168 enum radio_path rfpath, 169 u32 regaddr, u32 bitmask, u32 data) 170 { 171 struct rtl_priv *rtlpriv = rtl_priv(hw); 172 u32 original_value, bitshift; 173 174 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 175 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 176 regaddr, bitmask, data, rfpath); 177 178 spin_lock(&rtlpriv->locks.rf_lock); 179 180 if (bitmask != RFREG_OFFSET_MASK) { 181 original_value = 182 _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); 183 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); 184 data = ((original_value & (~bitmask)) | (data << bitshift)); 185 } 186 187 _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data); 188 189 spin_unlock(&rtlpriv->locks.rf_lock); 190 191 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 192 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 193 regaddr, bitmask, data, rfpath); 194 } 195 196 static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw, 197 enum radio_path rfpath, u32 offset) 198 { 199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 200 bool is_pi_mode = false; 201 u32 retvalue = 0; 202 203 /* 2009/06/17 MH We can not execute IO for power 204 save or other accident mode.*/ 205 if (RT_CANNOT_IO(hw)) { 206 pr_err("return all one\n"); 207 return 0xFFFFFFFF; 208 } 209 /* <20120809, Kordan> CCA OFF(when entering), 210 asked by James to avoid reading the wrong value. 211 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/ 212 if (offset != 0x0 && 213 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 214 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))) 215 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1); 216 offset &= 0xff; 217 218 if (rfpath == RF90_PATH_A) 219 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xC00, 0x4); 220 else if (rfpath == RF90_PATH_B) 221 is_pi_mode = (bool)rtl_get_bbreg(hw, 0xE00, 0x4); 222 223 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset); 224 225 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 226 (IS_VENDOR_8812A_C_CUT(rtlhal->version))) 227 udelay(20); 228 229 if (is_pi_mode) { 230 if (rfpath == RF90_PATH_A) 231 retvalue = 232 rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA); 233 else if (rfpath == RF90_PATH_B) 234 retvalue = 235 rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA); 236 } else { 237 if (rfpath == RF90_PATH_A) 238 retvalue = 239 rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA); 240 else if (rfpath == RF90_PATH_B) 241 retvalue = 242 rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA); 243 } 244 245 /*<20120809, Kordan> CCA ON(when exiting), 246 * asked by James to avoid reading the wrong value. 247 * <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it! 248 */ 249 if (offset != 0x0 && 250 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 251 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))) 252 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0); 253 return retvalue; 254 } 255 256 static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw, 257 enum radio_path rfpath, u32 offset, 258 u32 data) 259 { 260 struct rtl_priv *rtlpriv = rtl_priv(hw); 261 struct rtl_phy *rtlphy = &rtlpriv->phy; 262 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 263 u32 data_and_addr; 264 u32 newoffset; 265 266 if (RT_CANNOT_IO(hw)) { 267 pr_err("stop\n"); 268 return; 269 } 270 offset &= 0xff; 271 newoffset = offset; 272 data_and_addr = ((newoffset << 20) | 273 (data & 0x000fffff)) & 0x0fffffff; 274 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 275 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 276 "RFW-%d Addr[0x%x]=0x%x\n", 277 rfpath, pphyreg->rf3wire_offset, data_and_addr); 278 } 279 280 bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw) 281 { 282 bool rtstatus = 0; 283 284 rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw); 285 286 return rtstatus; 287 } 288 289 bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw) 290 { 291 bool rtstatus = true; 292 struct rtl_priv *rtlpriv = rtl_priv(hw); 293 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 294 struct rtl_phy *rtlphy = &rtlpriv->phy; 295 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 296 u8 regval; 297 u8 crystal_cap; 298 299 phy_init_bb_rf_register_definition(hw); 300 301 regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 302 regval |= FEN_PCIEA; 303 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval); 304 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 305 regval | FEN_BB_GLB_RSTN | FEN_BBRSTB); 306 307 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7); 308 rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7); 309 310 rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw); 311 312 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 313 crystal_cap = rtlefuse->crystalcap & 0x3F; 314 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000, 315 (crystal_cap | (crystal_cap << 6))); 316 } else { 317 crystal_cap = rtlefuse->crystalcap & 0x3F; 318 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, 319 (crystal_cap | (crystal_cap << 6))); 320 } 321 rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837); 322 323 return rtstatus; 324 } 325 326 bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw) 327 { 328 return rtl8821ae_phy_rf6052_config(hw); 329 } 330 331 static void _rtl8812ae_phy_set_rfe_reg_24g(struct ieee80211_hw *hw) 332 { 333 struct rtl_priv *rtlpriv = rtl_priv(hw); 334 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 335 u8 tmp; 336 337 switch (rtlhal->rfe_type) { 338 case 3: 339 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337770); 340 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337770); 341 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 342 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 343 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1); 344 break; 345 case 4: 346 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777); 347 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777); 348 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x001); 349 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x001); 350 break; 351 case 5: 352 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x77); 353 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777); 354 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3); 355 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp & ~0x1); 356 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 357 break; 358 case 1: 359 if (rtlpriv->btcoexist.bt_coexistence) { 360 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x777777); 361 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 362 0x77777777); 363 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000); 364 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 365 break; 366 } 367 fallthrough; 368 case 0: 369 case 2: 370 default: 371 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777); 372 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777); 373 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000); 374 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 375 break; 376 } 377 } 378 379 static void _rtl8812ae_phy_set_rfe_reg_5g(struct ieee80211_hw *hw) 380 { 381 struct rtl_priv *rtlpriv = rtl_priv(hw); 382 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 383 u8 tmp; 384 385 switch (rtlhal->rfe_type) { 386 case 0: 387 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337717); 388 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337717); 389 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 390 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 391 break; 392 case 1: 393 if (rtlpriv->btcoexist.bt_coexistence) { 394 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xffffff, 0x337717); 395 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 396 0x77337717); 397 rtl_set_bbreg(hw, RA_RFE_INV, 0x33f00000, 0x000); 398 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 399 } else { 400 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 401 0x77337717); 402 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 403 0x77337717); 404 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x000); 405 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x000); 406 } 407 break; 408 case 3: 409 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x54337717); 410 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x54337717); 411 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 412 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 413 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x1); 414 break; 415 case 5: 416 rtl_write_byte(rtlpriv, RA_RFE_PINMUX + 2, 0x33); 417 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777); 418 tmp = rtl_read_byte(rtlpriv, RA_RFE_INV + 3); 419 rtl_write_byte(rtlpriv, RA_RFE_INV + 3, tmp | 0x1); 420 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 421 break; 422 case 2: 423 case 4: 424 default: 425 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777); 426 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777); 427 rtl_set_bbreg(hw, RA_RFE_INV, BMASKRFEINV, 0x010); 428 rtl_set_bbreg(hw, RB_RFE_INV, BMASKRFEINV, 0x010); 429 break; 430 } 431 } 432 433 u32 phy_get_tx_swing_8812A(struct ieee80211_hw *hw, u8 band, 434 u8 rf_path) 435 { 436 struct rtl_priv *rtlpriv = rtl_priv(hw); 437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 438 struct rtl_dm *rtldm = rtl_dm(rtlpriv); 439 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 440 s8 reg_swing_2g = -1;/* 0xff; */ 441 s8 reg_swing_5g = -1;/* 0xff; */ 442 s8 swing_2g = -1 * reg_swing_2g; 443 s8 swing_5g = -1 * reg_swing_5g; 444 u32 out = 0x200; 445 const s8 auto_temp = -1; 446 447 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 448 "===> PHY_GetTXBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d,autoload_failflag=%d.\n", 449 (int)swing_2g, (int)swing_5g, 450 (int)rtlefuse->autoload_failflag); 451 452 if (rtlefuse->autoload_failflag) { 453 if (band == BAND_ON_2_4G) { 454 rtldm->swing_diff_2g = swing_2g; 455 if (swing_2g == 0) { 456 out = 0x200; /* 0 dB */ 457 } else if (swing_2g == -3) { 458 out = 0x16A; /* -3 dB */ 459 } else if (swing_2g == -6) { 460 out = 0x101; /* -6 dB */ 461 } else if (swing_2g == -9) { 462 out = 0x0B6; /* -9 dB */ 463 } else { 464 rtldm->swing_diff_2g = 0; 465 out = 0x200; 466 } 467 } else if (band == BAND_ON_5G) { 468 rtldm->swing_diff_5g = swing_5g; 469 if (swing_5g == 0) { 470 out = 0x200; /* 0 dB */ 471 } else if (swing_5g == -3) { 472 out = 0x16A; /* -3 dB */ 473 } else if (swing_5g == -6) { 474 out = 0x101; /* -6 dB */ 475 } else if (swing_5g == -9) { 476 out = 0x0B6; /* -9 dB */ 477 } else { 478 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 479 rtldm->swing_diff_5g = -3; 480 out = 0x16A; 481 } else { 482 rtldm->swing_diff_5g = 0; 483 out = 0x200; 484 } 485 } 486 } else { 487 rtldm->swing_diff_2g = -3; 488 rtldm->swing_diff_5g = -3; 489 out = 0x16A; /* -3 dB */ 490 } 491 } else { 492 u32 swing = 0, swing_a = 0, swing_b = 0; 493 494 if (band == BAND_ON_2_4G) { 495 if (reg_swing_2g == auto_temp) { 496 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing); 497 swing = (swing == 0xFF) ? 0x00 : swing; 498 } else if (swing_2g == 0) { 499 swing = 0x00; /* 0 dB */ 500 } else if (swing_2g == -3) { 501 swing = 0x05; /* -3 dB */ 502 } else if (swing_2g == -6) { 503 swing = 0x0A; /* -6 dB */ 504 } else if (swing_2g == -9) { 505 swing = 0xFF; /* -9 dB */ 506 } else { 507 swing = 0x00; 508 } 509 } else { 510 if (reg_swing_5g == auto_temp) { 511 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing); 512 swing = (swing == 0xFF) ? 0x00 : swing; 513 } else if (swing_5g == 0) { 514 swing = 0x00; /* 0 dB */ 515 } else if (swing_5g == -3) { 516 swing = 0x05; /* -3 dB */ 517 } else if (swing_5g == -6) { 518 swing = 0x0A; /* -6 dB */ 519 } else if (swing_5g == -9) { 520 swing = 0xFF; /* -9 dB */ 521 } else { 522 swing = 0x00; 523 } 524 } 525 526 swing_a = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */ 527 swing_b = (swing & 0xC) >> 2; /* 0xC6/C7[3:2] */ 528 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 529 "===> PHY_GetTXBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n", 530 swing_a, swing_b); 531 532 /* 3 Path-A */ 533 if (swing_a == 0x0) { 534 if (band == BAND_ON_2_4G) 535 rtldm->swing_diff_2g = 0; 536 else 537 rtldm->swing_diff_5g = 0; 538 out = 0x200; /* 0 dB */ 539 } else if (swing_a == 0x1) { 540 if (band == BAND_ON_2_4G) 541 rtldm->swing_diff_2g = -3; 542 else 543 rtldm->swing_diff_5g = -3; 544 out = 0x16A; /* -3 dB */ 545 } else if (swing_a == 0x2) { 546 if (band == BAND_ON_2_4G) 547 rtldm->swing_diff_2g = -6; 548 else 549 rtldm->swing_diff_5g = -6; 550 out = 0x101; /* -6 dB */ 551 } else if (swing_a == 0x3) { 552 if (band == BAND_ON_2_4G) 553 rtldm->swing_diff_2g = -9; 554 else 555 rtldm->swing_diff_5g = -9; 556 out = 0x0B6; /* -9 dB */ 557 } 558 /* 3 Path-B */ 559 if (swing_b == 0x0) { 560 if (band == BAND_ON_2_4G) 561 rtldm->swing_diff_2g = 0; 562 else 563 rtldm->swing_diff_5g = 0; 564 out = 0x200; /* 0 dB */ 565 } else if (swing_b == 0x1) { 566 if (band == BAND_ON_2_4G) 567 rtldm->swing_diff_2g = -3; 568 else 569 rtldm->swing_diff_5g = -3; 570 out = 0x16A; /* -3 dB */ 571 } else if (swing_b == 0x2) { 572 if (band == BAND_ON_2_4G) 573 rtldm->swing_diff_2g = -6; 574 else 575 rtldm->swing_diff_5g = -6; 576 out = 0x101; /* -6 dB */ 577 } else if (swing_b == 0x3) { 578 if (band == BAND_ON_2_4G) 579 rtldm->swing_diff_2g = -9; 580 else 581 rtldm->swing_diff_5g = -9; 582 out = 0x0B6; /* -9 dB */ 583 } 584 } 585 586 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 587 "<=== PHY_GetTXBBSwing_8812A, out = 0x%X\n", out); 588 return out; 589 } 590 591 void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 592 { 593 struct rtl_priv *rtlpriv = rtl_priv(hw); 594 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 595 struct rtl_dm *rtldm = rtl_dm(rtlpriv); 596 u8 current_band = rtlhal->current_bandtype; 597 u32 txpath, rxpath; 598 s8 bb_diff_between_band; 599 600 txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0); 601 rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000); 602 rtlhal->current_bandtype = (enum band_type) band; 603 /* reconfig BB/RF according to wireless mode */ 604 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 605 /* BB & RF Config */ 606 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03); 607 608 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 609 /* 0xCB0[15:12] = 0x7 (LNA_On)*/ 610 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7); 611 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/ 612 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7); 613 } 614 615 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 616 /*0x834[1:0] = 0x1*/ 617 rtl_set_bbreg(hw, 0x834, 0x3, 0x1); 618 } 619 620 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 621 /* 0xC1C[11:8] = 0 */ 622 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0); 623 } else { 624 /* 0x82C[1:0] = 2b'00 */ 625 rtl_set_bbreg(hw, 0x82c, 0x3, 0); 626 } 627 628 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 629 _rtl8812ae_phy_set_rfe_reg_24g(hw); 630 631 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0x1); 632 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0x1); 633 634 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0); 635 } else {/* 5G band */ 636 u16 count, reg_41a; 637 638 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 639 /*0xCB0[15:12] = 0x5 (LNA_On)*/ 640 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5); 641 /*0xCB0[7:4] = 0x4 (PAPE_A)*/ 642 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4); 643 } 644 /*CCK_CHECK_en*/ 645 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80); 646 647 count = 0; 648 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 649 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 650 "Reg41A value %d\n", reg_41a); 651 reg_41a &= 0x30; 652 while ((reg_41a != 0x30) && (count < 50)) { 653 udelay(50); 654 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "Delay 50us\n"); 655 656 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 657 reg_41a &= 0x30; 658 count++; 659 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 660 "Reg41A value %d\n", reg_41a); 661 } 662 if (count != 0) 663 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, 664 "PHY_SwitchWirelessBand8812(): Switch to 5G Band. Count = %d reg41A=0x%x\n", 665 count, reg_41a); 666 667 /* 2012/02/01, Sinda add registry to switch workaround 668 without long-run verification for scan issue. */ 669 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03); 670 671 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 672 /*0x834[1:0] = 0x2*/ 673 rtl_set_bbreg(hw, 0x834, 0x3, 0x2); 674 } 675 676 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 677 /* AGC table select */ 678 /* 0xC1C[11:8] = 1*/ 679 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1); 680 } else 681 /* 0x82C[1:0] = 2'b00 */ 682 rtl_set_bbreg(hw, 0x82c, 0x3, 1); 683 684 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 685 _rtl8812ae_phy_set_rfe_reg_5g(hw); 686 687 rtl_set_bbreg(hw, RTXPATH, 0xf0, 0); 688 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, 0xf); 689 690 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, 691 "==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n", 692 rtlpriv->dm.ofdm_index[RF90_PATH_A]); 693 } 694 695 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || 696 (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) { 697 /* 0xC1C[31:21] */ 698 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, 699 phy_get_tx_swing_8812A(hw, band, RF90_PATH_A)); 700 /* 0xE1C[31:21] */ 701 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, 702 phy_get_tx_swing_8812A(hw, band, RF90_PATH_B)); 703 704 /* <20121005, Kordan> When TxPowerTrack is ON, 705 * we should take care of the change of BB swing. 706 * That is, reset all info to trigger Tx power tracking. 707 */ 708 if (band != current_band) { 709 bb_diff_between_band = 710 (rtldm->swing_diff_2g - rtldm->swing_diff_5g); 711 bb_diff_between_band = (band == BAND_ON_2_4G) ? 712 bb_diff_between_band : 713 (-1 * bb_diff_between_band); 714 rtldm->default_ofdm_index += bb_diff_between_band * 2; 715 } 716 rtl8821ae_dm_clear_txpower_tracking_state(hw); 717 } 718 719 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 720 "<==%s():Switch Band OK.\n", __func__); 721 return; 722 } 723 724 static bool _rtl8821ae_check_positive(struct ieee80211_hw *hw, 725 const u32 condition1, 726 const u32 condition2) 727 { 728 struct rtl_priv *rtlpriv = rtl_priv(hw); 729 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 730 u32 cut_ver = ((rtlhal->version & CHIP_VER_RTL_MASK) 731 >> CHIP_VER_RTL_SHIFT); 732 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); 733 734 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ 735 ((rtlhal->board_type & BIT(3)) >> 3) << 1 | /* _GPA */ 736 ((rtlhal->board_type & BIT(7)) >> 7) << 2 | /* _ALNA */ 737 ((rtlhal->board_type & BIT(6)) >> 6) << 3 | /* _APA */ 738 ((rtlhal->board_type & BIT(2)) >> 2) << 4; /* _BT */ 739 740 u32 cond1 = condition1, cond2 = condition2; 741 u32 driver1 = cut_ver << 24 | /* CUT ver */ 742 0 << 20 | /* interface 2/2 */ 743 0x04 << 16 | /* platform */ 744 rtlhal->package_type << 12 | 745 intf << 8 | /* interface 1/2 */ 746 board_type; 747 748 u32 driver2 = rtlhal->type_glna << 0 | 749 rtlhal->type_gpa << 8 | 750 rtlhal->type_alna << 16 | 751 rtlhal->type_apa << 24; 752 753 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 754 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", 755 cond1, cond2); 756 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 757 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", 758 driver1, driver2); 759 760 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 761 " (Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf); 762 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 763 " (Board, Package) = (0x%X, 0x%X)\n", 764 rtlhal->board_type, rtlhal->package_type); 765 766 /*============== Value Defined Check ===============*/ 767 /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ 768 769 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != 770 (driver1 & 0x0000F000))) 771 return false; 772 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != 773 (driver1 & 0x0F000000))) 774 return false; 775 776 /*=============== Bit Defined Check ================*/ 777 /* We don't care [31:28] */ 778 779 cond1 &= 0x00FF0FFF; 780 driver1 &= 0x00FF0FFF; 781 782 if ((cond1 & driver1) == cond1) { 783 u32 mask = 0; 784 785 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ 786 return true; 787 788 if ((cond1 & BIT(0)) != 0) /*GLNA*/ 789 mask |= 0x000000FF; 790 if ((cond1 & BIT(1)) != 0) /*GPA*/ 791 mask |= 0x0000FF00; 792 if ((cond1 & BIT(2)) != 0) /*ALNA*/ 793 mask |= 0x00FF0000; 794 if ((cond1 & BIT(3)) != 0) /*APA*/ 795 mask |= 0xFF000000; 796 797 /* BoardType of each RF path is matched*/ 798 if ((cond2 & mask) == (driver2 & mask)) 799 return true; 800 else 801 return false; 802 } else 803 return false; 804 } 805 806 static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw, 807 const u32 condition) 808 { 809 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 810 u32 _board = rtlefuse->board_type; /*need efuse define*/ 811 u32 _interface = 0x01; /* ODM_ITRF_PCIE */ 812 u32 _platform = 0x08;/* ODM_WIN */ 813 u32 cond = condition; 814 815 if (condition == 0xCDCDCDCD) 816 return true; 817 818 cond = condition & 0xFF; 819 if ((_board != cond) && cond != 0xFF) 820 return false; 821 822 cond = condition & 0xFF00; 823 cond = cond >> 8; 824 if ((_interface & cond) == 0 && cond != 0x07) 825 return false; 826 827 cond = condition & 0xFF0000; 828 cond = cond >> 16; 829 if ((_platform & cond) == 0 && cond != 0x0F) 830 return false; 831 return true; 832 } 833 834 static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw, 835 u32 addr, u32 data, 836 enum radio_path rfpath, u32 regaddr) 837 { 838 if (addr == 0xfe || addr == 0xffe) { 839 /* In order not to disturb BT music when 840 * wifi init.(1ant NIC only) 841 */ 842 mdelay(50); 843 } else { 844 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); 845 udelay(1); 846 } 847 } 848 849 static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw, 850 u32 addr, u32 data) 851 { 852 u32 content = 0x1000; /*RF Content: radio_a_txt*/ 853 u32 maskforphyset = (u32)(content & 0xE000); 854 855 _rtl8821ae_config_rf_reg(hw, addr, data, 856 RF90_PATH_A, addr | maskforphyset); 857 } 858 859 static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw, 860 u32 addr, u32 data) 861 { 862 u32 content = 0x1001; /*RF Content: radio_b_txt*/ 863 u32 maskforphyset = (u32)(content & 0xE000); 864 865 _rtl8821ae_config_rf_reg(hw, addr, data, 866 RF90_PATH_B, addr | maskforphyset); 867 } 868 869 static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw, 870 u32 addr, u32 data) 871 { 872 if (addr == 0xfe) 873 mdelay(50); 874 else if (addr == 0xfd) 875 mdelay(5); 876 else if (addr == 0xfc) 877 mdelay(1); 878 else if (addr == 0xfb) 879 udelay(50); 880 else if (addr == 0xfa) 881 udelay(5); 882 else if (addr == 0xf9) 883 udelay(1); 884 else 885 rtl_set_bbreg(hw, addr, MASKDWORD, data); 886 887 udelay(1); 888 } 889 890 static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) 891 { 892 struct rtl_priv *rtlpriv = rtl_priv(hw); 893 struct rtl_phy *rtlphy = &rtlpriv->phy; 894 u8 band, rfpath, txnum, rate_section; 895 896 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) 897 for (rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath) 898 for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum) 899 for (rate_section = 0; 900 rate_section < TX_PWR_BY_RATE_NUM_SECTION; 901 ++rate_section) 902 rtlphy->tx_power_by_rate_offset[band] 903 [rfpath][txnum][rate_section] = 0; 904 } 905 906 static void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, 907 u8 band, u8 path, 908 u8 rate_section, 909 u8 txnum, u8 value) 910 { 911 struct rtl_priv *rtlpriv = rtl_priv(hw); 912 struct rtl_phy *rtlphy = &rtlpriv->phy; 913 914 if (path > RF90_PATH_D) { 915 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 916 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path); 917 return; 918 } 919 920 if (band == BAND_ON_2_4G) { 921 switch (rate_section) { 922 case CCK: 923 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; 924 break; 925 case OFDM: 926 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value; 927 break; 928 case HT_MCS0_MCS7: 929 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value; 930 break; 931 case HT_MCS8_MCS15: 932 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value; 933 break; 934 case VHT_1SSMCS0_1SSMCS9: 935 rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value; 936 break; 937 case VHT_2SSMCS0_2SSMCS9: 938 rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value; 939 break; 940 default: 941 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 942 "Invalid RateSection %d in Band 2.4G,Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n", 943 rate_section, path, txnum); 944 break; 945 } 946 } else if (band == BAND_ON_5G) { 947 switch (rate_section) { 948 case OFDM: 949 rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value; 950 break; 951 case HT_MCS0_MCS7: 952 rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value; 953 break; 954 case HT_MCS8_MCS15: 955 rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value; 956 break; 957 case VHT_1SSMCS0_1SSMCS9: 958 rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value; 959 break; 960 case VHT_2SSMCS0_2SSMCS9: 961 rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value; 962 break; 963 default: 964 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 965 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n", 966 rate_section, path, txnum); 967 break; 968 } 969 } else { 970 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 971 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band); 972 } 973 } 974 975 static u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, 976 u8 band, u8 path, 977 u8 txnum, u8 rate_section) 978 { 979 struct rtl_priv *rtlpriv = rtl_priv(hw); 980 struct rtl_phy *rtlphy = &rtlpriv->phy; 981 u8 value = 0; 982 983 if (path > RF90_PATH_D) { 984 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 985 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n", 986 path); 987 return 0; 988 } 989 990 if (band == BAND_ON_2_4G) { 991 switch (rate_section) { 992 case CCK: 993 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; 994 break; 995 case OFDM: 996 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1]; 997 break; 998 case HT_MCS0_MCS7: 999 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2]; 1000 break; 1001 case HT_MCS8_MCS15: 1002 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3]; 1003 break; 1004 case VHT_1SSMCS0_1SSMCS9: 1005 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4]; 1006 break; 1007 case VHT_2SSMCS0_2SSMCS9: 1008 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5]; 1009 break; 1010 default: 1011 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1012 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n", 1013 rate_section, path, txnum); 1014 break; 1015 } 1016 } else if (band == BAND_ON_5G) { 1017 switch (rate_section) { 1018 case OFDM: 1019 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0]; 1020 break; 1021 case HT_MCS0_MCS7: 1022 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1]; 1023 break; 1024 case HT_MCS8_MCS15: 1025 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2]; 1026 break; 1027 case VHT_1SSMCS0_1SSMCS9: 1028 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3]; 1029 break; 1030 case VHT_2SSMCS0_2SSMCS9: 1031 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4]; 1032 break; 1033 default: 1034 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1035 "Invalid RateSection %d in Band 5G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n", 1036 rate_section, path, txnum); 1037 break; 1038 } 1039 } else { 1040 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1041 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band); 1042 } 1043 1044 return value; 1045 } 1046 1047 static void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) 1048 { 1049 struct rtl_priv *rtlpriv = rtl_priv(hw); 1050 struct rtl_phy *rtlphy = &rtlpriv->phy; 1051 u16 rawvalue = 0; 1052 u8 base = 0, path = 0; 1053 1054 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) { 1055 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF; 1056 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1057 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base); 1058 1059 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF; 1060 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1061 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base); 1062 1063 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF; 1064 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1065 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base); 1066 1067 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF; 1068 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1069 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base); 1070 1071 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF; 1072 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1073 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); 1074 1075 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF; 1076 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1077 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); 1078 1079 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF; 1080 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1081 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base); 1082 1083 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF; 1084 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1085 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base); 1086 1087 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF; 1088 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1089 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base); 1090 1091 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF; 1092 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1093 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base); 1094 1095 rawvalue = (u16)(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF; 1096 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); 1097 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base); 1098 } 1099 } 1100 1101 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start, 1102 u8 end, u8 base_val) 1103 { 1104 int i; 1105 u8 temp_value = 0; 1106 u32 temp_data = 0; 1107 1108 for (i = 3; i >= 0; --i) { 1109 if (i >= start && i <= end) { 1110 /* Get the exact value */ 1111 temp_value = (u8)(*data >> (i * 8)) & 0xF; 1112 temp_value += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10; 1113 1114 /* Change the value to a relative value */ 1115 temp_value = (temp_value > base_val) ? temp_value - 1116 base_val : base_val - temp_value; 1117 } else { 1118 temp_value = (u8)(*data >> (i * 8)) & 0xFF; 1119 } 1120 temp_data <<= 8; 1121 temp_data |= temp_value; 1122 } 1123 *data = temp_data; 1124 } 1125 1126 static void _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(struct ieee80211_hw *hw) 1127 { 1128 struct rtl_priv *rtlpriv = rtl_priv(hw); 1129 struct rtl_phy *rtlphy = &rtlpriv->phy; 1130 u8 regulation, bw, channel, rate_section; 1131 s8 temp_pwrlmt = 0; 1132 1133 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1134 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { 1135 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) { 1136 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) { 1137 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation] 1138 [bw][rate_section][channel][RF90_PATH_A]; 1139 if (temp_pwrlmt == MAX_POWER_INDEX) { 1140 if (bw == 0 || bw == 1) { /*5G 20M 40M VHT and HT can cross reference*/ 1141 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1142 "No power limit table of the specified band %d, bandwidth %d, ratesection %d, channel %d, rf path %d\n", 1143 1, bw, rate_section, channel, RF90_PATH_A); 1144 if (rate_section == 2) { 1145 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A] = 1146 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A]; 1147 } else if (rate_section == 4) { 1148 rtlphy->txpwr_limit_5g[regulation][bw][4][channel][RF90_PATH_A] = 1149 rtlphy->txpwr_limit_5g[regulation][bw][2][channel][RF90_PATH_A]; 1150 } else if (rate_section == 3) { 1151 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A] = 1152 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A]; 1153 } else if (rate_section == 5) { 1154 rtlphy->txpwr_limit_5g[regulation][bw][5][channel][RF90_PATH_A] = 1155 rtlphy->txpwr_limit_5g[regulation][bw][3][channel][RF90_PATH_A]; 1156 } 1157 1158 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1159 "use other value %d\n", 1160 temp_pwrlmt); 1161 } 1162 } 1163 } 1164 } 1165 } 1166 } 1167 } 1168 1169 static u8 _rtl8812ae_phy_get_txpower_by_rate_base_index(struct ieee80211_hw *hw, 1170 enum band_type band, u8 rate) 1171 { 1172 struct rtl_priv *rtlpriv = rtl_priv(hw); 1173 u8 index = 0; 1174 if (band == BAND_ON_2_4G) { 1175 switch (rate) { 1176 case MGN_1M: 1177 case MGN_2M: 1178 case MGN_5_5M: 1179 case MGN_11M: 1180 index = 0; 1181 break; 1182 1183 case MGN_6M: 1184 case MGN_9M: 1185 case MGN_12M: 1186 case MGN_18M: 1187 case MGN_24M: 1188 case MGN_36M: 1189 case MGN_48M: 1190 case MGN_54M: 1191 index = 1; 1192 break; 1193 1194 case MGN_MCS0: 1195 case MGN_MCS1: 1196 case MGN_MCS2: 1197 case MGN_MCS3: 1198 case MGN_MCS4: 1199 case MGN_MCS5: 1200 case MGN_MCS6: 1201 case MGN_MCS7: 1202 index = 2; 1203 break; 1204 1205 case MGN_MCS8: 1206 case MGN_MCS9: 1207 case MGN_MCS10: 1208 case MGN_MCS11: 1209 case MGN_MCS12: 1210 case MGN_MCS13: 1211 case MGN_MCS14: 1212 case MGN_MCS15: 1213 index = 3; 1214 break; 1215 1216 default: 1217 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1218 "Wrong rate 0x%x to obtain index in 2.4G in PHY_GetTxPowerByRateBaseIndex()\n", 1219 rate); 1220 break; 1221 } 1222 } else if (band == BAND_ON_5G) { 1223 switch (rate) { 1224 case MGN_6M: 1225 case MGN_9M: 1226 case MGN_12M: 1227 case MGN_18M: 1228 case MGN_24M: 1229 case MGN_36M: 1230 case MGN_48M: 1231 case MGN_54M: 1232 index = 0; 1233 break; 1234 1235 case MGN_MCS0: 1236 case MGN_MCS1: 1237 case MGN_MCS2: 1238 case MGN_MCS3: 1239 case MGN_MCS4: 1240 case MGN_MCS5: 1241 case MGN_MCS6: 1242 case MGN_MCS7: 1243 index = 1; 1244 break; 1245 1246 case MGN_MCS8: 1247 case MGN_MCS9: 1248 case MGN_MCS10: 1249 case MGN_MCS11: 1250 case MGN_MCS12: 1251 case MGN_MCS13: 1252 case MGN_MCS14: 1253 case MGN_MCS15: 1254 index = 2; 1255 break; 1256 1257 case MGN_VHT1SS_MCS0: 1258 case MGN_VHT1SS_MCS1: 1259 case MGN_VHT1SS_MCS2: 1260 case MGN_VHT1SS_MCS3: 1261 case MGN_VHT1SS_MCS4: 1262 case MGN_VHT1SS_MCS5: 1263 case MGN_VHT1SS_MCS6: 1264 case MGN_VHT1SS_MCS7: 1265 case MGN_VHT1SS_MCS8: 1266 case MGN_VHT1SS_MCS9: 1267 index = 3; 1268 break; 1269 1270 case MGN_VHT2SS_MCS0: 1271 case MGN_VHT2SS_MCS1: 1272 case MGN_VHT2SS_MCS2: 1273 case MGN_VHT2SS_MCS3: 1274 case MGN_VHT2SS_MCS4: 1275 case MGN_VHT2SS_MCS5: 1276 case MGN_VHT2SS_MCS6: 1277 case MGN_VHT2SS_MCS7: 1278 case MGN_VHT2SS_MCS8: 1279 case MGN_VHT2SS_MCS9: 1280 index = 4; 1281 break; 1282 1283 default: 1284 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1285 "Wrong rate 0x%x to obtain index in 5G in PHY_GetTxPowerByRateBaseIndex()\n", 1286 rate); 1287 break; 1288 } 1289 } 1290 1291 return index; 1292 } 1293 1294 static void _rtl8812ae_phy_convert_txpower_limit_to_power_index(struct ieee80211_hw *hw) 1295 { 1296 struct rtl_priv *rtlpriv = rtl_priv(hw); 1297 struct rtl_phy *rtlphy = &rtlpriv->phy; 1298 u8 bw40_pwr_base_dbm2_4G, bw40_pwr_base_dbm5G; 1299 u8 regulation, bw, channel, rate_section; 1300 u8 base_index2_4G = 0; 1301 u8 base_index5G = 0; 1302 s8 temp_value = 0, temp_pwrlmt = 0; 1303 u8 rf_path = 0; 1304 1305 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1306 "=====> _rtl8812ae_phy_convert_txpower_limit_to_power_index()\n"); 1307 1308 _rtl8812ae_phy_cross_reference_ht_and_vht_txpower_limit(hw); 1309 1310 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1311 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { 1312 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) { 1313 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) { 1314 /* obtain the base dBm values in 2.4G band 1315 CCK => 11M, OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15*/ 1316 if (rate_section == 0) { /*CCK*/ 1317 base_index2_4G = 1318 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1319 BAND_ON_2_4G, MGN_11M); 1320 } else if (rate_section == 1) { /*OFDM*/ 1321 base_index2_4G = 1322 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1323 BAND_ON_2_4G, MGN_54M); 1324 } else if (rate_section == 2) { /*HT IT*/ 1325 base_index2_4G = 1326 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1327 BAND_ON_2_4G, MGN_MCS7); 1328 } else if (rate_section == 3) { /*HT 2T*/ 1329 base_index2_4G = 1330 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1331 BAND_ON_2_4G, MGN_MCS15); 1332 } 1333 1334 temp_pwrlmt = rtlphy->txpwr_limit_2_4g[regulation] 1335 [bw][rate_section][channel][RF90_PATH_A]; 1336 1337 for (rf_path = RF90_PATH_A; 1338 rf_path < MAX_RF_PATH_NUM; 1339 ++rf_path) { 1340 if (rate_section == 3) 1341 bw40_pwr_base_dbm2_4G = 1342 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_2TX][base_index2_4G]; 1343 else 1344 bw40_pwr_base_dbm2_4G = 1345 rtlphy->txpwr_by_rate_base_24g[rf_path][RF_1TX][base_index2_4G]; 1346 1347 if (temp_pwrlmt != MAX_POWER_INDEX) { 1348 temp_value = temp_pwrlmt - bw40_pwr_base_dbm2_4G; 1349 rtlphy->txpwr_limit_2_4g[regulation] 1350 [bw][rate_section][channel][rf_path] = 1351 temp_value; 1352 } 1353 1354 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1355 "TxPwrLimit_2_4G[regulation %d][bw %d][rateSection %d][channel %d] = %d\n(TxPwrLimit in dBm %d - BW40PwrLmt2_4G[channel %d][rfpath %d] %d)\n", 1356 regulation, bw, rate_section, channel, 1357 rtlphy->txpwr_limit_2_4g[regulation][bw] 1358 [rate_section][channel][rf_path], (temp_pwrlmt == 63) 1359 ? 0 : temp_pwrlmt/2, channel, rf_path, 1360 bw40_pwr_base_dbm2_4G); 1361 } 1362 } 1363 } 1364 } 1365 } 1366 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1367 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { 1368 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) { 1369 for (rate_section = 0; rate_section < MAX_RATE_SECTION_NUM; ++rate_section) { 1370 /* obtain the base dBm values in 5G band 1371 OFDM => 54M, HT 1T => MCS7, HT 2T => MCS15, 1372 VHT => 1SSMCS7, VHT 2T => 2SSMCS7*/ 1373 if (rate_section == 1) { /*OFDM*/ 1374 base_index5G = 1375 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1376 BAND_ON_5G, MGN_54M); 1377 } else if (rate_section == 2) { /*HT 1T*/ 1378 base_index5G = 1379 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1380 BAND_ON_5G, MGN_MCS7); 1381 } else if (rate_section == 3) { /*HT 2T*/ 1382 base_index5G = 1383 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1384 BAND_ON_5G, MGN_MCS15); 1385 } else if (rate_section == 4) { /*VHT 1T*/ 1386 base_index5G = 1387 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1388 BAND_ON_5G, MGN_VHT1SS_MCS7); 1389 } else if (rate_section == 5) { /*VHT 2T*/ 1390 base_index5G = 1391 _rtl8812ae_phy_get_txpower_by_rate_base_index(hw, 1392 BAND_ON_5G, MGN_VHT2SS_MCS7); 1393 } 1394 1395 temp_pwrlmt = rtlphy->txpwr_limit_5g[regulation] 1396 [bw][rate_section][channel] 1397 [RF90_PATH_A]; 1398 1399 for (rf_path = RF90_PATH_A; 1400 rf_path < MAX_RF_PATH_NUM; 1401 ++rf_path) { 1402 if (rate_section == 3 || rate_section == 5) 1403 bw40_pwr_base_dbm5G = 1404 rtlphy->txpwr_by_rate_base_5g[rf_path] 1405 [RF_2TX][base_index5G]; 1406 else 1407 bw40_pwr_base_dbm5G = 1408 rtlphy->txpwr_by_rate_base_5g[rf_path] 1409 [RF_1TX][base_index5G]; 1410 1411 if (temp_pwrlmt != MAX_POWER_INDEX) { 1412 temp_value = 1413 temp_pwrlmt - bw40_pwr_base_dbm5G; 1414 rtlphy->txpwr_limit_5g[regulation] 1415 [bw][rate_section][channel] 1416 [rf_path] = temp_value; 1417 } 1418 1419 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1420 "TxPwrLimit_5G[regulation %d][bw %d][rateSection %d][channel %d] =%d\n(TxPwrLimit in dBm %d - BW40PwrLmt5G[chnl group %d][rfpath %d] %d)\n", 1421 regulation, bw, rate_section, 1422 channel, rtlphy->txpwr_limit_5g[regulation] 1423 [bw][rate_section][channel][rf_path], 1424 temp_pwrlmt, channel, rf_path, bw40_pwr_base_dbm5G); 1425 } 1426 } 1427 } 1428 } 1429 } 1430 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1431 "<===== %s()\n", __func__); 1432 } 1433 1434 static void _rtl8821ae_phy_init_txpower_limit(struct ieee80211_hw *hw) 1435 { 1436 struct rtl_priv *rtlpriv = rtl_priv(hw); 1437 struct rtl_phy *rtlphy = &rtlpriv->phy; 1438 u8 i, j, k, l, m; 1439 1440 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1441 "=====>`%s()!\n", __func__); 1442 1443 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 1444 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) 1445 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) 1446 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m) 1447 for (l = 0; l < MAX_RF_PATH_NUM; ++l) 1448 rtlphy->txpwr_limit_2_4g 1449 [i][j][k][m][l] 1450 = MAX_POWER_INDEX; 1451 } 1452 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 1453 for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) 1454 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) 1455 for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m) 1456 for (l = 0; l < MAX_RF_PATH_NUM; ++l) 1457 rtlphy->txpwr_limit_5g 1458 [i][j][k][m][l] 1459 = MAX_POWER_INDEX; 1460 } 1461 1462 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1463 "<===== %s()!\n", __func__); 1464 } 1465 1466 static void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw) 1467 { 1468 struct rtl_priv *rtlpriv = rtl_priv(hw); 1469 struct rtl_phy *rtlphy = &rtlpriv->phy; 1470 u8 base = 0, rfpath = 0; 1471 1472 for (rfpath = RF90_PATH_A; rfpath <= RF90_PATH_B; ++rfpath) { 1473 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, CCK); 1474 _phy_convert_txpower_dbm_to_relative_value( 1475 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0], 1476 0, 3, base); 1477 1478 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, OFDM); 1479 _phy_convert_txpower_dbm_to_relative_value( 1480 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][1], 1481 0, 3, base); 1482 _phy_convert_txpower_dbm_to_relative_value( 1483 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][2], 1484 0, 3, base); 1485 1486 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, HT_MCS0_MCS7); 1487 _phy_convert_txpower_dbm_to_relative_value( 1488 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][3], 1489 0, 3, base); 1490 _phy_convert_txpower_dbm_to_relative_value( 1491 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][4], 1492 0, 3, base); 1493 1494 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, HT_MCS8_MCS15); 1495 1496 _phy_convert_txpower_dbm_to_relative_value( 1497 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][5], 1498 0, 3, base); 1499 1500 _phy_convert_txpower_dbm_to_relative_value( 1501 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][6], 1502 0, 3, base); 1503 1504 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9); 1505 _phy_convert_txpower_dbm_to_relative_value( 1506 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][7], 1507 0, 3, base); 1508 _phy_convert_txpower_dbm_to_relative_value( 1509 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][8], 1510 0, 3, base); 1511 _phy_convert_txpower_dbm_to_relative_value( 1512 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9], 1513 0, 1, base); 1514 1515 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9); 1516 _phy_convert_txpower_dbm_to_relative_value( 1517 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][9], 1518 2, 3, base); 1519 _phy_convert_txpower_dbm_to_relative_value( 1520 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][10], 1521 0, 3, base); 1522 _phy_convert_txpower_dbm_to_relative_value( 1523 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][11], 1524 0, 3, base); 1525 1526 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, OFDM); 1527 _phy_convert_txpower_dbm_to_relative_value( 1528 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][1], 1529 0, 3, base); 1530 _phy_convert_txpower_dbm_to_relative_value( 1531 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][2], 1532 0, 3, base); 1533 1534 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, HT_MCS0_MCS7); 1535 _phy_convert_txpower_dbm_to_relative_value( 1536 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][3], 1537 0, 3, base); 1538 _phy_convert_txpower_dbm_to_relative_value( 1539 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][4], 1540 0, 3, base); 1541 1542 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, HT_MCS8_MCS15); 1543 _phy_convert_txpower_dbm_to_relative_value( 1544 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][5], 1545 0, 3, base); 1546 _phy_convert_txpower_dbm_to_relative_value( 1547 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][6], 1548 0, 3, base); 1549 1550 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_1TX, VHT_1SSMCS0_1SSMCS9); 1551 _phy_convert_txpower_dbm_to_relative_value( 1552 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][7], 1553 0, 3, base); 1554 _phy_convert_txpower_dbm_to_relative_value( 1555 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][8], 1556 0, 3, base); 1557 _phy_convert_txpower_dbm_to_relative_value( 1558 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9], 1559 0, 1, base); 1560 1561 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfpath, RF_2TX, VHT_2SSMCS0_2SSMCS9); 1562 _phy_convert_txpower_dbm_to_relative_value( 1563 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_1TX][9], 1564 2, 3, base); 1565 _phy_convert_txpower_dbm_to_relative_value( 1566 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][10], 1567 0, 3, base); 1568 _phy_convert_txpower_dbm_to_relative_value( 1569 &rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfpath][RF_2TX][11], 1570 0, 3, base); 1571 } 1572 1573 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 1574 "<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n"); 1575 } 1576 1577 static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw) 1578 { 1579 _rtl8821ae_phy_store_txpower_by_rate_base(hw); 1580 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw); 1581 } 1582 1583 /* string is in decimal */ 1584 static bool _rtl8812ae_get_integer_from_string(const char *str, u8 *pint) 1585 { 1586 u16 i = 0; 1587 *pint = 0; 1588 1589 while (str[i] != '\0') { 1590 if (str[i] >= '0' && str[i] <= '9') { 1591 *pint *= 10; 1592 *pint += (str[i] - '0'); 1593 } else { 1594 return false; 1595 } 1596 ++i; 1597 } 1598 1599 return true; 1600 } 1601 1602 static bool _rtl8812ae_eq_n_byte(const char *str1, const char *str2, u32 num) 1603 { 1604 if (num == 0) 1605 return false; 1606 while (num > 0) { 1607 num--; 1608 if (str1[num] != str2[num]) 1609 return false; 1610 } 1611 return true; 1612 } 1613 1614 static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, 1615 u8 band, u8 channel) 1616 { 1617 struct rtl_priv *rtlpriv = rtl_priv(hw); 1618 s8 channel_index = -1; 1619 u8 i = 0; 1620 1621 if (band == BAND_ON_2_4G) 1622 channel_index = channel - 1; 1623 else if (band == BAND_ON_5G) { 1624 for (i = 0; i < sizeof(channel5g)/sizeof(u8); ++i) { 1625 if (channel5g[i] == channel) 1626 channel_index = i; 1627 } 1628 } else 1629 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Band %d in %s\n", 1630 band, __func__); 1631 1632 if (channel_index == -1) 1633 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1634 "Invalid Channel %d of Band %d in %s\n", channel, 1635 band, __func__); 1636 1637 return channel_index; 1638 } 1639 1640 static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, 1641 const char *pregulation, 1642 const char *pband, const char *pbandwidth, 1643 const char *prate_section, const char *prf_path, 1644 const char *pchannel, const char *ppower_limit) 1645 { 1646 struct rtl_priv *rtlpriv = rtl_priv(hw); 1647 struct rtl_phy *rtlphy = &rtlpriv->phy; 1648 u8 regulation = 0, bandwidth = 0, rate_section = 0, channel; 1649 u8 channel_index; 1650 s8 power_limit = 0, prev_power_limit, ret; 1651 1652 if (!_rtl8812ae_get_integer_from_string(pchannel, &channel) || 1653 !_rtl8812ae_get_integer_from_string(ppower_limit, 1654 &power_limit)) { 1655 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1656 "Illegal index of pwr_lmt table [chnl %d][val %d]\n", 1657 channel, power_limit); 1658 } 1659 1660 power_limit = power_limit > MAX_POWER_INDEX ? 1661 MAX_POWER_INDEX : power_limit; 1662 1663 if (_rtl8812ae_eq_n_byte(pregulation, "FCC", 3)) 1664 regulation = 0; 1665 else if (_rtl8812ae_eq_n_byte(pregulation, "MKK", 3)) 1666 regulation = 1; 1667 else if (_rtl8812ae_eq_n_byte(pregulation, "ETSI", 4)) 1668 regulation = 2; 1669 else if (_rtl8812ae_eq_n_byte(pregulation, "WW13", 4)) 1670 regulation = 3; 1671 1672 if (_rtl8812ae_eq_n_byte(prate_section, "CCK", 3)) 1673 rate_section = 0; 1674 else if (_rtl8812ae_eq_n_byte(prate_section, "OFDM", 4)) 1675 rate_section = 1; 1676 else if (_rtl8812ae_eq_n_byte(prate_section, "HT", 2) && 1677 _rtl8812ae_eq_n_byte(prf_path, "1T", 2)) 1678 rate_section = 2; 1679 else if (_rtl8812ae_eq_n_byte(prate_section, "HT", 2) && 1680 _rtl8812ae_eq_n_byte(prf_path, "2T", 2)) 1681 rate_section = 3; 1682 else if (_rtl8812ae_eq_n_byte(prate_section, "VHT", 3) && 1683 _rtl8812ae_eq_n_byte(prf_path, "1T", 2)) 1684 rate_section = 4; 1685 else if (_rtl8812ae_eq_n_byte(prate_section, "VHT", 3) && 1686 _rtl8812ae_eq_n_byte(prf_path, "2T", 2)) 1687 rate_section = 5; 1688 1689 if (_rtl8812ae_eq_n_byte(pbandwidth, "20M", 3)) 1690 bandwidth = 0; 1691 else if (_rtl8812ae_eq_n_byte(pbandwidth, "40M", 3)) 1692 bandwidth = 1; 1693 else if (_rtl8812ae_eq_n_byte(pbandwidth, "80M", 3)) 1694 bandwidth = 2; 1695 else if (_rtl8812ae_eq_n_byte(pbandwidth, "160M", 4)) 1696 bandwidth = 3; 1697 1698 if (_rtl8812ae_eq_n_byte(pband, "2.4G", 4)) { 1699 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 1700 BAND_ON_2_4G, 1701 channel); 1702 1703 if (ret == -1) 1704 return; 1705 1706 channel_index = ret; 1707 1708 prev_power_limit = rtlphy->txpwr_limit_2_4g[regulation] 1709 [bandwidth][rate_section] 1710 [channel_index][RF90_PATH_A]; 1711 1712 if (power_limit < prev_power_limit) 1713 rtlphy->txpwr_limit_2_4g[regulation][bandwidth] 1714 [rate_section][channel_index][RF90_PATH_A] = 1715 power_limit; 1716 1717 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1718 "2.4G [regula %d][bw %d][sec %d][chnl %d][val %d]\n", 1719 regulation, bandwidth, rate_section, channel_index, 1720 rtlphy->txpwr_limit_2_4g[regulation][bandwidth] 1721 [rate_section][channel_index][RF90_PATH_A]); 1722 } else if (_rtl8812ae_eq_n_byte(pband, "5G", 2)) { 1723 ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 1724 BAND_ON_5G, 1725 channel); 1726 1727 if (ret == -1) 1728 return; 1729 1730 channel_index = ret; 1731 1732 prev_power_limit = rtlphy->txpwr_limit_5g[regulation][bandwidth] 1733 [rate_section][channel_index] 1734 [RF90_PATH_A]; 1735 1736 if (power_limit < prev_power_limit) 1737 rtlphy->txpwr_limit_5g[regulation][bandwidth] 1738 [rate_section][channel_index][RF90_PATH_A] = power_limit; 1739 1740 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1741 "5G: [regul %d][bw %d][sec %d][chnl %d][val %d]\n", 1742 regulation, bandwidth, rate_section, channel, 1743 rtlphy->txpwr_limit_5g[regulation][bandwidth] 1744 [rate_section][channel_index][RF90_PATH_A]); 1745 } else { 1746 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1747 "Cannot recognize the band info in %s\n", pband); 1748 return; 1749 } 1750 } 1751 1752 static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw, 1753 const char *regulation, const char *band, 1754 const char *bandwidth, const char *rate_section, 1755 const char *rf_path, const char *channel, 1756 const char *power_limit) 1757 { 1758 _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth, 1759 rate_section, rf_path, channel, 1760 power_limit); 1761 } 1762 1763 static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) 1764 { 1765 struct rtl_priv *rtlpriv = rtl_priv(hw); 1766 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1767 u32 i = 0; 1768 u32 array_len; 1769 const char **array; 1770 1771 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1772 array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN; 1773 array = RTL8812AE_TXPWR_LMT; 1774 } else { 1775 array_len = RTL8821AE_TXPWR_LMT_ARRAY_LEN; 1776 array = RTL8821AE_TXPWR_LMT; 1777 } 1778 1779 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "\n"); 1780 1781 for (i = 0; i < array_len; i += 7) { 1782 const char *regulation = array[i]; 1783 const char *band = array[i+1]; 1784 const char *bandwidth = array[i+2]; 1785 const char *rate = array[i+3]; 1786 const char *rf_path = array[i+4]; 1787 const char *chnl = array[i+5]; 1788 const char *val = array[i+6]; 1789 1790 _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band, 1791 bandwidth, rate, rf_path, 1792 chnl, val); 1793 } 1794 } 1795 1796 static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw) 1797 { 1798 struct rtl_priv *rtlpriv = rtl_priv(hw); 1799 struct rtl_phy *rtlphy = &rtlpriv->phy; 1800 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1801 bool rtstatus; 1802 1803 _rtl8821ae_phy_init_txpower_limit(hw); 1804 1805 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */ 1806 if (rtlefuse->eeprom_regulatory != 2) 1807 _rtl8821ae_phy_read_and_config_txpwr_lmt(hw); 1808 1809 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw, 1810 BASEBAND_CONFIG_PHY_REG); 1811 if (!rtstatus) { 1812 pr_err("Write BB Reg Fail!!\n"); 1813 return false; 1814 } 1815 _rtl8821ae_phy_init_tx_power_by_rate(hw); 1816 if (rtlefuse->autoload_failflag == false) { 1817 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw, 1818 BASEBAND_CONFIG_PHY_REG); 1819 } 1820 if (!rtstatus) { 1821 pr_err("BB_PG Reg Fail!!\n"); 1822 return false; 1823 } 1824 1825 _rtl8821ae_phy_txpower_by_rate_configuration(hw); 1826 1827 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */ 1828 if (rtlefuse->eeprom_regulatory != 2) 1829 _rtl8812ae_phy_convert_txpower_limit_to_power_index(hw); 1830 1831 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw, 1832 BASEBAND_CONFIG_AGC_TAB); 1833 1834 if (!rtstatus) { 1835 pr_err("AGC Table Fail\n"); 1836 return false; 1837 } 1838 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, 1839 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 1840 return true; 1841 } 1842 1843 static bool 1844 __rtl8821ae_phy_config_with_headerfile(struct ieee80211_hw *hw, 1845 u32 *array_table, u16 arraylen, 1846 void (*set_reg)(struct ieee80211_hw *hw, 1847 u32 regaddr, u32 data)) 1848 { 1849 #define COND_ELSE 2 1850 #define COND_ENDIF 3 1851 1852 int i = 0; 1853 u8 cond; 1854 bool matched = true, skipped = false; 1855 1856 while ((i + 1) < arraylen) { 1857 u32 v1 = array_table[i]; 1858 u32 v2 = array_table[i + 1]; 1859 1860 if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ 1861 if (v1 & BIT(31)) {/* positive condition*/ 1862 cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); 1863 if (cond == COND_ENDIF) {/*end*/ 1864 matched = true; 1865 skipped = false; 1866 } else if (cond == COND_ELSE) /*else*/ 1867 matched = skipped ? false : true; 1868 else {/*if , else if*/ 1869 if (skipped) { 1870 matched = false; 1871 } else { 1872 if (_rtl8821ae_check_positive( 1873 hw, v1, v2)) { 1874 matched = true; 1875 skipped = true; 1876 } else { 1877 matched = false; 1878 skipped = false; 1879 } 1880 } 1881 } 1882 } else if (v1 & BIT(30)) { /*negative condition*/ 1883 /*do nothing*/ 1884 } 1885 } else { 1886 if (matched) 1887 set_reg(hw, v1, v2); 1888 } 1889 i = i + 2; 1890 } 1891 1892 return true; 1893 } 1894 1895 static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 1896 { 1897 struct rtl_priv *rtlpriv = rtl_priv(hw); 1898 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1899 u32 arraylength; 1900 u32 *ptrarray; 1901 1902 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read MAC_REG_Array\n"); 1903 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1904 arraylength = RTL8821AE_MAC_1T_ARRAYLEN; 1905 ptrarray = RTL8821AE_MAC_REG_ARRAY; 1906 } else { 1907 arraylength = RTL8812AE_MAC_1T_ARRAYLEN; 1908 ptrarray = RTL8812AE_MAC_REG_ARRAY; 1909 } 1910 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1911 "Img: MAC_REG_ARRAY LEN %d\n", arraylength); 1912 1913 return __rtl8821ae_phy_config_with_headerfile(hw, 1914 ptrarray, arraylength, rtl_write_byte_with_val32); 1915 } 1916 1917 static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 1918 u8 configtype) 1919 { 1920 struct rtl_priv *rtlpriv = rtl_priv(hw); 1921 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1922 u32 *array_table; 1923 u16 arraylen; 1924 1925 if (configtype == BASEBAND_CONFIG_PHY_REG) { 1926 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1927 arraylen = RTL8812AE_PHY_REG_1TARRAYLEN; 1928 array_table = RTL8812AE_PHY_REG_ARRAY; 1929 } else { 1930 arraylen = RTL8821AE_PHY_REG_1TARRAYLEN; 1931 array_table = RTL8821AE_PHY_REG_ARRAY; 1932 } 1933 1934 return __rtl8821ae_phy_config_with_headerfile(hw, 1935 array_table, arraylen, 1936 _rtl8821ae_config_bb_reg); 1937 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 1938 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1939 arraylen = RTL8812AE_AGC_TAB_1TARRAYLEN; 1940 array_table = RTL8812AE_AGC_TAB_ARRAY; 1941 } else { 1942 arraylen = RTL8821AE_AGC_TAB_1TARRAYLEN; 1943 array_table = RTL8821AE_AGC_TAB_ARRAY; 1944 } 1945 1946 return __rtl8821ae_phy_config_with_headerfile(hw, 1947 array_table, arraylen, 1948 rtl_set_bbreg_with_dwmask); 1949 } 1950 return true; 1951 } 1952 1953 static u8 _rtl8821ae_get_rate_section_index(u32 regaddr) 1954 { 1955 u8 index = 0; 1956 regaddr &= 0xFFF; 1957 if (regaddr >= 0xC20 && regaddr <= 0xC4C) 1958 index = (u8)((regaddr - 0xC20) / 4); 1959 else if (regaddr >= 0xE20 && regaddr <= 0xE4C) 1960 index = (u8)((regaddr - 0xE20) / 4); 1961 else 1962 WARN_ONCE(true, 1963 "rtl8821ae: Invalid RegAddr 0x%x\n", regaddr); 1964 return index; 1965 } 1966 1967 static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw, 1968 u32 band, u32 rfpath, 1969 u32 txnum, u32 regaddr, 1970 u32 bitmask, u32 data) 1971 { 1972 struct rtl_priv *rtlpriv = rtl_priv(hw); 1973 struct rtl_phy *rtlphy = &rtlpriv->phy; 1974 u8 rate_section = _rtl8821ae_get_rate_section_index(regaddr); 1975 1976 if (band != BAND_ON_2_4G && band != BAND_ON_5G) { 1977 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid Band %d\n", band); 1978 band = BAND_ON_2_4G; 1979 } 1980 if (rfpath >= MAX_RF_PATH) { 1981 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid RfPath %d\n", rfpath); 1982 rfpath = MAX_RF_PATH - 1; 1983 } 1984 if (txnum >= MAX_RF_PATH) { 1985 rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING, "Invalid TxNum %d\n", txnum); 1986 txnum = MAX_RF_PATH - 1; 1987 } 1988 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data; 1989 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1990 "TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n", 1991 band, rfpath, txnum, rate_section, 1992 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]); 1993 } 1994 1995 static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 1996 u8 configtype) 1997 { 1998 struct rtl_priv *rtlpriv = rtl_priv(hw); 1999 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2000 int i; 2001 u32 *array; 2002 u16 arraylen; 2003 u32 v1, v2, v3, v4, v5, v6; 2004 2005 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2006 arraylen = RTL8812AE_PHY_REG_ARRAY_PGLEN; 2007 array = RTL8812AE_PHY_REG_ARRAY_PG; 2008 } else { 2009 arraylen = RTL8821AE_PHY_REG_ARRAY_PGLEN; 2010 array = RTL8821AE_PHY_REG_ARRAY_PG; 2011 } 2012 2013 if (configtype != BASEBAND_CONFIG_PHY_REG) { 2014 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, 2015 "configtype != BaseBand_Config_PHY_REG\n"); 2016 return true; 2017 } 2018 for (i = 0; i < arraylen; i += 6) { 2019 v1 = array[i]; 2020 v2 = array[i+1]; 2021 v3 = array[i+2]; 2022 v4 = array[i+3]; 2023 v5 = array[i+4]; 2024 v6 = array[i+5]; 2025 2026 if (v1 < 0xCDCDCDCD) { 2027 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 2028 (v4 == 0xfe || v4 == 0xffe)) { 2029 msleep(50); 2030 continue; 2031 } 2032 2033 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2034 if (v4 == 0xfe) 2035 msleep(50); 2036 else if (v4 == 0xfd) 2037 mdelay(5); 2038 else if (v4 == 0xfc) 2039 mdelay(1); 2040 else if (v4 == 0xfb) 2041 udelay(50); 2042 else if (v4 == 0xfa) 2043 udelay(5); 2044 else if (v4 == 0xf9) 2045 udelay(1); 2046 } 2047 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, 2048 v4, v5, v6); 2049 continue; 2050 } else { 2051 /*don't need the hw_body*/ 2052 if (!_rtl8821ae_check_condition(hw, v1)) { 2053 i += 2; /* skip the pair of expression*/ 2054 v1 = array[i]; 2055 v2 = array[i+1]; 2056 v3 = array[i+2]; 2057 while (v2 != 0xDEAD) { 2058 i += 3; 2059 v1 = array[i]; 2060 v2 = array[i+1]; 2061 v3 = array[i+2]; 2062 } 2063 } 2064 } 2065 } 2066 2067 return true; 2068 } 2069 2070 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 2071 enum radio_path rfpath) 2072 { 2073 u32 *radioa_array_table_a, *radioa_array_table_b; 2074 u16 radioa_arraylen_a, radioa_arraylen_b; 2075 struct rtl_priv *rtlpriv = rtl_priv(hw); 2076 2077 radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN; 2078 radioa_array_table_a = RTL8812AE_RADIOA_ARRAY; 2079 radioa_arraylen_b = RTL8812AE_RADIOB_1TARRAYLEN; 2080 radioa_array_table_b = RTL8812AE_RADIOB_ARRAY; 2081 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2082 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen_a); 2083 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 2084 switch (rfpath) { 2085 case RF90_PATH_A: 2086 return __rtl8821ae_phy_config_with_headerfile(hw, 2087 radioa_array_table_a, radioa_arraylen_a, 2088 _rtl8821ae_config_rf_radio_a); 2089 case RF90_PATH_B: 2090 return __rtl8821ae_phy_config_with_headerfile(hw, 2091 radioa_array_table_b, radioa_arraylen_b, 2092 _rtl8821ae_config_rf_radio_b); 2093 case RF90_PATH_C: 2094 case RF90_PATH_D: 2095 pr_err("switch case %#x not processed\n", rfpath); 2096 break; 2097 } 2098 return true; 2099 } 2100 2101 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 2102 enum radio_path rfpath) 2103 { 2104 u32 *radioa_array_table; 2105 u16 radioa_arraylen; 2106 struct rtl_priv *rtlpriv = rtl_priv(hw); 2107 2108 radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN; 2109 radioa_array_table = RTL8821AE_RADIOA_ARRAY; 2110 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2111 "Radio_A:RTL8821AE_RADIOA_ARRAY %d\n", radioa_arraylen); 2112 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 2113 switch (rfpath) { 2114 case RF90_PATH_A: 2115 return __rtl8821ae_phy_config_with_headerfile(hw, 2116 radioa_array_table, radioa_arraylen, 2117 _rtl8821ae_config_rf_radio_a); 2118 2119 case RF90_PATH_B: 2120 case RF90_PATH_C: 2121 case RF90_PATH_D: 2122 pr_err("switch case %#x not processed\n", rfpath); 2123 break; 2124 } 2125 return true; 2126 } 2127 2128 void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 2129 { 2130 struct rtl_priv *rtlpriv = rtl_priv(hw); 2131 struct rtl_phy *rtlphy = &rtlpriv->phy; 2132 2133 rtlphy->default_initialgain[0] = 2134 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 2135 rtlphy->default_initialgain[1] = 2136 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 2137 rtlphy->default_initialgain[2] = 2138 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 2139 rtlphy->default_initialgain[3] = 2140 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 2141 2142 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2143 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 2144 rtlphy->default_initialgain[0], 2145 rtlphy->default_initialgain[1], 2146 rtlphy->default_initialgain[2], 2147 rtlphy->default_initialgain[3]); 2148 2149 rtlphy->framesync = (u8)rtl_get_bbreg(hw, 2150 ROFDM0_RXDETECTOR3, MASKBYTE0); 2151 rtlphy->framesync_c34 = rtl_get_bbreg(hw, 2152 ROFDM0_RXDETECTOR2, MASKDWORD); 2153 2154 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 2155 "Default framesync (0x%x) = 0x%x\n", 2156 ROFDM0_RXDETECTOR3, rtlphy->framesync); 2157 } 2158 2159 static void phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 2160 { 2161 struct rtl_priv *rtlpriv = rtl_priv(hw); 2162 struct rtl_phy *rtlphy = &rtlpriv->phy; 2163 2164 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 2165 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 2166 2167 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 2168 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 2169 2170 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 2171 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 2172 2173 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A; 2174 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A; 2175 2176 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE; 2177 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE; 2178 2179 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A; 2180 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A; 2181 2182 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A; 2183 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A; 2184 } 2185 2186 void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 2187 { 2188 struct rtl_priv *rtlpriv = rtl_priv(hw); 2189 struct rtl_phy *rtlphy = &rtlpriv->phy; 2190 u8 txpwr_level; 2191 long txpwr_dbm; 2192 2193 txpwr_level = rtlphy->cur_cck_txpwridx; 2194 txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw, 2195 WIRELESS_MODE_B, txpwr_level); 2196 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 2197 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw, 2198 WIRELESS_MODE_G, 2199 txpwr_level) > txpwr_dbm) 2200 txpwr_dbm = 2201 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 2202 txpwr_level); 2203 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 2204 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw, 2205 WIRELESS_MODE_N_24G, 2206 txpwr_level) > txpwr_dbm) 2207 txpwr_dbm = 2208 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 2209 txpwr_level); 2210 *powerlevel = txpwr_dbm; 2211 } 2212 2213 static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index) 2214 { 2215 u8 i = 0; 2216 bool in_24g = true; 2217 2218 if (channel <= 14) { 2219 in_24g = true; 2220 *chnl_index = channel - 1; 2221 } else { 2222 in_24g = false; 2223 2224 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; ++i) { 2225 if (channel5g[i] == channel) { 2226 *chnl_index = i; 2227 return in_24g; 2228 } 2229 } 2230 } 2231 return in_24g; 2232 } 2233 2234 static s8 _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate) 2235 { 2236 s8 rate_section = 0; 2237 switch (rate) { 2238 case DESC_RATE1M: 2239 case DESC_RATE2M: 2240 case DESC_RATE5_5M: 2241 case DESC_RATE11M: 2242 rate_section = 0; 2243 break; 2244 case DESC_RATE6M: 2245 case DESC_RATE9M: 2246 case DESC_RATE12M: 2247 case DESC_RATE18M: 2248 rate_section = 1; 2249 break; 2250 case DESC_RATE24M: 2251 case DESC_RATE36M: 2252 case DESC_RATE48M: 2253 case DESC_RATE54M: 2254 rate_section = 2; 2255 break; 2256 case DESC_RATEMCS0: 2257 case DESC_RATEMCS1: 2258 case DESC_RATEMCS2: 2259 case DESC_RATEMCS3: 2260 rate_section = 3; 2261 break; 2262 case DESC_RATEMCS4: 2263 case DESC_RATEMCS5: 2264 case DESC_RATEMCS6: 2265 case DESC_RATEMCS7: 2266 rate_section = 4; 2267 break; 2268 case DESC_RATEMCS8: 2269 case DESC_RATEMCS9: 2270 case DESC_RATEMCS10: 2271 case DESC_RATEMCS11: 2272 rate_section = 5; 2273 break; 2274 case DESC_RATEMCS12: 2275 case DESC_RATEMCS13: 2276 case DESC_RATEMCS14: 2277 case DESC_RATEMCS15: 2278 rate_section = 6; 2279 break; 2280 case DESC_RATEVHT1SS_MCS0: 2281 case DESC_RATEVHT1SS_MCS1: 2282 case DESC_RATEVHT1SS_MCS2: 2283 case DESC_RATEVHT1SS_MCS3: 2284 rate_section = 7; 2285 break; 2286 case DESC_RATEVHT1SS_MCS4: 2287 case DESC_RATEVHT1SS_MCS5: 2288 case DESC_RATEVHT1SS_MCS6: 2289 case DESC_RATEVHT1SS_MCS7: 2290 rate_section = 8; 2291 break; 2292 case DESC_RATEVHT1SS_MCS8: 2293 case DESC_RATEVHT1SS_MCS9: 2294 case DESC_RATEVHT2SS_MCS0: 2295 case DESC_RATEVHT2SS_MCS1: 2296 rate_section = 9; 2297 break; 2298 case DESC_RATEVHT2SS_MCS2: 2299 case DESC_RATEVHT2SS_MCS3: 2300 case DESC_RATEVHT2SS_MCS4: 2301 case DESC_RATEVHT2SS_MCS5: 2302 rate_section = 10; 2303 break; 2304 case DESC_RATEVHT2SS_MCS6: 2305 case DESC_RATEVHT2SS_MCS7: 2306 case DESC_RATEVHT2SS_MCS8: 2307 case DESC_RATEVHT2SS_MCS9: 2308 rate_section = 11; 2309 break; 2310 default: 2311 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n"); 2312 break; 2313 } 2314 2315 return rate_section; 2316 } 2317 2318 static s8 _rtl8812ae_phy_get_world_wide_limit(s8 *limit_table) 2319 { 2320 s8 min = limit_table[0]; 2321 u8 i = 0; 2322 2323 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 2324 if (limit_table[i] < min) 2325 min = limit_table[i]; 2326 } 2327 return min; 2328 } 2329 2330 static s8 _rtl8812ae_phy_get_txpower_limit(struct ieee80211_hw *hw, 2331 u8 band, 2332 enum ht_channel_width bandwidth, 2333 enum radio_path rf_path, 2334 u8 rate, u8 channel) 2335 { 2336 struct rtl_priv *rtlpriv = rtl_priv(hw); 2337 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 2338 struct rtl_phy *rtlphy = &rtlpriv->phy; 2339 short band_temp = -1, regulation = -1, bandwidth_temp = -1, 2340 rate_section = -1, channel_temp = -1; 2341 u16 regu, bdwidth, sec, chnl; 2342 s8 power_limit = MAX_POWER_INDEX; 2343 2344 if (rtlefuse->eeprom_regulatory == 2) 2345 return MAX_POWER_INDEX; 2346 2347 regulation = TXPWR_LMT_WW; 2348 2349 if (band == BAND_ON_2_4G) 2350 band_temp = 0; 2351 else if (band == BAND_ON_5G) 2352 band_temp = 1; 2353 2354 if (bandwidth == HT_CHANNEL_WIDTH_20) 2355 bandwidth_temp = 0; 2356 else if (bandwidth == HT_CHANNEL_WIDTH_20_40) 2357 bandwidth_temp = 1; 2358 else if (bandwidth == HT_CHANNEL_WIDTH_80) 2359 bandwidth_temp = 2; 2360 2361 switch (rate) { 2362 case DESC_RATE1M: 2363 case DESC_RATE2M: 2364 case DESC_RATE5_5M: 2365 case DESC_RATE11M: 2366 rate_section = 0; 2367 break; 2368 case DESC_RATE6M: 2369 case DESC_RATE9M: 2370 case DESC_RATE12M: 2371 case DESC_RATE18M: 2372 case DESC_RATE24M: 2373 case DESC_RATE36M: 2374 case DESC_RATE48M: 2375 case DESC_RATE54M: 2376 rate_section = 1; 2377 break; 2378 case DESC_RATEMCS0: 2379 case DESC_RATEMCS1: 2380 case DESC_RATEMCS2: 2381 case DESC_RATEMCS3: 2382 case DESC_RATEMCS4: 2383 case DESC_RATEMCS5: 2384 case DESC_RATEMCS6: 2385 case DESC_RATEMCS7: 2386 rate_section = 2; 2387 break; 2388 case DESC_RATEMCS8: 2389 case DESC_RATEMCS9: 2390 case DESC_RATEMCS10: 2391 case DESC_RATEMCS11: 2392 case DESC_RATEMCS12: 2393 case DESC_RATEMCS13: 2394 case DESC_RATEMCS14: 2395 case DESC_RATEMCS15: 2396 rate_section = 3; 2397 break; 2398 case DESC_RATEVHT1SS_MCS0: 2399 case DESC_RATEVHT1SS_MCS1: 2400 case DESC_RATEVHT1SS_MCS2: 2401 case DESC_RATEVHT1SS_MCS3: 2402 case DESC_RATEVHT1SS_MCS4: 2403 case DESC_RATEVHT1SS_MCS5: 2404 case DESC_RATEVHT1SS_MCS6: 2405 case DESC_RATEVHT1SS_MCS7: 2406 case DESC_RATEVHT1SS_MCS8: 2407 case DESC_RATEVHT1SS_MCS9: 2408 rate_section = 4; 2409 break; 2410 case DESC_RATEVHT2SS_MCS0: 2411 case DESC_RATEVHT2SS_MCS1: 2412 case DESC_RATEVHT2SS_MCS2: 2413 case DESC_RATEVHT2SS_MCS3: 2414 case DESC_RATEVHT2SS_MCS4: 2415 case DESC_RATEVHT2SS_MCS5: 2416 case DESC_RATEVHT2SS_MCS6: 2417 case DESC_RATEVHT2SS_MCS7: 2418 case DESC_RATEVHT2SS_MCS8: 2419 case DESC_RATEVHT2SS_MCS9: 2420 rate_section = 5; 2421 break; 2422 default: 2423 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2424 "Wrong rate 0x%x\n", rate); 2425 break; 2426 } 2427 2428 if (band_temp == BAND_ON_5G && rate_section == 0) 2429 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2430 "Wrong rate 0x%x: No CCK in 5G Band\n", rate); 2431 2432 /*workaround for wrong index combination to obtain tx power limit, 2433 OFDM only exists in BW 20M*/ 2434 if (rate_section == 1) 2435 bandwidth_temp = 0; 2436 2437 /*workaround for wrong index combination to obtain tx power limit, 2438 *HT on 80M will reference to HT on 40M 2439 */ 2440 if ((rate_section == 2 || rate_section == 3) && band == BAND_ON_5G && 2441 bandwidth_temp == 2) 2442 bandwidth_temp = 1; 2443 2444 if (band == BAND_ON_2_4G) 2445 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 2446 BAND_ON_2_4G, channel); 2447 else if (band == BAND_ON_5G) 2448 channel_temp = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, 2449 BAND_ON_5G, channel); 2450 else if (band == BAND_ON_BOTH) 2451 ;/* BAND_ON_BOTH don't care temporarily */ 2452 2453 if (band_temp == -1 || regulation == -1 || bandwidth_temp == -1 || 2454 rate_section == -1 || channel_temp == -1) { 2455 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2456 "Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnl %d]\n", 2457 band_temp, regulation, bandwidth_temp, rf_path, 2458 rate_section, channel_temp); 2459 return MAX_POWER_INDEX; 2460 } 2461 2462 regu = regulation; 2463 bdwidth = bandwidth_temp; 2464 sec = rate_section; 2465 chnl = channel_temp; 2466 2467 if (band == BAND_ON_2_4G) { 2468 s8 limits[10] = {0}; 2469 u8 i; 2470 2471 for (i = 0; i < 4; ++i) 2472 limits[i] = rtlphy->txpwr_limit_2_4g[i][bdwidth] 2473 [sec][chnl][rf_path]; 2474 2475 power_limit = (regulation == TXPWR_LMT_WW) ? 2476 _rtl8812ae_phy_get_world_wide_limit(limits) : 2477 rtlphy->txpwr_limit_2_4g[regu][bdwidth] 2478 [sec][chnl][rf_path]; 2479 } else if (band == BAND_ON_5G) { 2480 s8 limits[10] = {0}; 2481 u8 i; 2482 2483 for (i = 0; i < MAX_REGULATION_NUM; ++i) 2484 limits[i] = rtlphy->txpwr_limit_5g[i][bdwidth] 2485 [sec][chnl][rf_path]; 2486 2487 power_limit = (regulation == TXPWR_LMT_WW) ? 2488 _rtl8812ae_phy_get_world_wide_limit(limits) : 2489 rtlphy->txpwr_limit_5g[regu][chnl] 2490 [sec][chnl][rf_path]; 2491 } else { 2492 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 2493 "No power limit table of the specified band\n"); 2494 } 2495 return power_limit; 2496 } 2497 2498 static s8 _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw, 2499 u8 band, u8 path, u8 rate) 2500 { 2501 struct rtl_priv *rtlpriv = rtl_priv(hw); 2502 struct rtl_phy *rtlphy = &rtlpriv->phy; 2503 u8 shift = 0, rate_section, tx_num; 2504 s8 tx_pwr_diff = 0; 2505 s8 limit = 0; 2506 2507 rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate); 2508 tx_num = RF_TX_NUM_NONIMPLEMENT; 2509 2510 if (tx_num == RF_TX_NUM_NONIMPLEMENT) { 2511 if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) || 2512 (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9)) 2513 tx_num = RF_2TX; 2514 else 2515 tx_num = RF_1TX; 2516 } 2517 2518 switch (rate) { 2519 case DESC_RATE1M: 2520 case DESC_RATE6M: 2521 case DESC_RATE24M: 2522 case DESC_RATEMCS0: 2523 case DESC_RATEMCS4: 2524 case DESC_RATEMCS8: 2525 case DESC_RATEMCS12: 2526 case DESC_RATEVHT1SS_MCS0: 2527 case DESC_RATEVHT1SS_MCS4: 2528 case DESC_RATEVHT1SS_MCS8: 2529 case DESC_RATEVHT2SS_MCS2: 2530 case DESC_RATEVHT2SS_MCS6: 2531 shift = 0; 2532 break; 2533 case DESC_RATE2M: 2534 case DESC_RATE9M: 2535 case DESC_RATE36M: 2536 case DESC_RATEMCS1: 2537 case DESC_RATEMCS5: 2538 case DESC_RATEMCS9: 2539 case DESC_RATEMCS13: 2540 case DESC_RATEVHT1SS_MCS1: 2541 case DESC_RATEVHT1SS_MCS5: 2542 case DESC_RATEVHT1SS_MCS9: 2543 case DESC_RATEVHT2SS_MCS3: 2544 case DESC_RATEVHT2SS_MCS7: 2545 shift = 8; 2546 break; 2547 case DESC_RATE5_5M: 2548 case DESC_RATE12M: 2549 case DESC_RATE48M: 2550 case DESC_RATEMCS2: 2551 case DESC_RATEMCS6: 2552 case DESC_RATEMCS10: 2553 case DESC_RATEMCS14: 2554 case DESC_RATEVHT1SS_MCS2: 2555 case DESC_RATEVHT1SS_MCS6: 2556 case DESC_RATEVHT2SS_MCS0: 2557 case DESC_RATEVHT2SS_MCS4: 2558 case DESC_RATEVHT2SS_MCS8: 2559 shift = 16; 2560 break; 2561 case DESC_RATE11M: 2562 case DESC_RATE18M: 2563 case DESC_RATE54M: 2564 case DESC_RATEMCS3: 2565 case DESC_RATEMCS7: 2566 case DESC_RATEMCS11: 2567 case DESC_RATEMCS15: 2568 case DESC_RATEVHT1SS_MCS3: 2569 case DESC_RATEVHT1SS_MCS7: 2570 case DESC_RATEVHT2SS_MCS1: 2571 case DESC_RATEVHT2SS_MCS5: 2572 case DESC_RATEVHT2SS_MCS9: 2573 shift = 24; 2574 break; 2575 default: 2576 WARN_ONCE(true, "rtl8821ae: Rate_Section is Illegal\n"); 2577 break; 2578 } 2579 2580 tx_pwr_diff = (u8)(rtlphy->tx_power_by_rate_offset[band][path] 2581 [tx_num][rate_section] >> shift) & 0xff; 2582 2583 /* RegEnableTxPowerLimit == 1 for 8812a & 8821a */ 2584 if (rtlpriv->efuse.eeprom_regulatory != 2) { 2585 limit = _rtl8812ae_phy_get_txpower_limit(hw, band, 2586 rtlphy->current_chan_bw, path, rate, 2587 rtlphy->current_channel); 2588 2589 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 || 2590 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) { 2591 if (limit < 0) { 2592 if (tx_pwr_diff < (-limit)) 2593 tx_pwr_diff = -limit; 2594 } 2595 } else { 2596 if (limit < 0) 2597 tx_pwr_diff = limit; 2598 else 2599 tx_pwr_diff = tx_pwr_diff > limit ? limit : tx_pwr_diff; 2600 } 2601 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 2602 "Maximum power by rate %d, final power by rate %d\n", 2603 limit, tx_pwr_diff); 2604 } 2605 2606 return tx_pwr_diff; 2607 } 2608 2609 static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path, 2610 u8 rate, u8 bandwidth, u8 channel) 2611 { 2612 struct rtl_priv *rtlpriv = rtl_priv(hw); 2613 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2614 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2615 u8 index = (channel - 1); 2616 u8 txpower = 0; 2617 bool in_24g = false; 2618 s8 powerdiff_byrate = 0; 2619 2620 if (((rtlhal->current_bandtype == BAND_ON_2_4G) && 2621 (channel > 14 || channel < 1)) || 2622 ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) { 2623 index = 0; 2624 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 2625 "Illegal channel!!\n"); 2626 } 2627 2628 in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index); 2629 if (in_24g) { 2630 if (RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) 2631 txpower = rtlefuse->txpwrlevel_cck[path][index]; 2632 else if (DESC_RATE6M <= rate) 2633 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index]; 2634 else 2635 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "invalid rate\n"); 2636 2637 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && 2638 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) 2639 txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S]; 2640 2641 if (bandwidth == HT_CHANNEL_WIDTH_20) { 2642 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2643 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2644 txpower += rtlefuse->txpwr_ht20diff[path][TX_1S]; 2645 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2646 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2647 txpower += rtlefuse->txpwr_ht20diff[path][TX_2S]; 2648 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) { 2649 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2650 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2651 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S]; 2652 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2653 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9)) 2654 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S]; 2655 } else if (bandwidth == HT_CHANNEL_WIDTH_80) { 2656 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2657 (DESC_RATEVHT1SS_MCS0 <= rate && 2658 rate <= DESC_RATEVHT2SS_MCS9)) 2659 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S]; 2660 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2661 (DESC_RATEVHT2SS_MCS0 <= rate && 2662 rate <= DESC_RATEVHT2SS_MCS9)) 2663 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S]; 2664 } 2665 } else { 2666 if (DESC_RATE6M <= rate) 2667 txpower = rtlefuse->txpwr_5g_bw40base[path][index]; 2668 else 2669 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_WARNING, 2670 "INVALID Rate.\n"); 2671 2672 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && 2673 !RTL8821AE_RX_HAL_IS_CCK_RATE(rate)) 2674 txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S]; 2675 2676 if (bandwidth == HT_CHANNEL_WIDTH_20) { 2677 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2678 (DESC_RATEVHT1SS_MCS0 <= rate && 2679 rate <= DESC_RATEVHT2SS_MCS9)) 2680 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S]; 2681 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2682 (DESC_RATEVHT2SS_MCS0 <= rate && 2683 rate <= DESC_RATEVHT2SS_MCS9)) 2684 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S]; 2685 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) { 2686 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2687 (DESC_RATEVHT1SS_MCS0 <= rate && 2688 rate <= DESC_RATEVHT2SS_MCS9)) 2689 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S]; 2690 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2691 (DESC_RATEVHT2SS_MCS0 <= rate && 2692 rate <= DESC_RATEVHT2SS_MCS9)) 2693 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S]; 2694 } else if (bandwidth == HT_CHANNEL_WIDTH_80) { 2695 u8 i; 2696 2697 for (i = 0; i < sizeof(channel5g_80m) / sizeof(u8); ++i) 2698 if (channel5g_80m[i] == channel) 2699 index = i; 2700 2701 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) || 2702 (DESC_RATEVHT1SS_MCS0 <= rate && 2703 rate <= DESC_RATEVHT2SS_MCS9)) 2704 txpower = rtlefuse->txpwr_5g_bw80base[path][index] 2705 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]; 2706 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) || 2707 (DESC_RATEVHT2SS_MCS0 <= rate && 2708 rate <= DESC_RATEVHT2SS_MCS9)) 2709 txpower = rtlefuse->txpwr_5g_bw80base[path][index] 2710 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S] 2711 + rtlefuse->txpwr_5g_bw80diff[path][TX_2S]; 2712 } 2713 } 2714 if (rtlefuse->eeprom_regulatory != 2) 2715 powerdiff_byrate = 2716 _rtl8821ae_phy_get_txpower_by_rate(hw, (u8)(!in_24g), 2717 path, rate); 2718 2719 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 || 2720 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9) 2721 txpower -= powerdiff_byrate; 2722 else 2723 txpower += powerdiff_byrate; 2724 2725 if (rate > DESC_RATE11M) 2726 txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path]; 2727 else 2728 txpower += rtlpriv->dm.remnant_cck_idx; 2729 2730 if (txpower > MAX_POWER_INDEX) 2731 txpower = MAX_POWER_INDEX; 2732 2733 return txpower; 2734 } 2735 2736 static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw, 2737 u8 power_index, u8 path, u8 rate) 2738 { 2739 struct rtl_priv *rtlpriv = rtl_priv(hw); 2740 2741 if (path == RF90_PATH_A) { 2742 switch (rate) { 2743 case DESC_RATE1M: 2744 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2745 MASKBYTE0, power_index); 2746 break; 2747 case DESC_RATE2M: 2748 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2749 MASKBYTE1, power_index); 2750 break; 2751 case DESC_RATE5_5M: 2752 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2753 MASKBYTE2, power_index); 2754 break; 2755 case DESC_RATE11M: 2756 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, 2757 MASKBYTE3, power_index); 2758 break; 2759 case DESC_RATE6M: 2760 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2761 MASKBYTE0, power_index); 2762 break; 2763 case DESC_RATE9M: 2764 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2765 MASKBYTE1, power_index); 2766 break; 2767 case DESC_RATE12M: 2768 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2769 MASKBYTE2, power_index); 2770 break; 2771 case DESC_RATE18M: 2772 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, 2773 MASKBYTE3, power_index); 2774 break; 2775 case DESC_RATE24M: 2776 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2777 MASKBYTE0, power_index); 2778 break; 2779 case DESC_RATE36M: 2780 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2781 MASKBYTE1, power_index); 2782 break; 2783 case DESC_RATE48M: 2784 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2785 MASKBYTE2, power_index); 2786 break; 2787 case DESC_RATE54M: 2788 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, 2789 MASKBYTE3, power_index); 2790 break; 2791 case DESC_RATEMCS0: 2792 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2793 MASKBYTE0, power_index); 2794 break; 2795 case DESC_RATEMCS1: 2796 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2797 MASKBYTE1, power_index); 2798 break; 2799 case DESC_RATEMCS2: 2800 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2801 MASKBYTE2, power_index); 2802 break; 2803 case DESC_RATEMCS3: 2804 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, 2805 MASKBYTE3, power_index); 2806 break; 2807 case DESC_RATEMCS4: 2808 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2809 MASKBYTE0, power_index); 2810 break; 2811 case DESC_RATEMCS5: 2812 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2813 MASKBYTE1, power_index); 2814 break; 2815 case DESC_RATEMCS6: 2816 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2817 MASKBYTE2, power_index); 2818 break; 2819 case DESC_RATEMCS7: 2820 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, 2821 MASKBYTE3, power_index); 2822 break; 2823 case DESC_RATEMCS8: 2824 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2825 MASKBYTE0, power_index); 2826 break; 2827 case DESC_RATEMCS9: 2828 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2829 MASKBYTE1, power_index); 2830 break; 2831 case DESC_RATEMCS10: 2832 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2833 MASKBYTE2, power_index); 2834 break; 2835 case DESC_RATEMCS11: 2836 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, 2837 MASKBYTE3, power_index); 2838 break; 2839 case DESC_RATEMCS12: 2840 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2841 MASKBYTE0, power_index); 2842 break; 2843 case DESC_RATEMCS13: 2844 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2845 MASKBYTE1, power_index); 2846 break; 2847 case DESC_RATEMCS14: 2848 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2849 MASKBYTE2, power_index); 2850 break; 2851 case DESC_RATEMCS15: 2852 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, 2853 MASKBYTE3, power_index); 2854 break; 2855 case DESC_RATEVHT1SS_MCS0: 2856 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2857 MASKBYTE0, power_index); 2858 break; 2859 case DESC_RATEVHT1SS_MCS1: 2860 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2861 MASKBYTE1, power_index); 2862 break; 2863 case DESC_RATEVHT1SS_MCS2: 2864 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2865 MASKBYTE2, power_index); 2866 break; 2867 case DESC_RATEVHT1SS_MCS3: 2868 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, 2869 MASKBYTE3, power_index); 2870 break; 2871 case DESC_RATEVHT1SS_MCS4: 2872 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2873 MASKBYTE0, power_index); 2874 break; 2875 case DESC_RATEVHT1SS_MCS5: 2876 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2877 MASKBYTE1, power_index); 2878 break; 2879 case DESC_RATEVHT1SS_MCS6: 2880 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2881 MASKBYTE2, power_index); 2882 break; 2883 case DESC_RATEVHT1SS_MCS7: 2884 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, 2885 MASKBYTE3, power_index); 2886 break; 2887 case DESC_RATEVHT1SS_MCS8: 2888 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2889 MASKBYTE0, power_index); 2890 break; 2891 case DESC_RATEVHT1SS_MCS9: 2892 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2893 MASKBYTE1, power_index); 2894 break; 2895 case DESC_RATEVHT2SS_MCS0: 2896 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2897 MASKBYTE2, power_index); 2898 break; 2899 case DESC_RATEVHT2SS_MCS1: 2900 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, 2901 MASKBYTE3, power_index); 2902 break; 2903 case DESC_RATEVHT2SS_MCS2: 2904 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2905 MASKBYTE0, power_index); 2906 break; 2907 case DESC_RATEVHT2SS_MCS3: 2908 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2909 MASKBYTE1, power_index); 2910 break; 2911 case DESC_RATEVHT2SS_MCS4: 2912 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2913 MASKBYTE2, power_index); 2914 break; 2915 case DESC_RATEVHT2SS_MCS5: 2916 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, 2917 MASKBYTE3, power_index); 2918 break; 2919 case DESC_RATEVHT2SS_MCS6: 2920 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2921 MASKBYTE0, power_index); 2922 break; 2923 case DESC_RATEVHT2SS_MCS7: 2924 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2925 MASKBYTE1, power_index); 2926 break; 2927 case DESC_RATEVHT2SS_MCS8: 2928 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2929 MASKBYTE2, power_index); 2930 break; 2931 case DESC_RATEVHT2SS_MCS9: 2932 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, 2933 MASKBYTE3, power_index); 2934 break; 2935 default: 2936 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 2937 "Invalid Rate!!\n"); 2938 break; 2939 } 2940 } else if (path == RF90_PATH_B) { 2941 switch (rate) { 2942 case DESC_RATE1M: 2943 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2944 MASKBYTE0, power_index); 2945 break; 2946 case DESC_RATE2M: 2947 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2948 MASKBYTE1, power_index); 2949 break; 2950 case DESC_RATE5_5M: 2951 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2952 MASKBYTE2, power_index); 2953 break; 2954 case DESC_RATE11M: 2955 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, 2956 MASKBYTE3, power_index); 2957 break; 2958 case DESC_RATE6M: 2959 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2960 MASKBYTE0, power_index); 2961 break; 2962 case DESC_RATE9M: 2963 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2964 MASKBYTE1, power_index); 2965 break; 2966 case DESC_RATE12M: 2967 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2968 MASKBYTE2, power_index); 2969 break; 2970 case DESC_RATE18M: 2971 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, 2972 MASKBYTE3, power_index); 2973 break; 2974 case DESC_RATE24M: 2975 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2976 MASKBYTE0, power_index); 2977 break; 2978 case DESC_RATE36M: 2979 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2980 MASKBYTE1, power_index); 2981 break; 2982 case DESC_RATE48M: 2983 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2984 MASKBYTE2, power_index); 2985 break; 2986 case DESC_RATE54M: 2987 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, 2988 MASKBYTE3, power_index); 2989 break; 2990 case DESC_RATEMCS0: 2991 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 2992 MASKBYTE0, power_index); 2993 break; 2994 case DESC_RATEMCS1: 2995 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 2996 MASKBYTE1, power_index); 2997 break; 2998 case DESC_RATEMCS2: 2999 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 3000 MASKBYTE2, power_index); 3001 break; 3002 case DESC_RATEMCS3: 3003 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, 3004 MASKBYTE3, power_index); 3005 break; 3006 case DESC_RATEMCS4: 3007 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3008 MASKBYTE0, power_index); 3009 break; 3010 case DESC_RATEMCS5: 3011 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3012 MASKBYTE1, power_index); 3013 break; 3014 case DESC_RATEMCS6: 3015 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3016 MASKBYTE2, power_index); 3017 break; 3018 case DESC_RATEMCS7: 3019 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, 3020 MASKBYTE3, power_index); 3021 break; 3022 case DESC_RATEMCS8: 3023 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3024 MASKBYTE0, power_index); 3025 break; 3026 case DESC_RATEMCS9: 3027 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3028 MASKBYTE1, power_index); 3029 break; 3030 case DESC_RATEMCS10: 3031 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3032 MASKBYTE2, power_index); 3033 break; 3034 case DESC_RATEMCS11: 3035 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, 3036 MASKBYTE3, power_index); 3037 break; 3038 case DESC_RATEMCS12: 3039 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3040 MASKBYTE0, power_index); 3041 break; 3042 case DESC_RATEMCS13: 3043 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3044 MASKBYTE1, power_index); 3045 break; 3046 case DESC_RATEMCS14: 3047 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3048 MASKBYTE2, power_index); 3049 break; 3050 case DESC_RATEMCS15: 3051 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, 3052 MASKBYTE3, power_index); 3053 break; 3054 case DESC_RATEVHT1SS_MCS0: 3055 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3056 MASKBYTE0, power_index); 3057 break; 3058 case DESC_RATEVHT1SS_MCS1: 3059 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3060 MASKBYTE1, power_index); 3061 break; 3062 case DESC_RATEVHT1SS_MCS2: 3063 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3064 MASKBYTE2, power_index); 3065 break; 3066 case DESC_RATEVHT1SS_MCS3: 3067 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, 3068 MASKBYTE3, power_index); 3069 break; 3070 case DESC_RATEVHT1SS_MCS4: 3071 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3072 MASKBYTE0, power_index); 3073 break; 3074 case DESC_RATEVHT1SS_MCS5: 3075 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3076 MASKBYTE1, power_index); 3077 break; 3078 case DESC_RATEVHT1SS_MCS6: 3079 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3080 MASKBYTE2, power_index); 3081 break; 3082 case DESC_RATEVHT1SS_MCS7: 3083 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, 3084 MASKBYTE3, power_index); 3085 break; 3086 case DESC_RATEVHT1SS_MCS8: 3087 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3088 MASKBYTE0, power_index); 3089 break; 3090 case DESC_RATEVHT1SS_MCS9: 3091 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3092 MASKBYTE1, power_index); 3093 break; 3094 case DESC_RATEVHT2SS_MCS0: 3095 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3096 MASKBYTE2, power_index); 3097 break; 3098 case DESC_RATEVHT2SS_MCS1: 3099 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, 3100 MASKBYTE3, power_index); 3101 break; 3102 case DESC_RATEVHT2SS_MCS2: 3103 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3104 MASKBYTE0, power_index); 3105 break; 3106 case DESC_RATEVHT2SS_MCS3: 3107 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3108 MASKBYTE1, power_index); 3109 break; 3110 case DESC_RATEVHT2SS_MCS4: 3111 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3112 MASKBYTE2, power_index); 3113 break; 3114 case DESC_RATEVHT2SS_MCS5: 3115 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, 3116 MASKBYTE3, power_index); 3117 break; 3118 case DESC_RATEVHT2SS_MCS6: 3119 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3120 MASKBYTE0, power_index); 3121 break; 3122 case DESC_RATEVHT2SS_MCS7: 3123 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3124 MASKBYTE1, power_index); 3125 break; 3126 case DESC_RATEVHT2SS_MCS8: 3127 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3128 MASKBYTE2, power_index); 3129 break; 3130 case DESC_RATEVHT2SS_MCS9: 3131 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, 3132 MASKBYTE3, power_index); 3133 break; 3134 default: 3135 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 3136 "Invalid Rate!!\n"); 3137 break; 3138 } 3139 } else { 3140 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 3141 "Invalid RFPath!!\n"); 3142 } 3143 } 3144 3145 static void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, 3146 u8 *array, u8 path, 3147 u8 channel, u8 size) 3148 { 3149 struct rtl_priv *rtlpriv = rtl_priv(hw); 3150 struct rtl_phy *rtlphy = &rtlpriv->phy; 3151 u8 i; 3152 u8 power_index; 3153 3154 for (i = 0; i < size; i++) { 3155 power_index = 3156 _rtl8821ae_get_txpower_index(hw, path, array[i], 3157 rtlphy->current_chan_bw, 3158 channel); 3159 _rtl8821ae_phy_set_txpower_index(hw, power_index, path, 3160 array[i]); 3161 } 3162 } 3163 3164 static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw, 3165 u8 bw, u8 channel, u8 path) 3166 { 3167 struct rtl_priv *rtlpriv = rtl_priv(hw); 3168 struct rtl_phy *rtlphy = &rtlpriv->phy; 3169 3170 u8 i; 3171 u32 power_level, data, offset; 3172 3173 if (path >= rtlphy->num_total_rfpath) 3174 return; 3175 3176 data = 0; 3177 if (path == RF90_PATH_A) { 3178 power_level = 3179 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A, 3180 DESC_RATEMCS7, bw, channel); 3181 offset = RA_TXPWRTRAING; 3182 } else { 3183 power_level = 3184 _rtl8821ae_get_txpower_index(hw, RF90_PATH_B, 3185 DESC_RATEMCS7, bw, channel); 3186 offset = RB_TXPWRTRAING; 3187 } 3188 3189 for (i = 0; i < 3; i++) { 3190 if (i == 0) 3191 power_level = power_level - 10; 3192 else if (i == 1) 3193 power_level = power_level - 8; 3194 else 3195 power_level = power_level - 6; 3196 3197 data |= (((power_level > 2) ? (power_level) : 2) << (i * 8)); 3198 } 3199 rtl_set_bbreg(hw, offset, 0xffffff, data); 3200 } 3201 3202 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, 3203 u8 channel, u8 path) 3204 { 3205 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */ 3206 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3207 struct rtl_priv *rtlpriv = rtl_priv(hw); 3208 struct rtl_phy *rtlphy = &rtlpriv->phy; 3209 u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, 3210 DESC_RATE11M}; 3211 u8 sizes_of_cck_retes = 4; 3212 u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, 3213 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, 3214 DESC_RATE48M, DESC_RATE54M}; 3215 u8 sizes_of_ofdm_retes = 8; 3216 u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, 3217 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, 3218 DESC_RATEMCS6, DESC_RATEMCS7}; 3219 u8 sizes_of_ht_retes_1t = 8; 3220 u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9, 3221 DESC_RATEMCS10, DESC_RATEMCS11, 3222 DESC_RATEMCS12, DESC_RATEMCS13, 3223 DESC_RATEMCS14, DESC_RATEMCS15}; 3224 u8 sizes_of_ht_retes_2t = 8; 3225 u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, 3226 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, 3227 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, 3228 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, 3229 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9}; 3230 u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, 3231 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, 3232 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, 3233 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, 3234 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9}; 3235 u8 sizes_of_vht_retes = 10; 3236 3237 if (rtlhal->current_bandtype == BAND_ON_2_4G) 3238 _rtl8821ae_phy_set_txpower_level_by_path(hw, cck_rates, path, channel, 3239 sizes_of_cck_retes); 3240 3241 _rtl8821ae_phy_set_txpower_level_by_path(hw, ofdm_rates, path, channel, 3242 sizes_of_ofdm_retes); 3243 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_1t, path, channel, 3244 sizes_of_ht_retes_1t); 3245 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_1t, path, channel, 3246 sizes_of_vht_retes); 3247 3248 if (rtlphy->num_total_rfpath >= 2) { 3249 _rtl8821ae_phy_set_txpower_level_by_path(hw, ht_rates_2t, path, 3250 channel, 3251 sizes_of_ht_retes_2t); 3252 _rtl8821ae_phy_set_txpower_level_by_path(hw, vht_rates_2t, path, 3253 channel, 3254 sizes_of_vht_retes); 3255 } 3256 3257 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, 3258 channel, path); 3259 } 3260 3261 /*just in case, write txpower in DW, to reduce time*/ 3262 void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 3263 { 3264 struct rtl_priv *rtlpriv = rtl_priv(hw); 3265 struct rtl_phy *rtlphy = &rtlpriv->phy; 3266 u8 path = 0; 3267 3268 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path) 3269 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path); 3270 } 3271 3272 static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 3273 enum wireless_mode wirelessmode, 3274 u8 txpwridx) 3275 { 3276 long offset; 3277 long pwrout_dbm; 3278 3279 switch (wirelessmode) { 3280 case WIRELESS_MODE_B: 3281 offset = -7; 3282 break; 3283 case WIRELESS_MODE_G: 3284 case WIRELESS_MODE_N_24G: 3285 offset = -8; 3286 break; 3287 default: 3288 offset = -8; 3289 break; 3290 } 3291 pwrout_dbm = txpwridx / 2 + offset; 3292 return pwrout_dbm; 3293 } 3294 3295 void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) 3296 { 3297 struct rtl_priv *rtlpriv = rtl_priv(hw); 3298 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3299 enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 3300 3301 if (!is_hal_stop(rtlhal)) { 3302 switch (operation) { 3303 case SCAN_OPT_BACKUP_BAND0: 3304 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 3305 rtlpriv->cfg->ops->set_hw_reg(hw, 3306 HW_VAR_IO_CMD, 3307 (u8 *)&iotype); 3308 3309 break; 3310 case SCAN_OPT_BACKUP_BAND1: 3311 iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN; 3312 rtlpriv->cfg->ops->set_hw_reg(hw, 3313 HW_VAR_IO_CMD, 3314 (u8 *)&iotype); 3315 3316 break; 3317 case SCAN_OPT_RESTORE: 3318 iotype = IO_CMD_RESUME_DM_BY_SCAN; 3319 rtlpriv->cfg->ops->set_hw_reg(hw, 3320 HW_VAR_IO_CMD, 3321 (u8 *)&iotype); 3322 break; 3323 default: 3324 pr_err("Unknown Scan Backup operation.\n"); 3325 break; 3326 } 3327 } 3328 } 3329 3330 static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv *rtlpriv, u8 bw) 3331 { 3332 u16 reg_rf_mode_bw, tmp = 0; 3333 3334 reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL); 3335 switch (bw) { 3336 case HT_CHANNEL_WIDTH_20: 3337 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F); 3338 break; 3339 case HT_CHANNEL_WIDTH_20_40: 3340 tmp = reg_rf_mode_bw | BIT(7); 3341 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF); 3342 break; 3343 case HT_CHANNEL_WIDTH_80: 3344 tmp = reg_rf_mode_bw | BIT(8); 3345 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F); 3346 break; 3347 default: 3348 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "unknown Bandwidth: 0x%x\n", bw); 3349 break; 3350 } 3351 } 3352 3353 static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv *rtlpriv) 3354 { 3355 struct rtl_phy *rtlphy = &rtlpriv->phy; 3356 struct rtl_mac *mac = rtl_mac(rtlpriv); 3357 u8 sc_set_40 = 0, sc_set_20 = 0; 3358 3359 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) { 3360 if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER) 3361 sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ; 3362 else if (mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER) 3363 sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ; 3364 else 3365 pr_err("SCMapping: Not Correct Primary40MHz Setting\n"); 3366 3367 if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) && 3368 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)) 3369 sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ; 3370 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) && 3371 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER)) 3372 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; 3373 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) && 3374 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER)) 3375 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; 3376 else if ((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) && 3377 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER)) 3378 sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ; 3379 else 3380 pr_err("SCMapping: Not Correct Primary40MHz Setting\n"); 3381 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { 3382 if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) 3383 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; 3384 else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) 3385 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; 3386 else 3387 pr_err("SCMapping: Not Correct Primary40MHz Setting\n"); 3388 } 3389 return (sc_set_40 << 4) | sc_set_20; 3390 } 3391 3392 void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 3393 { 3394 struct rtl_priv *rtlpriv = rtl_priv(hw); 3395 struct rtl_phy *rtlphy = &rtlpriv->phy; 3396 u8 sub_chnl = 0; 3397 u8 l1pk_val = 0; 3398 3399 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 3400 "Switch to %s bandwidth\n", 3401 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 3402 "20MHz" : 3403 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ? 3404 "40MHz" : "80MHz"))); 3405 3406 _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw); 3407 sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv); 3408 rtl_write_byte(rtlpriv, 0x0483, sub_chnl); 3409 3410 switch (rtlphy->current_chan_bw) { 3411 case HT_CHANNEL_WIDTH_20: 3412 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200); 3413 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); 3414 3415 if (rtlphy->rf_type == RF_2T2R) 3416 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7); 3417 else 3418 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8); 3419 break; 3420 case HT_CHANNEL_WIDTH_20_40: 3421 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201); 3422 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0); 3423 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl); 3424 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl); 3425 3426 if (rtlphy->reg_837 & BIT(2)) 3427 l1pk_val = 6; 3428 else { 3429 if (rtlphy->rf_type == RF_2T2R) 3430 l1pk_val = 7; 3431 else 3432 l1pk_val = 8; 3433 } 3434 /* 0x848[25:22] = 0x6 */ 3435 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); 3436 3437 if (sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ) 3438 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1); 3439 else 3440 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0); 3441 break; 3442 3443 case HT_CHANNEL_WIDTH_80: 3444 /* 0x8ac[21,20,9:6,1,0]=8'b11100010 */ 3445 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202); 3446 /* 0x8c4[30] = 1 */ 3447 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); 3448 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl); 3449 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl); 3450 3451 if (rtlphy->reg_837 & BIT(2)) 3452 l1pk_val = 5; 3453 else { 3454 if (rtlphy->rf_type == RF_2T2R) 3455 l1pk_val = 6; 3456 else 3457 l1pk_val = 7; 3458 } 3459 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); 3460 3461 break; 3462 default: 3463 pr_err("unknown bandwidth: %#X\n", 3464 rtlphy->current_chan_bw); 3465 break; 3466 } 3467 3468 rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel); 3469 3470 rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 3471 rtlphy->set_bwmode_inprogress = false; 3472 3473 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n"); 3474 } 3475 3476 void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw, 3477 enum nl80211_channel_type ch_type) 3478 { 3479 struct rtl_priv *rtlpriv = rtl_priv(hw); 3480 struct rtl_phy *rtlphy = &rtlpriv->phy; 3481 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3482 u8 tmp_bw = rtlphy->current_chan_bw; 3483 3484 if (rtlphy->set_bwmode_inprogress) 3485 return; 3486 rtlphy->set_bwmode_inprogress = true; 3487 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) 3488 rtl8821ae_phy_set_bw_mode_callback(hw); 3489 else { 3490 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 3491 "FALSE driver sleep or unload\n"); 3492 rtlphy->set_bwmode_inprogress = false; 3493 rtlphy->current_chan_bw = tmp_bw; 3494 } 3495 } 3496 3497 void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw) 3498 { 3499 struct rtl_priv *rtlpriv = rtl_priv(hw); 3500 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3501 struct rtl_phy *rtlphy = &rtlpriv->phy; 3502 u8 channel = rtlphy->current_channel; 3503 u8 path; 3504 u32 data; 3505 3506 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 3507 "switch to channel%d\n", rtlphy->current_channel); 3508 if (is_hal_stop(rtlhal)) 3509 return; 3510 3511 if (36 <= channel && channel <= 48) 3512 data = 0x494; 3513 else if (50 <= channel && channel <= 64) 3514 data = 0x453; 3515 else if (100 <= channel && channel <= 116) 3516 data = 0x452; 3517 else if (118 <= channel) 3518 data = 0x412; 3519 else 3520 data = 0x96a; 3521 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data); 3522 3523 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++) { 3524 if (36 <= channel && channel <= 64) 3525 data = 0x101; 3526 else if (100 <= channel && channel <= 140) 3527 data = 0x301; 3528 else if (140 < channel) 3529 data = 0x501; 3530 else 3531 data = 0x000; 3532 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW, 3533 BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data); 3534 3535 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW, 3536 BMASKBYTE0, channel); 3537 3538 if (channel > 14) { 3539 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 3540 if (36 <= channel && channel <= 64) 3541 data = 0x114E9; 3542 else 3543 data = 0x110E9; 3544 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK, 3545 BRFREGOFFSETMASK, data); 3546 } 3547 } 3548 } 3549 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 3550 } 3551 3552 u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw) 3553 { 3554 struct rtl_priv *rtlpriv = rtl_priv(hw); 3555 struct rtl_phy *rtlphy = &rtlpriv->phy; 3556 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3557 u32 timeout = 1000, timecount = 0; 3558 u8 channel = rtlphy->current_channel; 3559 3560 if (rtlphy->sw_chnl_inprogress) 3561 return 0; 3562 if (rtlphy->set_bwmode_inprogress) 3563 return 0; 3564 3565 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 3566 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 3567 "sw_chnl_inprogress false driver sleep or unload\n"); 3568 return 0; 3569 } 3570 while (rtlphy->lck_inprogress && timecount < timeout) { 3571 mdelay(50); 3572 timecount += 50; 3573 } 3574 3575 if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G) 3576 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G); 3577 else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G) 3578 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 3579 3580 rtlphy->sw_chnl_inprogress = true; 3581 if (channel == 0) 3582 channel = 1; 3583 3584 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 3585 "switch to channel%d, band type is %d\n", 3586 rtlphy->current_channel, rtlhal->current_bandtype); 3587 3588 rtl8821ae_phy_sw_chnl_callback(hw); 3589 3590 rtl8821ae_dm_clear_txpower_tracking_state(hw); 3591 rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel); 3592 3593 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 3594 rtlphy->sw_chnl_inprogress = false; 3595 return 1; 3596 } 3597 3598 u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl) 3599 { 3600 static const u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] = { 3601 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 3602 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 3603 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 3604 110, 112, 114, 116, 118, 120, 122, 124, 126, 3605 128, 130, 132, 134, 136, 138, 140, 149, 151, 3606 153, 155, 157, 159, 161, 163, 165}; 3607 u8 place; 3608 3609 if (chnl > 14) { 3610 for (place = 14; place < sizeof(channel_all); place++) 3611 if (channel_all[place] == chnl) 3612 return place-13; 3613 } 3614 3615 return 0; 3616 } 3617 3618 #define MACBB_REG_NUM 10 3619 #define AFE_REG_NUM 14 3620 #define RF_REG_NUM 3 3621 3622 static void _rtl8821ae_iqk_backup_macbb(struct ieee80211_hw *hw, 3623 u32 *macbb_backup, 3624 u32 *backup_macbb_reg, u32 mac_bb_num) 3625 { 3626 struct rtl_priv *rtlpriv = rtl_priv(hw); 3627 u32 i; 3628 3629 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3630 /*save MACBB default value*/ 3631 for (i = 0; i < mac_bb_num; i++) 3632 macbb_backup[i] = rtl_read_dword(rtlpriv, backup_macbb_reg[i]); 3633 3634 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupMacBB Success!!!!\n"); 3635 } 3636 3637 static void _rtl8821ae_iqk_backup_afe(struct ieee80211_hw *hw, u32 *afe_backup, 3638 u32 *backup_afe_REG, u32 afe_num) 3639 { 3640 struct rtl_priv *rtlpriv = rtl_priv(hw); 3641 u32 i; 3642 3643 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3644 /*Save AFE Parameters */ 3645 for (i = 0; i < afe_num; i++) 3646 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]); 3647 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupAFE Success!!!!\n"); 3648 } 3649 3650 static void _rtl8821ae_iqk_backup_rf(struct ieee80211_hw *hw, u32 *rfa_backup, 3651 u32 *rfb_backup, u32 *backup_rf_reg, 3652 u32 rf_num) 3653 { 3654 struct rtl_priv *rtlpriv = rtl_priv(hw); 3655 u32 i; 3656 3657 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3658 /*Save RF Parameters*/ 3659 for (i = 0; i < rf_num; i++) { 3660 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], 3661 BMASKDWORD); 3662 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], 3663 BMASKDWORD); 3664 } 3665 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "BackupRF Success!!!!\n"); 3666 } 3667 3668 static void _rtl8821ae_iqk_configure_mac( 3669 struct ieee80211_hw *hw 3670 ) 3671 { 3672 struct rtl_priv *rtlpriv = rtl_priv(hw); 3673 /* ========MAC register setting========*/ 3674 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3675 rtl_write_byte(rtlpriv, 0x522, 0x3f); 3676 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0); 3677 rtl_write_byte(rtlpriv, 0x808, 0x00); /*RX ante off*/ 3678 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/ 3679 } 3680 3681 static void _rtl8821ae_iqk_tx_fill_iqc(struct ieee80211_hw *hw, 3682 enum radio_path path, u32 tx_x, u32 tx_y) 3683 { 3684 struct rtl_priv *rtlpriv = rtl_priv(hw); 3685 switch (path) { 3686 case RF90_PATH_A: 3687 /* [31] = 1 --> Page C1 */ 3688 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); 3689 rtl_write_dword(rtlpriv, 0xc90, 0x00000080); 3690 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000); 3691 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000); 3692 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y); 3693 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x); 3694 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3695 "TX_X = %x;;TX_Y = %x =====> fill to IQC\n", 3696 tx_x, tx_y); 3697 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3698 "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", 3699 rtl_get_bbreg(hw, 0xcd4, 0x000007ff), 3700 rtl_get_bbreg(hw, 0xccc, 0x000007ff)); 3701 break; 3702 default: 3703 break; 3704 } 3705 } 3706 3707 static void _rtl8821ae_iqk_rx_fill_iqc(struct ieee80211_hw *hw, 3708 enum radio_path path, u32 rx_x, u32 rx_y) 3709 { 3710 struct rtl_priv *rtlpriv = rtl_priv(hw); 3711 switch (path) { 3712 case RF90_PATH_A: 3713 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3714 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1); 3715 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1); 3716 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3717 "rx_x = %x;;rx_y = %x ====>fill to IQC\n", 3718 rx_x >> 1, rx_y >> 1); 3719 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3720 "0xc10 = %x ====>fill to IQC\n", 3721 rtl_read_dword(rtlpriv, 0xc10)); 3722 break; 3723 default: 3724 break; 3725 } 3726 } 3727 3728 #define cal_num 10 3729 3730 static void _rtl8821ae_iqk_tx(struct ieee80211_hw *hw, enum radio_path path) 3731 { 3732 struct rtl_priv *rtlpriv = rtl_priv(hw); 3733 struct rtl_phy *rtlphy = &rtlpriv->phy; 3734 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3735 3736 u32 tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65; 3737 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0; 3738 int tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num], 3739 tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num], 3740 tx_dt[cal_num], rx_dt[cal_num]; 3741 bool tx0iqkok = false, rx0iqkok = false; 3742 bool vdf_enable = false; 3743 int i, k, vdf_y[3], vdf_x[3], 3744 ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0; 3745 3746 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3747 "BandWidth = %d.\n", 3748 rtlphy->current_chan_bw); 3749 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3750 vdf_enable = true; 3751 3752 while (cal < cal_num) { 3753 switch (path) { 3754 case RF90_PATH_A: 3755 temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff); 3756 /* Path-A LOK */ 3757 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/ 3758 /*========Path-A AFE all on========*/ 3759 /*Port 0 DAC/ADC on*/ 3760 rtl_write_dword(rtlpriv, 0xc60, 0x77777777); 3761 rtl_write_dword(rtlpriv, 0xc64, 0x77777777); 3762 rtl_write_dword(rtlpriv, 0xc68, 0x19791979); 3763 rtl_write_dword(rtlpriv, 0xc6c, 0x19791979); 3764 rtl_write_dword(rtlpriv, 0xc70, 0x19791979); 3765 rtl_write_dword(rtlpriv, 0xc74, 0x19791979); 3766 rtl_write_dword(rtlpriv, 0xc78, 0x19791979); 3767 rtl_write_dword(rtlpriv, 0xc7c, 0x19791979); 3768 rtl_write_dword(rtlpriv, 0xc80, 0x19791979); 3769 rtl_write_dword(rtlpriv, 0xc84, 0x19791979); 3770 3771 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/ 3772 3773 /* LOK Setting */ 3774 /* ====== LOK ====== */ 3775 /*DAC/ADC sampling rate (160 MHz)*/ 3776 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7); 3777 3778 /* 2. LoK RF Setting (at BW = 20M) */ 3779 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002); 3780 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3); /* BW 20M */ 3781 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000); 3782 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f); 3783 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3); 3784 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5); 3785 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 3786 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd); 3787 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 3788 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 3789 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); 3790 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */ 3791 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */ 3792 rtl_write_dword(rtlpriv, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */ 3793 3794 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3795 rtl_write_dword(rtlpriv, 0xc88, 0x821403f4); 3796 3797 if (rtlhal->current_bandtype) 3798 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96); 3799 else 3800 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96); 3801 3802 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3803 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3804 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 3805 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 3806 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 3807 3808 mdelay(10); /* Delay 10ms */ 3809 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 3810 3811 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3812 rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); /* Load LOK */ 3813 3814 switch (rtlphy->current_chan_bw) { 3815 case 1: 3816 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1); 3817 break; 3818 case 2: 3819 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0); 3820 break; 3821 default: 3822 break; 3823 } 3824 3825 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3826 3827 /* 3. TX RF Setting */ 3828 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3829 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 3830 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000); 3831 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f); 3832 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3); 3833 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5); 3834 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 3835 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 3836 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd); */ 3837 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 3838 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 3839 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1); 3840 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */ 3841 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */ 3842 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */ 3843 3844 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 3845 rtl_write_dword(rtlpriv, 0xc88, 0x821403f1); 3846 if (rtlhal->current_bandtype) 3847 rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96); 3848 else 3849 rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96); 3850 3851 if (vdf_enable == 1) { 3852 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "VDF_enable\n"); 3853 for (k = 0; k <= 2; k++) { 3854 switch (k) { 3855 case 0: 3856 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3857 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3858 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); 3859 break; 3860 case 1: 3861 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0); 3862 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0); 3863 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); 3864 break; 3865 case 2: 3866 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3867 "vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff); 3868 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 3869 "vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff); 3870 tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20); 3871 tx_dt[cal] = ((16*tx_dt[cal])*10000/15708); 3872 tx_dt[cal] = (tx_dt[cal] >> 1)+(tx_dt[cal] & BIT(0)); 3873 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3874 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3875 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); 3876 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff); 3877 break; 3878 default: 3879 break; 3880 } 3881 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 3882 cal_retry = 0; 3883 while (1) { 3884 /* one shot */ 3885 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 3886 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 3887 3888 mdelay(10); /* Delay 10ms */ 3889 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 3890 delay_count = 0; 3891 while (1) { 3892 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 3893 if ((~iqk_ready) || (delay_count > 20)) 3894 break; 3895 else{ 3896 mdelay(1); 3897 delay_count++; 3898 } 3899 } 3900 3901 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 3902 /* ============TXIQK Check============== */ 3903 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 3904 3905 if (~tx_fail) { 3906 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 3907 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3908 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 3909 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3910 tx0iqkok = true; 3911 break; 3912 } else { 3913 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0); 3914 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200); 3915 tx0iqkok = false; 3916 cal_retry++; 3917 if (cal_retry == 10) 3918 break; 3919 } 3920 } else { 3921 tx0iqkok = false; 3922 cal_retry++; 3923 if (cal_retry == 10) 3924 break; 3925 } 3926 } 3927 } 3928 if (k == 3) { 3929 tx_x0[cal] = vdf_x[k-1]; 3930 tx_y0[cal] = vdf_y[k-1]; 3931 } 3932 } else { 3933 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 3934 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 3935 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 3936 cal_retry = 0; 3937 while (1) { 3938 /* one shot */ 3939 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 3940 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 3941 3942 mdelay(10); /* Delay 10ms */ 3943 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 3944 delay_count = 0; 3945 while (1) { 3946 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 3947 if ((~iqk_ready) || (delay_count > 20)) 3948 break; 3949 else{ 3950 mdelay(1); 3951 delay_count++; 3952 } 3953 } 3954 3955 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 3956 /* ============TXIQK Check============== */ 3957 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 3958 3959 if (~tx_fail) { 3960 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 3961 tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3962 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 3963 tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 3964 tx0iqkok = true; 3965 break; 3966 } else { 3967 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0); 3968 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200); 3969 tx0iqkok = false; 3970 cal_retry++; 3971 if (cal_retry == 10) 3972 break; 3973 } 3974 } else { 3975 tx0iqkok = false; 3976 cal_retry++; 3977 if (cal_retry == 10) 3978 break; 3979 } 3980 } 3981 } 3982 3983 if (tx0iqkok == false) 3984 break; /* TXK fail, Don't do RXK */ 3985 3986 if (vdf_enable == 1) { 3987 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); /* TX VDF Disable */ 3988 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RXVDF Start\n"); 3989 for (k = 0; k <= 2; k++) { 3990 /* ====== RX mode TXK (RXK Step 1) ====== */ 3991 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 3992 /* 1. TX RF Setting */ 3993 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 3994 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 3995 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029); 3996 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb); 3997 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); 3998 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 3999 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4000 4001 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd); 4002 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y) */ 4003 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y) */ 4004 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */ 4005 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4006 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 4007 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4008 switch (k) { 4009 case 0: 4010 { 4011 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4012 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4013 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); 4014 } 4015 break; 4016 case 1: 4017 { 4018 rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4019 rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4020 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0); 4021 } 4022 break; 4023 case 2: 4024 { 4025 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4026 "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", 4027 vdf_y[1] >> 21 & 0x00007ff, 4028 vdf_y[0] >> 21 & 0x00007ff); 4029 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4030 "VDF_X[1] = %x;;;VDF_X[0] = %x\n", 4031 vdf_x[1] >> 21 & 0x00007ff, 4032 vdf_x[0] >> 21 & 0x00007ff); 4033 rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20); 4034 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "Rx_dt = %d\n", 4035 rx_dt[cal]); 4036 rx_dt[cal] = ((16*rx_dt[cal])*10000/13823); 4037 rx_dt[cal] = (rx_dt[cal] >> 1)+(rx_dt[cal] & BIT(0)); 4038 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4039 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4040 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff); 4041 } 4042 break; 4043 default: 4044 break; 4045 } 4046 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0); 4047 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96); 4048 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4049 cal_retry = 0; 4050 while (1) { 4051 /* one shot */ 4052 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4053 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4054 4055 mdelay(10); /* Delay 10ms */ 4056 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4057 delay_count = 0; 4058 while (1) { 4059 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4060 if ((~iqk_ready) || (delay_count > 20)) 4061 break; 4062 else{ 4063 mdelay(1); 4064 delay_count++; 4065 } 4066 } 4067 4068 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4069 /* ============TXIQK Check============== */ 4070 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 4071 4072 if (~tx_fail) { 4073 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 4074 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4075 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 4076 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4077 tx0iqkok = true; 4078 break; 4079 } else{ 4080 tx0iqkok = false; 4081 cal_retry++; 4082 if (cal_retry == 10) 4083 break; 4084 } 4085 } else { 4086 tx0iqkok = false; 4087 cal_retry++; 4088 if (cal_retry == 10) 4089 break; 4090 } 4091 } 4092 4093 if (tx0iqkok == false) { /* If RX mode TXK fail, then take TXK Result */ 4094 tx_x0_rxk[cal] = tx_x0[cal]; 4095 tx_y0_rxk[cal] = tx_y0[cal]; 4096 tx0iqkok = true; 4097 rtl_dbg(rtlpriv, 4098 COMP_IQK, 4099 DBG_LOUD, 4100 "RXK Step 1 fail\n"); 4101 } 4102 4103 /* ====== RX IQK ====== */ 4104 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4105 /* 1. RX RF Setting */ 4106 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 4107 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 4108 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f); 4109 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb); 4110 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001); 4111 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8); 4112 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4113 4114 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff); 4115 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff); 4116 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); 4117 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); 4118 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe); 4119 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4120 rtl_write_dword(rtlpriv, 0x984, 0x0046a911); 4121 4122 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4123 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1); 4124 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0); 4125 rtl_write_dword(rtlpriv, 0xc88, 0x02140119); 4126 4127 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */ 4128 4129 if (k == 2) 4130 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); /* RX VDF Enable */ 4131 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4132 4133 cal_retry = 0; 4134 while (1) { 4135 /* one shot */ 4136 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4137 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4138 4139 mdelay(10); /* Delay 10ms */ 4140 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4141 delay_count = 0; 4142 while (1) { 4143 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4144 if ((~iqk_ready) || (delay_count > 20)) 4145 break; 4146 else{ 4147 mdelay(1); 4148 delay_count++; 4149 } 4150 } 4151 4152 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4153 /* ============RXIQK Check============== */ 4154 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); 4155 if (rx_fail == 0) { 4156 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000); 4157 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4158 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000); 4159 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4160 rx0iqkok = true; 4161 break; 4162 } else { 4163 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1); 4164 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1); 4165 rx0iqkok = false; 4166 cal_retry++; 4167 if (cal_retry == 10) 4168 break; 4169 4170 } 4171 } else{ 4172 rx0iqkok = false; 4173 cal_retry++; 4174 if (cal_retry == 10) 4175 break; 4176 } 4177 } 4178 4179 } 4180 if (k == 3) { 4181 rx_x0[cal] = vdf_x[k-1]; 4182 rx_y0[cal] = vdf_y[k-1]; 4183 } 4184 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); /* TX VDF Enable */ 4185 } 4186 4187 else{ 4188 /* ====== RX mode TXK (RXK Step 1) ====== */ 4189 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4190 /* 1. TX RF Setting */ 4191 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 4192 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 4193 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029); 4194 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb); 4195 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); 4196 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001); 4197 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4198 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4199 rtl_write_dword(rtlpriv, 0xb00, 0x03000100); 4200 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */ 4201 4202 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4203 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4204 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4205 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0); 4206 /* ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96); */ 4207 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4208 cal_retry = 0; 4209 while (1) { 4210 /* one shot */ 4211 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4212 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4213 4214 mdelay(10); /* Delay 10ms */ 4215 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4216 delay_count = 0; 4217 while (1) { 4218 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4219 if ((~iqk_ready) || (delay_count > 20)) 4220 break; 4221 else{ 4222 mdelay(1); 4223 delay_count++; 4224 } 4225 } 4226 4227 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4228 /* ============TXIQK Check============== */ 4229 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12)); 4230 4231 if (~tx_fail) { 4232 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000); 4233 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4234 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000); 4235 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4236 tx0iqkok = true; 4237 break; 4238 } else { 4239 tx0iqkok = false; 4240 cal_retry++; 4241 if (cal_retry == 10) 4242 break; 4243 } 4244 } else{ 4245 tx0iqkok = false; 4246 cal_retry++; 4247 if (cal_retry == 10) 4248 break; 4249 } 4250 } 4251 4252 if (tx0iqkok == false) { /* If RX mode TXK fail, then take TXK Result */ 4253 tx_x0_rxk[cal] = tx_x0[cal]; 4254 tx_y0_rxk[cal] = tx_y0[cal]; 4255 tx0iqkok = true; 4256 rtl_dbg(rtlpriv, COMP_IQK, 4257 DBG_LOUD, "1"); 4258 } 4259 4260 /* ====== RX IQK ====== */ 4261 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4262 /* 1. RX RF Setting */ 4263 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000); 4264 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000); 4265 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f); 4266 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb); 4267 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001); 4268 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8); 4269 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000); 4270 4271 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff); 4272 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff); 4273 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1); 4274 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0); 4275 /* ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe); */ 4276 rtl_write_dword(rtlpriv, 0x90c, 0x00008000); 4277 rtl_write_dword(rtlpriv, 0x984, 0x0046a911); 4278 4279 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4280 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/* TX_TONE_idx[9:0], TxK_Mask[29] TX_Tone = 16 */ 4281 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/* RX_TONE_idx[9:0], RxK_Mask[29] */ 4282 rtl_write_dword(rtlpriv, 0xc88, 0x02140119); 4283 4284 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/ 4285 4286 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] \B1N SI/PI \A8ϥ\CE\C5v\A4\C1\B5\B9 iqk_dpk module */ 4287 4288 cal_retry = 0; 4289 while (1) { 4290 /* one shot */ 4291 rtl_write_dword(rtlpriv, 0x980, 0xfa000000); 4292 rtl_write_dword(rtlpriv, 0x980, 0xf8000000); 4293 4294 mdelay(10); /* Delay 10ms */ 4295 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000); 4296 delay_count = 0; 4297 while (1) { 4298 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10)); 4299 if ((~iqk_ready) || (delay_count > 20)) 4300 break; 4301 else{ 4302 mdelay(1); 4303 delay_count++; 4304 } 4305 } 4306 4307 if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */ 4308 /* ============RXIQK Check============== */ 4309 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11)); 4310 if (rx_fail == 0) { 4311 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000); 4312 rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4313 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000); 4314 rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; 4315 rx0iqkok = true; 4316 break; 4317 } else{ 4318 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1); 4319 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1); 4320 rx0iqkok = false; 4321 cal_retry++; 4322 if (cal_retry == 10) 4323 break; 4324 4325 } 4326 } else{ 4327 rx0iqkok = false; 4328 cal_retry++; 4329 if (cal_retry == 10) 4330 break; 4331 } 4332 } 4333 } 4334 4335 if (tx0iqkok) 4336 tx_average++; 4337 if (rx0iqkok) 4338 rx_average++; 4339 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4340 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65); 4341 break; 4342 default: 4343 break; 4344 } 4345 cal++; 4346 } 4347 4348 /* FillIQK Result */ 4349 switch (path) { 4350 case RF90_PATH_A: 4351 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4352 "========Path_A =======\n"); 4353 if (tx_average == 0) 4354 break; 4355 4356 for (i = 0; i < tx_average; i++) { 4357 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4358 "TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i, 4359 (tx_x0_rxk[i]) >> 21 & 0x000007ff, i, 4360 (tx_y0_rxk[i]) >> 21 & 0x000007ff); 4361 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4362 "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, 4363 (tx_x0[i]) >> 21 & 0x000007ff, i, 4364 (tx_y0[i]) >> 21 & 0x000007ff); 4365 } 4366 for (i = 0; i < tx_average; i++) { 4367 for (ii = i+1; ii < tx_average; ii++) { 4368 dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21); 4369 if (dx < 3 && dx > -3) { 4370 dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21); 4371 if (dy < 3 && dy > -3) { 4372 tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2; 4373 tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2; 4374 tx_finish = 1; 4375 break; 4376 } 4377 } 4378 } 4379 if (tx_finish == 1) 4380 break; 4381 } 4382 4383 if (tx_finish == 1) 4384 _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); /* ? */ 4385 else 4386 _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0); 4387 4388 if (rx_average == 0) 4389 break; 4390 4391 for (i = 0; i < rx_average; i++) 4392 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4393 "RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i, 4394 (rx_x0[i])>>21&0x000007ff, i, 4395 (rx_y0[i])>>21&0x000007ff); 4396 for (i = 0; i < rx_average; i++) { 4397 for (ii = i+1; ii < rx_average; ii++) { 4398 dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21); 4399 if (dx < 4 && dx > -4) { 4400 dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21); 4401 if (dy < 4 && dy > -4) { 4402 rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2; 4403 rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2; 4404 rx_finish = 1; 4405 break; 4406 } 4407 } 4408 } 4409 if (rx_finish == 1) 4410 break; 4411 } 4412 4413 if (rx_finish == 1) 4414 _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y); 4415 else 4416 _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0); 4417 break; 4418 default: 4419 break; 4420 } 4421 } 4422 4423 static void _rtl8821ae_iqk_restore_rf(struct ieee80211_hw *hw, 4424 enum radio_path path, 4425 u32 *backup_rf_reg, 4426 u32 *rf_backup, u32 rf_reg_num) 4427 { 4428 struct rtl_priv *rtlpriv = rtl_priv(hw); 4429 u32 i; 4430 4431 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4432 for (i = 0; i < RF_REG_NUM; i++) 4433 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK, 4434 rf_backup[i]); 4435 4436 switch (path) { 4437 case RF90_PATH_A: 4438 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4439 "RestoreRF Path A Success!!!!\n"); 4440 break; 4441 default: 4442 break; 4443 } 4444 } 4445 4446 static void _rtl8821ae_iqk_restore_afe(struct ieee80211_hw *hw, 4447 u32 *afe_backup, u32 *backup_afe_reg, 4448 u32 afe_num) 4449 { 4450 u32 i; 4451 struct rtl_priv *rtlpriv = rtl_priv(hw); 4452 4453 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4454 /* Reload AFE Parameters */ 4455 for (i = 0; i < afe_num; i++) 4456 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]); 4457 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */ 4458 rtl_write_dword(rtlpriv, 0xc80, 0x0); 4459 rtl_write_dword(rtlpriv, 0xc84, 0x0); 4460 rtl_write_dword(rtlpriv, 0xc88, 0x0); 4461 rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000); 4462 rtl_write_dword(rtlpriv, 0xc90, 0x00000080); 4463 rtl_write_dword(rtlpriv, 0xc94, 0x00000000); 4464 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000); 4465 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000); 4466 rtl_write_dword(rtlpriv, 0xcb8, 0x0); 4467 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreAFE Success!!!!\n"); 4468 } 4469 4470 static void _rtl8821ae_iqk_restore_macbb(struct ieee80211_hw *hw, 4471 u32 *macbb_backup, 4472 u32 *backup_macbb_reg, 4473 u32 macbb_num) 4474 { 4475 u32 i; 4476 struct rtl_priv *rtlpriv = rtl_priv(hw); 4477 4478 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */ 4479 /* Reload MacBB Parameters */ 4480 for (i = 0; i < macbb_num; i++) 4481 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]); 4482 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, "RestoreMacBB Success!!!!\n"); 4483 } 4484 4485 #undef MACBB_REG_NUM 4486 #undef AFE_REG_NUM 4487 #undef RF_REG_NUM 4488 4489 #define MACBB_REG_NUM 11 4490 #define AFE_REG_NUM 12 4491 #define RF_REG_NUM 3 4492 4493 static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw) 4494 { 4495 u32 macbb_backup[MACBB_REG_NUM]; 4496 u32 afe_backup[AFE_REG_NUM]; 4497 u32 rfa_backup[RF_REG_NUM]; 4498 u32 rfb_backup[RF_REG_NUM]; 4499 u32 backup_macbb_reg[MACBB_REG_NUM] = { 4500 0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50, 4501 0xe00, 0xe50, 0x838, 0x82c 4502 }; 4503 u32 backup_afe_reg[AFE_REG_NUM] = { 4504 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 4505 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8 4506 }; 4507 u32 backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0}; 4508 4509 _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, 4510 MACBB_REG_NUM); 4511 _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM); 4512 _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, 4513 RF_REG_NUM); 4514 4515 _rtl8821ae_iqk_configure_mac(hw); 4516 _rtl8821ae_iqk_tx(hw, RF90_PATH_A); 4517 _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, 4518 RF_REG_NUM); 4519 4520 _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM); 4521 _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, 4522 MACBB_REG_NUM); 4523 } 4524 4525 static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main) 4526 { 4527 struct rtl_priv *rtlpriv = rtl_priv(hw); 4528 /* struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); */ 4529 /* struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); */ 4530 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 4531 4532 if (main) 4533 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1); 4534 else 4535 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2); 4536 } 4537 4538 #undef IQK_ADDA_REG_NUM 4539 #undef IQK_DELAY_TIME 4540 4541 void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 4542 { 4543 } 4544 4545 void rtl8812ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index, 4546 u8 thermal_value, u8 threshold) 4547 { 4548 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 4549 4550 rtldm->thermalvalue_iqk = thermal_value; 4551 rtl8812ae_phy_iq_calibrate(hw, false); 4552 } 4553 4554 void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 4555 { 4556 struct rtl_priv *rtlpriv = rtl_priv(hw); 4557 struct rtl_phy *rtlphy = &rtlpriv->phy; 4558 4559 if (!rtlphy->lck_inprogress) { 4560 spin_lock(&rtlpriv->locks.iqk_lock); 4561 rtlphy->lck_inprogress = true; 4562 spin_unlock(&rtlpriv->locks.iqk_lock); 4563 4564 _rtl8821ae_phy_iq_calibrate(hw); 4565 4566 spin_lock(&rtlpriv->locks.iqk_lock); 4567 rtlphy->lck_inprogress = false; 4568 spin_unlock(&rtlpriv->locks.iqk_lock); 4569 } 4570 } 4571 4572 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw) 4573 { 4574 struct rtl_priv *rtlpriv = rtl_priv(hw); 4575 struct rtl_phy *rtlphy = &rtlpriv->phy; 4576 u8 i; 4577 4578 rtl_dbg(rtlpriv, COMP_IQK, DBG_LOUD, 4579 "rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n", 4580 (int)(sizeof(rtlphy->iqk_matrix) / 4581 sizeof(struct iqk_matrix_regs)), 4582 IQK_MATRIX_SETTINGS_NUM); 4583 4584 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { 4585 rtlphy->iqk_matrix[i].value[0][0] = 0x100; 4586 rtlphy->iqk_matrix[i].value[0][2] = 0x100; 4587 rtlphy->iqk_matrix[i].value[0][4] = 0x100; 4588 rtlphy->iqk_matrix[i].value[0][6] = 0x100; 4589 4590 rtlphy->iqk_matrix[i].value[0][1] = 0x0; 4591 rtlphy->iqk_matrix[i].value[0][3] = 0x0; 4592 rtlphy->iqk_matrix[i].value[0][5] = 0x0; 4593 rtlphy->iqk_matrix[i].value[0][7] = 0x0; 4594 4595 rtlphy->iqk_matrix[i].iqk_done = false; 4596 } 4597 } 4598 4599 void rtl8821ae_do_iqk(struct ieee80211_hw *hw, u8 delta_thermal_index, 4600 u8 thermal_value, u8 threshold) 4601 { 4602 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 4603 4604 rtl8821ae_reset_iqk_result(hw); 4605 4606 rtldm->thermalvalue_iqk = thermal_value; 4607 rtl8821ae_phy_iq_calibrate(hw, false); 4608 } 4609 4610 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw) 4611 { 4612 } 4613 4614 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) 4615 { 4616 } 4617 4618 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 4619 { 4620 _rtl8821ae_phy_set_rfpath_switch(hw, bmain); 4621 } 4622 4623 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 4624 { 4625 struct rtl_priv *rtlpriv = rtl_priv(hw); 4626 struct rtl_phy *rtlphy = &rtlpriv->phy; 4627 bool postprocessing = false; 4628 4629 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4630 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 4631 iotype, rtlphy->set_io_inprogress); 4632 do { 4633 switch (iotype) { 4634 case IO_CMD_RESUME_DM_BY_SCAN: 4635 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4636 "[IO CMD] Resume DM after scan.\n"); 4637 postprocessing = true; 4638 break; 4639 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 4640 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN: 4641 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4642 "[IO CMD] Pause DM before scan.\n"); 4643 postprocessing = true; 4644 break; 4645 default: 4646 pr_err("switch case %#x not processed\n", 4647 iotype); 4648 break; 4649 } 4650 } while (false); 4651 if (postprocessing && !rtlphy->set_io_inprogress) { 4652 rtlphy->set_io_inprogress = true; 4653 rtlphy->current_io_type = iotype; 4654 } else { 4655 return false; 4656 } 4657 rtl8821ae_phy_set_io(hw); 4658 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 4659 return true; 4660 } 4661 4662 static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw) 4663 { 4664 struct rtl_priv *rtlpriv = rtl_priv(hw); 4665 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 4666 struct rtl_phy *rtlphy = &rtlpriv->phy; 4667 4668 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4669 "--->Cmd(%#x), set_io_inprogress(%d)\n", 4670 rtlphy->current_io_type, rtlphy->set_io_inprogress); 4671 switch (rtlphy->current_io_type) { 4672 case IO_CMD_RESUME_DM_BY_SCAN: 4673 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) 4674 _rtl8821ae_resume_tx_beacon(hw); 4675 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); 4676 rtl8821ae_dm_write_cck_cca_thres(hw, 4677 rtlphy->initgain_backup.cca); 4678 break; 4679 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 4680 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) 4681 _rtl8821ae_stop_tx_beacon(hw); 4682 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 4683 rtl8821ae_dm_write_dig(hw, 0x17); 4684 rtlphy->initgain_backup.cca = dm_digtable->cur_cck_cca_thres; 4685 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40); 4686 break; 4687 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN: 4688 break; 4689 default: 4690 pr_err("switch case %#x not processed\n", 4691 rtlphy->current_io_type); 4692 break; 4693 } 4694 rtlphy->set_io_inprogress = false; 4695 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 4696 "(%#x)\n", rtlphy->current_io_type); 4697 } 4698 4699 static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw) 4700 { 4701 struct rtl_priv *rtlpriv = rtl_priv(hw); 4702 4703 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 4704 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 4705 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 4706 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 4707 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 4708 } 4709 4710 static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 4711 enum rf_pwrstate rfpwr_state) 4712 { 4713 struct rtl_priv *rtlpriv = rtl_priv(hw); 4714 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 4715 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 4716 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 4717 bool bresult = true; 4718 u8 i, queue_id; 4719 struct rtl8192_tx_ring *ring = NULL; 4720 4721 switch (rfpwr_state) { 4722 case ERFON: 4723 if ((ppsc->rfpwr_state == ERFOFF) && 4724 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 4725 bool rtstatus = false; 4726 u32 initializecount = 0; 4727 4728 do { 4729 initializecount++; 4730 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 4731 "IPS Set eRf nic enable\n"); 4732 rtstatus = rtl_ps_enable_nic(hw); 4733 } while (!rtstatus && (initializecount < 10)); 4734 RT_CLEAR_PS_LEVEL(ppsc, 4735 RT_RF_OFF_LEVL_HALT_NIC); 4736 } else { 4737 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 4738 "Set ERFON slept:%d ms\n", 4739 jiffies_to_msecs(jiffies - 4740 ppsc->last_sleep_jiffies)); 4741 ppsc->last_awake_jiffies = jiffies; 4742 rtl8821ae_phy_set_rf_on(hw); 4743 } 4744 if (mac->link_state == MAC80211_LINKED) { 4745 rtlpriv->cfg->ops->led_control(hw, 4746 LED_CTL_LINK); 4747 } else { 4748 rtlpriv->cfg->ops->led_control(hw, 4749 LED_CTL_NO_LINK); 4750 } 4751 break; 4752 case ERFOFF: 4753 for (queue_id = 0, i = 0; 4754 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 4755 ring = &pcipriv->dev.tx_ring[queue_id]; 4756 if (queue_id == BEACON_QUEUE || 4757 skb_queue_len(&ring->queue) == 0) { 4758 queue_id++; 4759 continue; 4760 } else { 4761 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 4762 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 4763 (i + 1), queue_id, 4764 skb_queue_len(&ring->queue)); 4765 4766 udelay(10); 4767 i++; 4768 } 4769 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 4770 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 4771 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 4772 MAX_DOZE_WAITING_TIMES_9x, 4773 queue_id, 4774 skb_queue_len(&ring->queue)); 4775 break; 4776 } 4777 } 4778 4779 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 4780 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 4781 "IPS Set eRf nic disable\n"); 4782 rtl_ps_disable_nic(hw); 4783 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 4784 } else { 4785 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 4786 rtlpriv->cfg->ops->led_control(hw, 4787 LED_CTL_NO_LINK); 4788 } else { 4789 rtlpriv->cfg->ops->led_control(hw, 4790 LED_CTL_POWER_OFF); 4791 } 4792 } 4793 break; 4794 default: 4795 pr_err("switch case %#x not processed\n", 4796 rfpwr_state); 4797 bresult = false; 4798 break; 4799 } 4800 if (bresult) 4801 ppsc->rfpwr_state = rfpwr_state; 4802 return bresult; 4803 } 4804 4805 bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw, 4806 enum rf_pwrstate rfpwr_state) 4807 { 4808 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 4809 4810 bool bresult = false; 4811 4812 if (rfpwr_state == ppsc->rfpwr_state) 4813 return bresult; 4814 bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state); 4815 return bresult; 4816 } 4817