1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 #include "../pwrseqcmd.h" 41 #include "pwrseq.h" 42 #include "../btcoexist/rtl_btc.h" 43 44 #define LLT_CONFIG 5 45 46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 51 unsigned long flags; 52 53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 54 while (skb_queue_len(&ring->queue)) { 55 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 56 struct sk_buff *skb = __skb_dequeue(&ring->queue); 57 58 pci_unmap_single(rtlpci->pdev, 59 rtlpriv->cfg->ops->get_desc( 60 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 61 skb->len, PCI_DMA_TODEVICE); 62 kfree_skb(skb); 63 ring->idx = (ring->idx + 1) % ring->entries; 64 } 65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 66 } 67 68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 69 u8 set_bits, u8 clear_bits) 70 { 71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 74 rtlpci->reg_bcn_ctrl_val |= set_bits; 75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 76 77 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 78 } 79 80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw) 81 { 82 struct rtl_priv *rtlpriv = rtl_priv(hw); 83 u8 tmp1byte; 84 85 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 86 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 89 tmp1byte &= ~(BIT(0)); 90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 91 } 92 93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw) 94 { 95 struct rtl_priv *rtlpriv = rtl_priv(hw); 96 u8 tmp1byte; 97 98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 101 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 102 tmp1byte |= BIT(0); 103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 104 } 105 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw) 107 { 108 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); 109 } 110 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw) 112 { 113 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0); 114 } 115 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw, 117 u8 rpwm_val, bool b_need_turn_off_ckk) 118 { 119 struct rtl_priv *rtlpriv = rtl_priv(hw); 120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 121 bool b_support_remote_wake_up; 122 u32 count = 0, isr_regaddr, content; 123 bool b_schedule_timer = b_need_turn_off_ckk; 124 125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 126 (u8 *)(&b_support_remote_wake_up)); 127 128 if (!rtlhal->fw_ready) 129 return; 130 if (!rtlpriv->psc.fw_current_inpsmode) 131 return; 132 133 while (1) { 134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 135 if (rtlhal->fw_clk_change_in_progress) { 136 while (rtlhal->fw_clk_change_in_progress) { 137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 138 count++; 139 udelay(100); 140 if (count > 1000) 141 goto change_done; 142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 143 } 144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 145 } else { 146 rtlhal->fw_clk_change_in_progress = false; 147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 148 goto change_done; 149 } 150 } 151 change_done: 152 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) { 153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 154 (u8 *)(&rpwm_val)); 155 if (FW_PS_IS_ACK(rpwm_val)) { 156 isr_regaddr = REG_HISR; 157 content = rtl_read_dword(rtlpriv, isr_regaddr); 158 while (!(content & IMR_CPWM) && (count < 500)) { 159 udelay(50); 160 count++; 161 content = rtl_read_dword(rtlpriv, isr_regaddr); 162 } 163 164 if (content & IMR_CPWM) { 165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE; 167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 168 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n", 169 rtlhal->fw_ps_state); 170 } 171 } 172 173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 174 rtlhal->fw_clk_change_in_progress = false; 175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 176 if (b_schedule_timer) 177 mod_timer(&rtlpriv->works.fw_clockoff_timer, 178 jiffies + MSECS(10)); 179 } else { 180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 181 rtlhal->fw_clk_change_in_progress = false; 182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 183 } 184 } 185 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw, 187 u8 rpwm_val) 188 { 189 struct rtl_priv *rtlpriv = rtl_priv(hw); 190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 192 struct rtl8192_tx_ring *ring; 193 enum rf_pwrstate rtstate; 194 bool b_schedule_timer = false; 195 u8 queue; 196 197 if (!rtlhal->fw_ready) 198 return; 199 if (!rtlpriv->psc.fw_current_inpsmode) 200 return; 201 if (!rtlhal->allow_sw_to_change_hwclc) 202 return; 203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 205 return; 206 207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 208 ring = &rtlpci->tx_ring[queue]; 209 if (skb_queue_len(&ring->queue)) { 210 b_schedule_timer = true; 211 break; 212 } 213 } 214 215 if (b_schedule_timer) { 216 mod_timer(&rtlpriv->works.fw_clockoff_timer, 217 jiffies + MSECS(10)); 218 return; 219 } 220 221 if (FW_PS_STATE(rtlhal->fw_ps_state) != 222 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) { 223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 224 if (!rtlhal->fw_clk_change_in_progress) { 225 rtlhal->fw_clk_change_in_progress = true; 226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 228 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 230 (u8 *)(&rpwm_val)); 231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 232 rtlhal->fw_clk_change_in_progress = false; 233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 234 } else { 235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 236 mod_timer(&rtlpriv->works.fw_clockoff_timer, 237 jiffies + MSECS(10)); 238 } 239 } 240 } 241 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw) 243 { 244 u8 rpwm_val = 0; 245 246 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK); 247 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true); 248 } 249 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw) 251 { 252 struct rtl_priv *rtlpriv = rtl_priv(hw); 253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 255 bool fw_current_inps = false; 256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 257 258 if (ppsc->low_power_enable) { 259 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */ 260 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false); 261 rtlhal->allow_sw_to_change_hwclc = false; 262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 263 (u8 *)(&fw_pwrmode)); 264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 265 (u8 *)(&fw_current_inps)); 266 } else { 267 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */ 268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 269 (u8 *)(&rpwm_val)); 270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 271 (u8 *)(&fw_pwrmode)); 272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 273 (u8 *)(&fw_current_inps)); 274 } 275 } 276 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw) 278 { 279 struct rtl_priv *rtlpriv = rtl_priv(hw); 280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 282 bool fw_current_inps = true; 283 u8 rpwm_val; 284 285 if (ppsc->low_power_enable) { 286 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */ 287 rtlpriv->cfg->ops->set_hw_reg(hw, 288 HW_VAR_FW_PSMODE_STATUS, 289 (u8 *)(&fw_current_inps)); 290 rtlpriv->cfg->ops->set_hw_reg(hw, 291 HW_VAR_H2C_FW_PWRMODE, 292 (u8 *)(&ppsc->fwctrl_psmode)); 293 rtlhal->allow_sw_to_change_hwclc = true; 294 _rtl8821ae_set_fw_clock_off(hw, rpwm_val); 295 } else { 296 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */ 297 rtlpriv->cfg->ops->set_hw_reg(hw, 298 HW_VAR_FW_PSMODE_STATUS, 299 (u8 *)(&fw_current_inps)); 300 rtlpriv->cfg->ops->set_hw_reg(hw, 301 HW_VAR_H2C_FW_PWRMODE, 302 (u8 *)(&ppsc->fwctrl_psmode)); 303 rtlpriv->cfg->ops->set_hw_reg(hw, 304 HW_VAR_SET_RPWM, 305 (u8 *)(&rpwm_val)); 306 } 307 } 308 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw, 310 bool dl_whole_packets) 311 { 312 struct rtl_priv *rtlpriv = rtl_priv(hw); 313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 314 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 315 u8 count = 0, dlbcn_count = 0; 316 bool send_beacon = false; 317 318 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 319 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0))); 320 321 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 322 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 323 324 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 325 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 326 tmp_reg422 & (~BIT(6))); 327 if (tmp_reg422 & BIT(6)) 328 send_beacon = true; 329 330 do { 331 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 332 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 333 (bcnvalid_reg | BIT(0))); 334 _rtl8821ae_return_beacon_queue_skb(hw); 335 336 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 337 rtl8812ae_set_fw_rsvdpagepkt(hw, false, 338 dl_whole_packets); 339 else 340 rtl8821ae_set_fw_rsvdpagepkt(hw, false, 341 dl_whole_packets); 342 343 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 344 count = 0; 345 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 346 count++; 347 udelay(10); 348 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 349 } 350 dlbcn_count++; 351 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 352 353 if (!(bcnvalid_reg & BIT(0))) 354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 355 "Download RSVD page failed!\n"); 356 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) { 357 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0)); 358 _rtl8821ae_return_beacon_queue_skb(hw); 359 if (send_beacon) { 360 dlbcn_count = 0; 361 do { 362 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 363 bcnvalid_reg | BIT(0)); 364 365 _rtl8821ae_return_beacon_queue_skb(hw); 366 367 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 368 rtl8812ae_set_fw_rsvdpagepkt(hw, true, 369 false); 370 else 371 rtl8821ae_set_fw_rsvdpagepkt(hw, true, 372 false); 373 374 /* check rsvd page download OK. */ 375 bcnvalid_reg = rtl_read_byte(rtlpriv, 376 REG_TDECTRL + 2); 377 count = 0; 378 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 379 count++; 380 udelay(10); 381 bcnvalid_reg = 382 rtl_read_byte(rtlpriv, 383 REG_TDECTRL + 2); 384 } 385 dlbcn_count++; 386 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 387 388 if (!(bcnvalid_reg & BIT(0))) 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 390 "2 Download RSVD page failed!\n"); 391 } 392 } 393 394 if (bcnvalid_reg & BIT(0)) 395 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); 396 397 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 398 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 399 400 if (send_beacon) 401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 402 403 if (!rtlhal->enter_pnp_sleep) { 404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); 406 } 407 } 408 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 410 { 411 struct rtl_priv *rtlpriv = rtl_priv(hw); 412 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 414 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 415 416 switch (variable) { 417 case HW_VAR_ETHER_ADDR: 418 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID); 419 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4); 420 break; 421 case HW_VAR_BSSID: 422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID); 423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4); 424 break; 425 case HW_VAR_MEDIA_STATUS: 426 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3; 427 break; 428 case HW_VAR_SLOT_TIME: 429 *((u8 *)(val)) = mac->slot_time; 430 break; 431 case HW_VAR_BEACON_INTERVAL: 432 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL); 433 break; 434 case HW_VAR_ATIM_WINDOW: 435 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND); 436 break; 437 case HW_VAR_RCR: 438 *((u32 *)(val)) = rtlpci->receive_config; 439 break; 440 case HW_VAR_RF_STATE: 441 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 442 break; 443 case HW_VAR_FWLPS_RF_ON:{ 444 enum rf_pwrstate rfstate; 445 u32 val_rcr; 446 447 rtlpriv->cfg->ops->get_hw_reg(hw, 448 HW_VAR_RF_STATE, 449 (u8 *)(&rfstate)); 450 if (rfstate == ERFOFF) { 451 *((bool *)(val)) = true; 452 } else { 453 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 454 val_rcr &= 0x00070000; 455 if (val_rcr) 456 *((bool *)(val)) = false; 457 else 458 *((bool *)(val)) = true; 459 } 460 break; } 461 case HW_VAR_FW_PSMODE_STATUS: 462 *((bool *)(val)) = ppsc->fw_current_inpsmode; 463 break; 464 case HW_VAR_CORRECT_TSF:{ 465 u64 tsf; 466 u32 *ptsf_low = (u32 *)&tsf; 467 u32 *ptsf_high = ((u32 *)&tsf) + 1; 468 469 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 470 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 471 472 *((u64 *)(val)) = tsf; 473 474 break; } 475 case HAL_DEF_WOWLAN: 476 if (ppsc->wo_wlan_mode) 477 *((bool *)(val)) = true; 478 else 479 *((bool *)(val)) = false; 480 break; 481 default: 482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 483 "switch case %#x not processed\n", variable); 484 break; 485 } 486 } 487 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 489 { 490 struct rtl_priv *rtlpriv = rtl_priv(hw); 491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 494 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 496 u8 idx; 497 498 switch (variable) { 499 case HW_VAR_ETHER_ADDR:{ 500 for (idx = 0; idx < ETH_ALEN; idx++) { 501 rtl_write_byte(rtlpriv, (REG_MACID + idx), 502 val[idx]); 503 } 504 break; 505 } 506 case HW_VAR_BASIC_RATE:{ 507 u16 b_rate_cfg = ((u16 *)val)[0]; 508 b_rate_cfg = b_rate_cfg & 0x15f; 509 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg); 510 break; 511 } 512 case HW_VAR_BSSID:{ 513 for (idx = 0; idx < ETH_ALEN; idx++) { 514 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 515 val[idx]); 516 } 517 break; 518 } 519 case HW_VAR_SIFS: 520 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 521 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]); 522 523 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 524 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 525 526 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]); 528 break; 529 case HW_VAR_R2T_SIFS: 530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 531 break; 532 case HW_VAR_SLOT_TIME:{ 533 u8 e_aci; 534 535 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 536 "HW_VAR_SLOT_TIME %x\n", val[0]); 537 538 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 539 540 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 541 rtlpriv->cfg->ops->set_hw_reg(hw, 542 HW_VAR_AC_PARAM, 543 (u8 *)(&e_aci)); 544 } 545 break; } 546 case HW_VAR_ACK_PREAMBLE:{ 547 u8 reg_tmp; 548 u8 short_preamble = (bool)(*(u8 *)val); 549 550 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 551 if (short_preamble) { 552 reg_tmp |= BIT(1); 553 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, 554 reg_tmp); 555 } else { 556 reg_tmp &= (~BIT(1)); 557 rtl_write_byte(rtlpriv, 558 REG_TRXPTCL_CTL + 2, 559 reg_tmp); 560 } 561 break; } 562 case HW_VAR_WPA_CONFIG: 563 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 564 break; 565 case HW_VAR_AMPDU_MIN_SPACE:{ 566 u8 min_spacing_to_set; 567 u8 sec_min_space; 568 569 min_spacing_to_set = *((u8 *)val); 570 if (min_spacing_to_set <= 7) { 571 sec_min_space = 0; 572 573 if (min_spacing_to_set < sec_min_space) 574 min_spacing_to_set = sec_min_space; 575 576 mac->min_space_cfg = ((mac->min_space_cfg & 577 0xf8) | 578 min_spacing_to_set); 579 580 *val = min_spacing_to_set; 581 582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 584 mac->min_space_cfg); 585 586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 587 mac->min_space_cfg); 588 } 589 break; } 590 case HW_VAR_SHORTGI_DENSITY:{ 591 u8 density_to_set; 592 593 density_to_set = *((u8 *)val); 594 mac->min_space_cfg |= (density_to_set << 3); 595 596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 598 mac->min_space_cfg); 599 600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 601 mac->min_space_cfg); 602 603 break; } 604 case HW_VAR_AMPDU_FACTOR:{ 605 u32 ampdu_len = (*((u8 *)val)); 606 607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 608 if (ampdu_len < VHT_AGG_SIZE_128K) 609 ampdu_len = 610 (0x2000 << (*((u8 *)val))) - 1; 611 else 612 ampdu_len = 0x1ffff; 613 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 614 if (ampdu_len < HT_AGG_SIZE_64K) 615 ampdu_len = 616 (0x2000 << (*((u8 *)val))) - 1; 617 else 618 ampdu_len = 0xffff; 619 } 620 ampdu_len |= BIT(31); 621 622 rtl_write_dword(rtlpriv, 623 REG_AMPDU_MAX_LENGTH_8812, ampdu_len); 624 break; } 625 case HW_VAR_AC_PARAM:{ 626 u8 e_aci = *((u8 *)val); 627 628 rtl8821ae_dm_init_edca_turbo(hw); 629 if (rtlpci->acm_method != EACMWAY2_SW) 630 rtlpriv->cfg->ops->set_hw_reg(hw, 631 HW_VAR_ACM_CTRL, 632 (u8 *)(&e_aci)); 633 break; } 634 case HW_VAR_ACM_CTRL:{ 635 u8 e_aci = *((u8 *)val); 636 union aci_aifsn *p_aci_aifsn = 637 (union aci_aifsn *)(&mac->ac[0].aifs); 638 u8 acm = p_aci_aifsn->f.acm; 639 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 640 641 acm_ctrl = 642 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 643 644 if (acm) { 645 switch (e_aci) { 646 case AC0_BE: 647 acm_ctrl |= ACMHW_BEQEN; 648 break; 649 case AC2_VI: 650 acm_ctrl |= ACMHW_VIQEN; 651 break; 652 case AC3_VO: 653 acm_ctrl |= ACMHW_VOQEN; 654 break; 655 default: 656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 657 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 658 acm); 659 break; 660 } 661 } else { 662 switch (e_aci) { 663 case AC0_BE: 664 acm_ctrl &= (~ACMHW_BEQEN); 665 break; 666 case AC2_VI: 667 acm_ctrl &= (~ACMHW_VIQEN); 668 break; 669 case AC3_VO: 670 acm_ctrl &= (~ACMHW_VOQEN); 671 break; 672 default: 673 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 674 "switch case %#x not processed\n", 675 e_aci); 676 break; 677 } 678 } 679 680 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 681 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 682 acm_ctrl); 683 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 684 break; } 685 case HW_VAR_RCR: 686 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 687 rtlpci->receive_config = ((u32 *)(val))[0]; 688 break; 689 case HW_VAR_RETRY_LIMIT:{ 690 u8 retry_limit = ((u8 *)(val))[0]; 691 692 rtl_write_word(rtlpriv, REG_RL, 693 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 694 retry_limit << RETRY_LIMIT_LONG_SHIFT); 695 break; } 696 case HW_VAR_DUAL_TSF_RST: 697 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 698 break; 699 case HW_VAR_EFUSE_BYTES: 700 rtlefuse->efuse_usedbytes = *((u16 *)val); 701 break; 702 case HW_VAR_EFUSE_USAGE: 703 rtlefuse->efuse_usedpercentage = *((u8 *)val); 704 break; 705 case HW_VAR_IO_CMD: 706 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); 707 break; 708 case HW_VAR_SET_RPWM:{ 709 u8 rpwm_val; 710 711 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 712 udelay(1); 713 714 if (rpwm_val & BIT(7)) { 715 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 716 (*(u8 *)val)); 717 } else { 718 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 719 ((*(u8 *)val) | BIT(7))); 720 } 721 722 break; } 723 case HW_VAR_H2C_FW_PWRMODE: 724 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 725 break; 726 case HW_VAR_FW_PSMODE_STATUS: 727 ppsc->fw_current_inpsmode = *((bool *)val); 728 break; 729 case HW_VAR_INIT_RTS_RATE: 730 break; 731 case HW_VAR_RESUME_CLK_ON: 732 _rtl8821ae_set_fw_ps_rf_on(hw); 733 break; 734 case HW_VAR_FW_LPS_ACTION:{ 735 bool b_enter_fwlps = *((bool *)val); 736 737 if (b_enter_fwlps) 738 _rtl8821ae_fwlps_enter(hw); 739 else 740 _rtl8821ae_fwlps_leave(hw); 741 break; } 742 case HW_VAR_H2C_FW_JOINBSSRPT:{ 743 u8 mstatus = (*(u8 *)val); 744 745 if (mstatus == RT_MEDIA_CONNECT) { 746 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 747 NULL); 748 _rtl8821ae_download_rsvd_page(hw, false); 749 } 750 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus); 751 752 break; } 753 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 754 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 755 break; 756 case HW_VAR_AID:{ 757 u16 u2btmp; 758 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 759 u2btmp &= 0xC000; 760 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 761 mac->assoc_id)); 762 break; } 763 case HW_VAR_CORRECT_TSF:{ 764 u8 btype_ibss = ((u8 *)(val))[0]; 765 766 if (btype_ibss) 767 _rtl8821ae_stop_tx_beacon(hw); 768 769 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 770 771 rtl_write_dword(rtlpriv, REG_TSFTR, 772 (u32)(mac->tsf & 0xffffffff)); 773 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 774 (u32)((mac->tsf >> 32) & 0xffffffff)); 775 776 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 777 778 if (btype_ibss) 779 _rtl8821ae_resume_tx_beacon(hw); 780 break; } 781 case HW_VAR_NAV_UPPER: { 782 u32 us_nav_upper = ((u32)*val); 783 784 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) { 785 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING, 786 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", 787 us_nav_upper, HAL_92C_NAV_UPPER_UNIT); 788 break; 789 } 790 rtl_write_byte(rtlpriv, REG_NAV_UPPER, 791 ((u8)((us_nav_upper + 792 HAL_92C_NAV_UPPER_UNIT - 1) / 793 HAL_92C_NAV_UPPER_UNIT))); 794 break; } 795 case HW_VAR_KEEP_ALIVE: { 796 u8 array[2]; 797 array[0] = 0xff; 798 array[1] = *((u8 *)val); 799 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, 800 array); 801 break; } 802 default: 803 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 804 "switch case %#x not processed\n", variable); 805 break; 806 } 807 } 808 809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 810 { 811 struct rtl_priv *rtlpriv = rtl_priv(hw); 812 bool status = true; 813 long count = 0; 814 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 815 _LLT_OP(_LLT_WRITE_ACCESS); 816 817 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 818 819 do { 820 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 821 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 822 break; 823 824 if (count > POLLING_LLT_THRESHOLD) { 825 pr_err("Failed to polling write LLT done at address %d!\n", 826 address); 827 status = false; 828 break; 829 } 830 } while (++count); 831 832 return status; 833 } 834 835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw) 836 { 837 struct rtl_priv *rtlpriv = rtl_priv(hw); 838 unsigned short i; 839 u8 txpktbuf_bndy; 840 u32 rqpn; 841 u8 maxpage; 842 bool status; 843 844 maxpage = 255; 845 txpktbuf_bndy = 0xF8; 846 rqpn = 0x80e70808; 847 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) { 848 txpktbuf_bndy = 0xFA; 849 rqpn = 0x80e90808; 850 } 851 852 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 853 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1); 854 855 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 856 857 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 858 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 859 860 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 861 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 862 863 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 864 status = _rtl8821ae_llt_write(hw, i, i + 1); 865 if (!status) 866 return status; 867 } 868 869 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 870 if (!status) 871 return status; 872 873 for (i = txpktbuf_bndy; i < maxpage; i++) { 874 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 875 if (!status) 876 return status; 877 } 878 879 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy); 880 if (!status) 881 return status; 882 883 rtl_write_dword(rtlpriv, REG_RQPN, rqpn); 884 885 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00); 886 887 return true; 888 } 889 890 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw) 891 { 892 struct rtl_priv *rtlpriv = rtl_priv(hw); 893 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 894 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 895 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0; 896 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 897 898 if (rtlpriv->rtlhal.up_first_time) 899 return; 900 901 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 902 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 903 rtl8812ae_sw_led_on(hw, pled0); 904 else 905 rtl8821ae_sw_led_on(hw, pled0); 906 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 907 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 908 rtl8812ae_sw_led_on(hw, pled0); 909 else 910 rtl8821ae_sw_led_on(hw, pled0); 911 else 912 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 913 rtl8812ae_sw_led_off(hw, pled0); 914 else 915 rtl8821ae_sw_led_off(hw, pled0); 916 } 917 918 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw) 919 { 920 struct rtl_priv *rtlpriv = rtl_priv(hw); 921 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 923 924 u8 bytetmp = 0; 925 u16 wordtmp = 0; 926 bool mac_func_enable = rtlhal->mac_func_enable; 927 928 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 929 930 /*Auto Power Down to CHIP-off State*/ 931 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 932 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 933 934 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 935 /* HW Power on sequence*/ 936 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 937 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 938 RTL8812_NIC_ENABLE_FLOW)) { 939 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 940 "init 8812 MAC Fail as power on failure\n"); 941 return false; 942 } 943 } else { 944 /* HW Power on sequence */ 945 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, 946 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 947 RTL8821A_NIC_ENABLE_FLOW)){ 948 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 949 "init 8821 MAC Fail as power on failure\n"); 950 return false; 951 } 952 } 953 954 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 955 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 956 957 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 958 bytetmp = 0xff; 959 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 960 mdelay(2); 961 962 bytetmp = 0xff; 963 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 964 mdelay(2); 965 966 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 967 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 968 if (bytetmp & BIT(0)) { 969 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 970 bytetmp |= BIT(6); 971 rtl_write_byte(rtlpriv, 0x7c, bytetmp); 972 } 973 } 974 975 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 976 bytetmp &= ~BIT(4); 977 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp); 978 979 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 980 981 if (!mac_func_enable) { 982 if (!_rtl8821ae_llt_table_init(hw)) 983 return false; 984 } 985 986 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 987 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 988 989 /* Enable FW Beamformer Interrupt */ 990 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3); 991 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); 992 993 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 994 wordtmp &= 0xf; 995 wordtmp |= 0xF5B1; 996 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 997 998 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 999 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 1000 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 1001 /*low address*/ 1002 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 1003 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1004 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1005 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1006 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1007 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1008 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1009 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1010 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1011 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1012 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1013 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1014 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1015 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1016 rtl_write_dword(rtlpriv, REG_RX_DESA, 1017 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1018 1019 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 1020 1021 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 1022 1023 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0); 1024 1025 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 1026 _rtl8821ae_gen_refresh_led_state(hw); 1027 1028 return true; 1029 } 1030 1031 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw) 1032 { 1033 struct rtl_priv *rtlpriv = rtl_priv(hw); 1034 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1035 u32 reg_rrsr; 1036 1037 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 1038 1039 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 1040 /* ARFB table 9 for 11ac 5G 2SS */ 1041 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000); 1042 /* ARFB table 10 for 11ac 5G 1SS */ 1043 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000); 1044 /* ARFB table 11 for 11ac 24G 1SS */ 1045 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015); 1046 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000); 1047 /* ARFB table 12 for 11ac 24G 1SS */ 1048 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015); 1049 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000); 1050 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */ 1051 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00); 1052 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70); 1053 1054 /*Set retry limit*/ 1055 rtl_write_word(rtlpriv, REG_RL, 0x0707); 1056 1057 /* Set Data / Response auto rate fallack retry count*/ 1058 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 1059 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 1060 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 1061 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 1062 1063 rtlpci->reg_bcn_ctrl_val = 0x1d; 1064 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 1065 1066 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 1067 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1068 1069 /* AGGR_BK_TIME Reg51A 0x16 */ 1070 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 1071 1072 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 1073 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 1074 1075 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80); 1076 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1077 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F); 1078 } 1079 1080 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr) 1081 { 1082 u16 ret = 0; 1083 u8 tmp = 0, count = 0; 1084 1085 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); 1086 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1087 count = 0; 1088 while (tmp && count < 20) { 1089 udelay(10); 1090 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1091 count++; 1092 } 1093 if (0 == tmp) 1094 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA); 1095 1096 return ret; 1097 } 1098 1099 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data) 1100 { 1101 u8 tmp = 0, count = 0; 1102 1103 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data); 1104 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); 1105 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1106 count = 0; 1107 while (tmp && count < 20) { 1108 udelay(10); 1109 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1110 count++; 1111 } 1112 } 1113 1114 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr) 1115 { 1116 u16 read_addr = addr & 0xfffc; 1117 u8 tmp = 0, count = 0, ret = 0; 1118 1119 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr); 1120 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2); 1121 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1122 count = 0; 1123 while (tmp && count < 20) { 1124 udelay(10); 1125 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1126 count++; 1127 } 1128 if (0 == tmp) { 1129 read_addr = REG_DBI_RDATA + addr % 4; 1130 ret = rtl_read_byte(rtlpriv, read_addr); 1131 } 1132 return ret; 1133 } 1134 1135 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data) 1136 { 1137 u8 tmp = 0, count = 0; 1138 u16 wrtie_addr, remainder = addr % 4; 1139 1140 wrtie_addr = REG_DBI_WDATA + remainder; 1141 rtl_write_byte(rtlpriv, wrtie_addr, data); 1142 1143 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); 1144 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr); 1145 1146 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1); 1147 1148 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1149 count = 0; 1150 while (tmp && count < 20) { 1151 udelay(10); 1152 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1153 count++; 1154 } 1155 } 1156 1157 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw) 1158 { 1159 struct rtl_priv *rtlpriv = rtl_priv(hw); 1160 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1161 u8 tmp; 1162 1163 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1164 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544) 1165 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544); 1166 1167 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070) 1168 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070); 1169 } 1170 1171 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f); 1172 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7)); 1173 1174 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719); 1175 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4)); 1176 1177 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1178 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1179 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4)); 1180 } 1181 } 1182 1183 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw) 1184 { 1185 struct rtl_priv *rtlpriv = rtl_priv(hw); 1186 u8 sec_reg_value; 1187 u8 tmp; 1188 1189 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1190 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1191 rtlpriv->sec.pairwise_enc_algorithm, 1192 rtlpriv->sec.group_enc_algorithm); 1193 1194 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1195 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1196 "not open hw encryption\n"); 1197 return; 1198 } 1199 1200 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1201 1202 if (rtlpriv->sec.use_defaultkey) { 1203 sec_reg_value |= SCR_TXUSEDK; 1204 sec_reg_value |= SCR_RXUSEDK; 1205 } 1206 1207 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1208 1209 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1210 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1211 1212 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1213 "The SECR-value %x\n", sec_reg_value); 1214 1215 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1216 } 1217 1218 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */ 1219 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0 1220 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1 1221 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2 1222 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3 1223 /* ----------------------------------------------------------- */ 1224 1225 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw) 1226 { 1227 struct rtl_priv *rtlpriv = rtl_priv(hw); 1228 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1, 1229 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1230 MAC_ID_STATIC_FOR_BT_CLIENT_END}; 1231 1232 rtlpriv->cfg->ops->set_hw_reg(hw, 1233 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt); 1234 1235 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1236 "Initialize MacId media status: from %d to %d\n", 1237 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1238 MAC_ID_STATIC_FOR_BT_CLIENT_END); 1239 } 1240 1241 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw) 1242 { 1243 struct rtl_priv *rtlpriv = rtl_priv(hw); 1244 u8 tmp; 1245 1246 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1247 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1248 if (!(tmp & BIT(2))) { 1249 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); 1250 mdelay(100); 1251 } 1252 1253 /* read reg 0x350 Bit[25] if 1 : RX hang */ 1254 /* read reg 0x350 Bit[24] if 1 : TX hang */ 1255 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1256 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1257 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1258 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n"); 1259 return true; 1260 } else { 1261 return false; 1262 } 1263 } 1264 1265 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw, 1266 bool mac_power_on, 1267 bool in_watchdog) 1268 { 1269 struct rtl_priv *rtlpriv = rtl_priv(hw); 1270 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1271 u8 tmp; 1272 bool release_mac_rx_pause; 1273 u8 backup_pcie_dma_pause; 1274 1275 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1276 1277 /* 1. Disable register write lock. 0x1c[1] = 0 */ 1278 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1279 tmp &= ~(BIT(1)); 1280 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1281 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1282 /* write 0xCC bit[2] = 1'b1 */ 1283 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1284 tmp |= BIT(2); 1285 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1286 } 1287 1288 /* 2. Check and pause TRX DMA */ 1289 /* write 0x284 bit[18] = 1'b1 */ 1290 /* write 0x301 = 0xFF */ 1291 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1292 if (tmp & BIT(2)) { 1293 /* Already pause before the function for another purpose. */ 1294 release_mac_rx_pause = false; 1295 } else { 1296 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1297 release_mac_rx_pause = true; 1298 } 1299 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1300 if (backup_pcie_dma_pause != 0xFF) 1301 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1302 1303 if (mac_power_on) { 1304 /* 3. reset TRX function */ 1305 /* write 0x100 = 0x00 */ 1306 rtl_write_byte(rtlpriv, REG_CR, 0); 1307 } 1308 1309 /* 4. Reset PCIe DMA. 0x3[0] = 0 */ 1310 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1311 tmp &= ~(BIT(0)); 1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1313 1314 /* 5. Enable PCIe DMA. 0x3[0] = 1 */ 1315 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1316 tmp |= BIT(0); 1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1318 1319 if (mac_power_on) { 1320 /* 6. enable TRX function */ 1321 /* write 0x100 = 0xFF */ 1322 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1323 1324 /* We should init LLT & RQPN and 1325 * prepare Tx/Rx descrptor address later 1326 * because MAC function is reset.*/ 1327 } 1328 1329 /* 7. Restore PCIe autoload down bit */ 1330 /* 8812AE does not has the defination. */ 1331 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1332 /* write 0xF8 bit[17] = 1'b1 */ 1333 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1334 tmp |= BIT(1); 1335 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1336 } 1337 1338 /* In MAC power on state, BB and RF maybe in ON state, 1339 * if we release TRx DMA here. 1340 * it will cause packets to be started to Tx/Rx, 1341 * so we release Tx/Rx DMA later.*/ 1342 if (!mac_power_on/* || in_watchdog*/) { 1343 /* 8. release TRX DMA */ 1344 /* write 0x284 bit[18] = 1'b0 */ 1345 /* write 0x301 = 0x00 */ 1346 if (release_mac_rx_pause) { 1347 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1348 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1349 tmp & (~BIT(2))); 1350 } 1351 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1352 backup_pcie_dma_pause); 1353 } 1354 1355 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1356 /* 9. lock system register */ 1357 /* write 0xCC bit[2] = 1'b0 */ 1358 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1359 tmp &= ~(BIT(2)); 1360 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1361 } 1362 return true; 1363 } 1364 1365 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw) 1366 { 1367 struct rtl_priv *rtlpriv = rtl_priv(hw); 1368 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1369 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1370 u8 fw_reason = 0; 1371 struct timeval ts; 1372 1373 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN); 1374 1375 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n", 1376 fw_reason); 1377 1378 ppsc->wakeup_reason = 0; 1379 1380 rtlhal->last_suspend_sec = ts.tv_sec; 1381 1382 switch (fw_reason) { 1383 case FW_WOW_V2_PTK_UPDATE_EVENT: 1384 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE; 1385 do_gettimeofday(&ts); 1386 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000; 1387 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1388 "It's a WOL PTK Key update event!\n"); 1389 break; 1390 case FW_WOW_V2_GTK_UPDATE_EVENT: 1391 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE; 1392 do_gettimeofday(&ts); 1393 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000; 1394 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1395 "It's a WOL GTK Key update event!\n"); 1396 break; 1397 case FW_WOW_V2_DISASSOC_EVENT: 1398 ppsc->wakeup_reason = WOL_REASON_DISASSOC; 1399 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1400 "It's a disassociation event!\n"); 1401 break; 1402 case FW_WOW_V2_DEAUTH_EVENT: 1403 ppsc->wakeup_reason = WOL_REASON_DEAUTH; 1404 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1405 "It's a deauth event!\n"); 1406 break; 1407 case FW_WOW_V2_FW_DISCONNECT_EVENT: 1408 ppsc->wakeup_reason = WOL_REASON_AP_LOST; 1409 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1410 "It's a Fw disconnect decision (AP lost) event!\n"); 1411 break; 1412 case FW_WOW_V2_MAGIC_PKT_EVENT: 1413 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT; 1414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1415 "It's a magic packet event!\n"); 1416 break; 1417 case FW_WOW_V2_UNICAST_PKT_EVENT: 1418 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT; 1419 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1420 "It's an unicast packet event!\n"); 1421 break; 1422 case FW_WOW_V2_PATTERN_PKT_EVENT: 1423 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT; 1424 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1425 "It's a pattern match event!\n"); 1426 break; 1427 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT: 1428 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH; 1429 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1430 "It's an RTD3 Ssid match event!\n"); 1431 break; 1432 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT: 1433 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT; 1434 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1435 "It's an RealWoW wake packet event!\n"); 1436 break; 1437 case FW_WOW_V2_REALWOW_V2_ACKLOST: 1438 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST; 1439 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1440 "It's an RealWoW ack lost event!\n"); 1441 break; 1442 default: 1443 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1444 "WOL Read 0x1c7 = %02X, Unknown reason!\n", 1445 fw_reason); 1446 break; 1447 } 1448 } 1449 1450 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw) 1451 { 1452 struct rtl_priv *rtlpriv = rtl_priv(hw); 1453 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1454 1455 /*low address*/ 1456 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 1457 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1458 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1459 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1460 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1461 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1462 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1463 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1464 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1465 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1466 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1467 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1468 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1469 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1470 rtl_write_dword(rtlpriv, REG_RX_DESA, 1471 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1472 } 1473 1474 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 1475 { 1476 bool status = true; 1477 u32 i; 1478 u32 txpktbuf_bndy = boundary; 1479 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER; 1480 1481 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) { 1482 status = _rtl8821ae_llt_write(hw, i , i + 1); 1483 if (!status) 1484 return status; 1485 } 1486 1487 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 1488 if (!status) 1489 return status; 1490 1491 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) { 1492 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 1493 if (!status) 1494 return status; 1495 } 1496 1497 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf, 1498 txpktbuf_bndy); 1499 if (!status) 1500 return status; 1501 1502 return status; 1503 } 1504 1505 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary, 1506 u16 npq_rqpn_value, u32 rqpn_val) 1507 { 1508 struct rtl_priv *rtlpriv = rtl_priv(hw); 1509 u8 tmp; 1510 bool ret = true; 1511 u16 count = 0, tmp16; 1512 bool support_remote_wakeup; 1513 1514 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1515 (u8 *)(&support_remote_wakeup)); 1516 1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1518 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n", 1519 boundary, npq_rqpn_value, rqpn_val); 1520 1521 /* stop PCIe DMA 1522 * 1. 0x301[7:0] = 0xFE */ 1523 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1524 1525 /* wait TXFF empty 1526 * 2. polling till 0x41A[15:0]=0x07FF */ 1527 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1528 while ((tmp16 & 0x07FF) != 0x07FF) { 1529 udelay(100); 1530 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1531 count++; 1532 if ((count % 200) == 0) { 1533 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1534 "Tx queue is not empty for 20ms!\n"); 1535 } 1536 if (count >= 1000) { 1537 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1538 "Wait for Tx FIFO empty timeout!\n"); 1539 break; 1540 } 1541 } 1542 1543 /* TX pause 1544 * 3. reg 0x522=0xFF */ 1545 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1546 1547 /* Wait TX State Machine OK 1548 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */ 1549 count = 0; 1550 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) { 1551 udelay(100); 1552 count++; 1553 if (count >= 500) { 1554 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1555 "Wait for TX State Machine ready timeout !!\n"); 1556 break; 1557 } 1558 } 1559 1560 /* stop RX DMA path 1561 * 5. 0x284[18] = 1 1562 * 6. wait till 0x284[17] == 1 1563 * wait RX DMA idle */ 1564 count = 0; 1565 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1566 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1567 do { 1568 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1569 udelay(10); 1570 count++; 1571 } while (!(tmp & BIT(1)) && count < 100); 1572 1573 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1574 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n", 1575 count, tmp); 1576 1577 /* reset BB 1578 * 7. 0x02 [0] = 0 */ 1579 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1580 tmp &= ~(BIT(0)); 1581 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp); 1582 1583 /* Reset TRX MAC 1584 * 8. 0x100 = 0x00 1585 * Delay (1ms) */ 1586 rtl_write_byte(rtlpriv, REG_CR, 0x00); 1587 udelay(1000); 1588 1589 /* Disable MAC Security Engine 1590 * 9. 0x100 bit[9]=0 */ 1591 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1592 tmp &= ~(BIT(1)); 1593 rtl_write_byte(rtlpriv, REG_CR + 1, tmp); 1594 1595 /* To avoid DD-Tim Circuit hang 1596 * 10. 0x553 bit[5]=1 */ 1597 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST); 1598 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5))); 1599 1600 /* Enable MAC Security Engine 1601 * 11. 0x100 bit[9]=1 */ 1602 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1603 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1))); 1604 1605 /* Enable TRX MAC 1606 * 12. 0x100 = 0xFF 1607 * Delay (1ms) */ 1608 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1609 udelay(1000); 1610 1611 /* Enable BB 1612 * 13. 0x02 [0] = 1 */ 1613 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1614 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0))); 1615 1616 /* beacon setting 1617 * 14,15. set beacon head page (reg 0x209 and 0x424) */ 1618 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary); 1619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary); 1620 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary); 1621 1622 /* 16. WMAC_LBK_BF_HD 0x45D[7:0] 1623 * WMAC_LBK_BF_HD */ 1624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, 1625 (u8)boundary); 1626 1627 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary); 1628 1629 /* init LLT 1630 * 17. init LLT */ 1631 if (!_rtl8821ae_init_llt_table(hw, boundary)) { 1632 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 1633 "Failed to init LLT table!\n"); 1634 return false; 1635 } 1636 1637 /* reallocate RQPN 1638 * 18. reallocate RQPN and init LLT */ 1639 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value); 1640 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val); 1641 1642 /* release Tx pause 1643 * 19. 0x522=0x00 */ 1644 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1645 1646 /* enable PCIE DMA 1647 * 20. 0x301[7:0] = 0x00 1648 * 21. 0x284[18] = 0 */ 1649 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1650 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1651 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2))); 1652 1653 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n"); 1654 return ret; 1655 } 1656 1657 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw) 1658 { 1659 struct rtl_priv *rtlpriv = rtl_priv(hw); 1660 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1661 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1662 1663 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 1664 /* Re-download normal Fw. */ 1665 rtl8821ae_set_fw_related_for_wowlan(hw, false); 1666 #endif 1667 1668 /* Re-Initialize LLT table. */ 1669 if (rtlhal->re_init_llt_table) { 1670 u32 rqpn = 0x80e70808; 1671 u8 rqpn_npq = 0, boundary = 0xF8; 1672 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1673 rqpn = 0x80e90808; 1674 boundary = 0xFA; 1675 } 1676 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn)) 1677 rtlhal->re_init_llt_table = false; 1678 } 1679 1680 ppsc->rfpwr_state = ERFON; 1681 } 1682 1683 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw) 1684 { 1685 u8 tmp = 0; 1686 struct rtl_priv *rtlpriv = rtl_priv(hw); 1687 1688 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1689 1690 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160); 1691 if (!(tmp & (BIT(2) | BIT(3)))) { 1692 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD, 1693 "0x160(%#x)return!!\n", tmp); 1694 return; 1695 } 1696 1697 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b); 1698 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4))); 1699 1700 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1701 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5)); 1702 1703 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1704 } 1705 1706 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw) 1707 { 1708 u8 tmp = 0; 1709 struct rtl_priv *rtlpriv = rtl_priv(hw); 1710 1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1712 1713 /* Check 0x98[10] */ 1714 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99); 1715 if (!(tmp & BIT(2))) { 1716 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1717 "<---0x99(%#x) return!!\n", tmp); 1718 return; 1719 } 1720 1721 /* LTR idle latency, 0x90 for 144us */ 1722 rtl_write_dword(rtlpriv, 0x798, 0x88908890); 1723 1724 /* LTR active latency, 0x3c for 60us */ 1725 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c); 1726 1727 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1728 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4))); 1729 1730 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1731 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0)))); 1732 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0))); 1733 1734 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1735 } 1736 1737 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw) 1738 { 1739 struct rtl_priv *rtlpriv = rtl_priv(hw); 1740 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1741 bool init_finished = true; 1742 u8 tmp = 0; 1743 1744 /* Get Fw wake up reason. */ 1745 _rtl8821ae_get_wakeup_reason(hw); 1746 1747 /* Patch Pcie Rx DMA hang after S3/S4 several times. 1748 * The root cause has not be found. */ 1749 if (_rtl8821ae_check_pcie_dma_hang(hw)) 1750 _rtl8821ae_reset_pcie_interface_dma(hw, true, false); 1751 1752 /* Prepare Tx/Rx Desc Hw address. */ 1753 _rtl8821ae_init_trx_desc_hw_address(hw); 1754 1755 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */ 1756 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1757 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n"); 1758 1759 /* Check wake up event. 1760 * We should check wake packet bit before disable wowlan by H2C or 1761 * Fw will clear the bit. */ 1762 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3); 1763 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1764 "Read REG_FTISR 0x13f = %#X\n", tmp); 1765 1766 /* Set the WoWLAN related function control disable. */ 1767 rtl8821ae_set_fw_wowlan_mode(hw, false); 1768 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0); 1769 1770 if (rtlhal->hw_rof_enable) { 1771 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 1772 if (tmp & BIT(1)) { 1773 /* Clear GPIO9 ISR */ 1774 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 1775 init_finished = false; 1776 } else { 1777 init_finished = true; 1778 } 1779 } 1780 1781 if (init_finished) { 1782 _rtl8821ae_simple_initialize_adapter(hw); 1783 1784 /* Release Pcie Interface Tx DMA. */ 1785 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1786 /* Release Pcie RX DMA */ 1787 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02); 1788 1789 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1790 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0)))); 1791 1792 _rtl8821ae_enable_l1off(hw); 1793 _rtl8821ae_enable_ltr(hw); 1794 } 1795 1796 return init_finished; 1797 } 1798 1799 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw) 1800 { 1801 /* BB OFDM RX Path_A */ 1802 rtl_set_bbreg(hw, 0x808, 0xff, 0x11); 1803 /* BB OFDM TX Path_A */ 1804 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111); 1805 /* BB CCK R/Rx Path_A */ 1806 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0); 1807 /* MCS support */ 1808 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4); 1809 /* RF Path_B HSSI OFF */ 1810 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4); 1811 /* RF Path_B Power Down */ 1812 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0); 1813 /* ADDA Path_B OFF */ 1814 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0); 1815 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0); 1816 } 1817 1818 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw) 1819 { 1820 struct rtl_priv *rtlpriv = rtl_priv(hw); 1821 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1822 u8 u1b_tmp; 1823 1824 rtlhal->mac_func_enable = false; 1825 1826 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1827 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1828 /* 1. Run LPS WL RFOFF flow */ 1829 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1830 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"); 1831 */ 1832 rtl_hal_pwrseqcmdparsing(rtlpriv, 1833 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1834 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW); 1835 } 1836 /* 2. 0x1F[7:0] = 0 */ 1837 /* turn off RF */ 1838 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */ 1839 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1840 rtlhal->fw_ready) { 1841 rtl8821ae_firmware_selfreset(hw); 1842 } 1843 1844 /* Reset MCU. Suggested by Filen. */ 1845 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1846 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1847 1848 /* g. MCUFWDL 0x80[1:0]=0 */ 1849 /* reset MCU ready status */ 1850 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1851 1852 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1853 /* HW card disable configuration. */ 1854 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1855 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW); 1856 } else { 1857 /* HW card disable configuration. */ 1858 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1859 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW); 1860 } 1861 1862 /* Reset MCU IO Wrapper */ 1863 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1864 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1865 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1866 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1867 1868 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1869 /* lock ISO/CLK/Power control register */ 1870 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1871 } 1872 1873 int rtl8821ae_hw_init(struct ieee80211_hw *hw) 1874 { 1875 struct rtl_priv *rtlpriv = rtl_priv(hw); 1876 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1877 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1878 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1879 bool rtstatus = true; 1880 int err; 1881 u8 tmp_u1b; 1882 bool support_remote_wakeup; 1883 u32 nav_upper = WIFI_NAV_UPPER_US; 1884 1885 rtlhal->being_init_adapter = true; 1886 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1887 (u8 *)(&support_remote_wakeup)); 1888 rtlpriv->intf_ops->disable_aspm(hw); 1889 1890 /*YP wowlan not considered*/ 1891 1892 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR); 1893 if (tmp_u1b != 0 && tmp_u1b != 0xEA) { 1894 rtlhal->mac_func_enable = true; 1895 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1896 "MAC has already power on.\n"); 1897 } else { 1898 rtlhal->mac_func_enable = false; 1899 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1900 } 1901 1902 if (support_remote_wakeup && 1903 rtlhal->wake_from_pnp_sleep && 1904 rtlhal->mac_func_enable) { 1905 if (_rtl8821ae_wowlan_initialize_adapter(hw)) { 1906 rtlhal->being_init_adapter = false; 1907 return 0; 1908 } 1909 } 1910 1911 if (_rtl8821ae_check_pcie_dma_hang(hw)) { 1912 _rtl8821ae_reset_pcie_interface_dma(hw, 1913 rtlhal->mac_func_enable, 1914 false); 1915 rtlhal->mac_func_enable = false; 1916 } 1917 1918 /* Reset MAC/BB/RF status if it is not powered off 1919 * before calling initialize Hw flow to prevent 1920 * from interface and MAC status mismatch. 1921 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */ 1922 if (rtlhal->mac_func_enable) { 1923 _rtl8821ae_poweroff_adapter(hw); 1924 rtlhal->mac_func_enable = false; 1925 } 1926 1927 rtstatus = _rtl8821ae_init_mac(hw); 1928 if (rtstatus != true) { 1929 pr_err("Init MAC failed\n"); 1930 err = 1; 1931 return err; 1932 } 1933 1934 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1935 tmp_u1b &= 0x7F; 1936 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b); 1937 1938 err = rtl8821ae_download_fw(hw, false); 1939 if (err) { 1940 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1941 "Failed to download FW. Init HW without FW now\n"); 1942 err = 1; 1943 rtlhal->fw_ready = false; 1944 return err; 1945 } else { 1946 rtlhal->fw_ready = true; 1947 } 1948 ppsc->fw_current_inpsmode = false; 1949 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1950 rtlhal->fw_clk_change_in_progress = false; 1951 rtlhal->allow_sw_to_change_hwclc = false; 1952 rtlhal->last_hmeboxnum = 0; 1953 1954 /*SIC_Init(Adapter); 1955 if(rtlhal->AMPDUBurstMode) 1956 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/ 1957 1958 rtl8821ae_phy_mac_config(hw); 1959 /* because last function modify RCR, so we update 1960 * rcr var here, or TP will unstable for receive_config 1961 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1962 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1963 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1964 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1965 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/ 1966 rtl8821ae_phy_bb_config(hw); 1967 1968 rtl8821ae_phy_rf_config(hw); 1969 1970 if (rtlpriv->phy.rf_type == RF_1T1R && 1971 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 1972 _rtl8812ae_bb8812_config_1t(hw); 1973 1974 _rtl8821ae_hw_configure(hw); 1975 1976 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 1977 1978 /*set wireless mode*/ 1979 1980 rtlhal->mac_func_enable = true; 1981 1982 rtl_cam_reset_all_entry(hw); 1983 1984 rtl8821ae_enable_hw_security_config(hw); 1985 1986 ppsc->rfpwr_state = ERFON; 1987 1988 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1989 _rtl8821ae_enable_aspm_back_door(hw); 1990 rtlpriv->intf_ops->enable_aspm(hw); 1991 1992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 1993 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5)) 1994 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302); 1995 1996 rtl8821ae_bt_hw_init(hw); 1997 rtlpriv->rtlhal.being_init_adapter = false; 1998 1999 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper); 2000 2001 /* rtl8821ae_dm_check_txpower_tracking(hw); */ 2002 /* rtl8821ae_phy_lc_calibrate(hw); */ 2003 if (support_remote_wakeup) 2004 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0); 2005 2006 /* Release Rx DMA*/ 2007 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2008 if (tmp_u1b & BIT(2)) { 2009 /* Release Rx DMA if needed*/ 2010 tmp_u1b &= ~BIT(2); 2011 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b); 2012 } 2013 2014 /* Release Tx/Rx PCIE DMA if*/ 2015 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0); 2016 2017 rtl8821ae_dm_init(hw); 2018 rtl8821ae_macid_initialize_mediastatus(hw); 2019 2020 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n"); 2021 return err; 2022 } 2023 2024 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw) 2025 { 2026 struct rtl_priv *rtlpriv = rtl_priv(hw); 2027 struct rtl_phy *rtlphy = &rtlpriv->phy; 2028 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2029 enum version_8821ae version = VERSION_UNKNOWN; 2030 u32 value32; 2031 2032 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 2033 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2034 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32); 2035 2036 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 2037 rtlphy->rf_type = RF_2T2R; 2038 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) 2039 rtlphy->rf_type = RF_1T1R; 2040 2041 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2042 "RF_Type is %x!!\n", rtlphy->rf_type); 2043 2044 if (value32 & TRP_VAUX_EN) { 2045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2046 if (rtlphy->rf_type == RF_2T2R) 2047 version = VERSION_TEST_CHIP_2T2R_8812; 2048 else 2049 version = VERSION_TEST_CHIP_1T1R_8812; 2050 } else 2051 version = VERSION_TEST_CHIP_8821; 2052 } else { 2053 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2054 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1; 2055 2056 if (rtlphy->rf_type == RF_2T2R) 2057 version = 2058 (enum version_8821ae)(CHIP_8812 2059 | NORMAL_CHIP | 2060 RF_TYPE_2T2R); 2061 else 2062 version = (enum version_8821ae)(CHIP_8812 2063 | NORMAL_CHIP); 2064 2065 version = (enum version_8821ae)(version | (rtl_id << 12)); 2066 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2067 u32 rtl_id = value32 & CHIP_VER_RTL_MASK; 2068 2069 version = (enum version_8821ae)(CHIP_8821 2070 | NORMAL_CHIP | rtl_id); 2071 } 2072 } 2073 2074 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2075 /*WL_HWROF_EN.*/ 2076 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2077 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0); 2078 } 2079 2080 switch (version) { 2081 case VERSION_TEST_CHIP_1T1R_8812: 2082 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2083 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n"); 2084 break; 2085 case VERSION_TEST_CHIP_2T2R_8812: 2086 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2087 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n"); 2088 break; 2089 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812: 2090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2091 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n"); 2092 break; 2093 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812: 2094 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2095 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n"); 2096 break; 2097 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT: 2098 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2099 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n"); 2100 break; 2101 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT: 2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2103 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n"); 2104 break; 2105 case VERSION_TEST_CHIP_8821: 2106 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2107 "Chip Version ID: VERSION_TEST_CHIP_8821\n"); 2108 break; 2109 case VERSION_NORMAL_TSMC_CHIP_8821: 2110 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2111 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n"); 2112 break; 2113 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT: 2114 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2115 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n"); 2116 break; 2117 default: 2118 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2119 "Chip Version ID: Unknow (0x%X)\n", version); 2120 break; 2121 } 2122 2123 return version; 2124 } 2125 2126 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw, 2127 enum nl80211_iftype type) 2128 { 2129 struct rtl_priv *rtlpriv = rtl_priv(hw); 2130 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 2131 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 2132 bt_msr &= 0xfc; 2133 2134 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 2135 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 2136 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 2137 2138 if (type == NL80211_IFTYPE_UNSPECIFIED || 2139 type == NL80211_IFTYPE_STATION) { 2140 _rtl8821ae_stop_tx_beacon(hw); 2141 _rtl8821ae_enable_bcn_sub_func(hw); 2142 } else if (type == NL80211_IFTYPE_ADHOC || 2143 type == NL80211_IFTYPE_AP) { 2144 _rtl8821ae_resume_tx_beacon(hw); 2145 _rtl8821ae_disable_bcn_sub_func(hw); 2146 } else { 2147 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2148 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 2149 type); 2150 } 2151 2152 switch (type) { 2153 case NL80211_IFTYPE_UNSPECIFIED: 2154 bt_msr |= MSR_NOLINK; 2155 ledaction = LED_CTL_LINK; 2156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2157 "Set Network type to NO LINK!\n"); 2158 break; 2159 case NL80211_IFTYPE_ADHOC: 2160 bt_msr |= MSR_ADHOC; 2161 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2162 "Set Network type to Ad Hoc!\n"); 2163 break; 2164 case NL80211_IFTYPE_STATION: 2165 bt_msr |= MSR_INFRA; 2166 ledaction = LED_CTL_LINK; 2167 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2168 "Set Network type to STA!\n"); 2169 break; 2170 case NL80211_IFTYPE_AP: 2171 bt_msr |= MSR_AP; 2172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2173 "Set Network type to AP!\n"); 2174 break; 2175 default: 2176 pr_err("Network type %d not support!\n", type); 2177 return 1; 2178 } 2179 2180 rtl_write_byte(rtlpriv, MSR, bt_msr); 2181 rtlpriv->cfg->ops->led_control(hw, ledaction); 2182 if ((bt_msr & MSR_MASK) == MSR_AP) 2183 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 2184 else 2185 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 2186 2187 return 0; 2188 } 2189 2190 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 2191 { 2192 struct rtl_priv *rtlpriv = rtl_priv(hw); 2193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2194 u32 reg_rcr = rtlpci->receive_config; 2195 2196 if (rtlpriv->psc.rfpwr_state != ERFON) 2197 return; 2198 2199 if (check_bssid) { 2200 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 2201 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 2202 (u8 *)(®_rcr)); 2203 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 2204 } else if (!check_bssid) { 2205 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 2206 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 2207 rtlpriv->cfg->ops->set_hw_reg(hw, 2208 HW_VAR_RCR, (u8 *)(®_rcr)); 2209 } 2210 } 2211 2212 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 2213 { 2214 struct rtl_priv *rtlpriv = rtl_priv(hw); 2215 2216 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n"); 2217 2218 if (_rtl8821ae_set_media_status(hw, type)) 2219 return -EOPNOTSUPP; 2220 2221 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 2222 if (type != NL80211_IFTYPE_AP) 2223 rtl8821ae_set_check_bssid(hw, true); 2224 } else { 2225 rtl8821ae_set_check_bssid(hw, false); 2226 } 2227 2228 return 0; 2229 } 2230 2231 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 2232 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci) 2233 { 2234 struct rtl_priv *rtlpriv = rtl_priv(hw); 2235 rtl8821ae_dm_init_edca_turbo(hw); 2236 switch (aci) { 2237 case AC1_BK: 2238 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 2239 break; 2240 case AC0_BE: 2241 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 2242 break; 2243 case AC2_VI: 2244 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 2245 break; 2246 case AC3_VO: 2247 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 2248 break; 2249 default: 2250 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci); 2251 break; 2252 } 2253 } 2254 2255 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw) 2256 { 2257 struct rtl_priv *rtlpriv = rtl_priv(hw); 2258 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR); 2259 2260 rtl_write_dword(rtlpriv, REG_HISR, tmp); 2261 2262 tmp = rtl_read_dword(rtlpriv, REG_HISRE); 2263 rtl_write_dword(rtlpriv, REG_HISRE, tmp); 2264 2265 tmp = rtl_read_dword(rtlpriv, REG_HSISR); 2266 rtl_write_dword(rtlpriv, REG_HSISR, tmp); 2267 } 2268 2269 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw) 2270 { 2271 struct rtl_priv *rtlpriv = rtl_priv(hw); 2272 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2273 2274 if (rtlpci->int_clear) 2275 rtl8821ae_clear_interrupt(hw);/*clear it here first*/ 2276 2277 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 2278 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 2279 rtlpci->irq_enabled = true; 2280 /* there are some C2H CMDs have been sent before 2281 system interrupt is enabled, e.g., C2H, CPWM. 2282 *So we need to clear all C2H events that FW has 2283 notified, otherwise FW won't schedule any commands anymore. 2284 */ 2285 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */ 2286 /*enable system interrupt*/ 2287 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 2288 } 2289 2290 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw) 2291 { 2292 struct rtl_priv *rtlpriv = rtl_priv(hw); 2293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2294 2295 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 2296 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 2297 rtlpci->irq_enabled = false; 2298 /*synchronize_irq(rtlpci->pdev->irq);*/ 2299 } 2300 2301 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw) 2302 { 2303 struct rtl_priv *rtlpriv = rtl_priv(hw); 2304 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2305 u16 cap_hdr; 2306 u8 cap_pointer; 2307 u8 cap_id = 0xff; 2308 u8 pmcs_reg; 2309 u8 cnt = 0; 2310 2311 /* Get the Capability pointer first, 2312 * the Capability Pointer is located at 2313 * offset 0x34 from the Function Header */ 2314 2315 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer); 2316 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2317 "PCI configuration 0x34 = 0x%2x\n", cap_pointer); 2318 2319 do { 2320 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr); 2321 cap_id = cap_hdr & 0xFF; 2322 2323 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2324 "in pci configuration, cap_pointer%x = %x\n", 2325 cap_pointer, cap_id); 2326 2327 if (cap_id == 0x01) { 2328 break; 2329 } else { 2330 /* point to next Capability */ 2331 cap_pointer = (cap_hdr >> 8) & 0xFF; 2332 /* 0: end of pci capability, 0xff: invalid value */ 2333 if (cap_pointer == 0x00 || cap_pointer == 0xff) { 2334 cap_id = 0xff; 2335 break; 2336 } 2337 } 2338 } while (cnt++ < 200); 2339 2340 if (cap_id == 0x01) { 2341 /* Get the PM CSR (Control/Status Register), 2342 * The PME_Status is located at PM Capatibility offset 5, bit 7 2343 */ 2344 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg); 2345 2346 if (pmcs_reg & BIT(7)) { 2347 /* PME event occured, clear the PM_Status by write 1 */ 2348 pmcs_reg = pmcs_reg | BIT(7); 2349 2350 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5, 2351 pmcs_reg); 2352 /* Read it back to check */ 2353 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, 2354 &pmcs_reg); 2355 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2356 "Clear PME status 0x%2x to 0x%2x\n", 2357 cap_pointer + 5, pmcs_reg); 2358 } else { 2359 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2360 "PME status(0x%2x) = 0x%2x\n", 2361 cap_pointer + 5, pmcs_reg); 2362 } 2363 } else { 2364 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 2365 "Cannot find PME Capability\n"); 2366 } 2367 } 2368 2369 void rtl8821ae_card_disable(struct ieee80211_hw *hw) 2370 { 2371 struct rtl_priv *rtlpriv = rtl_priv(hw); 2372 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2373 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 2374 struct rtl_mac *mac = rtl_mac(rtlpriv); 2375 enum nl80211_iftype opmode; 2376 bool support_remote_wakeup; 2377 u8 tmp; 2378 u32 count = 0; 2379 2380 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 2381 (u8 *)(&support_remote_wakeup)); 2382 2383 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2384 2385 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION) 2386 || !rtlhal->enter_pnp_sleep) { 2387 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n"); 2388 mac->link_state = MAC80211_NOLINK; 2389 opmode = NL80211_IFTYPE_UNSPECIFIED; 2390 _rtl8821ae_set_media_status(hw, opmode); 2391 _rtl8821ae_poweroff_adapter(hw); 2392 } else { 2393 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n"); 2394 /* 3 <1> Prepare for configuring wowlan related infomations */ 2395 /* Clear Fw WoWLAN event. */ 2396 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0); 2397 2398 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 2399 rtl8821ae_set_fw_related_for_wowlan(hw, true); 2400 #endif 2401 /* Dynamically adjust Tx packet boundary 2402 * for download reserved page packet. 2403 * reserve 30 pages for rsvd page */ 2404 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d)) 2405 rtlhal->re_init_llt_table = true; 2406 2407 /* 3 <2> Set Fw releted H2C cmd. */ 2408 2409 /* Set WoWLAN related security information. */ 2410 rtl8821ae_set_fw_global_info_cmd(hw); 2411 2412 _rtl8821ae_download_rsvd_page(hw, true); 2413 2414 /* Just enable AOAC related functions when we connect to AP. */ 2415 printk("mac->link_state = %d\n", mac->link_state); 2416 if (mac->link_state >= MAC80211_LINKED && 2417 mac->opmode == NL80211_IFTYPE_STATION) { 2418 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 2419 rtl8821ae_set_fw_media_status_rpt_cmd(hw, 2420 RT_MEDIA_CONNECT); 2421 2422 rtl8821ae_set_fw_wowlan_mode(hw, true); 2423 /* Enable Fw Keep alive mechanism. */ 2424 rtl8821ae_set_fw_keep_alive_cmd(hw, true); 2425 2426 /* Enable disconnect decision control. */ 2427 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true); 2428 } 2429 2430 /* 3 <3> Hw Configutations */ 2431 2432 /* Wait untill Rx DMA Finished before host sleep. 2433 * FW Pause Rx DMA may happens when received packet doing dma. 2434 */ 2435 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2)); 2436 2437 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2438 count = 0; 2439 while (!(tmp & BIT(1)) && (count++ < 100)) { 2440 udelay(10); 2441 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2442 } 2443 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2444 "Wait Rx DMA Finished before host sleep. count=%d\n", 2445 count); 2446 2447 /* reset trx ring */ 2448 rtlpriv->intf_ops->reset_trx_ring(hw); 2449 2450 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0); 2451 2452 _rtl8821ae_clear_pci_pme_status(hw); 2453 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 2454 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3)); 2455 /* prevent 8051 to be reset by PERST */ 2456 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20); 2457 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60); 2458 } 2459 2460 if (rtlpriv->rtlhal.driver_is_goingto_unload || 2461 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 2462 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 2463 /* For wowlan+LPS+32k. */ 2464 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) { 2465 /* Set the WoWLAN related function control enable. 2466 * It should be the last H2C cmd in the WoWLAN flow. */ 2467 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1); 2468 2469 /* Stop Pcie Interface Tx DMA. */ 2470 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 2471 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n"); 2472 2473 /* Wait for TxDMA idle. */ 2474 count = 0; 2475 do { 2476 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG); 2477 udelay(10); 2478 count++; 2479 } while ((tmp != 0) && (count < 100)); 2480 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2481 "Wait Tx DMA Finished before host sleep. count=%d\n", 2482 count); 2483 2484 if (rtlhal->hw_rof_enable) { 2485 printk("hw_rof_enable\n"); 2486 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 2487 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 2488 } 2489 } 2490 /* after power off we should do iqk again */ 2491 rtlpriv->phy.iqk_initialized = false; 2492 } 2493 2494 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw, 2495 u32 *p_inta, u32 *p_intb) 2496 { 2497 struct rtl_priv *rtlpriv = rtl_priv(hw); 2498 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2499 2500 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 2501 rtl_write_dword(rtlpriv, ISR, *p_inta); 2502 2503 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 2504 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb); 2505 } 2506 2507 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw) 2508 { 2509 struct rtl_priv *rtlpriv = rtl_priv(hw); 2510 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2511 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2512 u16 bcn_interval, atim_window; 2513 2514 bcn_interval = mac->beacon_interval; 2515 atim_window = 2; /*FIX MERGE */ 2516 rtl8821ae_disable_interrupt(hw); 2517 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 2518 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2519 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 2520 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 2521 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 2522 rtl_write_byte(rtlpriv, 0x606, 0x30); 2523 rtlpci->reg_bcn_ctrl_val |= BIT(3); 2524 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 2525 rtl8821ae_enable_interrupt(hw); 2526 } 2527 2528 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw) 2529 { 2530 struct rtl_priv *rtlpriv = rtl_priv(hw); 2531 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2532 u16 bcn_interval = mac->beacon_interval; 2533 2534 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 2535 "beacon_interval:%d\n", bcn_interval); 2536 rtl8821ae_disable_interrupt(hw); 2537 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2538 rtl8821ae_enable_interrupt(hw); 2539 } 2540 2541 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw, 2542 u32 add_msr, u32 rm_msr) 2543 { 2544 struct rtl_priv *rtlpriv = rtl_priv(hw); 2545 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2546 2547 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 2548 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 2549 2550 if (add_msr) 2551 rtlpci->irq_mask[0] |= add_msr; 2552 if (rm_msr) 2553 rtlpci->irq_mask[0] &= (~rm_msr); 2554 rtl8821ae_disable_interrupt(hw); 2555 rtl8821ae_enable_interrupt(hw); 2556 } 2557 2558 static u8 _rtl8821ae_get_chnl_group(u8 chnl) 2559 { 2560 u8 group = 0; 2561 2562 if (chnl <= 14) { 2563 if (1 <= chnl && chnl <= 2) 2564 group = 0; 2565 else if (3 <= chnl && chnl <= 5) 2566 group = 1; 2567 else if (6 <= chnl && chnl <= 8) 2568 group = 2; 2569 else if (9 <= chnl && chnl <= 11) 2570 group = 3; 2571 else /*if (12 <= chnl && chnl <= 14)*/ 2572 group = 4; 2573 } else { 2574 if (36 <= chnl && chnl <= 42) 2575 group = 0; 2576 else if (44 <= chnl && chnl <= 48) 2577 group = 1; 2578 else if (50 <= chnl && chnl <= 58) 2579 group = 2; 2580 else if (60 <= chnl && chnl <= 64) 2581 group = 3; 2582 else if (100 <= chnl && chnl <= 106) 2583 group = 4; 2584 else if (108 <= chnl && chnl <= 114) 2585 group = 5; 2586 else if (116 <= chnl && chnl <= 122) 2587 group = 6; 2588 else if (124 <= chnl && chnl <= 130) 2589 group = 7; 2590 else if (132 <= chnl && chnl <= 138) 2591 group = 8; 2592 else if (140 <= chnl && chnl <= 144) 2593 group = 9; 2594 else if (149 <= chnl && chnl <= 155) 2595 group = 10; 2596 else if (157 <= chnl && chnl <= 161) 2597 group = 11; 2598 else if (165 <= chnl && chnl <= 171) 2599 group = 12; 2600 else if (173 <= chnl && chnl <= 177) 2601 group = 13; 2602 else 2603 WARN_ONCE(true, 2604 "rtl8821ae: 5G, Channel %d in Group not found\n", 2605 chnl); 2606 } 2607 return group; 2608 } 2609 2610 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw, 2611 struct txpower_info_2g *pwrinfo24g, 2612 struct txpower_info_5g *pwrinfo5g, 2613 bool autoload_fail, 2614 u8 *hwinfo) 2615 { 2616 struct rtl_priv *rtlpriv = rtl_priv(hw); 2617 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0; 2618 2619 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2620 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n", 2621 (eeAddr+1), hwinfo[eeAddr+1]); 2622 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/ 2623 autoload_fail = true; 2624 2625 if (autoload_fail) { 2626 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2627 "auto load fail : Use Default value!\n"); 2628 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2629 /*2.4G default value*/ 2630 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2631 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D; 2632 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D; 2633 } 2634 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2635 if (TxCount == 0) { 2636 pwrinfo24g->bw20_diff[rfPath][0] = 0x02; 2637 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04; 2638 } else { 2639 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE; 2640 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE; 2641 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE; 2642 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE; 2643 } 2644 } 2645 /*5G default value*/ 2646 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 2647 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A; 2648 2649 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2650 if (TxCount == 0) { 2651 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04; 2652 pwrinfo5g->bw20_diff[rfPath][0] = 0x00; 2653 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE; 2654 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE; 2655 } else { 2656 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE; 2657 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE; 2658 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE; 2659 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE; 2660 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE; 2661 } 2662 } 2663 } 2664 return; 2665 } 2666 2667 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 2668 2669 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2670 /*2.4G default value*/ 2671 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2672 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++]; 2673 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF) 2674 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D; 2675 } 2676 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 2677 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++]; 2678 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF) 2679 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D; 2680 } 2681 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2682 if (TxCount == 0) { 2683 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0; 2684 /*bit sign number to 8 bit sign number*/ 2685 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2686 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) 2687 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0; 2688 /*bit sign number to 8 bit sign number*/ 2689 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2690 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2691 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2692 2693 pwrinfo24g->cck_diff[rfPath][TxCount] = 0; 2694 eeAddr++; 2695 } else { 2696 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4; 2697 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3)) 2698 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0; 2699 2700 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2701 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) 2702 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0; 2703 2704 eeAddr++; 2705 2706 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2707 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2708 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2709 2710 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2711 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3)) 2712 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0; 2713 2714 eeAddr++; 2715 } 2716 } 2717 2718 /*5G default value*/ 2719 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 2720 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++]; 2721 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF) 2722 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE; 2723 } 2724 2725 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2726 if (TxCount == 0) { 2727 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0; 2728 2729 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4; 2730 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3)) 2731 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0; 2732 2733 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f); 2734 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2735 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2736 2737 eeAddr++; 2738 } else { 2739 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2740 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3)) 2741 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0; 2742 2743 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2744 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3)) 2745 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0; 2746 2747 eeAddr++; 2748 } 2749 } 2750 2751 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4; 2752 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f); 2753 2754 eeAddr++; 2755 2756 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f); 2757 2758 eeAddr++; 2759 2760 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) { 2761 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2762 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2763 } 2764 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2765 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2766 /* 4bit sign number to 8 bit sign number */ 2767 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3)) 2768 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0; 2769 /* 4bit sign number to 8 bit sign number */ 2770 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2771 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3)) 2772 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0; 2773 2774 eeAddr++; 2775 } 2776 } 2777 } 2778 #if 0 2779 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2780 bool autoload_fail, 2781 u8 *hwinfo) 2782 { 2783 struct rtl_priv *rtlpriv = rtl_priv(hw); 2784 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2785 struct txpower_info_2g pwrinfo24g; 2786 struct txpower_info_5g pwrinfo5g; 2787 u8 rf_path, index; 2788 u8 i; 2789 2790 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2791 &pwrinfo5g, autoload_fail, hwinfo); 2792 2793 for (rf_path = 0; rf_path < 2; rf_path++) { 2794 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2795 index = _rtl8821ae_get_chnl_group(i + 1); 2796 2797 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2798 rtlefuse->txpwrlevel_cck[rf_path][i] = 2799 pwrinfo24g.index_cck_base[rf_path][5]; 2800 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2801 pwrinfo24g.index_bw40_base[rf_path][index]; 2802 } else { 2803 rtlefuse->txpwrlevel_cck[rf_path][i] = 2804 pwrinfo24g.index_cck_base[rf_path][index]; 2805 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2806 pwrinfo24g.index_bw40_base[rf_path][index]; 2807 } 2808 } 2809 2810 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2811 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2812 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2813 pwrinfo5g.index_bw40_base[rf_path][index]; 2814 } 2815 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2816 u8 upper, lower; 2817 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2818 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2819 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2820 2821 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2822 } 2823 for (i = 0; i < MAX_TX_COUNT; i++) { 2824 rtlefuse->txpwr_cckdiff[rf_path][i] = 2825 pwrinfo24g.cck_diff[rf_path][i]; 2826 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2827 pwrinfo24g.ofdm_diff[rf_path][i]; 2828 rtlefuse->txpwr_ht20diff[rf_path][i] = 2829 pwrinfo24g.bw20_diff[rf_path][i]; 2830 rtlefuse->txpwr_ht40diff[rf_path][i] = 2831 pwrinfo24g.bw40_diff[rf_path][i]; 2832 2833 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2834 pwrinfo5g.ofdm_diff[rf_path][i]; 2835 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2836 pwrinfo5g.bw20_diff[rf_path][i]; 2837 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2838 pwrinfo5g.bw40_diff[rf_path][i]; 2839 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2840 pwrinfo5g.bw80_diff[rf_path][i]; 2841 } 2842 } 2843 2844 if (!autoload_fail) { 2845 rtlefuse->eeprom_regulatory = 2846 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/ 2847 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2848 rtlefuse->eeprom_regulatory = 0; 2849 } else { 2850 rtlefuse->eeprom_regulatory = 0; 2851 } 2852 2853 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2854 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2855 } 2856 #endif 2857 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2858 bool autoload_fail, 2859 u8 *hwinfo) 2860 { 2861 struct rtl_priv *rtlpriv = rtl_priv(hw); 2862 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2863 struct txpower_info_2g pwrinfo24g; 2864 struct txpower_info_5g pwrinfo5g; 2865 u8 rf_path, index; 2866 u8 i; 2867 2868 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2869 &pwrinfo5g, autoload_fail, hwinfo); 2870 2871 for (rf_path = 0; rf_path < 2; rf_path++) { 2872 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2873 index = _rtl8821ae_get_chnl_group(i + 1); 2874 2875 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2876 rtlefuse->txpwrlevel_cck[rf_path][i] = 2877 pwrinfo24g.index_cck_base[rf_path][5]; 2878 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2879 pwrinfo24g.index_bw40_base[rf_path][index]; 2880 } else { 2881 rtlefuse->txpwrlevel_cck[rf_path][i] = 2882 pwrinfo24g.index_cck_base[rf_path][index]; 2883 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2884 pwrinfo24g.index_bw40_base[rf_path][index]; 2885 } 2886 } 2887 2888 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2889 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2890 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2891 pwrinfo5g.index_bw40_base[rf_path][index]; 2892 } 2893 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2894 u8 upper, lower; 2895 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2896 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2897 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2898 2899 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2900 } 2901 for (i = 0; i < MAX_TX_COUNT; i++) { 2902 rtlefuse->txpwr_cckdiff[rf_path][i] = 2903 pwrinfo24g.cck_diff[rf_path][i]; 2904 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2905 pwrinfo24g.ofdm_diff[rf_path][i]; 2906 rtlefuse->txpwr_ht20diff[rf_path][i] = 2907 pwrinfo24g.bw20_diff[rf_path][i]; 2908 rtlefuse->txpwr_ht40diff[rf_path][i] = 2909 pwrinfo24g.bw40_diff[rf_path][i]; 2910 2911 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2912 pwrinfo5g.ofdm_diff[rf_path][i]; 2913 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2914 pwrinfo5g.bw20_diff[rf_path][i]; 2915 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2916 pwrinfo5g.bw40_diff[rf_path][i]; 2917 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2918 pwrinfo5g.bw80_diff[rf_path][i]; 2919 } 2920 } 2921 /*bit0~2*/ 2922 if (!autoload_fail) { 2923 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07; 2924 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2925 rtlefuse->eeprom_regulatory = 0; 2926 } else { 2927 rtlefuse->eeprom_regulatory = 0; 2928 } 2929 2930 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2931 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2932 } 2933 2934 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2935 bool autoload_fail) 2936 { 2937 struct rtl_priv *rtlpriv = rtl_priv(hw); 2938 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2939 2940 if (!autoload_fail) { 2941 rtlhal->pa_type_2g = hwinfo[0xBC]; 2942 rtlhal->lna_type_2g = hwinfo[0xBD]; 2943 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2944 rtlhal->pa_type_2g = 0; 2945 rtlhal->lna_type_2g = 0; 2946 } 2947 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) && 2948 (rtlhal->pa_type_2g & BIT(4))) ? 2949 1 : 0; 2950 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) && 2951 (rtlhal->lna_type_2g & BIT(3))) ? 2952 1 : 0; 2953 2954 rtlhal->pa_type_5g = hwinfo[0xBC]; 2955 rtlhal->lna_type_5g = hwinfo[0xBF]; 2956 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2957 rtlhal->pa_type_5g = 0; 2958 rtlhal->lna_type_5g = 0; 2959 } 2960 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) && 2961 (rtlhal->pa_type_5g & BIT(0))) ? 2962 1 : 0; 2963 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) && 2964 (rtlhal->lna_type_5g & BIT(3))) ? 2965 1 : 0; 2966 } else { 2967 rtlhal->external_pa_2g = 0; 2968 rtlhal->external_lna_2g = 0; 2969 rtlhal->external_pa_5g = 0; 2970 rtlhal->external_lna_5g = 0; 2971 } 2972 } 2973 2974 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2975 bool autoload_fail) 2976 { 2977 struct rtl_priv *rtlpriv = rtl_priv(hw); 2978 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2979 2980 if (!autoload_fail) { 2981 rtlhal->pa_type_2g = hwinfo[0xBC]; 2982 rtlhal->lna_type_2g = hwinfo[0xBD]; 2983 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2984 rtlhal->pa_type_2g = 0; 2985 rtlhal->lna_type_2g = 0; 2986 } 2987 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0; 2988 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0; 2989 2990 rtlhal->pa_type_5g = hwinfo[0xBC]; 2991 rtlhal->lna_type_5g = hwinfo[0xBF]; 2992 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2993 rtlhal->pa_type_5g = 0; 2994 rtlhal->lna_type_5g = 0; 2995 } 2996 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0; 2997 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0; 2998 } else { 2999 rtlhal->external_pa_2g = 0; 3000 rtlhal->external_lna_2g = 0; 3001 rtlhal->external_pa_5g = 0; 3002 rtlhal->external_lna_5g = 0; 3003 } 3004 } 3005 3006 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo, 3007 bool autoload_fail) 3008 { 3009 struct rtl_priv *rtlpriv = rtl_priv(hw); 3010 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3011 3012 if (!autoload_fail) { 3013 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) { 3014 if (rtlhal->external_lna_5g) { 3015 if (rtlhal->external_pa_5g) { 3016 if (rtlhal->external_lna_2g && 3017 rtlhal->external_pa_2g) 3018 rtlhal->rfe_type = 3; 3019 else 3020 rtlhal->rfe_type = 0; 3021 } else { 3022 rtlhal->rfe_type = 2; 3023 } 3024 } else { 3025 rtlhal->rfe_type = 4; 3026 } 3027 } else { 3028 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F; 3029 3030 if (rtlhal->rfe_type == 4 && 3031 (rtlhal->external_pa_5g || 3032 rtlhal->external_pa_2g || 3033 rtlhal->external_lna_5g || 3034 rtlhal->external_lna_2g)) { 3035 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 3036 rtlhal->rfe_type = 2; 3037 } 3038 } 3039 } else { 3040 rtlhal->rfe_type = 0x04; 3041 } 3042 3043 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3044 "RFE Type: 0x%2x\n", rtlhal->rfe_type); 3045 } 3046 3047 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3048 bool auto_load_fail, u8 *hwinfo) 3049 { 3050 struct rtl_priv *rtlpriv = rtl_priv(hw); 3051 u8 value; 3052 3053 if (!auto_load_fail) { 3054 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION]; 3055 if (((value & 0xe0) >> 5) == 0x1) 3056 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3057 else 3058 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3059 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3060 3061 value = hwinfo[EEPROM_RF_BT_SETTING]; 3062 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3063 } else { 3064 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3065 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3066 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3067 } 3068 /*move BT_InitHalVars() to init_sw_vars*/ 3069 } 3070 3071 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3072 bool auto_load_fail, u8 *hwinfo) 3073 { 3074 struct rtl_priv *rtlpriv = rtl_priv(hw); 3075 u8 value; 3076 u32 tmpu_32; 3077 3078 if (!auto_load_fail) { 3079 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 3080 if (tmpu_32 & BIT(18)) 3081 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3082 else 3083 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3084 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3085 3086 value = hwinfo[EEPROM_RF_BT_SETTING]; 3087 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3088 } else { 3089 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3090 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3091 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3092 } 3093 /*move BT_InitHalVars() to init_sw_vars*/ 3094 } 3095 3096 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test) 3097 { 3098 struct rtl_priv *rtlpriv = rtl_priv(hw); 3099 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3100 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3101 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3102 int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID, 3103 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 3104 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 3105 COUNTRY_CODE_WORLD_WIDE_13}; 3106 u8 *hwinfo; 3107 3108 if (b_pseudo_test) { 3109 ;/* need add */ 3110 } 3111 3112 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 3113 if (!hwinfo) 3114 return; 3115 3116 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 3117 goto exit; 3118 3119 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 3120 hwinfo); 3121 3122 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 3123 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag); 3124 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw, 3125 rtlefuse->autoload_failflag, hwinfo); 3126 } else { 3127 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag); 3128 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw, 3129 rtlefuse->autoload_failflag, hwinfo); 3130 } 3131 3132 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag); 3133 /*board type*/ 3134 rtlefuse->board_type = ODM_BOARD_DEFAULT; 3135 if (rtlhal->external_lna_2g != 0) 3136 rtlefuse->board_type |= ODM_BOARD_EXT_LNA; 3137 if (rtlhal->external_lna_5g != 0) 3138 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G; 3139 if (rtlhal->external_pa_2g != 0) 3140 rtlefuse->board_type |= ODM_BOARD_EXT_PA; 3141 if (rtlhal->external_pa_5g != 0) 3142 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G; 3143 3144 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 3145 rtlefuse->board_type |= ODM_BOARD_BT; 3146 3147 rtlhal->board_type = rtlefuse->board_type; 3148 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3149 "board_type = 0x%x\n", rtlefuse->board_type); 3150 3151 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 3152 if (rtlefuse->eeprom_channelplan == 0xff) 3153 rtlefuse->eeprom_channelplan = 0x7F; 3154 3155 /* set channel plan from efuse */ 3156 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 3157 3158 /*parse xtal*/ 3159 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE]; 3160 if (rtlefuse->crystalcap == 0xFF) 3161 rtlefuse->crystalcap = 0x20; 3162 3163 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER]; 3164 if ((rtlefuse->eeprom_thermalmeter == 0xff) || 3165 rtlefuse->autoload_failflag) { 3166 rtlefuse->apk_thermalmeterignore = true; 3167 rtlefuse->eeprom_thermalmeter = 0xff; 3168 } 3169 3170 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 3171 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3172 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 3173 3174 if (!rtlefuse->autoload_failflag) { 3175 rtlefuse->antenna_div_cfg = 3176 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3; 3177 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff) 3178 rtlefuse->antenna_div_cfg = 0; 3179 3180 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 && 3181 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1) 3182 rtlefuse->antenna_div_cfg = 0; 3183 3184 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 3185 if (rtlefuse->antenna_div_type == 0xff) 3186 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV; 3187 } else { 3188 rtlefuse->antenna_div_cfg = 0; 3189 rtlefuse->antenna_div_type = 0; 3190 } 3191 3192 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3193 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n", 3194 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type); 3195 3196 pcipriv->ledctl.led_opendrain = true; 3197 3198 if (rtlhal->oem_id == RT_CID_DEFAULT) { 3199 switch (rtlefuse->eeprom_oemid) { 3200 case RT_CID_DEFAULT: 3201 break; 3202 case EEPROM_CID_TOSHIBA: 3203 rtlhal->oem_id = RT_CID_TOSHIBA; 3204 break; 3205 case EEPROM_CID_CCX: 3206 rtlhal->oem_id = RT_CID_CCX; 3207 break; 3208 case EEPROM_CID_QMI: 3209 rtlhal->oem_id = RT_CID_819X_QMI; 3210 break; 3211 case EEPROM_CID_WHQL: 3212 break; 3213 default: 3214 break; 3215 } 3216 } 3217 exit: 3218 kfree(hwinfo); 3219 } 3220 3221 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw) 3222 { 3223 struct rtl_priv *rtlpriv = rtl_priv(hw); 3224 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3225 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3226 3227 pcipriv->ledctl.led_opendrain = true; 3228 switch (rtlhal->oem_id) { 3229 case RT_CID_819X_HP: 3230 pcipriv->ledctl.led_opendrain = true; 3231 break; 3232 case RT_CID_819X_LENOVO: 3233 case RT_CID_DEFAULT: 3234 case RT_CID_TOSHIBA: 3235 case RT_CID_CCX: 3236 case RT_CID_819X_ACER: 3237 case RT_CID_WHQL: 3238 default: 3239 break; 3240 } 3241 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3242 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 3243 }*/ 3244 3245 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw) 3246 { 3247 struct rtl_priv *rtlpriv = rtl_priv(hw); 3248 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3249 struct rtl_phy *rtlphy = &rtlpriv->phy; 3250 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3251 u8 tmp_u1b; 3252 3253 rtlhal->version = _rtl8821ae_read_chip_version(hw); 3254 if (get_rf_type(rtlphy) == RF_1T1R) 3255 rtlpriv->dm.rfpath_rxenable[0] = true; 3256 else 3257 rtlpriv->dm.rfpath_rxenable[0] = 3258 rtlpriv->dm.rfpath_rxenable[1] = true; 3259 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 3260 rtlhal->version); 3261 3262 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 3263 if (tmp_u1b & BIT(4)) { 3264 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 3265 rtlefuse->epromtype = EEPROM_93C46; 3266 } else { 3267 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 3268 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 3269 } 3270 3271 if (tmp_u1b & BIT(5)) { 3272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 3273 rtlefuse->autoload_failflag = false; 3274 _rtl8821ae_read_adapter_info(hw, false); 3275 } else { 3276 pr_err("Autoload ERR!!\n"); 3277 } 3278 /*hal_ReadRFType_8812A()*/ 3279 /* _rtl8821ae_hal_customized_behavior(hw); */ 3280 } 3281 3282 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw, 3283 struct ieee80211_sta *sta) 3284 { 3285 struct rtl_priv *rtlpriv = rtl_priv(hw); 3286 struct rtl_phy *rtlphy = &rtlpriv->phy; 3287 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3288 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3289 u32 ratr_value; 3290 u8 ratr_index = 0; 3291 u8 b_nmode = mac->ht_enable; 3292 u8 mimo_ps = IEEE80211_SMPS_OFF; 3293 u16 shortgi_rate; 3294 u32 tmp_ratr_value; 3295 u8 curtxbw_40mhz = mac->bw_40; 3296 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3297 1 : 0; 3298 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3299 1 : 0; 3300 enum wireless_mode wirelessmode = mac->mode; 3301 3302 if (rtlhal->current_bandtype == BAND_ON_5G) 3303 ratr_value = sta->supp_rates[1] << 4; 3304 else 3305 ratr_value = sta->supp_rates[0]; 3306 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3307 ratr_value = 0xfff; 3308 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3309 sta->ht_cap.mcs.rx_mask[0] << 12); 3310 switch (wirelessmode) { 3311 case WIRELESS_MODE_B: 3312 if (ratr_value & 0x0000000c) 3313 ratr_value &= 0x0000000d; 3314 else 3315 ratr_value &= 0x0000000f; 3316 break; 3317 case WIRELESS_MODE_G: 3318 ratr_value &= 0x00000FF5; 3319 break; 3320 case WIRELESS_MODE_N_24G: 3321 case WIRELESS_MODE_N_5G: 3322 b_nmode = 1; 3323 if (mimo_ps == IEEE80211_SMPS_STATIC) { 3324 ratr_value &= 0x0007F005; 3325 } else { 3326 u32 ratr_mask; 3327 3328 if (get_rf_type(rtlphy) == RF_1T2R || 3329 get_rf_type(rtlphy) == RF_1T1R) 3330 ratr_mask = 0x000ff005; 3331 else 3332 ratr_mask = 0x0f0ff005; 3333 3334 ratr_value &= ratr_mask; 3335 } 3336 break; 3337 default: 3338 if (rtlphy->rf_type == RF_1T2R) 3339 ratr_value &= 0x000ff0ff; 3340 else 3341 ratr_value &= 0x0f0ff0ff; 3342 3343 break; 3344 } 3345 3346 if ((rtlpriv->btcoexist.bt_coexistence) && 3347 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 3348 (rtlpriv->btcoexist.bt_cur_state) && 3349 (rtlpriv->btcoexist.bt_ant_isolation) && 3350 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 3351 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 3352 ratr_value &= 0x0fffcfc0; 3353 else 3354 ratr_value &= 0x0FFFFFFF; 3355 3356 if (b_nmode && ((curtxbw_40mhz && 3357 b_curshortgi_40mhz) || (!curtxbw_40mhz && 3358 b_curshortgi_20mhz))) { 3359 ratr_value |= 0x10000000; 3360 tmp_ratr_value = (ratr_value >> 12); 3361 3362 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 3363 if ((1 << shortgi_rate) & tmp_ratr_value) 3364 break; 3365 } 3366 3367 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 3368 (shortgi_rate << 4) | (shortgi_rate); 3369 } 3370 3371 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 3372 3373 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3374 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 3375 } 3376 3377 static u8 _rtl8821ae_mrate_idx_to_arfr_id( 3378 struct ieee80211_hw *hw, u8 rate_index, 3379 enum wireless_mode wirelessmode) 3380 { 3381 struct rtl_priv *rtlpriv = rtl_priv(hw); 3382 struct rtl_phy *rtlphy = &rtlpriv->phy; 3383 u8 ret = 0; 3384 switch (rate_index) { 3385 case RATR_INX_WIRELESS_NGB: 3386 if (rtlphy->rf_type == RF_1T1R) 3387 ret = 1; 3388 else 3389 ret = 0; 3390 ; break; 3391 case RATR_INX_WIRELESS_N: 3392 case RATR_INX_WIRELESS_NG: 3393 if (rtlphy->rf_type == RF_1T1R) 3394 ret = 5; 3395 else 3396 ret = 4; 3397 ; break; 3398 case RATR_INX_WIRELESS_NB: 3399 if (rtlphy->rf_type == RF_1T1R) 3400 ret = 3; 3401 else 3402 ret = 2; 3403 ; break; 3404 case RATR_INX_WIRELESS_GB: 3405 ret = 6; 3406 break; 3407 case RATR_INX_WIRELESS_G: 3408 ret = 7; 3409 break; 3410 case RATR_INX_WIRELESS_B: 3411 ret = 8; 3412 break; 3413 case RATR_INX_WIRELESS_MC: 3414 if ((wirelessmode == WIRELESS_MODE_B) 3415 || (wirelessmode == WIRELESS_MODE_G) 3416 || (wirelessmode == WIRELESS_MODE_N_24G) 3417 || (wirelessmode == WIRELESS_MODE_AC_24G)) 3418 ret = 6; 3419 else 3420 ret = 7; 3421 case RATR_INX_WIRELESS_AC_5N: 3422 if (rtlphy->rf_type == RF_1T1R) 3423 ret = 10; 3424 else 3425 ret = 9; 3426 break; 3427 case RATR_INX_WIRELESS_AC_24N: 3428 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) { 3429 if (rtlphy->rf_type == RF_1T1R) 3430 ret = 10; 3431 else 3432 ret = 9; 3433 } else { 3434 if (rtlphy->rf_type == RF_1T1R) 3435 ret = 11; 3436 else 3437 ret = 12; 3438 } 3439 break; 3440 default: 3441 ret = 0; break; 3442 } 3443 return ret; 3444 } 3445 3446 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate) 3447 { 3448 u8 i, j, tmp_rate; 3449 u32 rate_bitmap = 0; 3450 3451 for (i = j = 0; i < 4; i += 2, j += 10) { 3452 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3; 3453 3454 switch (tmp_rate) { 3455 case 2: 3456 rate_bitmap = rate_bitmap | (0x03ff << j); 3457 break; 3458 case 1: 3459 rate_bitmap = rate_bitmap | (0x01ff << j); 3460 break; 3461 case 0: 3462 rate_bitmap = rate_bitmap | (0x00ff << j); 3463 break; 3464 default: 3465 break; 3466 } 3467 } 3468 3469 return rate_bitmap; 3470 } 3471 3472 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw, 3473 enum wireless_mode wirelessmode, 3474 u32 ratr_bitmap) 3475 { 3476 struct rtl_priv *rtlpriv = rtl_priv(hw); 3477 struct rtl_phy *rtlphy = &rtlpriv->phy; 3478 u32 ret_bitmap = ratr_bitmap; 3479 3480 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 3481 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3482 ret_bitmap = ratr_bitmap; 3483 else if (wirelessmode == WIRELESS_MODE_AC_5G 3484 || wirelessmode == WIRELESS_MODE_AC_24G) { 3485 if (rtlphy->rf_type == RF_1T1R) 3486 ret_bitmap = ratr_bitmap & (~BIT21); 3487 else 3488 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21)); 3489 } 3490 3491 return ret_bitmap; 3492 } 3493 3494 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode, 3495 u32 ratr_bitmap) 3496 { 3497 u8 ret = 0; 3498 if (wirelessmode < WIRELESS_MODE_N_24G) 3499 ret = 0; 3500 else if (wirelessmode == WIRELESS_MODE_AC_24G) { 3501 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */ 3502 ret = 3; 3503 else /* Mix, 1SS */ 3504 ret = 2; 3505 } else if (wirelessmode == WIRELESS_MODE_AC_5G) { 3506 ret = 1; 3507 } /* VHT */ 3508 3509 return ret << 4; 3510 } 3511 3512 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw, 3513 u8 mac_id, struct rtl_sta_info *sta_entry, 3514 enum wireless_mode wirelessmode) 3515 { 3516 u8 b_ldpc = 0; 3517 /*not support ldpc, do not open*/ 3518 return b_ldpc << 2; 3519 } 3520 3521 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw, 3522 enum wireless_mode wirelessmode, 3523 u32 ratr_bitmap) 3524 { 3525 struct rtl_priv *rtlpriv = rtl_priv(hw); 3526 struct rtl_phy *rtlphy = &rtlpriv->phy; 3527 u8 rf_type = RF_1T1R; 3528 3529 if (rtlphy->rf_type == RF_1T1R) 3530 rf_type = RF_1T1R; 3531 else if (wirelessmode == WIRELESS_MODE_AC_5G 3532 || wirelessmode == WIRELESS_MODE_AC_24G 3533 || wirelessmode == WIRELESS_MODE_AC_ONLY) { 3534 if (ratr_bitmap & 0xffc00000) 3535 rf_type = RF_2T2R; 3536 } else if (wirelessmode == WIRELESS_MODE_N_5G 3537 || wirelessmode == WIRELESS_MODE_N_24G) { 3538 if (ratr_bitmap & 0xfff00000) 3539 rf_type = RF_2T2R; 3540 } 3541 3542 return rf_type; 3543 } 3544 3545 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 3546 u8 mac_id) 3547 { 3548 bool b_short_gi = false; 3549 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3550 1 : 0; 3551 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3552 1 : 0; 3553 u8 b_curshortgi_80mhz = 0; 3554 b_curshortgi_80mhz = (sta->vht_cap.cap & 3555 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0; 3556 3557 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) 3558 b_short_gi = false; 3559 3560 if (b_curshortgi_40mhz || b_curshortgi_80mhz 3561 || b_curshortgi_20mhz) 3562 b_short_gi = true; 3563 3564 return b_short_gi; 3565 } 3566 3567 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw, 3568 struct ieee80211_sta *sta, u8 rssi_level) 3569 { 3570 struct rtl_priv *rtlpriv = rtl_priv(hw); 3571 struct rtl_phy *rtlphy = &rtlpriv->phy; 3572 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3573 struct rtl_sta_info *sta_entry = NULL; 3574 u32 ratr_bitmap; 3575 u8 ratr_index; 3576 enum wireless_mode wirelessmode = 0; 3577 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 3578 ? 1 : 0; 3579 bool b_shortgi = false; 3580 u8 rate_mask[7]; 3581 u8 macid = 0; 3582 u8 mimo_ps = IEEE80211_SMPS_OFF; 3583 u8 rf_type; 3584 3585 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 3586 wirelessmode = sta_entry->wireless_mode; 3587 3588 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3589 "wireless mode = 0x%x\n", wirelessmode); 3590 if (mac->opmode == NL80211_IFTYPE_STATION || 3591 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 3592 curtxbw_40mhz = mac->bw_40; 3593 } else if (mac->opmode == NL80211_IFTYPE_AP || 3594 mac->opmode == NL80211_IFTYPE_ADHOC) 3595 macid = sta->aid + 1; 3596 if (wirelessmode == WIRELESS_MODE_N_5G || 3597 wirelessmode == WIRELESS_MODE_AC_5G || 3598 wirelessmode == WIRELESS_MODE_A) 3599 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4; 3600 else 3601 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ]; 3602 3603 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3604 ratr_bitmap = 0xfff; 3605 3606 if (wirelessmode == WIRELESS_MODE_N_24G 3607 || wirelessmode == WIRELESS_MODE_N_5G) 3608 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3609 sta->ht_cap.mcs.rx_mask[0] << 12); 3610 else if (wirelessmode == WIRELESS_MODE_AC_24G 3611 || wirelessmode == WIRELESS_MODE_AC_5G 3612 || wirelessmode == WIRELESS_MODE_AC_ONLY) 3613 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht( 3614 sta->vht_cap.vht_mcs.rx_mcs_map) << 12; 3615 3616 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid); 3617 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap); 3618 3619 /*mac id owner*/ 3620 switch (wirelessmode) { 3621 case WIRELESS_MODE_B: 3622 ratr_index = RATR_INX_WIRELESS_B; 3623 if (ratr_bitmap & 0x0000000c) 3624 ratr_bitmap &= 0x0000000d; 3625 else 3626 ratr_bitmap &= 0x0000000f; 3627 break; 3628 case WIRELESS_MODE_G: 3629 ratr_index = RATR_INX_WIRELESS_GB; 3630 3631 if (rssi_level == 1) 3632 ratr_bitmap &= 0x00000f00; 3633 else if (rssi_level == 2) 3634 ratr_bitmap &= 0x00000ff0; 3635 else 3636 ratr_bitmap &= 0x00000ff5; 3637 break; 3638 case WIRELESS_MODE_A: 3639 ratr_index = RATR_INX_WIRELESS_G; 3640 ratr_bitmap &= 0x00000ff0; 3641 break; 3642 case WIRELESS_MODE_N_24G: 3643 case WIRELESS_MODE_N_5G: 3644 if (wirelessmode == WIRELESS_MODE_N_24G) 3645 ratr_index = RATR_INX_WIRELESS_NGB; 3646 else 3647 ratr_index = RATR_INX_WIRELESS_NG; 3648 3649 if (mimo_ps == IEEE80211_SMPS_STATIC 3650 || mimo_ps == IEEE80211_SMPS_DYNAMIC) { 3651 if (rssi_level == 1) 3652 ratr_bitmap &= 0x000f0000; 3653 else if (rssi_level == 2) 3654 ratr_bitmap &= 0x000ff000; 3655 else 3656 ratr_bitmap &= 0x000ff005; 3657 } else { 3658 if (rf_type == RF_1T1R) { 3659 if (curtxbw_40mhz) { 3660 if (rssi_level == 1) 3661 ratr_bitmap &= 0x000f0000; 3662 else if (rssi_level == 2) 3663 ratr_bitmap &= 0x000ff000; 3664 else 3665 ratr_bitmap &= 0x000ff015; 3666 } else { 3667 if (rssi_level == 1) 3668 ratr_bitmap &= 0x000f0000; 3669 else if (rssi_level == 2) 3670 ratr_bitmap &= 0x000ff000; 3671 else 3672 ratr_bitmap &= 0x000ff005; 3673 } 3674 } else { 3675 if (curtxbw_40mhz) { 3676 if (rssi_level == 1) 3677 ratr_bitmap &= 0x0fff0000; 3678 else if (rssi_level == 2) 3679 ratr_bitmap &= 0x0ffff000; 3680 else 3681 ratr_bitmap &= 0x0ffff015; 3682 } else { 3683 if (rssi_level == 1) 3684 ratr_bitmap &= 0x0fff0000; 3685 else if (rssi_level == 2) 3686 ratr_bitmap &= 0x0ffff000; 3687 else 3688 ratr_bitmap &= 0x0ffff005; 3689 } 3690 } 3691 } 3692 break; 3693 3694 case WIRELESS_MODE_AC_24G: 3695 ratr_index = RATR_INX_WIRELESS_AC_24N; 3696 if (rssi_level == 1) 3697 ratr_bitmap &= 0xfc3f0000; 3698 else if (rssi_level == 2) 3699 ratr_bitmap &= 0xfffff000; 3700 else 3701 ratr_bitmap &= 0xffffffff; 3702 break; 3703 3704 case WIRELESS_MODE_AC_5G: 3705 ratr_index = RATR_INX_WIRELESS_AC_5N; 3706 3707 if (rf_type == RF_1T1R) { 3708 if (rssi_level == 1) /*add by Gary for ac-series*/ 3709 ratr_bitmap &= 0x003f8000; 3710 else if (rssi_level == 2) 3711 ratr_bitmap &= 0x003ff000; 3712 else 3713 ratr_bitmap &= 0x003ff010; 3714 } else { 3715 if (rssi_level == 1) 3716 ratr_bitmap &= 0xfe3f8000; 3717 else if (rssi_level == 2) 3718 ratr_bitmap &= 0xfffff000; 3719 else 3720 ratr_bitmap &= 0xfffff010; 3721 } 3722 break; 3723 3724 default: 3725 ratr_index = RATR_INX_WIRELESS_NGB; 3726 3727 if (rf_type == RF_1T2R) 3728 ratr_bitmap &= 0x000ff0ff; 3729 else 3730 ratr_bitmap &= 0x0f8ff0ff; 3731 break; 3732 } 3733 3734 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode); 3735 sta_entry->ratr_index = ratr_index; 3736 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode, 3737 ratr_bitmap); 3738 3739 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3740 "ratr_bitmap :%x\n", ratr_bitmap); 3741 3742 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) | 3743 (ratr_index << 28)); */ 3744 3745 rate_mask[0] = macid; 3746 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 3747 rate_mask[2] = rtlphy->current_chan_bw 3748 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap) 3749 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode); 3750 3751 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 3752 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 3753 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 3754 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 3755 3756 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3757 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 3758 ratr_index, ratr_bitmap, 3759 rate_mask[0], rate_mask[1], 3760 rate_mask[2], rate_mask[3], 3761 rate_mask[4], rate_mask[5], 3762 rate_mask[6]); 3763 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask); 3764 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 3765 } 3766 3767 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 3768 struct ieee80211_sta *sta, u8 rssi_level) 3769 { 3770 struct rtl_priv *rtlpriv = rtl_priv(hw); 3771 if (rtlpriv->dm.useramask) 3772 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level); 3773 else 3774 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD, 3775 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/ 3776 rtl8821ae_update_hal_rate_table(hw, sta); 3777 } 3778 3779 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw) 3780 { 3781 struct rtl_priv *rtlpriv = rtl_priv(hw); 3782 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3783 u16 wireless_mode = mac->mode; 3784 u8 sifs_timer, r2t_sifs; 3785 3786 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 3787 (u8 *)&mac->slot_time); 3788 if (wireless_mode == WIRELESS_MODE_G) 3789 sifs_timer = 0x0a; 3790 else 3791 sifs_timer = 0x0e; 3792 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 3793 3794 r2t_sifs = 0xa; 3795 3796 if (wireless_mode == WIRELESS_MODE_AC_5G && 3797 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) && 3798 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) { 3799 if (mac->vendor == PEER_ATH) 3800 r2t_sifs = 0x8; 3801 else 3802 r2t_sifs = 0xa; 3803 } else if (wireless_mode == WIRELESS_MODE_AC_5G) { 3804 r2t_sifs = 0xa; 3805 } 3806 3807 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs); 3808 } 3809 3810 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 3811 { 3812 struct rtl_priv *rtlpriv = rtl_priv(hw); 3813 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3814 struct rtl_phy *rtlphy = &rtlpriv->phy; 3815 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 3816 u8 u1tmp = 0; 3817 bool b_actuallyset = false; 3818 3819 if (rtlpriv->rtlhal.being_init_adapter) 3820 return false; 3821 3822 if (ppsc->swrf_processing) 3823 return false; 3824 3825 spin_lock(&rtlpriv->locks.rf_ps_lock); 3826 if (ppsc->rfchange_inprogress) { 3827 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3828 return false; 3829 } else { 3830 ppsc->rfchange_inprogress = true; 3831 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3832 } 3833 3834 cur_rfstate = ppsc->rfpwr_state; 3835 3836 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 3837 rtl_read_byte(rtlpriv, 3838 REG_GPIO_IO_SEL_2) & ~(BIT(1))); 3839 3840 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 3841 3842 if (rtlphy->polarity_ctl) 3843 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 3844 else 3845 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 3846 3847 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 3848 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3849 "GPIOChangeRF - HW Radio ON, RF ON\n"); 3850 3851 e_rfpowerstate_toset = ERFON; 3852 ppsc->hwradiooff = false; 3853 b_actuallyset = true; 3854 } else if ((!ppsc->hwradiooff) 3855 && (e_rfpowerstate_toset == ERFOFF)) { 3856 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3857 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 3858 3859 e_rfpowerstate_toset = ERFOFF; 3860 ppsc->hwradiooff = true; 3861 b_actuallyset = true; 3862 } 3863 3864 if (b_actuallyset) { 3865 spin_lock(&rtlpriv->locks.rf_ps_lock); 3866 ppsc->rfchange_inprogress = false; 3867 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3868 } else { 3869 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 3870 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3871 3872 spin_lock(&rtlpriv->locks.rf_ps_lock); 3873 ppsc->rfchange_inprogress = false; 3874 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3875 } 3876 3877 *valid = 1; 3878 return !ppsc->hwradiooff; 3879 } 3880 3881 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index, 3882 u8 *p_macaddr, bool is_group, u8 enc_algo, 3883 bool is_wepkey, bool clear_all) 3884 { 3885 struct rtl_priv *rtlpriv = rtl_priv(hw); 3886 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3887 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3888 u8 *macaddr = p_macaddr; 3889 u32 entry_id = 0; 3890 bool is_pairwise = false; 3891 3892 static u8 cam_const_addr[4][6] = { 3893 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 3894 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 3895 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 3896 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 3897 }; 3898 static u8 cam_const_broad[] = { 3899 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 3900 }; 3901 3902 if (clear_all) { 3903 u8 idx = 0; 3904 u8 cam_offset = 0; 3905 u8 clear_number = 5; 3906 3907 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 3908 3909 for (idx = 0; idx < clear_number; idx++) { 3910 rtl_cam_mark_invalid(hw, cam_offset + idx); 3911 rtl_cam_empty_entry(hw, cam_offset + idx); 3912 3913 if (idx < 5) { 3914 memset(rtlpriv->sec.key_buf[idx], 0, 3915 MAX_KEY_LEN); 3916 rtlpriv->sec.key_len[idx] = 0; 3917 } 3918 } 3919 } else { 3920 switch (enc_algo) { 3921 case WEP40_ENCRYPTION: 3922 enc_algo = CAM_WEP40; 3923 break; 3924 case WEP104_ENCRYPTION: 3925 enc_algo = CAM_WEP104; 3926 break; 3927 case TKIP_ENCRYPTION: 3928 enc_algo = CAM_TKIP; 3929 break; 3930 case AESCCMP_ENCRYPTION: 3931 enc_algo = CAM_AES; 3932 break; 3933 default: 3934 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 3935 "switch case %#x not processed\n", enc_algo); 3936 enc_algo = CAM_TKIP; 3937 break; 3938 } 3939 3940 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 3941 macaddr = cam_const_addr[key_index]; 3942 entry_id = key_index; 3943 } else { 3944 if (is_group) { 3945 macaddr = cam_const_broad; 3946 entry_id = key_index; 3947 } else { 3948 if (mac->opmode == NL80211_IFTYPE_AP) { 3949 entry_id = rtl_cam_get_free_entry(hw, p_macaddr); 3950 if (entry_id >= TOTAL_CAM_ENTRY) { 3951 pr_err("an not find free hwsecurity cam entry\n"); 3952 return; 3953 } 3954 } else { 3955 entry_id = CAM_PAIRWISE_KEY_POSITION; 3956 } 3957 3958 key_index = PAIRWISE_KEYIDX; 3959 is_pairwise = true; 3960 } 3961 } 3962 3963 if (rtlpriv->sec.key_len[key_index] == 0) { 3964 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3965 "delete one entry, entry_id is %d\n", 3966 entry_id); 3967 if (mac->opmode == NL80211_IFTYPE_AP) 3968 rtl_cam_del_entry(hw, p_macaddr); 3969 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 3970 } else { 3971 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3972 "add one entry\n"); 3973 if (is_pairwise) { 3974 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3975 "set Pairwise key\n"); 3976 3977 rtl_cam_add_one_entry(hw, macaddr, key_index, 3978 entry_id, enc_algo, 3979 CAM_CONFIG_NO_USEDK, 3980 rtlpriv->sec.key_buf[key_index]); 3981 } else { 3982 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3983 "set group key\n"); 3984 3985 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 3986 rtl_cam_add_one_entry(hw, 3987 rtlefuse->dev_addr, 3988 PAIRWISE_KEYIDX, 3989 CAM_PAIRWISE_KEY_POSITION, 3990 enc_algo, 3991 CAM_CONFIG_NO_USEDK, 3992 rtlpriv->sec.key_buf 3993 [entry_id]); 3994 } 3995 3996 rtl_cam_add_one_entry(hw, macaddr, key_index, 3997 entry_id, enc_algo, 3998 CAM_CONFIG_NO_USEDK, 3999 rtlpriv->sec.key_buf[entry_id]); 4000 } 4001 } 4002 } 4003 } 4004 4005 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw) 4006 { 4007 struct rtl_priv *rtlpriv = rtl_priv(hw); 4008 4009 /* 0:Low, 1:High, 2:From Efuse. */ 4010 rtlpriv->btcoexist.reg_bt_iso = 2; 4011 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 4012 rtlpriv->btcoexist.reg_bt_sco = 3; 4013 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 4014 rtlpriv->btcoexist.reg_bt_sco = 0; 4015 } 4016 4017 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw) 4018 { 4019 struct rtl_priv *rtlpriv = rtl_priv(hw); 4020 4021 if (rtlpriv->cfg->ops->get_btc_status()) 4022 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 4023 } 4024 4025 void rtl8821ae_suspend(struct ieee80211_hw *hw) 4026 { 4027 } 4028 4029 void rtl8821ae_resume(struct ieee80211_hw *hw) 4030 { 4031 } 4032 4033 /* Turn on AAP (RCR:bit 0) for promicuous mode. */ 4034 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw, 4035 bool allow_all_da, bool write_into_reg) 4036 { 4037 struct rtl_priv *rtlpriv = rtl_priv(hw); 4038 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 4039 4040 if (allow_all_da) /* Set BIT0 */ 4041 rtlpci->receive_config |= RCR_AAP; 4042 else /* Clear BIT0 */ 4043 rtlpci->receive_config &= ~RCR_AAP; 4044 4045 if (write_into_reg) 4046 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 4047 4048 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 4049 "receive_config=0x%08X, write_into_reg=%d\n", 4050 rtlpci->receive_config, write_into_reg); 4051 } 4052 4053 /* WKFMCAMAddAllEntry8812 */ 4054 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw, 4055 struct rtl_wow_pattern *rtl_pattern, 4056 u8 index) 4057 { 4058 struct rtl_priv *rtlpriv = rtl_priv(hw); 4059 u32 cam = 0; 4060 u8 addr = 0; 4061 u16 rxbuf_addr; 4062 u8 tmp, count = 0; 4063 u16 cam_start; 4064 u16 offset; 4065 4066 /* Count the WFCAM entry start offset. */ 4067 4068 /* RX page size = 128 byte */ 4069 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128; 4070 /* We should start from the boundry */ 4071 cam_start = offset * 128; 4072 4073 /* Enable Rx packet buffer access. */ 4074 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); 4075 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) { 4076 /* Set Rx packet buffer offset. 4077 * RxBufer pointer increases 1, 4078 * we can access 8 bytes in Rx packet buffer. 4079 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE 4080 * RxBufer addr = (CAM start offset + 4081 * per entry offset of a WKFM CAM)/8 4082 * * index: The index of the wake up frame mask 4083 * * WKFMCAM_SIZE: the total size of one WKFM CAM 4084 * * per entry offset of a WKFM CAM: Addr*4 bytes 4085 */ 4086 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3; 4087 /* Set R/W start offset */ 4088 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr); 4089 4090 if (addr == 0) { 4091 cam = BIT(31) | rtl_pattern->crc; 4092 4093 if (rtl_pattern->type == UNICAST_PATTERN) 4094 cam |= BIT(24); 4095 else if (rtl_pattern->type == MULTICAST_PATTERN) 4096 cam |= BIT(25); 4097 else if (rtl_pattern->type == BROADCAST_PATTERN) 4098 cam |= BIT(26); 4099 4100 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4101 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4102 "WRITE entry[%d] 0x%x: %x\n", addr, 4103 REG_PKTBUF_DBG_DATA_L, cam); 4104 4105 /* Write to Rx packet buffer. */ 4106 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4107 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */ 4108 cam = rtl_pattern->mask[addr - 2]; 4109 4110 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4111 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4112 "WRITE entry[%d] 0x%x: %x\n", addr, 4113 REG_PKTBUF_DBG_DATA_L, cam); 4114 4115 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4116 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */ 4117 cam = rtl_pattern->mask[addr - 2]; 4118 4119 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam); 4120 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4121 "WRITE entry[%d] 0x%x: %x\n", addr, 4122 REG_PKTBUF_DBG_DATA_H, cam); 4123 4124 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001); 4125 } 4126 4127 count = 0; 4128 do { 4129 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL); 4130 udelay(2); 4131 count++; 4132 } while (tmp && count < 100); 4133 4134 WARN_ONCE((count >= 100), 4135 "rtl8821ae: Write wake up frame mask FAIL %d value!\n", 4136 tmp); 4137 } 4138 /* Disable Rx packet buffer access. */ 4139 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, 4140 DISABLE_TRXPKT_BUF_ACCESS); 4141 } 4142