1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 #include "../pwrseqcmd.h" 41 #include "pwrseq.h" 42 #include "../btcoexist/rtl_btc.h" 43 44 #define LLT_CONFIG 5 45 46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 51 unsigned long flags; 52 53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 54 while (skb_queue_len(&ring->queue)) { 55 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 56 struct sk_buff *skb = __skb_dequeue(&ring->queue); 57 58 pci_unmap_single(rtlpci->pdev, 59 rtlpriv->cfg->ops->get_desc( 60 hw, 61 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 62 skb->len, PCI_DMA_TODEVICE); 63 kfree_skb(skb); 64 ring->idx = (ring->idx + 1) % ring->entries; 65 } 66 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 67 } 68 69 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 70 u8 set_bits, u8 clear_bits) 71 { 72 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 73 struct rtl_priv *rtlpriv = rtl_priv(hw); 74 75 rtlpci->reg_bcn_ctrl_val |= set_bits; 76 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 77 78 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 79 } 80 81 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw) 82 { 83 struct rtl_priv *rtlpriv = rtl_priv(hw); 84 u8 tmp1byte; 85 86 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 87 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 88 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 89 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 90 tmp1byte &= ~(BIT(0)); 91 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 92 } 93 94 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw) 95 { 96 struct rtl_priv *rtlpriv = rtl_priv(hw); 97 u8 tmp1byte; 98 99 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 100 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 101 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 102 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 103 tmp1byte |= BIT(0); 104 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 105 } 106 107 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw) 108 { 109 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); 110 } 111 112 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw) 113 { 114 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0); 115 } 116 117 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw, 118 u8 rpwm_val, bool b_need_turn_off_ckk) 119 { 120 struct rtl_priv *rtlpriv = rtl_priv(hw); 121 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 122 bool b_support_remote_wake_up; 123 u32 count = 0, isr_regaddr, content; 124 bool b_schedule_timer = b_need_turn_off_ckk; 125 126 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 127 (u8 *)(&b_support_remote_wake_up)); 128 129 if (!rtlhal->fw_ready) 130 return; 131 if (!rtlpriv->psc.fw_current_inpsmode) 132 return; 133 134 while (1) { 135 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 136 if (rtlhal->fw_clk_change_in_progress) { 137 while (rtlhal->fw_clk_change_in_progress) { 138 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 139 count++; 140 udelay(100); 141 if (count > 1000) 142 goto change_done; 143 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 144 } 145 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 146 } else { 147 rtlhal->fw_clk_change_in_progress = false; 148 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 149 goto change_done; 150 } 151 } 152 change_done: 153 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) { 154 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 155 (u8 *)(&rpwm_val)); 156 if (FW_PS_IS_ACK(rpwm_val)) { 157 isr_regaddr = REG_HISR; 158 content = rtl_read_dword(rtlpriv, isr_regaddr); 159 while (!(content & IMR_CPWM) && (count < 500)) { 160 udelay(50); 161 count++; 162 content = rtl_read_dword(rtlpriv, isr_regaddr); 163 } 164 165 if (content & IMR_CPWM) { 166 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 167 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE; 168 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 169 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n", 170 rtlhal->fw_ps_state); 171 } 172 } 173 174 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 175 rtlhal->fw_clk_change_in_progress = false; 176 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 177 if (b_schedule_timer) 178 mod_timer(&rtlpriv->works.fw_clockoff_timer, 179 jiffies + MSECS(10)); 180 } else { 181 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 182 rtlhal->fw_clk_change_in_progress = false; 183 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 184 } 185 } 186 187 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw, 188 u8 rpwm_val) 189 { 190 struct rtl_priv *rtlpriv = rtl_priv(hw); 191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 193 struct rtl8192_tx_ring *ring; 194 enum rf_pwrstate rtstate; 195 bool b_schedule_timer = false; 196 u8 queue; 197 198 if (!rtlhal->fw_ready) 199 return; 200 if (!rtlpriv->psc.fw_current_inpsmode) 201 return; 202 if (!rtlhal->allow_sw_to_change_hwclc) 203 return; 204 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 205 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 206 return; 207 208 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 209 ring = &rtlpci->tx_ring[queue]; 210 if (skb_queue_len(&ring->queue)) { 211 b_schedule_timer = true; 212 break; 213 } 214 } 215 216 if (b_schedule_timer) { 217 mod_timer(&rtlpriv->works.fw_clockoff_timer, 218 jiffies + MSECS(10)); 219 return; 220 } 221 222 if (FW_PS_STATE(rtlhal->fw_ps_state) != 223 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) { 224 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 225 if (!rtlhal->fw_clk_change_in_progress) { 226 rtlhal->fw_clk_change_in_progress = true; 227 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 228 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 229 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 230 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 231 (u8 *)(&rpwm_val)); 232 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 233 rtlhal->fw_clk_change_in_progress = false; 234 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 235 } else { 236 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 237 mod_timer(&rtlpriv->works.fw_clockoff_timer, 238 jiffies + MSECS(10)); 239 } 240 } 241 } 242 243 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw) 244 { 245 u8 rpwm_val = 0; 246 247 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK); 248 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true); 249 } 250 251 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw) 252 { 253 struct rtl_priv *rtlpriv = rtl_priv(hw); 254 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 255 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 256 bool fw_current_inps = false; 257 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 258 259 if (ppsc->low_power_enable) { 260 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */ 261 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false); 262 rtlhal->allow_sw_to_change_hwclc = false; 263 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 264 (u8 *)(&fw_pwrmode)); 265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 266 (u8 *)(&fw_current_inps)); 267 } else { 268 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */ 269 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 270 (u8 *)(&rpwm_val)); 271 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 272 (u8 *)(&fw_pwrmode)); 273 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 274 (u8 *)(&fw_current_inps)); 275 } 276 } 277 278 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw) 279 { 280 struct rtl_priv *rtlpriv = rtl_priv(hw); 281 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 282 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 283 bool fw_current_inps = true; 284 u8 rpwm_val; 285 286 if (ppsc->low_power_enable) { 287 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */ 288 rtlpriv->cfg->ops->set_hw_reg(hw, 289 HW_VAR_FW_PSMODE_STATUS, 290 (u8 *)(&fw_current_inps)); 291 rtlpriv->cfg->ops->set_hw_reg(hw, 292 HW_VAR_H2C_FW_PWRMODE, 293 (u8 *)(&ppsc->fwctrl_psmode)); 294 rtlhal->allow_sw_to_change_hwclc = true; 295 _rtl8821ae_set_fw_clock_off(hw, rpwm_val); 296 } else { 297 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */ 298 rtlpriv->cfg->ops->set_hw_reg(hw, 299 HW_VAR_FW_PSMODE_STATUS, 300 (u8 *)(&fw_current_inps)); 301 rtlpriv->cfg->ops->set_hw_reg(hw, 302 HW_VAR_H2C_FW_PWRMODE, 303 (u8 *)(&ppsc->fwctrl_psmode)); 304 rtlpriv->cfg->ops->set_hw_reg(hw, 305 HW_VAR_SET_RPWM, 306 (u8 *)(&rpwm_val)); 307 } 308 } 309 310 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw, 311 bool dl_whole_packets) 312 { 313 struct rtl_priv *rtlpriv = rtl_priv(hw); 314 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 315 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 316 u8 count = 0, dlbcn_count = 0; 317 bool send_beacon = false; 318 319 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 320 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0))); 321 322 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 323 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 324 325 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 326 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 327 tmp_reg422 & (~BIT(6))); 328 if (tmp_reg422 & BIT(6)) 329 send_beacon = true; 330 331 do { 332 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 333 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 334 (bcnvalid_reg | BIT(0))); 335 _rtl8821ae_return_beacon_queue_skb(hw); 336 337 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 338 rtl8812ae_set_fw_rsvdpagepkt(hw, false, 339 dl_whole_packets); 340 else 341 rtl8821ae_set_fw_rsvdpagepkt(hw, false, 342 dl_whole_packets); 343 344 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 345 count = 0; 346 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 347 count++; 348 udelay(10); 349 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 350 } 351 dlbcn_count++; 352 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 353 354 if (!(bcnvalid_reg & BIT(0))) 355 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 356 "Download RSVD page failed!\n"); 357 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) { 358 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0)); 359 _rtl8821ae_return_beacon_queue_skb(hw); 360 if (send_beacon) { 361 dlbcn_count = 0; 362 do { 363 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 364 bcnvalid_reg | BIT(0)); 365 366 _rtl8821ae_return_beacon_queue_skb(hw); 367 368 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 369 rtl8812ae_set_fw_rsvdpagepkt(hw, true, 370 false); 371 else 372 rtl8821ae_set_fw_rsvdpagepkt(hw, true, 373 false); 374 375 /* check rsvd page download OK. */ 376 bcnvalid_reg = rtl_read_byte(rtlpriv, 377 REG_TDECTRL + 2); 378 count = 0; 379 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 380 count++; 381 udelay(10); 382 bcnvalid_reg = 383 rtl_read_byte(rtlpriv, 384 REG_TDECTRL + 2); 385 } 386 dlbcn_count++; 387 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 388 389 if (!(bcnvalid_reg & BIT(0))) 390 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 391 "2 Download RSVD page failed!\n"); 392 } 393 } 394 395 if (bcnvalid_reg & BIT(0)) 396 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); 397 398 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 399 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 400 401 if (send_beacon) 402 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 403 404 if (!rtlhal->enter_pnp_sleep) { 405 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 406 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); 407 } 408 } 409 410 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 411 { 412 struct rtl_priv *rtlpriv = rtl_priv(hw); 413 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 414 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 415 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 416 417 switch (variable) { 418 case HW_VAR_ETHER_ADDR: 419 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID); 420 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4); 421 break; 422 case HW_VAR_BSSID: 423 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID); 424 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4); 425 break; 426 case HW_VAR_MEDIA_STATUS: 427 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3; 428 break; 429 case HW_VAR_SLOT_TIME: 430 *((u8 *)(val)) = mac->slot_time; 431 break; 432 case HW_VAR_BEACON_INTERVAL: 433 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL); 434 break; 435 case HW_VAR_ATIM_WINDOW: 436 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND); 437 break; 438 case HW_VAR_RCR: 439 *((u32 *)(val)) = rtlpci->receive_config; 440 break; 441 case HW_VAR_RF_STATE: 442 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 443 break; 444 case HW_VAR_FWLPS_RF_ON:{ 445 enum rf_pwrstate rfstate; 446 u32 val_rcr; 447 448 rtlpriv->cfg->ops->get_hw_reg(hw, 449 HW_VAR_RF_STATE, 450 (u8 *)(&rfstate)); 451 if (rfstate == ERFOFF) { 452 *((bool *)(val)) = true; 453 } else { 454 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 455 val_rcr &= 0x00070000; 456 if (val_rcr) 457 *((bool *)(val)) = false; 458 else 459 *((bool *)(val)) = true; 460 } 461 break; } 462 case HW_VAR_FW_PSMODE_STATUS: 463 *((bool *)(val)) = ppsc->fw_current_inpsmode; 464 break; 465 case HW_VAR_CORRECT_TSF:{ 466 u64 tsf; 467 u32 *ptsf_low = (u32 *)&tsf; 468 u32 *ptsf_high = ((u32 *)&tsf) + 1; 469 470 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 471 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 472 473 *((u64 *)(val)) = tsf; 474 475 break; } 476 case HAL_DEF_WOWLAN: 477 if (ppsc->wo_wlan_mode) 478 *((bool *)(val)) = true; 479 else 480 *((bool *)(val)) = false; 481 break; 482 default: 483 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 484 "switch case %#x not processed\n", variable); 485 break; 486 } 487 } 488 489 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 490 { 491 struct rtl_priv *rtlpriv = rtl_priv(hw); 492 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 493 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 494 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 495 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 496 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 497 u8 idx; 498 499 switch (variable) { 500 case HW_VAR_ETHER_ADDR:{ 501 for (idx = 0; idx < ETH_ALEN; idx++) { 502 rtl_write_byte(rtlpriv, (REG_MACID + idx), 503 val[idx]); 504 } 505 break; 506 } 507 case HW_VAR_BASIC_RATE:{ 508 u16 b_rate_cfg = ((u16 *)val)[0]; 509 b_rate_cfg = b_rate_cfg & 0x15f; 510 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg); 511 break; 512 } 513 case HW_VAR_BSSID:{ 514 for (idx = 0; idx < ETH_ALEN; idx++) { 515 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 516 val[idx]); 517 } 518 break; 519 } 520 case HW_VAR_SIFS: 521 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 522 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]); 523 524 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 525 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 526 527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 528 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]); 529 break; 530 case HW_VAR_R2T_SIFS: 531 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 532 break; 533 case HW_VAR_SLOT_TIME:{ 534 u8 e_aci; 535 536 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 537 "HW_VAR_SLOT_TIME %x\n", val[0]); 538 539 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 540 541 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 542 rtlpriv->cfg->ops->set_hw_reg(hw, 543 HW_VAR_AC_PARAM, 544 (u8 *)(&e_aci)); 545 } 546 break; } 547 case HW_VAR_ACK_PREAMBLE:{ 548 u8 reg_tmp; 549 u8 short_preamble = (bool)(*(u8 *)val); 550 551 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 552 if (short_preamble) { 553 reg_tmp |= BIT(1); 554 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, 555 reg_tmp); 556 } else { 557 reg_tmp &= (~BIT(1)); 558 rtl_write_byte(rtlpriv, 559 REG_TRXPTCL_CTL + 2, 560 reg_tmp); 561 } 562 break; } 563 case HW_VAR_WPA_CONFIG: 564 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 565 break; 566 case HW_VAR_AMPDU_MIN_SPACE:{ 567 u8 min_spacing_to_set; 568 u8 sec_min_space; 569 570 min_spacing_to_set = *((u8 *)val); 571 if (min_spacing_to_set <= 7) { 572 sec_min_space = 0; 573 574 if (min_spacing_to_set < sec_min_space) 575 min_spacing_to_set = sec_min_space; 576 577 mac->min_space_cfg = ((mac->min_space_cfg & 578 0xf8) | 579 min_spacing_to_set); 580 581 *val = min_spacing_to_set; 582 583 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 584 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 585 mac->min_space_cfg); 586 587 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 588 mac->min_space_cfg); 589 } 590 break; } 591 case HW_VAR_SHORTGI_DENSITY:{ 592 u8 density_to_set; 593 594 density_to_set = *((u8 *)val); 595 mac->min_space_cfg |= (density_to_set << 3); 596 597 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 598 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 599 mac->min_space_cfg); 600 601 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 602 mac->min_space_cfg); 603 604 break; } 605 case HW_VAR_AMPDU_FACTOR:{ 606 u32 ampdu_len = (*((u8 *)val)); 607 608 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 609 if (ampdu_len < VHT_AGG_SIZE_128K) 610 ampdu_len = 611 (0x2000 << (*((u8 *)val))) - 1; 612 else 613 ampdu_len = 0x1ffff; 614 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 615 if (ampdu_len < HT_AGG_SIZE_64K) 616 ampdu_len = 617 (0x2000 << (*((u8 *)val))) - 1; 618 else 619 ampdu_len = 0xffff; 620 } 621 ampdu_len |= BIT(31); 622 623 rtl_write_dword(rtlpriv, 624 REG_AMPDU_MAX_LENGTH_8812, ampdu_len); 625 break; } 626 case HW_VAR_AC_PARAM:{ 627 u8 e_aci = *((u8 *)val); 628 629 rtl8821ae_dm_init_edca_turbo(hw); 630 if (rtlpci->acm_method != EACMWAY2_SW) 631 rtlpriv->cfg->ops->set_hw_reg(hw, 632 HW_VAR_ACM_CTRL, 633 (u8 *)(&e_aci)); 634 break; } 635 case HW_VAR_ACM_CTRL:{ 636 u8 e_aci = *((u8 *)val); 637 union aci_aifsn *p_aci_aifsn = 638 (union aci_aifsn *)(&mac->ac[0].aifs); 639 u8 acm = p_aci_aifsn->f.acm; 640 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 641 642 acm_ctrl = 643 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 644 645 if (acm) { 646 switch (e_aci) { 647 case AC0_BE: 648 acm_ctrl |= ACMHW_BEQEN; 649 break; 650 case AC2_VI: 651 acm_ctrl |= ACMHW_VIQEN; 652 break; 653 case AC3_VO: 654 acm_ctrl |= ACMHW_VOQEN; 655 break; 656 default: 657 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 658 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 659 acm); 660 break; 661 } 662 } else { 663 switch (e_aci) { 664 case AC0_BE: 665 acm_ctrl &= (~ACMHW_BEQEN); 666 break; 667 case AC2_VI: 668 acm_ctrl &= (~ACMHW_VIQEN); 669 break; 670 case AC3_VO: 671 acm_ctrl &= (~ACMHW_VOQEN); 672 break; 673 default: 674 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 675 "switch case %#x not processed\n", 676 e_aci); 677 break; 678 } 679 } 680 681 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 682 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 683 acm_ctrl); 684 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 685 break; } 686 case HW_VAR_RCR: 687 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 688 rtlpci->receive_config = ((u32 *)(val))[0]; 689 break; 690 case HW_VAR_RETRY_LIMIT:{ 691 u8 retry_limit = ((u8 *)(val))[0]; 692 693 rtl_write_word(rtlpriv, REG_RL, 694 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 695 retry_limit << RETRY_LIMIT_LONG_SHIFT); 696 break; } 697 case HW_VAR_DUAL_TSF_RST: 698 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 699 break; 700 case HW_VAR_EFUSE_BYTES: 701 rtlefuse->efuse_usedbytes = *((u16 *)val); 702 break; 703 case HW_VAR_EFUSE_USAGE: 704 rtlefuse->efuse_usedpercentage = *((u8 *)val); 705 break; 706 case HW_VAR_IO_CMD: 707 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); 708 break; 709 case HW_VAR_SET_RPWM:{ 710 u8 rpwm_val; 711 712 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 713 udelay(1); 714 715 if (rpwm_val & BIT(7)) { 716 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 717 (*(u8 *)val)); 718 } else { 719 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 720 ((*(u8 *)val) | BIT(7))); 721 } 722 723 break; } 724 case HW_VAR_H2C_FW_PWRMODE: 725 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 726 break; 727 case HW_VAR_FW_PSMODE_STATUS: 728 ppsc->fw_current_inpsmode = *((bool *)val); 729 break; 730 case HW_VAR_INIT_RTS_RATE: 731 break; 732 case HW_VAR_RESUME_CLK_ON: 733 _rtl8821ae_set_fw_ps_rf_on(hw); 734 break; 735 case HW_VAR_FW_LPS_ACTION:{ 736 bool b_enter_fwlps = *((bool *)val); 737 738 if (b_enter_fwlps) 739 _rtl8821ae_fwlps_enter(hw); 740 else 741 _rtl8821ae_fwlps_leave(hw); 742 break; } 743 case HW_VAR_H2C_FW_JOINBSSRPT:{ 744 u8 mstatus = (*(u8 *)val); 745 746 if (mstatus == RT_MEDIA_CONNECT) { 747 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 748 NULL); 749 _rtl8821ae_download_rsvd_page(hw, false); 750 } 751 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus); 752 753 break; } 754 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 755 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 756 break; 757 case HW_VAR_AID:{ 758 u16 u2btmp; 759 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 760 u2btmp &= 0xC000; 761 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 762 mac->assoc_id)); 763 break; } 764 case HW_VAR_CORRECT_TSF:{ 765 u8 btype_ibss = ((u8 *)(val))[0]; 766 767 if (btype_ibss) 768 _rtl8821ae_stop_tx_beacon(hw); 769 770 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 771 772 rtl_write_dword(rtlpriv, REG_TSFTR, 773 (u32)(mac->tsf & 0xffffffff)); 774 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 775 (u32)((mac->tsf >> 32) & 0xffffffff)); 776 777 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 778 779 if (btype_ibss) 780 _rtl8821ae_resume_tx_beacon(hw); 781 break; } 782 case HW_VAR_NAV_UPPER: { 783 u32 us_nav_upper = *(u32 *)val; 784 785 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) { 786 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING, 787 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", 788 us_nav_upper, HAL_92C_NAV_UPPER_UNIT); 789 break; 790 } 791 rtl_write_byte(rtlpriv, REG_NAV_UPPER, 792 ((u8)((us_nav_upper + 793 HAL_92C_NAV_UPPER_UNIT - 1) / 794 HAL_92C_NAV_UPPER_UNIT))); 795 break; } 796 case HW_VAR_KEEP_ALIVE: { 797 u8 array[2]; 798 array[0] = 0xff; 799 array[1] = *((u8 *)val); 800 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, 801 array); 802 break; } 803 default: 804 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 805 "switch case %#x not processed\n", variable); 806 break; 807 } 808 } 809 810 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 811 { 812 struct rtl_priv *rtlpriv = rtl_priv(hw); 813 bool status = true; 814 long count = 0; 815 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 816 _LLT_OP(_LLT_WRITE_ACCESS); 817 818 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 819 820 do { 821 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 822 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 823 break; 824 825 if (count > POLLING_LLT_THRESHOLD) { 826 pr_err("Failed to polling write LLT done at address %d!\n", 827 address); 828 status = false; 829 break; 830 } 831 } while (++count); 832 833 return status; 834 } 835 836 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw) 837 { 838 struct rtl_priv *rtlpriv = rtl_priv(hw); 839 unsigned short i; 840 u8 txpktbuf_bndy; 841 u32 rqpn; 842 u8 maxpage; 843 bool status; 844 845 maxpage = 255; 846 txpktbuf_bndy = 0xF7; 847 rqpn = 0x80e60808; 848 849 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 850 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1); 851 852 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 853 854 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 855 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 856 857 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 858 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 859 860 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 861 status = _rtl8821ae_llt_write(hw, i, i + 1); 862 if (!status) 863 return status; 864 } 865 866 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 867 if (!status) 868 return status; 869 870 for (i = txpktbuf_bndy; i < maxpage; i++) { 871 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 872 if (!status) 873 return status; 874 } 875 876 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy); 877 if (!status) 878 return status; 879 880 rtl_write_dword(rtlpriv, REG_RQPN, rqpn); 881 882 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00); 883 884 return true; 885 } 886 887 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw) 888 { 889 struct rtl_priv *rtlpriv = rtl_priv(hw); 890 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 891 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 892 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 893 894 if (rtlpriv->rtlhal.up_first_time) 895 return; 896 897 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 898 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 899 rtl8812ae_sw_led_on(hw, pled0); 900 else 901 rtl8821ae_sw_led_on(hw, pled0); 902 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 903 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 904 rtl8812ae_sw_led_on(hw, pled0); 905 else 906 rtl8821ae_sw_led_on(hw, pled0); 907 else 908 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 909 rtl8812ae_sw_led_off(hw, pled0); 910 else 911 rtl8821ae_sw_led_off(hw, pled0); 912 } 913 914 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw) 915 { 916 struct rtl_priv *rtlpriv = rtl_priv(hw); 917 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 918 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 919 920 u8 bytetmp = 0; 921 u16 wordtmp = 0; 922 bool mac_func_enable = rtlhal->mac_func_enable; 923 924 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 925 926 /*Auto Power Down to CHIP-off State*/ 927 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 928 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 929 930 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 931 /* HW Power on sequence*/ 932 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 933 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 934 RTL8812_NIC_ENABLE_FLOW)) { 935 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 936 "init 8812 MAC Fail as power on failure\n"); 937 return false; 938 } 939 } else { 940 /* HW Power on sequence */ 941 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, 942 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 943 RTL8821A_NIC_ENABLE_FLOW)){ 944 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 945 "init 8821 MAC Fail as power on failure\n"); 946 return false; 947 } 948 } 949 950 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 951 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 952 953 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 954 bytetmp = 0xff; 955 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 956 mdelay(2); 957 958 bytetmp = 0xff; 959 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 960 mdelay(2); 961 962 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 963 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 964 if (bytetmp & BIT(0)) { 965 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 966 bytetmp |= BIT(6); 967 rtl_write_byte(rtlpriv, 0x7c, bytetmp); 968 } 969 } 970 971 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 972 bytetmp &= ~BIT(4); 973 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp); 974 975 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 976 977 if (!mac_func_enable) { 978 if (!_rtl8821ae_llt_table_init(hw)) 979 return false; 980 } 981 982 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 983 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 984 985 /* Enable FW Beamformer Interrupt */ 986 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3); 987 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); 988 989 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 990 wordtmp &= 0xf; 991 wordtmp |= 0xF5B1; 992 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 993 994 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 995 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 996 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 997 /*low address*/ 998 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 999 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1000 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1001 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1002 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1003 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1004 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1005 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1006 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1007 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1008 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1009 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1010 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1011 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1012 rtl_write_dword(rtlpriv, REG_RX_DESA, 1013 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1014 1015 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 1016 1017 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 1018 1019 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0); 1020 1021 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 1022 _rtl8821ae_gen_refresh_led_state(hw); 1023 1024 return true; 1025 } 1026 1027 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw) 1028 { 1029 struct rtl_priv *rtlpriv = rtl_priv(hw); 1030 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1031 u32 reg_rrsr; 1032 1033 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 1034 1035 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 1036 /* ARFB table 9 for 11ac 5G 2SS */ 1037 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000); 1038 /* ARFB table 10 for 11ac 5G 1SS */ 1039 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000); 1040 /* ARFB table 11 for 11ac 24G 1SS */ 1041 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015); 1042 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000); 1043 /* ARFB table 12 for 11ac 24G 1SS */ 1044 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015); 1045 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000); 1046 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */ 1047 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00); 1048 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70); 1049 1050 /*Set retry limit*/ 1051 rtl_write_word(rtlpriv, REG_RL, 0x0707); 1052 1053 /* Set Data / Response auto rate fallack retry count*/ 1054 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 1055 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 1056 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 1057 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 1058 1059 rtlpci->reg_bcn_ctrl_val = 0x1d; 1060 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 1061 1062 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 1063 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1064 1065 /* AGGR_BK_TIME Reg51A 0x16 */ 1066 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 1067 1068 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 1069 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 1070 1071 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80); 1072 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1073 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F); 1074 } 1075 1076 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr) 1077 { 1078 u16 ret = 0; 1079 u8 tmp = 0, count = 0; 1080 1081 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); 1082 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1083 count = 0; 1084 while (tmp && count < 20) { 1085 udelay(10); 1086 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1087 count++; 1088 } 1089 if (0 == tmp) 1090 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA); 1091 1092 return ret; 1093 } 1094 1095 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data) 1096 { 1097 u8 tmp = 0, count = 0; 1098 1099 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data); 1100 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); 1101 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1102 count = 0; 1103 while (tmp && count < 20) { 1104 udelay(10); 1105 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1106 count++; 1107 } 1108 } 1109 1110 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr) 1111 { 1112 u16 read_addr = addr & 0xfffc; 1113 u8 tmp = 0, count = 0, ret = 0; 1114 1115 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr); 1116 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2); 1117 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1118 count = 0; 1119 while (tmp && count < 20) { 1120 udelay(10); 1121 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1122 count++; 1123 } 1124 if (0 == tmp) { 1125 read_addr = REG_DBI_RDATA + addr % 4; 1126 ret = rtl_read_word(rtlpriv, read_addr); 1127 } 1128 return ret; 1129 } 1130 1131 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data) 1132 { 1133 u8 tmp = 0, count = 0; 1134 u16 write_addr, remainder = addr % 4; 1135 1136 write_addr = REG_DBI_WDATA + remainder; 1137 rtl_write_byte(rtlpriv, write_addr, data); 1138 1139 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); 1140 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr); 1141 1142 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1); 1143 1144 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1145 count = 0; 1146 while (tmp && count < 20) { 1147 udelay(10); 1148 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1149 count++; 1150 } 1151 } 1152 1153 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw) 1154 { 1155 struct rtl_priv *rtlpriv = rtl_priv(hw); 1156 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1157 u8 tmp; 1158 1159 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1160 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544) 1161 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544); 1162 1163 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070) 1164 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070); 1165 } 1166 1167 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f); 1168 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7)); 1169 1170 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719); 1171 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4)); 1172 1173 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1174 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1175 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4)); 1176 } 1177 } 1178 1179 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw) 1180 { 1181 struct rtl_priv *rtlpriv = rtl_priv(hw); 1182 u8 sec_reg_value; 1183 u8 tmp; 1184 1185 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1186 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1187 rtlpriv->sec.pairwise_enc_algorithm, 1188 rtlpriv->sec.group_enc_algorithm); 1189 1190 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1191 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1192 "not open hw encryption\n"); 1193 return; 1194 } 1195 1196 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1197 1198 if (rtlpriv->sec.use_defaultkey) { 1199 sec_reg_value |= SCR_TXUSEDK; 1200 sec_reg_value |= SCR_RXUSEDK; 1201 } 1202 1203 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1204 1205 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1206 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1207 1208 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1209 "The SECR-value %x\n", sec_reg_value); 1210 1211 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1212 } 1213 1214 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */ 1215 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0 1216 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1 1217 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2 1218 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3 1219 /* ----------------------------------------------------------- */ 1220 1221 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw) 1222 { 1223 struct rtl_priv *rtlpriv = rtl_priv(hw); 1224 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1, 1225 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1226 MAC_ID_STATIC_FOR_BT_CLIENT_END}; 1227 1228 rtlpriv->cfg->ops->set_hw_reg(hw, 1229 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt); 1230 1231 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1232 "Initialize MacId media status: from %d to %d\n", 1233 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1234 MAC_ID_STATIC_FOR_BT_CLIENT_END); 1235 } 1236 1237 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw) 1238 { 1239 struct rtl_priv *rtlpriv = rtl_priv(hw); 1240 u8 tmp; 1241 1242 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1243 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1244 if (!(tmp & BIT(2))) { 1245 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); 1246 mdelay(100); 1247 } 1248 1249 /* read reg 0x350 Bit[25] if 1 : RX hang */ 1250 /* read reg 0x350 Bit[24] if 1 : TX hang */ 1251 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1252 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1253 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1254 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n"); 1255 return true; 1256 } else { 1257 return false; 1258 } 1259 } 1260 1261 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw, 1262 bool mac_power_on, 1263 bool in_watchdog) 1264 { 1265 struct rtl_priv *rtlpriv = rtl_priv(hw); 1266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1267 u8 tmp; 1268 bool release_mac_rx_pause; 1269 u8 backup_pcie_dma_pause; 1270 1271 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1272 1273 /* 1. Disable register write lock. 0x1c[1] = 0 */ 1274 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1275 tmp &= ~(BIT(1)); 1276 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1277 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1278 /* write 0xCC bit[2] = 1'b1 */ 1279 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1280 tmp |= BIT(2); 1281 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1282 } 1283 1284 /* 2. Check and pause TRX DMA */ 1285 /* write 0x284 bit[18] = 1'b1 */ 1286 /* write 0x301 = 0xFF */ 1287 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1288 if (tmp & BIT(2)) { 1289 /* Already pause before the function for another purpose. */ 1290 release_mac_rx_pause = false; 1291 } else { 1292 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1293 release_mac_rx_pause = true; 1294 } 1295 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1296 if (backup_pcie_dma_pause != 0xFF) 1297 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1298 1299 if (mac_power_on) { 1300 /* 3. reset TRX function */ 1301 /* write 0x100 = 0x00 */ 1302 rtl_write_byte(rtlpriv, REG_CR, 0); 1303 } 1304 1305 /* 4. Reset PCIe DMA. 0x3[0] = 0 */ 1306 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1307 tmp &= ~(BIT(0)); 1308 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1309 1310 /* 5. Enable PCIe DMA. 0x3[0] = 1 */ 1311 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1312 tmp |= BIT(0); 1313 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1314 1315 if (mac_power_on) { 1316 /* 6. enable TRX function */ 1317 /* write 0x100 = 0xFF */ 1318 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1319 1320 /* We should init LLT & RQPN and 1321 * prepare Tx/Rx descrptor address later 1322 * because MAC function is reset.*/ 1323 } 1324 1325 /* 7. Restore PCIe autoload down bit */ 1326 /* 8812AE does not has the defination. */ 1327 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1328 /* write 0xF8 bit[17] = 1'b1 */ 1329 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1330 tmp |= BIT(1); 1331 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1332 } 1333 1334 /* In MAC power on state, BB and RF maybe in ON state, 1335 * if we release TRx DMA here. 1336 * it will cause packets to be started to Tx/Rx, 1337 * so we release Tx/Rx DMA later.*/ 1338 if (!mac_power_on/* || in_watchdog*/) { 1339 /* 8. release TRX DMA */ 1340 /* write 0x284 bit[18] = 1'b0 */ 1341 /* write 0x301 = 0x00 */ 1342 if (release_mac_rx_pause) { 1343 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1344 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1345 tmp & (~BIT(2))); 1346 } 1347 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1348 backup_pcie_dma_pause); 1349 } 1350 1351 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1352 /* 9. lock system register */ 1353 /* write 0xCC bit[2] = 1'b0 */ 1354 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1355 tmp &= ~(BIT(2)); 1356 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1357 } 1358 return true; 1359 } 1360 1361 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw) 1362 { 1363 struct rtl_priv *rtlpriv = rtl_priv(hw); 1364 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1365 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1366 u8 fw_reason = 0; 1367 1368 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN); 1369 1370 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n", 1371 fw_reason); 1372 1373 ppsc->wakeup_reason = 0; 1374 1375 rtlhal->last_suspend_sec = ktime_get_real_seconds(); 1376 1377 switch (fw_reason) { 1378 case FW_WOW_V2_PTK_UPDATE_EVENT: 1379 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE; 1380 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1381 "It's a WOL PTK Key update event!\n"); 1382 break; 1383 case FW_WOW_V2_GTK_UPDATE_EVENT: 1384 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE; 1385 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1386 "It's a WOL GTK Key update event!\n"); 1387 break; 1388 case FW_WOW_V2_DISASSOC_EVENT: 1389 ppsc->wakeup_reason = WOL_REASON_DISASSOC; 1390 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1391 "It's a disassociation event!\n"); 1392 break; 1393 case FW_WOW_V2_DEAUTH_EVENT: 1394 ppsc->wakeup_reason = WOL_REASON_DEAUTH; 1395 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1396 "It's a deauth event!\n"); 1397 break; 1398 case FW_WOW_V2_FW_DISCONNECT_EVENT: 1399 ppsc->wakeup_reason = WOL_REASON_AP_LOST; 1400 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1401 "It's a Fw disconnect decision (AP lost) event!\n"); 1402 break; 1403 case FW_WOW_V2_MAGIC_PKT_EVENT: 1404 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT; 1405 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1406 "It's a magic packet event!\n"); 1407 break; 1408 case FW_WOW_V2_UNICAST_PKT_EVENT: 1409 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT; 1410 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1411 "It's an unicast packet event!\n"); 1412 break; 1413 case FW_WOW_V2_PATTERN_PKT_EVENT: 1414 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT; 1415 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1416 "It's a pattern match event!\n"); 1417 break; 1418 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT: 1419 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH; 1420 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1421 "It's an RTD3 Ssid match event!\n"); 1422 break; 1423 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT: 1424 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT; 1425 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1426 "It's an RealWoW wake packet event!\n"); 1427 break; 1428 case FW_WOW_V2_REALWOW_V2_ACKLOST: 1429 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST; 1430 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1431 "It's an RealWoW ack lost event!\n"); 1432 break; 1433 default: 1434 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1435 "WOL Read 0x1c7 = %02X, Unknown reason!\n", 1436 fw_reason); 1437 break; 1438 } 1439 } 1440 1441 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw) 1442 { 1443 struct rtl_priv *rtlpriv = rtl_priv(hw); 1444 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1445 1446 /*low address*/ 1447 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 1448 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1449 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1450 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1451 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1452 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1453 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1454 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1455 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1456 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1457 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1458 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1459 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1460 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1461 rtl_write_dword(rtlpriv, REG_RX_DESA, 1462 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1463 } 1464 1465 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 1466 { 1467 bool status = true; 1468 u32 i; 1469 u32 txpktbuf_bndy = boundary; 1470 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER; 1471 1472 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) { 1473 status = _rtl8821ae_llt_write(hw, i , i + 1); 1474 if (!status) 1475 return status; 1476 } 1477 1478 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 1479 if (!status) 1480 return status; 1481 1482 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) { 1483 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 1484 if (!status) 1485 return status; 1486 } 1487 1488 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf, 1489 txpktbuf_bndy); 1490 if (!status) 1491 return status; 1492 1493 return status; 1494 } 1495 1496 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary, 1497 u16 npq_rqpn_value, u32 rqpn_val) 1498 { 1499 struct rtl_priv *rtlpriv = rtl_priv(hw); 1500 u8 tmp; 1501 bool ret = true; 1502 u16 count = 0, tmp16; 1503 bool support_remote_wakeup; 1504 1505 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1506 (u8 *)(&support_remote_wakeup)); 1507 1508 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1509 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n", 1510 boundary, npq_rqpn_value, rqpn_val); 1511 1512 /* stop PCIe DMA 1513 * 1. 0x301[7:0] = 0xFE */ 1514 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1515 1516 /* wait TXFF empty 1517 * 2. polling till 0x41A[15:0]=0x07FF */ 1518 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1519 while ((tmp16 & 0x07FF) != 0x07FF) { 1520 udelay(100); 1521 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1522 count++; 1523 if ((count % 200) == 0) { 1524 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1525 "Tx queue is not empty for 20ms!\n"); 1526 } 1527 if (count >= 1000) { 1528 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1529 "Wait for Tx FIFO empty timeout!\n"); 1530 break; 1531 } 1532 } 1533 1534 /* TX pause 1535 * 3. reg 0x522=0xFF */ 1536 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1537 1538 /* Wait TX State Machine OK 1539 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */ 1540 count = 0; 1541 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) { 1542 udelay(100); 1543 count++; 1544 if (count >= 500) { 1545 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1546 "Wait for TX State Machine ready timeout !!\n"); 1547 break; 1548 } 1549 } 1550 1551 /* stop RX DMA path 1552 * 5. 0x284[18] = 1 1553 * 6. wait till 0x284[17] == 1 1554 * wait RX DMA idle */ 1555 count = 0; 1556 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1557 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1558 do { 1559 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1560 udelay(10); 1561 count++; 1562 } while (!(tmp & BIT(1)) && count < 100); 1563 1564 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1565 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n", 1566 count, tmp); 1567 1568 /* reset BB 1569 * 7. 0x02 [0] = 0 */ 1570 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1571 tmp &= ~(BIT(0)); 1572 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp); 1573 1574 /* Reset TRX MAC 1575 * 8. 0x100 = 0x00 1576 * Delay (1ms) */ 1577 rtl_write_byte(rtlpriv, REG_CR, 0x00); 1578 udelay(1000); 1579 1580 /* Disable MAC Security Engine 1581 * 9. 0x100 bit[9]=0 */ 1582 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1583 tmp &= ~(BIT(1)); 1584 rtl_write_byte(rtlpriv, REG_CR + 1, tmp); 1585 1586 /* To avoid DD-Tim Circuit hang 1587 * 10. 0x553 bit[5]=1 */ 1588 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST); 1589 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5))); 1590 1591 /* Enable MAC Security Engine 1592 * 11. 0x100 bit[9]=1 */ 1593 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1594 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1))); 1595 1596 /* Enable TRX MAC 1597 * 12. 0x100 = 0xFF 1598 * Delay (1ms) */ 1599 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1600 udelay(1000); 1601 1602 /* Enable BB 1603 * 13. 0x02 [0] = 1 */ 1604 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1605 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0))); 1606 1607 /* beacon setting 1608 * 14,15. set beacon head page (reg 0x209 and 0x424) */ 1609 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary); 1610 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary); 1611 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary); 1612 1613 /* 16. WMAC_LBK_BF_HD 0x45D[7:0] 1614 * WMAC_LBK_BF_HD */ 1615 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, 1616 (u8)boundary); 1617 1618 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary); 1619 1620 /* init LLT 1621 * 17. init LLT */ 1622 if (!_rtl8821ae_init_llt_table(hw, boundary)) { 1623 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 1624 "Failed to init LLT table!\n"); 1625 return false; 1626 } 1627 1628 /* reallocate RQPN 1629 * 18. reallocate RQPN and init LLT */ 1630 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value); 1631 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val); 1632 1633 /* release Tx pause 1634 * 19. 0x522=0x00 */ 1635 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1636 1637 /* enable PCIE DMA 1638 * 20. 0x301[7:0] = 0x00 1639 * 21. 0x284[18] = 0 */ 1640 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1641 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1642 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2))); 1643 1644 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n"); 1645 return ret; 1646 } 1647 1648 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw) 1649 { 1650 struct rtl_priv *rtlpriv = rtl_priv(hw); 1651 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1652 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1653 1654 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 1655 /* Re-download normal Fw. */ 1656 rtl8821ae_set_fw_related_for_wowlan(hw, false); 1657 #endif 1658 1659 /* Re-Initialize LLT table. */ 1660 if (rtlhal->re_init_llt_table) { 1661 u32 rqpn = 0x80e70808; 1662 u8 rqpn_npq = 0, boundary = 0xF8; 1663 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1664 rqpn = 0x80e90808; 1665 boundary = 0xFA; 1666 } 1667 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn)) 1668 rtlhal->re_init_llt_table = false; 1669 } 1670 1671 ppsc->rfpwr_state = ERFON; 1672 } 1673 1674 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw) 1675 { 1676 u8 tmp = 0; 1677 struct rtl_priv *rtlpriv = rtl_priv(hw); 1678 1679 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1680 1681 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160); 1682 if (!(tmp & (BIT(2) | BIT(3)))) { 1683 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD, 1684 "0x160(%#x)return!!\n", tmp); 1685 return; 1686 } 1687 1688 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b); 1689 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4))); 1690 1691 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1692 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5)); 1693 1694 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1695 } 1696 1697 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw) 1698 { 1699 u8 tmp = 0; 1700 struct rtl_priv *rtlpriv = rtl_priv(hw); 1701 1702 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1703 1704 /* Check 0x98[10] */ 1705 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99); 1706 if (!(tmp & BIT(2))) { 1707 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1708 "<---0x99(%#x) return!!\n", tmp); 1709 return; 1710 } 1711 1712 /* LTR idle latency, 0x90 for 144us */ 1713 rtl_write_dword(rtlpriv, 0x798, 0x88908890); 1714 1715 /* LTR active latency, 0x3c for 60us */ 1716 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c); 1717 1718 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1719 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4))); 1720 1721 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1722 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0)))); 1723 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0))); 1724 1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1726 } 1727 1728 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw) 1729 { 1730 struct rtl_priv *rtlpriv = rtl_priv(hw); 1731 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1732 bool init_finished = true; 1733 u8 tmp = 0; 1734 1735 /* Get Fw wake up reason. */ 1736 _rtl8821ae_get_wakeup_reason(hw); 1737 1738 /* Patch Pcie Rx DMA hang after S3/S4 several times. 1739 * The root cause has not be found. */ 1740 if (_rtl8821ae_check_pcie_dma_hang(hw)) 1741 _rtl8821ae_reset_pcie_interface_dma(hw, true, false); 1742 1743 /* Prepare Tx/Rx Desc Hw address. */ 1744 _rtl8821ae_init_trx_desc_hw_address(hw); 1745 1746 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */ 1747 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1748 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n"); 1749 1750 /* Check wake up event. 1751 * We should check wake packet bit before disable wowlan by H2C or 1752 * Fw will clear the bit. */ 1753 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3); 1754 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1755 "Read REG_FTISR 0x13f = %#X\n", tmp); 1756 1757 /* Set the WoWLAN related function control disable. */ 1758 rtl8821ae_set_fw_wowlan_mode(hw, false); 1759 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0); 1760 1761 if (rtlhal->hw_rof_enable) { 1762 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 1763 if (tmp & BIT(1)) { 1764 /* Clear GPIO9 ISR */ 1765 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 1766 init_finished = false; 1767 } else { 1768 init_finished = true; 1769 } 1770 } 1771 1772 if (init_finished) { 1773 _rtl8821ae_simple_initialize_adapter(hw); 1774 1775 /* Release Pcie Interface Tx DMA. */ 1776 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1777 /* Release Pcie RX DMA */ 1778 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02); 1779 1780 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1781 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0)))); 1782 1783 _rtl8821ae_enable_l1off(hw); 1784 _rtl8821ae_enable_ltr(hw); 1785 } 1786 1787 return init_finished; 1788 } 1789 1790 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw) 1791 { 1792 /* BB OFDM RX Path_A */ 1793 rtl_set_bbreg(hw, 0x808, 0xff, 0x11); 1794 /* BB OFDM TX Path_A */ 1795 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111); 1796 /* BB CCK R/Rx Path_A */ 1797 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0); 1798 /* MCS support */ 1799 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4); 1800 /* RF Path_B HSSI OFF */ 1801 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4); 1802 /* RF Path_B Power Down */ 1803 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0); 1804 /* ADDA Path_B OFF */ 1805 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0); 1806 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0); 1807 } 1808 1809 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw) 1810 { 1811 struct rtl_priv *rtlpriv = rtl_priv(hw); 1812 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1813 u8 u1b_tmp; 1814 1815 rtlhal->mac_func_enable = false; 1816 1817 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1818 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1819 /* 1. Run LPS WL RFOFF flow */ 1820 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1821 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"); 1822 */ 1823 rtl_hal_pwrseqcmdparsing(rtlpriv, 1824 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1825 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW); 1826 } 1827 /* 2. 0x1F[7:0] = 0 */ 1828 /* turn off RF */ 1829 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */ 1830 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1831 rtlhal->fw_ready) { 1832 rtl8821ae_firmware_selfreset(hw); 1833 } 1834 1835 /* Reset MCU. Suggested by Filen. */ 1836 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1837 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1838 1839 /* g. MCUFWDL 0x80[1:0]=0 */ 1840 /* reset MCU ready status */ 1841 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1842 1843 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1844 /* HW card disable configuration. */ 1845 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1846 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW); 1847 } else { 1848 /* HW card disable configuration. */ 1849 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1850 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW); 1851 } 1852 1853 /* Reset MCU IO Wrapper */ 1854 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1855 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1856 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1857 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1858 1859 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1860 /* lock ISO/CLK/Power control register */ 1861 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1862 } 1863 1864 int rtl8821ae_hw_init(struct ieee80211_hw *hw) 1865 { 1866 struct rtl_priv *rtlpriv = rtl_priv(hw); 1867 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1868 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1869 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1870 bool rtstatus = true; 1871 int err; 1872 u8 tmp_u1b; 1873 bool support_remote_wakeup; 1874 u32 nav_upper = WIFI_NAV_UPPER_US; 1875 1876 rtlhal->being_init_adapter = true; 1877 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1878 (u8 *)(&support_remote_wakeup)); 1879 rtlpriv->intf_ops->disable_aspm(hw); 1880 1881 /*YP wowlan not considered*/ 1882 1883 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR); 1884 if (tmp_u1b != 0 && tmp_u1b != 0xEA) { 1885 rtlhal->mac_func_enable = true; 1886 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1887 "MAC has already power on.\n"); 1888 } else { 1889 rtlhal->mac_func_enable = false; 1890 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1891 } 1892 1893 if (support_remote_wakeup && 1894 rtlhal->wake_from_pnp_sleep && 1895 rtlhal->mac_func_enable) { 1896 if (_rtl8821ae_wowlan_initialize_adapter(hw)) { 1897 rtlhal->being_init_adapter = false; 1898 return 0; 1899 } 1900 } 1901 1902 if (_rtl8821ae_check_pcie_dma_hang(hw)) { 1903 _rtl8821ae_reset_pcie_interface_dma(hw, 1904 rtlhal->mac_func_enable, 1905 false); 1906 rtlhal->mac_func_enable = false; 1907 } 1908 1909 /* Reset MAC/BB/RF status if it is not powered off 1910 * before calling initialize Hw flow to prevent 1911 * from interface and MAC status mismatch. 1912 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */ 1913 if (rtlhal->mac_func_enable) { 1914 _rtl8821ae_poweroff_adapter(hw); 1915 rtlhal->mac_func_enable = false; 1916 } 1917 1918 rtstatus = _rtl8821ae_init_mac(hw); 1919 if (rtstatus != true) { 1920 pr_err("Init MAC failed\n"); 1921 err = 1; 1922 return err; 1923 } 1924 1925 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1926 tmp_u1b &= 0x7F; 1927 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b); 1928 1929 err = rtl8821ae_download_fw(hw, false); 1930 if (err) { 1931 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1932 "Failed to download FW. Init HW without FW now\n"); 1933 err = 1; 1934 rtlhal->fw_ready = false; 1935 return err; 1936 } else { 1937 rtlhal->fw_ready = true; 1938 } 1939 ppsc->fw_current_inpsmode = false; 1940 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1941 rtlhal->fw_clk_change_in_progress = false; 1942 rtlhal->allow_sw_to_change_hwclc = false; 1943 rtlhal->last_hmeboxnum = 0; 1944 1945 /*SIC_Init(Adapter); 1946 if(rtlhal->AMPDUBurstMode) 1947 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/ 1948 1949 rtl8821ae_phy_mac_config(hw); 1950 /* because last function modify RCR, so we update 1951 * rcr var here, or TP will unstable for receive_config 1952 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1953 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1954 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1955 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1956 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/ 1957 rtl8821ae_phy_bb_config(hw); 1958 1959 rtl8821ae_phy_rf_config(hw); 1960 1961 if (rtlpriv->phy.rf_type == RF_1T1R && 1962 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 1963 _rtl8812ae_bb8812_config_1t(hw); 1964 1965 _rtl8821ae_hw_configure(hw); 1966 1967 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 1968 1969 /*set wireless mode*/ 1970 1971 rtlhal->mac_func_enable = true; 1972 1973 rtl_cam_reset_all_entry(hw); 1974 1975 rtl8821ae_enable_hw_security_config(hw); 1976 1977 ppsc->rfpwr_state = ERFON; 1978 1979 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1980 _rtl8821ae_enable_aspm_back_door(hw); 1981 rtlpriv->intf_ops->enable_aspm(hw); 1982 1983 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 1984 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5)) 1985 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302); 1986 1987 rtl8821ae_bt_hw_init(hw); 1988 rtlpriv->rtlhal.being_init_adapter = false; 1989 1990 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper); 1991 1992 /* rtl8821ae_dm_check_txpower_tracking(hw); */ 1993 /* rtl8821ae_phy_lc_calibrate(hw); */ 1994 if (support_remote_wakeup) 1995 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0); 1996 1997 /* Release Rx DMA*/ 1998 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1999 if (tmp_u1b & BIT(2)) { 2000 /* Release Rx DMA if needed*/ 2001 tmp_u1b &= ~BIT(2); 2002 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b); 2003 } 2004 2005 /* Release Tx/Rx PCIE DMA if*/ 2006 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0); 2007 2008 rtl8821ae_dm_init(hw); 2009 rtl8821ae_macid_initialize_mediastatus(hw); 2010 2011 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n"); 2012 return err; 2013 } 2014 2015 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw) 2016 { 2017 struct rtl_priv *rtlpriv = rtl_priv(hw); 2018 struct rtl_phy *rtlphy = &rtlpriv->phy; 2019 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2020 enum version_8821ae version = VERSION_UNKNOWN; 2021 u32 value32; 2022 2023 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 2024 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2025 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32); 2026 2027 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 2028 rtlphy->rf_type = RF_2T2R; 2029 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) 2030 rtlphy->rf_type = RF_1T1R; 2031 2032 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2033 "RF_Type is %x!!\n", rtlphy->rf_type); 2034 2035 if (value32 & TRP_VAUX_EN) { 2036 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2037 if (rtlphy->rf_type == RF_2T2R) 2038 version = VERSION_TEST_CHIP_2T2R_8812; 2039 else 2040 version = VERSION_TEST_CHIP_1T1R_8812; 2041 } else 2042 version = VERSION_TEST_CHIP_8821; 2043 } else { 2044 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2045 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1; 2046 2047 if (rtlphy->rf_type == RF_2T2R) 2048 version = 2049 (enum version_8821ae)(CHIP_8812 2050 | NORMAL_CHIP | 2051 RF_TYPE_2T2R); 2052 else 2053 version = (enum version_8821ae)(CHIP_8812 2054 | NORMAL_CHIP); 2055 2056 version = (enum version_8821ae)(version | (rtl_id << 12)); 2057 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2058 u32 rtl_id = value32 & CHIP_VER_RTL_MASK; 2059 2060 version = (enum version_8821ae)(CHIP_8821 2061 | NORMAL_CHIP | rtl_id); 2062 } 2063 } 2064 2065 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2066 /*WL_HWROF_EN.*/ 2067 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2068 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0); 2069 } 2070 2071 switch (version) { 2072 case VERSION_TEST_CHIP_1T1R_8812: 2073 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2074 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n"); 2075 break; 2076 case VERSION_TEST_CHIP_2T2R_8812: 2077 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2078 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n"); 2079 break; 2080 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812: 2081 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2082 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n"); 2083 break; 2084 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812: 2085 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2086 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n"); 2087 break; 2088 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT: 2089 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2090 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n"); 2091 break; 2092 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT: 2093 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2094 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n"); 2095 break; 2096 case VERSION_TEST_CHIP_8821: 2097 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2098 "Chip Version ID: VERSION_TEST_CHIP_8821\n"); 2099 break; 2100 case VERSION_NORMAL_TSMC_CHIP_8821: 2101 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2102 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n"); 2103 break; 2104 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT: 2105 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2106 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n"); 2107 break; 2108 default: 2109 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2110 "Chip Version ID: Unknown (0x%X)\n", version); 2111 break; 2112 } 2113 2114 return version; 2115 } 2116 2117 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw, 2118 enum nl80211_iftype type) 2119 { 2120 struct rtl_priv *rtlpriv = rtl_priv(hw); 2121 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 2122 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 2123 bt_msr &= 0xfc; 2124 2125 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 2126 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 2127 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 2128 2129 if (type == NL80211_IFTYPE_UNSPECIFIED || 2130 type == NL80211_IFTYPE_STATION) { 2131 _rtl8821ae_stop_tx_beacon(hw); 2132 _rtl8821ae_enable_bcn_sub_func(hw); 2133 } else if (type == NL80211_IFTYPE_ADHOC || 2134 type == NL80211_IFTYPE_AP) { 2135 _rtl8821ae_resume_tx_beacon(hw); 2136 _rtl8821ae_disable_bcn_sub_func(hw); 2137 } else { 2138 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2139 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 2140 type); 2141 } 2142 2143 switch (type) { 2144 case NL80211_IFTYPE_UNSPECIFIED: 2145 bt_msr |= MSR_NOLINK; 2146 ledaction = LED_CTL_LINK; 2147 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2148 "Set Network type to NO LINK!\n"); 2149 break; 2150 case NL80211_IFTYPE_ADHOC: 2151 bt_msr |= MSR_ADHOC; 2152 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2153 "Set Network type to Ad Hoc!\n"); 2154 break; 2155 case NL80211_IFTYPE_STATION: 2156 bt_msr |= MSR_INFRA; 2157 ledaction = LED_CTL_LINK; 2158 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2159 "Set Network type to STA!\n"); 2160 break; 2161 case NL80211_IFTYPE_AP: 2162 bt_msr |= MSR_AP; 2163 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2164 "Set Network type to AP!\n"); 2165 break; 2166 default: 2167 pr_err("Network type %d not support!\n", type); 2168 return 1; 2169 } 2170 2171 rtl_write_byte(rtlpriv, MSR, bt_msr); 2172 rtlpriv->cfg->ops->led_control(hw, ledaction); 2173 if ((bt_msr & MSR_MASK) == MSR_AP) 2174 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 2175 else 2176 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 2177 2178 return 0; 2179 } 2180 2181 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 2182 { 2183 struct rtl_priv *rtlpriv = rtl_priv(hw); 2184 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2185 u32 reg_rcr = rtlpci->receive_config; 2186 2187 if (rtlpriv->psc.rfpwr_state != ERFON) 2188 return; 2189 2190 if (check_bssid) { 2191 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 2192 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 2193 (u8 *)(®_rcr)); 2194 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 2195 } else if (!check_bssid) { 2196 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 2197 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 2198 rtlpriv->cfg->ops->set_hw_reg(hw, 2199 HW_VAR_RCR, (u8 *)(®_rcr)); 2200 } 2201 } 2202 2203 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 2204 { 2205 struct rtl_priv *rtlpriv = rtl_priv(hw); 2206 2207 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n"); 2208 2209 if (_rtl8821ae_set_media_status(hw, type)) 2210 return -EOPNOTSUPP; 2211 2212 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 2213 if (type != NL80211_IFTYPE_AP) 2214 rtl8821ae_set_check_bssid(hw, true); 2215 } else { 2216 rtl8821ae_set_check_bssid(hw, false); 2217 } 2218 2219 return 0; 2220 } 2221 2222 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 2223 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci) 2224 { 2225 struct rtl_priv *rtlpriv = rtl_priv(hw); 2226 rtl8821ae_dm_init_edca_turbo(hw); 2227 switch (aci) { 2228 case AC1_BK: 2229 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 2230 break; 2231 case AC0_BE: 2232 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 2233 break; 2234 case AC2_VI: 2235 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 2236 break; 2237 case AC3_VO: 2238 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 2239 break; 2240 default: 2241 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci); 2242 break; 2243 } 2244 } 2245 2246 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw) 2247 { 2248 struct rtl_priv *rtlpriv = rtl_priv(hw); 2249 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR); 2250 2251 rtl_write_dword(rtlpriv, REG_HISR, tmp); 2252 2253 tmp = rtl_read_dword(rtlpriv, REG_HISRE); 2254 rtl_write_dword(rtlpriv, REG_HISRE, tmp); 2255 2256 tmp = rtl_read_dword(rtlpriv, REG_HSISR); 2257 rtl_write_dword(rtlpriv, REG_HSISR, tmp); 2258 } 2259 2260 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw) 2261 { 2262 struct rtl_priv *rtlpriv = rtl_priv(hw); 2263 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2264 2265 if (rtlpci->int_clear) 2266 rtl8821ae_clear_interrupt(hw);/*clear it here first*/ 2267 2268 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 2269 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 2270 rtlpci->irq_enabled = true; 2271 /* there are some C2H CMDs have been sent before 2272 system interrupt is enabled, e.g., C2H, CPWM. 2273 *So we need to clear all C2H events that FW has 2274 notified, otherwise FW won't schedule any commands anymore. 2275 */ 2276 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */ 2277 /*enable system interrupt*/ 2278 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 2279 } 2280 2281 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw) 2282 { 2283 struct rtl_priv *rtlpriv = rtl_priv(hw); 2284 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2285 2286 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 2287 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 2288 rtlpci->irq_enabled = false; 2289 /*synchronize_irq(rtlpci->pdev->irq);*/ 2290 } 2291 2292 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw) 2293 { 2294 struct rtl_priv *rtlpriv = rtl_priv(hw); 2295 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2296 u16 cap_hdr; 2297 u8 cap_pointer; 2298 u8 cap_id = 0xff; 2299 u8 pmcs_reg; 2300 u8 cnt = 0; 2301 2302 /* Get the Capability pointer first, 2303 * the Capability Pointer is located at 2304 * offset 0x34 from the Function Header */ 2305 2306 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer); 2307 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2308 "PCI configuration 0x34 = 0x%2x\n", cap_pointer); 2309 2310 do { 2311 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr); 2312 cap_id = cap_hdr & 0xFF; 2313 2314 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2315 "in pci configuration, cap_pointer%x = %x\n", 2316 cap_pointer, cap_id); 2317 2318 if (cap_id == 0x01) { 2319 break; 2320 } else { 2321 /* point to next Capability */ 2322 cap_pointer = (cap_hdr >> 8) & 0xFF; 2323 /* 0: end of pci capability, 0xff: invalid value */ 2324 if (cap_pointer == 0x00 || cap_pointer == 0xff) { 2325 cap_id = 0xff; 2326 break; 2327 } 2328 } 2329 } while (cnt++ < 200); 2330 2331 if (cap_id == 0x01) { 2332 /* Get the PM CSR (Control/Status Register), 2333 * The PME_Status is located at PM Capatibility offset 5, bit 7 2334 */ 2335 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg); 2336 2337 if (pmcs_reg & BIT(7)) { 2338 /* PME event occured, clear the PM_Status by write 1 */ 2339 pmcs_reg = pmcs_reg | BIT(7); 2340 2341 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5, 2342 pmcs_reg); 2343 /* Read it back to check */ 2344 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, 2345 &pmcs_reg); 2346 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2347 "Clear PME status 0x%2x to 0x%2x\n", 2348 cap_pointer + 5, pmcs_reg); 2349 } else { 2350 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2351 "PME status(0x%2x) = 0x%2x\n", 2352 cap_pointer + 5, pmcs_reg); 2353 } 2354 } else { 2355 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 2356 "Cannot find PME Capability\n"); 2357 } 2358 } 2359 2360 void rtl8821ae_card_disable(struct ieee80211_hw *hw) 2361 { 2362 struct rtl_priv *rtlpriv = rtl_priv(hw); 2363 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2364 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 2365 struct rtl_mac *mac = rtl_mac(rtlpriv); 2366 enum nl80211_iftype opmode; 2367 bool support_remote_wakeup; 2368 u8 tmp; 2369 u32 count = 0; 2370 2371 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 2372 (u8 *)(&support_remote_wakeup)); 2373 2374 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2375 2376 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION) 2377 || !rtlhal->enter_pnp_sleep) { 2378 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n"); 2379 mac->link_state = MAC80211_NOLINK; 2380 opmode = NL80211_IFTYPE_UNSPECIFIED; 2381 _rtl8821ae_set_media_status(hw, opmode); 2382 _rtl8821ae_poweroff_adapter(hw); 2383 } else { 2384 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n"); 2385 /* 3 <1> Prepare for configuring wowlan related infomations */ 2386 /* Clear Fw WoWLAN event. */ 2387 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0); 2388 2389 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 2390 rtl8821ae_set_fw_related_for_wowlan(hw, true); 2391 #endif 2392 /* Dynamically adjust Tx packet boundary 2393 * for download reserved page packet. 2394 * reserve 30 pages for rsvd page */ 2395 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d)) 2396 rtlhal->re_init_llt_table = true; 2397 2398 /* 3 <2> Set Fw releted H2C cmd. */ 2399 2400 /* Set WoWLAN related security information. */ 2401 rtl8821ae_set_fw_global_info_cmd(hw); 2402 2403 _rtl8821ae_download_rsvd_page(hw, true); 2404 2405 /* Just enable AOAC related functions when we connect to AP. */ 2406 printk("mac->link_state = %d\n", mac->link_state); 2407 if (mac->link_state >= MAC80211_LINKED && 2408 mac->opmode == NL80211_IFTYPE_STATION) { 2409 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 2410 rtl8821ae_set_fw_media_status_rpt_cmd(hw, 2411 RT_MEDIA_CONNECT); 2412 2413 rtl8821ae_set_fw_wowlan_mode(hw, true); 2414 /* Enable Fw Keep alive mechanism. */ 2415 rtl8821ae_set_fw_keep_alive_cmd(hw, true); 2416 2417 /* Enable disconnect decision control. */ 2418 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true); 2419 } 2420 2421 /* 3 <3> Hw Configutations */ 2422 2423 /* Wait untill Rx DMA Finished before host sleep. 2424 * FW Pause Rx DMA may happens when received packet doing dma. 2425 */ 2426 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2)); 2427 2428 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2429 count = 0; 2430 while (!(tmp & BIT(1)) && (count++ < 100)) { 2431 udelay(10); 2432 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2433 } 2434 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2435 "Wait Rx DMA Finished before host sleep. count=%d\n", 2436 count); 2437 2438 /* reset trx ring */ 2439 rtlpriv->intf_ops->reset_trx_ring(hw); 2440 2441 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0); 2442 2443 _rtl8821ae_clear_pci_pme_status(hw); 2444 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 2445 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3)); 2446 /* prevent 8051 to be reset by PERST */ 2447 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20); 2448 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60); 2449 } 2450 2451 if (rtlpriv->rtlhal.driver_is_goingto_unload || 2452 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 2453 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 2454 /* For wowlan+LPS+32k. */ 2455 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) { 2456 /* Set the WoWLAN related function control enable. 2457 * It should be the last H2C cmd in the WoWLAN flow. */ 2458 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1); 2459 2460 /* Stop Pcie Interface Tx DMA. */ 2461 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 2462 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n"); 2463 2464 /* Wait for TxDMA idle. */ 2465 count = 0; 2466 do { 2467 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG); 2468 udelay(10); 2469 count++; 2470 } while ((tmp != 0) && (count < 100)); 2471 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2472 "Wait Tx DMA Finished before host sleep. count=%d\n", 2473 count); 2474 2475 if (rtlhal->hw_rof_enable) { 2476 printk("hw_rof_enable\n"); 2477 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 2478 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 2479 } 2480 } 2481 /* after power off we should do iqk again */ 2482 rtlpriv->phy.iqk_initialized = false; 2483 } 2484 2485 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw, 2486 u32 *p_inta, u32 *p_intb, 2487 u32 *p_intc, u32 *p_intd) 2488 { 2489 struct rtl_priv *rtlpriv = rtl_priv(hw); 2490 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2491 2492 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 2493 rtl_write_dword(rtlpriv, ISR, *p_inta); 2494 2495 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 2496 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb); 2497 } 2498 2499 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw) 2500 { 2501 struct rtl_priv *rtlpriv = rtl_priv(hw); 2502 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2503 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2504 u16 bcn_interval, atim_window; 2505 2506 bcn_interval = mac->beacon_interval; 2507 atim_window = 2; /*FIX MERGE */ 2508 rtl8821ae_disable_interrupt(hw); 2509 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 2510 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2511 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 2512 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 2513 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 2514 rtl_write_byte(rtlpriv, 0x606, 0x30); 2515 rtlpci->reg_bcn_ctrl_val |= BIT(3); 2516 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 2517 rtl8821ae_enable_interrupt(hw); 2518 } 2519 2520 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw) 2521 { 2522 struct rtl_priv *rtlpriv = rtl_priv(hw); 2523 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2524 u16 bcn_interval = mac->beacon_interval; 2525 2526 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 2527 "beacon_interval:%d\n", bcn_interval); 2528 rtl8821ae_disable_interrupt(hw); 2529 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2530 rtl8821ae_enable_interrupt(hw); 2531 } 2532 2533 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw, 2534 u32 add_msr, u32 rm_msr) 2535 { 2536 struct rtl_priv *rtlpriv = rtl_priv(hw); 2537 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2538 2539 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 2540 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 2541 2542 if (add_msr) 2543 rtlpci->irq_mask[0] |= add_msr; 2544 if (rm_msr) 2545 rtlpci->irq_mask[0] &= (~rm_msr); 2546 rtl8821ae_disable_interrupt(hw); 2547 rtl8821ae_enable_interrupt(hw); 2548 } 2549 2550 static u8 _rtl8821ae_get_chnl_group(u8 chnl) 2551 { 2552 u8 group = 0; 2553 2554 if (chnl <= 14) { 2555 if (1 <= chnl && chnl <= 2) 2556 group = 0; 2557 else if (3 <= chnl && chnl <= 5) 2558 group = 1; 2559 else if (6 <= chnl && chnl <= 8) 2560 group = 2; 2561 else if (9 <= chnl && chnl <= 11) 2562 group = 3; 2563 else /*if (12 <= chnl && chnl <= 14)*/ 2564 group = 4; 2565 } else { 2566 if (36 <= chnl && chnl <= 42) 2567 group = 0; 2568 else if (44 <= chnl && chnl <= 48) 2569 group = 1; 2570 else if (50 <= chnl && chnl <= 58) 2571 group = 2; 2572 else if (60 <= chnl && chnl <= 64) 2573 group = 3; 2574 else if (100 <= chnl && chnl <= 106) 2575 group = 4; 2576 else if (108 <= chnl && chnl <= 114) 2577 group = 5; 2578 else if (116 <= chnl && chnl <= 122) 2579 group = 6; 2580 else if (124 <= chnl && chnl <= 130) 2581 group = 7; 2582 else if (132 <= chnl && chnl <= 138) 2583 group = 8; 2584 else if (140 <= chnl && chnl <= 144) 2585 group = 9; 2586 else if (149 <= chnl && chnl <= 155) 2587 group = 10; 2588 else if (157 <= chnl && chnl <= 161) 2589 group = 11; 2590 else if (165 <= chnl && chnl <= 171) 2591 group = 12; 2592 else if (173 <= chnl && chnl <= 177) 2593 group = 13; 2594 else 2595 WARN_ONCE(true, 2596 "rtl8821ae: 5G, Channel %d in Group not found\n", 2597 chnl); 2598 } 2599 return group; 2600 } 2601 2602 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw, 2603 struct txpower_info_2g *pwrinfo24g, 2604 struct txpower_info_5g *pwrinfo5g, 2605 bool autoload_fail, 2606 u8 *hwinfo) 2607 { 2608 struct rtl_priv *rtlpriv = rtl_priv(hw); 2609 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0; 2610 2611 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2612 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n", 2613 (eeAddr+1), hwinfo[eeAddr+1]); 2614 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/ 2615 autoload_fail = true; 2616 2617 if (autoload_fail) { 2618 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2619 "auto load fail : Use Default value!\n"); 2620 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2621 /*2.4G default value*/ 2622 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2623 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D; 2624 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D; 2625 } 2626 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2627 if (TxCount == 0) { 2628 pwrinfo24g->bw20_diff[rfPath][0] = 0x02; 2629 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04; 2630 } else { 2631 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE; 2632 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE; 2633 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE; 2634 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE; 2635 } 2636 } 2637 /*5G default value*/ 2638 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 2639 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A; 2640 2641 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2642 if (TxCount == 0) { 2643 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04; 2644 pwrinfo5g->bw20_diff[rfPath][0] = 0x00; 2645 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE; 2646 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE; 2647 } else { 2648 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE; 2649 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE; 2650 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE; 2651 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE; 2652 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE; 2653 } 2654 } 2655 } 2656 return; 2657 } 2658 2659 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 2660 2661 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2662 /*2.4G default value*/ 2663 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2664 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++]; 2665 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF) 2666 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D; 2667 } 2668 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 2669 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++]; 2670 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF) 2671 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D; 2672 } 2673 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2674 if (TxCount == 0) { 2675 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0; 2676 /*bit sign number to 8 bit sign number*/ 2677 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2678 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) 2679 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0; 2680 /*bit sign number to 8 bit sign number*/ 2681 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2682 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2683 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2684 2685 pwrinfo24g->cck_diff[rfPath][TxCount] = 0; 2686 eeAddr++; 2687 } else { 2688 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4; 2689 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3)) 2690 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0; 2691 2692 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2693 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) 2694 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0; 2695 2696 eeAddr++; 2697 2698 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2699 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2700 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2701 2702 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2703 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3)) 2704 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0; 2705 2706 eeAddr++; 2707 } 2708 } 2709 2710 /*5G default value*/ 2711 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 2712 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++]; 2713 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF) 2714 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE; 2715 } 2716 2717 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2718 if (TxCount == 0) { 2719 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0; 2720 2721 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4; 2722 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3)) 2723 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0; 2724 2725 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f); 2726 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2727 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2728 2729 eeAddr++; 2730 } else { 2731 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2732 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3)) 2733 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0; 2734 2735 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2736 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3)) 2737 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0; 2738 2739 eeAddr++; 2740 } 2741 } 2742 2743 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4; 2744 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f); 2745 2746 eeAddr++; 2747 2748 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f); 2749 2750 eeAddr++; 2751 2752 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) { 2753 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2754 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2755 } 2756 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2757 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2758 /* 4bit sign number to 8 bit sign number */ 2759 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3)) 2760 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0; 2761 /* 4bit sign number to 8 bit sign number */ 2762 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2763 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3)) 2764 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0; 2765 2766 eeAddr++; 2767 } 2768 } 2769 } 2770 #if 0 2771 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2772 bool autoload_fail, 2773 u8 *hwinfo) 2774 { 2775 struct rtl_priv *rtlpriv = rtl_priv(hw); 2776 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2777 struct txpower_info_2g pwrinfo24g; 2778 struct txpower_info_5g pwrinfo5g; 2779 u8 rf_path, index; 2780 u8 i; 2781 2782 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2783 &pwrinfo5g, autoload_fail, hwinfo); 2784 2785 for (rf_path = 0; rf_path < 2; rf_path++) { 2786 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2787 index = _rtl8821ae_get_chnl_group(i + 1); 2788 2789 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2790 rtlefuse->txpwrlevel_cck[rf_path][i] = 2791 pwrinfo24g.index_cck_base[rf_path][5]; 2792 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2793 pwrinfo24g.index_bw40_base[rf_path][index]; 2794 } else { 2795 rtlefuse->txpwrlevel_cck[rf_path][i] = 2796 pwrinfo24g.index_cck_base[rf_path][index]; 2797 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2798 pwrinfo24g.index_bw40_base[rf_path][index]; 2799 } 2800 } 2801 2802 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2803 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2804 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2805 pwrinfo5g.index_bw40_base[rf_path][index]; 2806 } 2807 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2808 u8 upper, lower; 2809 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2810 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2811 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2812 2813 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2814 } 2815 for (i = 0; i < MAX_TX_COUNT; i++) { 2816 rtlefuse->txpwr_cckdiff[rf_path][i] = 2817 pwrinfo24g.cck_diff[rf_path][i]; 2818 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2819 pwrinfo24g.ofdm_diff[rf_path][i]; 2820 rtlefuse->txpwr_ht20diff[rf_path][i] = 2821 pwrinfo24g.bw20_diff[rf_path][i]; 2822 rtlefuse->txpwr_ht40diff[rf_path][i] = 2823 pwrinfo24g.bw40_diff[rf_path][i]; 2824 2825 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2826 pwrinfo5g.ofdm_diff[rf_path][i]; 2827 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2828 pwrinfo5g.bw20_diff[rf_path][i]; 2829 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2830 pwrinfo5g.bw40_diff[rf_path][i]; 2831 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2832 pwrinfo5g.bw80_diff[rf_path][i]; 2833 } 2834 } 2835 2836 if (!autoload_fail) { 2837 rtlefuse->eeprom_regulatory = 2838 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/ 2839 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2840 rtlefuse->eeprom_regulatory = 0; 2841 } else { 2842 rtlefuse->eeprom_regulatory = 0; 2843 } 2844 2845 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2846 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2847 } 2848 #endif 2849 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2850 bool autoload_fail, 2851 u8 *hwinfo) 2852 { 2853 struct rtl_priv *rtlpriv = rtl_priv(hw); 2854 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2855 struct txpower_info_2g pwrinfo24g; 2856 struct txpower_info_5g pwrinfo5g; 2857 u8 rf_path, index; 2858 u8 i; 2859 2860 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2861 &pwrinfo5g, autoload_fail, hwinfo); 2862 2863 for (rf_path = 0; rf_path < 2; rf_path++) { 2864 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2865 index = _rtl8821ae_get_chnl_group(i + 1); 2866 2867 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2868 rtlefuse->txpwrlevel_cck[rf_path][i] = 2869 pwrinfo24g.index_cck_base[rf_path][5]; 2870 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2871 pwrinfo24g.index_bw40_base[rf_path][index]; 2872 } else { 2873 rtlefuse->txpwrlevel_cck[rf_path][i] = 2874 pwrinfo24g.index_cck_base[rf_path][index]; 2875 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2876 pwrinfo24g.index_bw40_base[rf_path][index]; 2877 } 2878 } 2879 2880 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2881 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2882 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2883 pwrinfo5g.index_bw40_base[rf_path][index]; 2884 } 2885 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2886 u8 upper, lower; 2887 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2888 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2889 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2890 2891 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2892 } 2893 for (i = 0; i < MAX_TX_COUNT; i++) { 2894 rtlefuse->txpwr_cckdiff[rf_path][i] = 2895 pwrinfo24g.cck_diff[rf_path][i]; 2896 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2897 pwrinfo24g.ofdm_diff[rf_path][i]; 2898 rtlefuse->txpwr_ht20diff[rf_path][i] = 2899 pwrinfo24g.bw20_diff[rf_path][i]; 2900 rtlefuse->txpwr_ht40diff[rf_path][i] = 2901 pwrinfo24g.bw40_diff[rf_path][i]; 2902 2903 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2904 pwrinfo5g.ofdm_diff[rf_path][i]; 2905 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2906 pwrinfo5g.bw20_diff[rf_path][i]; 2907 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2908 pwrinfo5g.bw40_diff[rf_path][i]; 2909 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2910 pwrinfo5g.bw80_diff[rf_path][i]; 2911 } 2912 } 2913 /*bit0~2*/ 2914 if (!autoload_fail) { 2915 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07; 2916 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2917 rtlefuse->eeprom_regulatory = 0; 2918 } else { 2919 rtlefuse->eeprom_regulatory = 0; 2920 } 2921 2922 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2923 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2924 } 2925 2926 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2927 bool autoload_fail) 2928 { 2929 struct rtl_priv *rtlpriv = rtl_priv(hw); 2930 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2931 2932 if (!autoload_fail) { 2933 rtlhal->pa_type_2g = hwinfo[0xBC]; 2934 rtlhal->lna_type_2g = hwinfo[0xBD]; 2935 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2936 rtlhal->pa_type_2g = 0; 2937 rtlhal->lna_type_2g = 0; 2938 } 2939 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) && 2940 (rtlhal->pa_type_2g & BIT(4))) ? 2941 1 : 0; 2942 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) && 2943 (rtlhal->lna_type_2g & BIT(3))) ? 2944 1 : 0; 2945 2946 rtlhal->pa_type_5g = hwinfo[0xBC]; 2947 rtlhal->lna_type_5g = hwinfo[0xBF]; 2948 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2949 rtlhal->pa_type_5g = 0; 2950 rtlhal->lna_type_5g = 0; 2951 } 2952 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) && 2953 (rtlhal->pa_type_5g & BIT(0))) ? 2954 1 : 0; 2955 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) && 2956 (rtlhal->lna_type_5g & BIT(3))) ? 2957 1 : 0; 2958 } else { 2959 rtlhal->external_pa_2g = 0; 2960 rtlhal->external_lna_2g = 0; 2961 rtlhal->external_pa_5g = 0; 2962 rtlhal->external_lna_5g = 0; 2963 } 2964 } 2965 2966 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo, 2967 bool autoload_fail) 2968 { 2969 struct rtl_priv *rtlpriv = rtl_priv(hw); 2970 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2971 2972 u8 ext_type_pa_2g_a = (hwinfo[0xBD] & BIT(2)) >> 2; /* 0xBD[2] */ 2973 u8 ext_type_pa_2g_b = (hwinfo[0xBD] & BIT(6)) >> 6; /* 0xBD[6] */ 2974 u8 ext_type_pa_5g_a = (hwinfo[0xBF] & BIT(2)) >> 2; /* 0xBF[2] */ 2975 u8 ext_type_pa_5g_b = (hwinfo[0xBF] & BIT(6)) >> 6; /* 0xBF[6] */ 2976 /* 0xBD[1:0] */ 2977 u8 ext_type_lna_2g_a = (hwinfo[0xBD] & (BIT(1) | BIT(0))) >> 0; 2978 /* 0xBD[5:4] */ 2979 u8 ext_type_lna_2g_b = (hwinfo[0xBD] & (BIT(5) | BIT(4))) >> 4; 2980 /* 0xBF[1:0] */ 2981 u8 ext_type_lna_5g_a = (hwinfo[0xBF] & (BIT(1) | BIT(0))) >> 0; 2982 /* 0xBF[5:4] */ 2983 u8 ext_type_lna_5g_b = (hwinfo[0xBF] & (BIT(5) | BIT(4))) >> 4; 2984 2985 _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail); 2986 2987 /* [2.4G] Path A and B are both extPA */ 2988 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4))) 2989 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a; 2990 2991 /* [5G] Path A and B are both extPA */ 2992 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0))) 2993 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a; 2994 2995 /* [2.4G] Path A and B are both extLNA */ 2996 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 2997 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a; 2998 2999 /* [5G] Path A and B are both extLNA */ 3000 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 3001 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a; 3002 } 3003 3004 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 3005 bool autoload_fail) 3006 { 3007 struct rtl_priv *rtlpriv = rtl_priv(hw); 3008 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3009 3010 if (!autoload_fail) { 3011 rtlhal->pa_type_2g = hwinfo[0xBC]; 3012 rtlhal->lna_type_2g = hwinfo[0xBD]; 3013 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 3014 rtlhal->pa_type_2g = 0; 3015 rtlhal->lna_type_2g = 0; 3016 } 3017 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0; 3018 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0; 3019 3020 rtlhal->pa_type_5g = hwinfo[0xBC]; 3021 rtlhal->lna_type_5g = hwinfo[0xBF]; 3022 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 3023 rtlhal->pa_type_5g = 0; 3024 rtlhal->lna_type_5g = 0; 3025 } 3026 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0; 3027 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0; 3028 } else { 3029 rtlhal->external_pa_2g = 0; 3030 rtlhal->external_lna_2g = 0; 3031 rtlhal->external_pa_5g = 0; 3032 rtlhal->external_lna_5g = 0; 3033 } 3034 } 3035 3036 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo, 3037 bool autoload_fail) 3038 { 3039 struct rtl_priv *rtlpriv = rtl_priv(hw); 3040 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3041 3042 if (!autoload_fail) { 3043 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) { 3044 if (rtlhal->external_lna_5g) { 3045 if (rtlhal->external_pa_5g) { 3046 if (rtlhal->external_lna_2g && 3047 rtlhal->external_pa_2g) 3048 rtlhal->rfe_type = 3; 3049 else 3050 rtlhal->rfe_type = 0; 3051 } else { 3052 rtlhal->rfe_type = 2; 3053 } 3054 } else { 3055 rtlhal->rfe_type = 4; 3056 } 3057 } else { 3058 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F; 3059 3060 if (rtlhal->rfe_type == 4 && 3061 (rtlhal->external_pa_5g || 3062 rtlhal->external_pa_2g || 3063 rtlhal->external_lna_5g || 3064 rtlhal->external_lna_2g)) { 3065 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 3066 rtlhal->rfe_type = 2; 3067 } 3068 } 3069 } else { 3070 rtlhal->rfe_type = 0x04; 3071 } 3072 3073 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3074 "RFE Type: 0x%2x\n", rtlhal->rfe_type); 3075 } 3076 3077 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3078 bool auto_load_fail, u8 *hwinfo) 3079 { 3080 struct rtl_priv *rtlpriv = rtl_priv(hw); 3081 u8 value; 3082 3083 if (!auto_load_fail) { 3084 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION]; 3085 if (((value & 0xe0) >> 5) == 0x1) 3086 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3087 else 3088 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3089 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3090 3091 value = hwinfo[EEPROM_RF_BT_SETTING]; 3092 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3093 } else { 3094 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3095 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3096 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3097 } 3098 /*move BT_InitHalVars() to init_sw_vars*/ 3099 } 3100 3101 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3102 bool auto_load_fail, u8 *hwinfo) 3103 { 3104 struct rtl_priv *rtlpriv = rtl_priv(hw); 3105 u8 value; 3106 u32 tmpu_32; 3107 3108 if (!auto_load_fail) { 3109 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 3110 if (tmpu_32 & BIT(18)) 3111 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3112 else 3113 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3114 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3115 3116 value = hwinfo[EEPROM_RF_BT_SETTING]; 3117 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3118 } else { 3119 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3120 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3121 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3122 } 3123 /*move BT_InitHalVars() to init_sw_vars*/ 3124 } 3125 3126 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test) 3127 { 3128 struct rtl_priv *rtlpriv = rtl_priv(hw); 3129 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3130 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3131 int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID, 3132 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 3133 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 3134 COUNTRY_CODE_WORLD_WIDE_13}; 3135 u8 *hwinfo; 3136 3137 if (b_pseudo_test) { 3138 ;/* need add */ 3139 } 3140 3141 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 3142 if (!hwinfo) 3143 return; 3144 3145 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 3146 goto exit; 3147 3148 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 3149 hwinfo); 3150 3151 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 3152 _rtl8812ae_read_amplifier_type(hw, hwinfo, 3153 rtlefuse->autoload_failflag); 3154 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw, 3155 rtlefuse->autoload_failflag, hwinfo); 3156 } else { 3157 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag); 3158 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw, 3159 rtlefuse->autoload_failflag, hwinfo); 3160 } 3161 3162 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag); 3163 /*board type*/ 3164 rtlefuse->board_type = ODM_BOARD_DEFAULT; 3165 if (rtlhal->external_lna_2g != 0) 3166 rtlefuse->board_type |= ODM_BOARD_EXT_LNA; 3167 if (rtlhal->external_lna_5g != 0) 3168 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G; 3169 if (rtlhal->external_pa_2g != 0) 3170 rtlefuse->board_type |= ODM_BOARD_EXT_PA; 3171 if (rtlhal->external_pa_5g != 0) 3172 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G; 3173 3174 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 3175 rtlefuse->board_type |= ODM_BOARD_BT; 3176 3177 rtlhal->board_type = rtlefuse->board_type; 3178 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3179 "board_type = 0x%x\n", rtlefuse->board_type); 3180 3181 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 3182 if (rtlefuse->eeprom_channelplan == 0xff) 3183 rtlefuse->eeprom_channelplan = 0x7F; 3184 3185 /* set channel plan from efuse */ 3186 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 3187 3188 /*parse xtal*/ 3189 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE]; 3190 if (rtlefuse->crystalcap == 0xFF) 3191 rtlefuse->crystalcap = 0x20; 3192 3193 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER]; 3194 if ((rtlefuse->eeprom_thermalmeter == 0xff) || 3195 rtlefuse->autoload_failflag) { 3196 rtlefuse->apk_thermalmeterignore = true; 3197 rtlefuse->eeprom_thermalmeter = 0xff; 3198 } 3199 3200 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 3201 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3202 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 3203 3204 if (!rtlefuse->autoload_failflag) { 3205 rtlefuse->antenna_div_cfg = 3206 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3; 3207 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff) 3208 rtlefuse->antenna_div_cfg = 0; 3209 3210 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 && 3211 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1) 3212 rtlefuse->antenna_div_cfg = 0; 3213 3214 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 3215 if (rtlefuse->antenna_div_type == 0xff) 3216 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV; 3217 } else { 3218 rtlefuse->antenna_div_cfg = 0; 3219 rtlefuse->antenna_div_type = 0; 3220 } 3221 3222 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3223 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n", 3224 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type); 3225 3226 rtlpriv->ledctl.led_opendrain = true; 3227 3228 if (rtlhal->oem_id == RT_CID_DEFAULT) { 3229 switch (rtlefuse->eeprom_oemid) { 3230 case RT_CID_DEFAULT: 3231 break; 3232 case EEPROM_CID_TOSHIBA: 3233 rtlhal->oem_id = RT_CID_TOSHIBA; 3234 break; 3235 case EEPROM_CID_CCX: 3236 rtlhal->oem_id = RT_CID_CCX; 3237 break; 3238 case EEPROM_CID_QMI: 3239 rtlhal->oem_id = RT_CID_819X_QMI; 3240 break; 3241 case EEPROM_CID_WHQL: 3242 break; 3243 default: 3244 break; 3245 } 3246 } 3247 exit: 3248 kfree(hwinfo); 3249 } 3250 3251 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw) 3252 { 3253 struct rtl_priv *rtlpriv = rtl_priv(hw); 3254 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3255 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3256 3257 rtlpriv->ledctl.led_opendrain = true; 3258 switch (rtlhal->oem_id) { 3259 case RT_CID_819X_HP: 3260 rtlpriv->ledctl.led_opendrain = true; 3261 break; 3262 case RT_CID_819X_LENOVO: 3263 case RT_CID_DEFAULT: 3264 case RT_CID_TOSHIBA: 3265 case RT_CID_CCX: 3266 case RT_CID_819X_ACER: 3267 case RT_CID_WHQL: 3268 default: 3269 break; 3270 } 3271 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3272 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 3273 }*/ 3274 3275 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw) 3276 { 3277 struct rtl_priv *rtlpriv = rtl_priv(hw); 3278 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3279 struct rtl_phy *rtlphy = &rtlpriv->phy; 3280 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3281 u8 tmp_u1b; 3282 3283 rtlhal->version = _rtl8821ae_read_chip_version(hw); 3284 if (get_rf_type(rtlphy) == RF_1T1R) 3285 rtlpriv->dm.rfpath_rxenable[0] = true; 3286 else 3287 rtlpriv->dm.rfpath_rxenable[0] = 3288 rtlpriv->dm.rfpath_rxenable[1] = true; 3289 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 3290 rtlhal->version); 3291 3292 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 3293 if (tmp_u1b & BIT(4)) { 3294 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 3295 rtlefuse->epromtype = EEPROM_93C46; 3296 } else { 3297 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 3298 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 3299 } 3300 3301 if (tmp_u1b & BIT(5)) { 3302 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 3303 rtlefuse->autoload_failflag = false; 3304 _rtl8821ae_read_adapter_info(hw, false); 3305 } else { 3306 pr_err("Autoload ERR!!\n"); 3307 } 3308 /*hal_ReadRFType_8812A()*/ 3309 /* _rtl8821ae_hal_customized_behavior(hw); */ 3310 } 3311 3312 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw, 3313 struct ieee80211_sta *sta) 3314 { 3315 struct rtl_priv *rtlpriv = rtl_priv(hw); 3316 struct rtl_phy *rtlphy = &rtlpriv->phy; 3317 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3318 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3319 u32 ratr_value; 3320 u8 ratr_index = 0; 3321 u8 b_nmode = mac->ht_enable; 3322 u8 mimo_ps = IEEE80211_SMPS_OFF; 3323 u16 shortgi_rate; 3324 u32 tmp_ratr_value; 3325 u8 curtxbw_40mhz = mac->bw_40; 3326 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3327 1 : 0; 3328 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3329 1 : 0; 3330 enum wireless_mode wirelessmode = mac->mode; 3331 3332 if (rtlhal->current_bandtype == BAND_ON_5G) 3333 ratr_value = sta->supp_rates[1] << 4; 3334 else 3335 ratr_value = sta->supp_rates[0]; 3336 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3337 ratr_value = 0xfff; 3338 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3339 sta->ht_cap.mcs.rx_mask[0] << 12); 3340 switch (wirelessmode) { 3341 case WIRELESS_MODE_B: 3342 if (ratr_value & 0x0000000c) 3343 ratr_value &= 0x0000000d; 3344 else 3345 ratr_value &= 0x0000000f; 3346 break; 3347 case WIRELESS_MODE_G: 3348 ratr_value &= 0x00000FF5; 3349 break; 3350 case WIRELESS_MODE_N_24G: 3351 case WIRELESS_MODE_N_5G: 3352 b_nmode = 1; 3353 if (mimo_ps == IEEE80211_SMPS_STATIC) { 3354 ratr_value &= 0x0007F005; 3355 } else { 3356 u32 ratr_mask; 3357 3358 if (get_rf_type(rtlphy) == RF_1T2R || 3359 get_rf_type(rtlphy) == RF_1T1R) 3360 ratr_mask = 0x000ff005; 3361 else 3362 ratr_mask = 0x0f0ff005; 3363 3364 ratr_value &= ratr_mask; 3365 } 3366 break; 3367 default: 3368 if (rtlphy->rf_type == RF_1T2R) 3369 ratr_value &= 0x000ff0ff; 3370 else 3371 ratr_value &= 0x0f0ff0ff; 3372 3373 break; 3374 } 3375 3376 if ((rtlpriv->btcoexist.bt_coexistence) && 3377 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 3378 (rtlpriv->btcoexist.bt_cur_state) && 3379 (rtlpriv->btcoexist.bt_ant_isolation) && 3380 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 3381 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 3382 ratr_value &= 0x0fffcfc0; 3383 else 3384 ratr_value &= 0x0FFFFFFF; 3385 3386 if (b_nmode && ((curtxbw_40mhz && 3387 b_curshortgi_40mhz) || (!curtxbw_40mhz && 3388 b_curshortgi_20mhz))) { 3389 ratr_value |= 0x10000000; 3390 tmp_ratr_value = (ratr_value >> 12); 3391 3392 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 3393 if ((1 << shortgi_rate) & tmp_ratr_value) 3394 break; 3395 } 3396 3397 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 3398 (shortgi_rate << 4) | (shortgi_rate); 3399 } 3400 3401 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 3402 3403 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3404 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 3405 } 3406 3407 static u8 _rtl8821ae_mrate_idx_to_arfr_id( 3408 struct ieee80211_hw *hw, u8 rate_index, 3409 enum wireless_mode wirelessmode) 3410 { 3411 struct rtl_priv *rtlpriv = rtl_priv(hw); 3412 struct rtl_phy *rtlphy = &rtlpriv->phy; 3413 u8 ret = 0; 3414 switch (rate_index) { 3415 case RATR_INX_WIRELESS_NGB: 3416 if (rtlphy->rf_type == RF_1T1R) 3417 ret = 1; 3418 else 3419 ret = 0; 3420 ; break; 3421 case RATR_INX_WIRELESS_N: 3422 case RATR_INX_WIRELESS_NG: 3423 if (rtlphy->rf_type == RF_1T1R) 3424 ret = 5; 3425 else 3426 ret = 4; 3427 ; break; 3428 case RATR_INX_WIRELESS_NB: 3429 if (rtlphy->rf_type == RF_1T1R) 3430 ret = 3; 3431 else 3432 ret = 2; 3433 ; break; 3434 case RATR_INX_WIRELESS_GB: 3435 ret = 6; 3436 break; 3437 case RATR_INX_WIRELESS_G: 3438 ret = 7; 3439 break; 3440 case RATR_INX_WIRELESS_B: 3441 ret = 8; 3442 break; 3443 case RATR_INX_WIRELESS_MC: 3444 if ((wirelessmode == WIRELESS_MODE_B) 3445 || (wirelessmode == WIRELESS_MODE_G) 3446 || (wirelessmode == WIRELESS_MODE_N_24G) 3447 || (wirelessmode == WIRELESS_MODE_AC_24G)) 3448 ret = 6; 3449 else 3450 ret = 7; 3451 case RATR_INX_WIRELESS_AC_5N: 3452 if (rtlphy->rf_type == RF_1T1R) 3453 ret = 10; 3454 else 3455 ret = 9; 3456 break; 3457 case RATR_INX_WIRELESS_AC_24N: 3458 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) { 3459 if (rtlphy->rf_type == RF_1T1R) 3460 ret = 10; 3461 else 3462 ret = 9; 3463 } else { 3464 if (rtlphy->rf_type == RF_1T1R) 3465 ret = 11; 3466 else 3467 ret = 12; 3468 } 3469 break; 3470 default: 3471 ret = 0; break; 3472 } 3473 return ret; 3474 } 3475 3476 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate) 3477 { 3478 u8 i, j, tmp_rate; 3479 u32 rate_bitmap = 0; 3480 3481 for (i = j = 0; i < 4; i += 2, j += 10) { 3482 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3; 3483 3484 switch (tmp_rate) { 3485 case 2: 3486 rate_bitmap = rate_bitmap | (0x03ff << j); 3487 break; 3488 case 1: 3489 rate_bitmap = rate_bitmap | (0x01ff << j); 3490 break; 3491 case 0: 3492 rate_bitmap = rate_bitmap | (0x00ff << j); 3493 break; 3494 default: 3495 break; 3496 } 3497 } 3498 3499 return rate_bitmap; 3500 } 3501 3502 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw, 3503 enum wireless_mode wirelessmode, 3504 u32 ratr_bitmap) 3505 { 3506 struct rtl_priv *rtlpriv = rtl_priv(hw); 3507 struct rtl_phy *rtlphy = &rtlpriv->phy; 3508 u32 ret_bitmap = ratr_bitmap; 3509 3510 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 3511 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3512 ret_bitmap = ratr_bitmap; 3513 else if (wirelessmode == WIRELESS_MODE_AC_5G 3514 || wirelessmode == WIRELESS_MODE_AC_24G) { 3515 if (rtlphy->rf_type == RF_1T1R) 3516 ret_bitmap = ratr_bitmap & (~BIT21); 3517 else 3518 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21)); 3519 } 3520 3521 return ret_bitmap; 3522 } 3523 3524 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode, 3525 u32 ratr_bitmap) 3526 { 3527 u8 ret = 0; 3528 if (wirelessmode < WIRELESS_MODE_N_24G) 3529 ret = 0; 3530 else if (wirelessmode == WIRELESS_MODE_AC_24G) { 3531 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */ 3532 ret = 3; 3533 else /* Mix, 1SS */ 3534 ret = 2; 3535 } else if (wirelessmode == WIRELESS_MODE_AC_5G) { 3536 ret = 1; 3537 } /* VHT */ 3538 3539 return ret << 4; 3540 } 3541 3542 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw, 3543 u8 mac_id, struct rtl_sta_info *sta_entry, 3544 enum wireless_mode wirelessmode) 3545 { 3546 u8 b_ldpc = 0; 3547 /*not support ldpc, do not open*/ 3548 return b_ldpc << 2; 3549 } 3550 3551 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw, 3552 enum wireless_mode wirelessmode, 3553 u32 ratr_bitmap) 3554 { 3555 struct rtl_priv *rtlpriv = rtl_priv(hw); 3556 struct rtl_phy *rtlphy = &rtlpriv->phy; 3557 u8 rf_type = RF_1T1R; 3558 3559 if (rtlphy->rf_type == RF_1T1R) 3560 rf_type = RF_1T1R; 3561 else if (wirelessmode == WIRELESS_MODE_AC_5G 3562 || wirelessmode == WIRELESS_MODE_AC_24G 3563 || wirelessmode == WIRELESS_MODE_AC_ONLY) { 3564 if (ratr_bitmap & 0xffc00000) 3565 rf_type = RF_2T2R; 3566 } else if (wirelessmode == WIRELESS_MODE_N_5G 3567 || wirelessmode == WIRELESS_MODE_N_24G) { 3568 if (ratr_bitmap & 0xfff00000) 3569 rf_type = RF_2T2R; 3570 } 3571 3572 return rf_type; 3573 } 3574 3575 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 3576 u8 mac_id) 3577 { 3578 bool b_short_gi = false; 3579 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3580 1 : 0; 3581 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3582 1 : 0; 3583 u8 b_curshortgi_80mhz = 0; 3584 b_curshortgi_80mhz = (sta->vht_cap.cap & 3585 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0; 3586 3587 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) 3588 b_short_gi = false; 3589 3590 if (b_curshortgi_40mhz || b_curshortgi_80mhz 3591 || b_curshortgi_20mhz) 3592 b_short_gi = true; 3593 3594 return b_short_gi; 3595 } 3596 3597 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw, 3598 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 3599 { 3600 struct rtl_priv *rtlpriv = rtl_priv(hw); 3601 struct rtl_phy *rtlphy = &rtlpriv->phy; 3602 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3603 struct rtl_sta_info *sta_entry = NULL; 3604 u32 ratr_bitmap; 3605 u8 ratr_index; 3606 enum wireless_mode wirelessmode = 0; 3607 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 3608 ? 1 : 0; 3609 bool b_shortgi = false; 3610 u8 rate_mask[7]; 3611 u8 macid = 0; 3612 u8 mimo_ps = IEEE80211_SMPS_OFF; 3613 u8 rf_type; 3614 3615 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 3616 wirelessmode = sta_entry->wireless_mode; 3617 3618 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3619 "wireless mode = 0x%x\n", wirelessmode); 3620 if (mac->opmode == NL80211_IFTYPE_STATION || 3621 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 3622 curtxbw_40mhz = mac->bw_40; 3623 } else if (mac->opmode == NL80211_IFTYPE_AP || 3624 mac->opmode == NL80211_IFTYPE_ADHOC) 3625 macid = sta->aid + 1; 3626 if (wirelessmode == WIRELESS_MODE_N_5G || 3627 wirelessmode == WIRELESS_MODE_AC_5G || 3628 wirelessmode == WIRELESS_MODE_A) 3629 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4; 3630 else 3631 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ]; 3632 3633 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3634 ratr_bitmap = 0xfff; 3635 3636 if (wirelessmode == WIRELESS_MODE_N_24G 3637 || wirelessmode == WIRELESS_MODE_N_5G) 3638 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3639 sta->ht_cap.mcs.rx_mask[0] << 12); 3640 else if (wirelessmode == WIRELESS_MODE_AC_24G 3641 || wirelessmode == WIRELESS_MODE_AC_5G 3642 || wirelessmode == WIRELESS_MODE_AC_ONLY) 3643 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht( 3644 sta->vht_cap.vht_mcs.rx_mcs_map) << 12; 3645 3646 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid); 3647 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap); 3648 3649 /*mac id owner*/ 3650 switch (wirelessmode) { 3651 case WIRELESS_MODE_B: 3652 ratr_index = RATR_INX_WIRELESS_B; 3653 if (ratr_bitmap & 0x0000000c) 3654 ratr_bitmap &= 0x0000000d; 3655 else 3656 ratr_bitmap &= 0x0000000f; 3657 break; 3658 case WIRELESS_MODE_G: 3659 ratr_index = RATR_INX_WIRELESS_GB; 3660 3661 if (rssi_level == 1) 3662 ratr_bitmap &= 0x00000f00; 3663 else if (rssi_level == 2) 3664 ratr_bitmap &= 0x00000ff0; 3665 else 3666 ratr_bitmap &= 0x00000ff5; 3667 break; 3668 case WIRELESS_MODE_A: 3669 ratr_index = RATR_INX_WIRELESS_G; 3670 ratr_bitmap &= 0x00000ff0; 3671 break; 3672 case WIRELESS_MODE_N_24G: 3673 case WIRELESS_MODE_N_5G: 3674 if (wirelessmode == WIRELESS_MODE_N_24G) 3675 ratr_index = RATR_INX_WIRELESS_NGB; 3676 else 3677 ratr_index = RATR_INX_WIRELESS_NG; 3678 3679 if (mimo_ps == IEEE80211_SMPS_STATIC 3680 || mimo_ps == IEEE80211_SMPS_DYNAMIC) { 3681 if (rssi_level == 1) 3682 ratr_bitmap &= 0x000f0000; 3683 else if (rssi_level == 2) 3684 ratr_bitmap &= 0x000ff000; 3685 else 3686 ratr_bitmap &= 0x000ff005; 3687 } else { 3688 if (rf_type == RF_1T1R) { 3689 if (curtxbw_40mhz) { 3690 if (rssi_level == 1) 3691 ratr_bitmap &= 0x000f0000; 3692 else if (rssi_level == 2) 3693 ratr_bitmap &= 0x000ff000; 3694 else 3695 ratr_bitmap &= 0x000ff015; 3696 } else { 3697 if (rssi_level == 1) 3698 ratr_bitmap &= 0x000f0000; 3699 else if (rssi_level == 2) 3700 ratr_bitmap &= 0x000ff000; 3701 else 3702 ratr_bitmap &= 0x000ff005; 3703 } 3704 } else { 3705 if (curtxbw_40mhz) { 3706 if (rssi_level == 1) 3707 ratr_bitmap &= 0x0fff0000; 3708 else if (rssi_level == 2) 3709 ratr_bitmap &= 0x0ffff000; 3710 else 3711 ratr_bitmap &= 0x0ffff015; 3712 } else { 3713 if (rssi_level == 1) 3714 ratr_bitmap &= 0x0fff0000; 3715 else if (rssi_level == 2) 3716 ratr_bitmap &= 0x0ffff000; 3717 else 3718 ratr_bitmap &= 0x0ffff005; 3719 } 3720 } 3721 } 3722 break; 3723 3724 case WIRELESS_MODE_AC_24G: 3725 ratr_index = RATR_INX_WIRELESS_AC_24N; 3726 if (rssi_level == 1) 3727 ratr_bitmap &= 0xfc3f0000; 3728 else if (rssi_level == 2) 3729 ratr_bitmap &= 0xfffff000; 3730 else 3731 ratr_bitmap &= 0xffffffff; 3732 break; 3733 3734 case WIRELESS_MODE_AC_5G: 3735 ratr_index = RATR_INX_WIRELESS_AC_5N; 3736 3737 if (rf_type == RF_1T1R) { 3738 if (rssi_level == 1) /*add by Gary for ac-series*/ 3739 ratr_bitmap &= 0x003f8000; 3740 else if (rssi_level == 2) 3741 ratr_bitmap &= 0x003ff000; 3742 else 3743 ratr_bitmap &= 0x003ff010; 3744 } else { 3745 if (rssi_level == 1) 3746 ratr_bitmap &= 0xfe3f8000; 3747 else if (rssi_level == 2) 3748 ratr_bitmap &= 0xfffff000; 3749 else 3750 ratr_bitmap &= 0xfffff010; 3751 } 3752 break; 3753 3754 default: 3755 ratr_index = RATR_INX_WIRELESS_NGB; 3756 3757 if (rf_type == RF_1T2R) 3758 ratr_bitmap &= 0x000ff0ff; 3759 else 3760 ratr_bitmap &= 0x0f8ff0ff; 3761 break; 3762 } 3763 3764 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode); 3765 sta_entry->ratr_index = ratr_index; 3766 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode, 3767 ratr_bitmap); 3768 3769 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3770 "ratr_bitmap :%x\n", ratr_bitmap); 3771 3772 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) | 3773 (ratr_index << 28)); */ 3774 3775 rate_mask[0] = macid; 3776 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 3777 rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3) 3778 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap) 3779 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode); 3780 3781 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 3782 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 3783 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 3784 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 3785 3786 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3787 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 3788 ratr_index, ratr_bitmap, 3789 rate_mask[0], rate_mask[1], 3790 rate_mask[2], rate_mask[3], 3791 rate_mask[4], rate_mask[5], 3792 rate_mask[6]); 3793 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask); 3794 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 3795 } 3796 3797 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 3798 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 3799 { 3800 struct rtl_priv *rtlpriv = rtl_priv(hw); 3801 if (rtlpriv->dm.useramask) 3802 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 3803 else 3804 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD, 3805 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/ 3806 rtl8821ae_update_hal_rate_table(hw, sta); 3807 } 3808 3809 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw) 3810 { 3811 struct rtl_priv *rtlpriv = rtl_priv(hw); 3812 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3813 u16 wireless_mode = mac->mode; 3814 u8 sifs_timer, r2t_sifs; 3815 3816 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 3817 (u8 *)&mac->slot_time); 3818 if (wireless_mode == WIRELESS_MODE_G) 3819 sifs_timer = 0x0a; 3820 else 3821 sifs_timer = 0x0e; 3822 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 3823 3824 r2t_sifs = 0xa; 3825 3826 if (wireless_mode == WIRELESS_MODE_AC_5G && 3827 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) && 3828 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) { 3829 if (mac->vendor == PEER_ATH) 3830 r2t_sifs = 0x8; 3831 else 3832 r2t_sifs = 0xa; 3833 } else if (wireless_mode == WIRELESS_MODE_AC_5G) { 3834 r2t_sifs = 0xa; 3835 } 3836 3837 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs); 3838 } 3839 3840 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 3841 { 3842 struct rtl_priv *rtlpriv = rtl_priv(hw); 3843 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3844 struct rtl_phy *rtlphy = &rtlpriv->phy; 3845 enum rf_pwrstate e_rfpowerstate_toset; 3846 u8 u1tmp = 0; 3847 bool b_actuallyset = false; 3848 3849 if (rtlpriv->rtlhal.being_init_adapter) 3850 return false; 3851 3852 if (ppsc->swrf_processing) 3853 return false; 3854 3855 spin_lock(&rtlpriv->locks.rf_ps_lock); 3856 if (ppsc->rfchange_inprogress) { 3857 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3858 return false; 3859 } else { 3860 ppsc->rfchange_inprogress = true; 3861 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3862 } 3863 3864 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 3865 rtl_read_byte(rtlpriv, 3866 REG_GPIO_IO_SEL_2) & ~(BIT(1))); 3867 3868 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 3869 3870 if (rtlphy->polarity_ctl) 3871 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 3872 else 3873 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 3874 3875 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 3876 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3877 "GPIOChangeRF - HW Radio ON, RF ON\n"); 3878 3879 e_rfpowerstate_toset = ERFON; 3880 ppsc->hwradiooff = false; 3881 b_actuallyset = true; 3882 } else if ((!ppsc->hwradiooff) 3883 && (e_rfpowerstate_toset == ERFOFF)) { 3884 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3885 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 3886 3887 e_rfpowerstate_toset = ERFOFF; 3888 ppsc->hwradiooff = true; 3889 b_actuallyset = true; 3890 } 3891 3892 if (b_actuallyset) { 3893 spin_lock(&rtlpriv->locks.rf_ps_lock); 3894 ppsc->rfchange_inprogress = false; 3895 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3896 } else { 3897 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 3898 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3899 3900 spin_lock(&rtlpriv->locks.rf_ps_lock); 3901 ppsc->rfchange_inprogress = false; 3902 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3903 } 3904 3905 *valid = 1; 3906 return !ppsc->hwradiooff; 3907 } 3908 3909 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index, 3910 u8 *p_macaddr, bool is_group, u8 enc_algo, 3911 bool is_wepkey, bool clear_all) 3912 { 3913 struct rtl_priv *rtlpriv = rtl_priv(hw); 3914 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3915 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3916 u8 *macaddr = p_macaddr; 3917 u32 entry_id = 0; 3918 bool is_pairwise = false; 3919 3920 static u8 cam_const_addr[4][6] = { 3921 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 3922 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 3923 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 3924 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 3925 }; 3926 static u8 cam_const_broad[] = { 3927 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 3928 }; 3929 3930 if (clear_all) { 3931 u8 idx = 0; 3932 u8 cam_offset = 0; 3933 u8 clear_number = 5; 3934 3935 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 3936 3937 for (idx = 0; idx < clear_number; idx++) { 3938 rtl_cam_mark_invalid(hw, cam_offset + idx); 3939 rtl_cam_empty_entry(hw, cam_offset + idx); 3940 3941 if (idx < 5) { 3942 memset(rtlpriv->sec.key_buf[idx], 0, 3943 MAX_KEY_LEN); 3944 rtlpriv->sec.key_len[idx] = 0; 3945 } 3946 } 3947 } else { 3948 switch (enc_algo) { 3949 case WEP40_ENCRYPTION: 3950 enc_algo = CAM_WEP40; 3951 break; 3952 case WEP104_ENCRYPTION: 3953 enc_algo = CAM_WEP104; 3954 break; 3955 case TKIP_ENCRYPTION: 3956 enc_algo = CAM_TKIP; 3957 break; 3958 case AESCCMP_ENCRYPTION: 3959 enc_algo = CAM_AES; 3960 break; 3961 default: 3962 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 3963 "switch case %#x not processed\n", enc_algo); 3964 enc_algo = CAM_TKIP; 3965 break; 3966 } 3967 3968 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 3969 macaddr = cam_const_addr[key_index]; 3970 entry_id = key_index; 3971 } else { 3972 if (is_group) { 3973 macaddr = cam_const_broad; 3974 entry_id = key_index; 3975 } else { 3976 if (mac->opmode == NL80211_IFTYPE_AP) { 3977 entry_id = rtl_cam_get_free_entry(hw, p_macaddr); 3978 if (entry_id >= TOTAL_CAM_ENTRY) { 3979 pr_err("an not find free hwsecurity cam entry\n"); 3980 return; 3981 } 3982 } else { 3983 entry_id = CAM_PAIRWISE_KEY_POSITION; 3984 } 3985 3986 key_index = PAIRWISE_KEYIDX; 3987 is_pairwise = true; 3988 } 3989 } 3990 3991 if (rtlpriv->sec.key_len[key_index] == 0) { 3992 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3993 "delete one entry, entry_id is %d\n", 3994 entry_id); 3995 if (mac->opmode == NL80211_IFTYPE_AP) 3996 rtl_cam_del_entry(hw, p_macaddr); 3997 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 3998 } else { 3999 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 4000 "add one entry\n"); 4001 if (is_pairwise) { 4002 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 4003 "set Pairwise key\n"); 4004 4005 rtl_cam_add_one_entry(hw, macaddr, key_index, 4006 entry_id, enc_algo, 4007 CAM_CONFIG_NO_USEDK, 4008 rtlpriv->sec.key_buf[key_index]); 4009 } else { 4010 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 4011 "set group key\n"); 4012 4013 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 4014 rtl_cam_add_one_entry(hw, 4015 rtlefuse->dev_addr, 4016 PAIRWISE_KEYIDX, 4017 CAM_PAIRWISE_KEY_POSITION, 4018 enc_algo, 4019 CAM_CONFIG_NO_USEDK, 4020 rtlpriv->sec.key_buf 4021 [entry_id]); 4022 } 4023 4024 rtl_cam_add_one_entry(hw, macaddr, key_index, 4025 entry_id, enc_algo, 4026 CAM_CONFIG_NO_USEDK, 4027 rtlpriv->sec.key_buf[entry_id]); 4028 } 4029 } 4030 } 4031 } 4032 4033 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw) 4034 { 4035 struct rtl_priv *rtlpriv = rtl_priv(hw); 4036 4037 /* 0:Low, 1:High, 2:From Efuse. */ 4038 rtlpriv->btcoexist.reg_bt_iso = 2; 4039 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 4040 rtlpriv->btcoexist.reg_bt_sco = 3; 4041 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 4042 rtlpriv->btcoexist.reg_bt_sco = 0; 4043 } 4044 4045 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw) 4046 { 4047 struct rtl_priv *rtlpriv = rtl_priv(hw); 4048 4049 if (rtlpriv->cfg->ops->get_btc_status()) 4050 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 4051 } 4052 4053 void rtl8821ae_suspend(struct ieee80211_hw *hw) 4054 { 4055 } 4056 4057 void rtl8821ae_resume(struct ieee80211_hw *hw) 4058 { 4059 } 4060 4061 /* Turn on AAP (RCR:bit 0) for promicuous mode. */ 4062 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw, 4063 bool allow_all_da, bool write_into_reg) 4064 { 4065 struct rtl_priv *rtlpriv = rtl_priv(hw); 4066 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 4067 4068 if (allow_all_da) /* Set BIT0 */ 4069 rtlpci->receive_config |= RCR_AAP; 4070 else /* Clear BIT0 */ 4071 rtlpci->receive_config &= ~RCR_AAP; 4072 4073 if (write_into_reg) 4074 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 4075 4076 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 4077 "receive_config=0x%08X, write_into_reg=%d\n", 4078 rtlpci->receive_config, write_into_reg); 4079 } 4080 4081 /* WKFMCAMAddAllEntry8812 */ 4082 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw, 4083 struct rtl_wow_pattern *rtl_pattern, 4084 u8 index) 4085 { 4086 struct rtl_priv *rtlpriv = rtl_priv(hw); 4087 u32 cam = 0; 4088 u8 addr = 0; 4089 u16 rxbuf_addr; 4090 u8 tmp, count = 0; 4091 u16 cam_start; 4092 u16 offset; 4093 4094 /* Count the WFCAM entry start offset. */ 4095 4096 /* RX page size = 128 byte */ 4097 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128; 4098 /* We should start from the boundry */ 4099 cam_start = offset * 128; 4100 4101 /* Enable Rx packet buffer access. */ 4102 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); 4103 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) { 4104 /* Set Rx packet buffer offset. 4105 * RxBufer pointer increases 1, 4106 * we can access 8 bytes in Rx packet buffer. 4107 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE 4108 * RxBufer addr = (CAM start offset + 4109 * per entry offset of a WKFM CAM)/8 4110 * * index: The index of the wake up frame mask 4111 * * WKFMCAM_SIZE: the total size of one WKFM CAM 4112 * * per entry offset of a WKFM CAM: Addr*4 bytes 4113 */ 4114 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3; 4115 /* Set R/W start offset */ 4116 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr); 4117 4118 if (addr == 0) { 4119 cam = BIT(31) | rtl_pattern->crc; 4120 4121 if (rtl_pattern->type == UNICAST_PATTERN) 4122 cam |= BIT(24); 4123 else if (rtl_pattern->type == MULTICAST_PATTERN) 4124 cam |= BIT(25); 4125 else if (rtl_pattern->type == BROADCAST_PATTERN) 4126 cam |= BIT(26); 4127 4128 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4129 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4130 "WRITE entry[%d] 0x%x: %x\n", addr, 4131 REG_PKTBUF_DBG_DATA_L, cam); 4132 4133 /* Write to Rx packet buffer. */ 4134 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4135 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */ 4136 cam = rtl_pattern->mask[addr - 2]; 4137 4138 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4139 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4140 "WRITE entry[%d] 0x%x: %x\n", addr, 4141 REG_PKTBUF_DBG_DATA_L, cam); 4142 4143 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4144 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */ 4145 cam = rtl_pattern->mask[addr - 2]; 4146 4147 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam); 4148 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4149 "WRITE entry[%d] 0x%x: %x\n", addr, 4150 REG_PKTBUF_DBG_DATA_H, cam); 4151 4152 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001); 4153 } 4154 4155 count = 0; 4156 do { 4157 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL); 4158 udelay(2); 4159 count++; 4160 } while (tmp && count < 100); 4161 4162 WARN_ONCE((count >= 100), 4163 "rtl8821ae: Write wake up frame mask FAIL %d value!\n", 4164 tmp); 4165 } 4166 /* Disable Rx packet buffer access. */ 4167 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, 4168 DISABLE_TRXPKT_BUF_ACCESS); 4169 } 4170