1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 #include "../pwrseqcmd.h" 41 #include "pwrseq.h" 42 #include "../btcoexist/rtl_btc.h" 43 44 #define LLT_CONFIG 5 45 46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE]; 51 unsigned long flags; 52 53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 54 while (skb_queue_len(&ring->queue)) { 55 struct rtl_tx_desc *entry = &ring->desc[ring->idx]; 56 struct sk_buff *skb = __skb_dequeue(&ring->queue); 57 58 pci_unmap_single(rtlpci->pdev, 59 rtlpriv->cfg->ops->get_desc( 60 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), 61 skb->len, PCI_DMA_TODEVICE); 62 kfree_skb(skb); 63 ring->idx = (ring->idx + 1) % ring->entries; 64 } 65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 66 } 67 68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 69 u8 set_bits, u8 clear_bits) 70 { 71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 74 rtlpci->reg_bcn_ctrl_val |= set_bits; 75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 76 77 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 78 } 79 80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw) 81 { 82 struct rtl_priv *rtlpriv = rtl_priv(hw); 83 u8 tmp1byte; 84 85 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 86 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 89 tmp1byte &= ~(BIT(0)); 90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 91 } 92 93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw) 94 { 95 struct rtl_priv *rtlpriv = rtl_priv(hw); 96 u8 tmp1byte; 97 98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 101 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 102 tmp1byte |= BIT(0); 103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 104 } 105 106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw) 107 { 108 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); 109 } 110 111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw) 112 { 113 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0); 114 } 115 116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw, 117 u8 rpwm_val, bool b_need_turn_off_ckk) 118 { 119 struct rtl_priv *rtlpriv = rtl_priv(hw); 120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 121 bool b_support_remote_wake_up; 122 u32 count = 0, isr_regaddr, content; 123 bool b_schedule_timer = b_need_turn_off_ckk; 124 125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 126 (u8 *)(&b_support_remote_wake_up)); 127 128 if (!rtlhal->fw_ready) 129 return; 130 if (!rtlpriv->psc.fw_current_inpsmode) 131 return; 132 133 while (1) { 134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 135 if (rtlhal->fw_clk_change_in_progress) { 136 while (rtlhal->fw_clk_change_in_progress) { 137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 138 count++; 139 udelay(100); 140 if (count > 1000) 141 goto change_done; 142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 143 } 144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 145 } else { 146 rtlhal->fw_clk_change_in_progress = false; 147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 148 goto change_done; 149 } 150 } 151 change_done: 152 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) { 153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 154 (u8 *)(&rpwm_val)); 155 if (FW_PS_IS_ACK(rpwm_val)) { 156 isr_regaddr = REG_HISR; 157 content = rtl_read_dword(rtlpriv, isr_regaddr); 158 while (!(content & IMR_CPWM) && (count < 500)) { 159 udelay(50); 160 count++; 161 content = rtl_read_dword(rtlpriv, isr_regaddr); 162 } 163 164 if (content & IMR_CPWM) { 165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE; 167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 168 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n", 169 rtlhal->fw_ps_state); 170 } 171 } 172 173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 174 rtlhal->fw_clk_change_in_progress = false; 175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 176 if (b_schedule_timer) 177 mod_timer(&rtlpriv->works.fw_clockoff_timer, 178 jiffies + MSECS(10)); 179 } else { 180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 181 rtlhal->fw_clk_change_in_progress = false; 182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 183 } 184 } 185 186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw, 187 u8 rpwm_val) 188 { 189 struct rtl_priv *rtlpriv = rtl_priv(hw); 190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 192 struct rtl8192_tx_ring *ring; 193 enum rf_pwrstate rtstate; 194 bool b_schedule_timer = false; 195 u8 queue; 196 197 if (!rtlhal->fw_ready) 198 return; 199 if (!rtlpriv->psc.fw_current_inpsmode) 200 return; 201 if (!rtlhal->allow_sw_to_change_hwclc) 202 return; 203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 205 return; 206 207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 208 ring = &rtlpci->tx_ring[queue]; 209 if (skb_queue_len(&ring->queue)) { 210 b_schedule_timer = true; 211 break; 212 } 213 } 214 215 if (b_schedule_timer) { 216 mod_timer(&rtlpriv->works.fw_clockoff_timer, 217 jiffies + MSECS(10)); 218 return; 219 } 220 221 if (FW_PS_STATE(rtlhal->fw_ps_state) != 222 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) { 223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 224 if (!rtlhal->fw_clk_change_in_progress) { 225 rtlhal->fw_clk_change_in_progress = true; 226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 228 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 230 (u8 *)(&rpwm_val)); 231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 232 rtlhal->fw_clk_change_in_progress = false; 233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 234 } else { 235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 236 mod_timer(&rtlpriv->works.fw_clockoff_timer, 237 jiffies + MSECS(10)); 238 } 239 } 240 } 241 242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw) 243 { 244 u8 rpwm_val = 0; 245 246 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK); 247 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true); 248 } 249 250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw) 251 { 252 struct rtl_priv *rtlpriv = rtl_priv(hw); 253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 255 bool fw_current_inps = false; 256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 257 258 if (ppsc->low_power_enable) { 259 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */ 260 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false); 261 rtlhal->allow_sw_to_change_hwclc = false; 262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 263 (u8 *)(&fw_pwrmode)); 264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 265 (u8 *)(&fw_current_inps)); 266 } else { 267 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */ 268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 269 (u8 *)(&rpwm_val)); 270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 271 (u8 *)(&fw_pwrmode)); 272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 273 (u8 *)(&fw_current_inps)); 274 } 275 } 276 277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw) 278 { 279 struct rtl_priv *rtlpriv = rtl_priv(hw); 280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 282 bool fw_current_inps = true; 283 u8 rpwm_val; 284 285 if (ppsc->low_power_enable) { 286 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */ 287 rtlpriv->cfg->ops->set_hw_reg(hw, 288 HW_VAR_FW_PSMODE_STATUS, 289 (u8 *)(&fw_current_inps)); 290 rtlpriv->cfg->ops->set_hw_reg(hw, 291 HW_VAR_H2C_FW_PWRMODE, 292 (u8 *)(&ppsc->fwctrl_psmode)); 293 rtlhal->allow_sw_to_change_hwclc = true; 294 _rtl8821ae_set_fw_clock_off(hw, rpwm_val); 295 } else { 296 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */ 297 rtlpriv->cfg->ops->set_hw_reg(hw, 298 HW_VAR_FW_PSMODE_STATUS, 299 (u8 *)(&fw_current_inps)); 300 rtlpriv->cfg->ops->set_hw_reg(hw, 301 HW_VAR_H2C_FW_PWRMODE, 302 (u8 *)(&ppsc->fwctrl_psmode)); 303 rtlpriv->cfg->ops->set_hw_reg(hw, 304 HW_VAR_SET_RPWM, 305 (u8 *)(&rpwm_val)); 306 } 307 } 308 309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw, 310 bool dl_whole_packets) 311 { 312 struct rtl_priv *rtlpriv = rtl_priv(hw); 313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 314 u8 tmp_regcr, tmp_reg422, bcnvalid_reg; 315 u8 count = 0, dlbcn_count = 0; 316 bool send_beacon = false; 317 318 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 319 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0))); 320 321 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 322 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 323 324 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 325 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 326 tmp_reg422 & (~BIT(6))); 327 if (tmp_reg422 & BIT(6)) 328 send_beacon = true; 329 330 do { 331 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 332 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 333 (bcnvalid_reg | BIT(0))); 334 _rtl8821ae_return_beacon_queue_skb(hw); 335 336 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 337 rtl8812ae_set_fw_rsvdpagepkt(hw, false, 338 dl_whole_packets); 339 else 340 rtl8821ae_set_fw_rsvdpagepkt(hw, false, 341 dl_whole_packets); 342 343 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 344 count = 0; 345 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 346 count++; 347 udelay(10); 348 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2); 349 } 350 dlbcn_count++; 351 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 352 353 if (!(bcnvalid_reg & BIT(0))) 354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 355 "Download RSVD page failed!\n"); 356 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) { 357 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0)); 358 _rtl8821ae_return_beacon_queue_skb(hw); 359 if (send_beacon) { 360 dlbcn_count = 0; 361 do { 362 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, 363 bcnvalid_reg | BIT(0)); 364 365 _rtl8821ae_return_beacon_queue_skb(hw); 366 367 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 368 rtl8812ae_set_fw_rsvdpagepkt(hw, true, 369 false); 370 else 371 rtl8821ae_set_fw_rsvdpagepkt(hw, true, 372 false); 373 374 /* check rsvd page download OK. */ 375 bcnvalid_reg = rtl_read_byte(rtlpriv, 376 REG_TDECTRL + 2); 377 count = 0; 378 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 379 count++; 380 udelay(10); 381 bcnvalid_reg = 382 rtl_read_byte(rtlpriv, 383 REG_TDECTRL + 2); 384 } 385 dlbcn_count++; 386 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 387 388 if (!(bcnvalid_reg & BIT(0))) 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 390 "2 Download RSVD page failed!\n"); 391 } 392 } 393 394 if (bcnvalid_reg & BIT(0)) 395 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0)); 396 397 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 398 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 399 400 if (send_beacon) 401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 402 403 if (!rtlhal->enter_pnp_sleep) { 404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0)))); 406 } 407 } 408 409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 410 { 411 struct rtl_priv *rtlpriv = rtl_priv(hw); 412 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 414 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 415 416 switch (variable) { 417 case HW_VAR_ETHER_ADDR: 418 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID); 419 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4); 420 break; 421 case HW_VAR_BSSID: 422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID); 423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4); 424 break; 425 case HW_VAR_MEDIA_STATUS: 426 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3; 427 break; 428 case HW_VAR_SLOT_TIME: 429 *((u8 *)(val)) = mac->slot_time; 430 break; 431 case HW_VAR_BEACON_INTERVAL: 432 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL); 433 break; 434 case HW_VAR_ATIM_WINDOW: 435 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND); 436 break; 437 case HW_VAR_RCR: 438 *((u32 *)(val)) = rtlpci->receive_config; 439 break; 440 case HW_VAR_RF_STATE: 441 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 442 break; 443 case HW_VAR_FWLPS_RF_ON:{ 444 enum rf_pwrstate rfstate; 445 u32 val_rcr; 446 447 rtlpriv->cfg->ops->get_hw_reg(hw, 448 HW_VAR_RF_STATE, 449 (u8 *)(&rfstate)); 450 if (rfstate == ERFOFF) { 451 *((bool *)(val)) = true; 452 } else { 453 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 454 val_rcr &= 0x00070000; 455 if (val_rcr) 456 *((bool *)(val)) = false; 457 else 458 *((bool *)(val)) = true; 459 } 460 break; } 461 case HW_VAR_FW_PSMODE_STATUS: 462 *((bool *)(val)) = ppsc->fw_current_inpsmode; 463 break; 464 case HW_VAR_CORRECT_TSF:{ 465 u64 tsf; 466 u32 *ptsf_low = (u32 *)&tsf; 467 u32 *ptsf_high = ((u32 *)&tsf) + 1; 468 469 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 470 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 471 472 *((u64 *)(val)) = tsf; 473 474 break; } 475 case HAL_DEF_WOWLAN: 476 if (ppsc->wo_wlan_mode) 477 *((bool *)(val)) = true; 478 else 479 *((bool *)(val)) = false; 480 break; 481 default: 482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 483 "switch case %#x not processed\n", variable); 484 break; 485 } 486 } 487 488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 489 { 490 struct rtl_priv *rtlpriv = rtl_priv(hw); 491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 494 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 496 u8 idx; 497 498 switch (variable) { 499 case HW_VAR_ETHER_ADDR:{ 500 for (idx = 0; idx < ETH_ALEN; idx++) { 501 rtl_write_byte(rtlpriv, (REG_MACID + idx), 502 val[idx]); 503 } 504 break; 505 } 506 case HW_VAR_BASIC_RATE:{ 507 u16 b_rate_cfg = ((u16 *)val)[0]; 508 b_rate_cfg = b_rate_cfg & 0x15f; 509 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg); 510 break; 511 } 512 case HW_VAR_BSSID:{ 513 for (idx = 0; idx < ETH_ALEN; idx++) { 514 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 515 val[idx]); 516 } 517 break; 518 } 519 case HW_VAR_SIFS: 520 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 521 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]); 522 523 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 524 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 525 526 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]); 528 break; 529 case HW_VAR_R2T_SIFS: 530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]); 531 break; 532 case HW_VAR_SLOT_TIME:{ 533 u8 e_aci; 534 535 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 536 "HW_VAR_SLOT_TIME %x\n", val[0]); 537 538 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 539 540 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 541 rtlpriv->cfg->ops->set_hw_reg(hw, 542 HW_VAR_AC_PARAM, 543 (u8 *)(&e_aci)); 544 } 545 break; } 546 case HW_VAR_ACK_PREAMBLE:{ 547 u8 reg_tmp; 548 u8 short_preamble = (bool)(*(u8 *)val); 549 550 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2); 551 if (short_preamble) { 552 reg_tmp |= BIT(1); 553 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, 554 reg_tmp); 555 } else { 556 reg_tmp &= (~BIT(1)); 557 rtl_write_byte(rtlpriv, 558 REG_TRXPTCL_CTL + 2, 559 reg_tmp); 560 } 561 break; } 562 case HW_VAR_WPA_CONFIG: 563 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 564 break; 565 case HW_VAR_AMPDU_MIN_SPACE:{ 566 u8 min_spacing_to_set; 567 u8 sec_min_space; 568 569 min_spacing_to_set = *((u8 *)val); 570 if (min_spacing_to_set <= 7) { 571 sec_min_space = 0; 572 573 if (min_spacing_to_set < sec_min_space) 574 min_spacing_to_set = sec_min_space; 575 576 mac->min_space_cfg = ((mac->min_space_cfg & 577 0xf8) | 578 min_spacing_to_set); 579 580 *val = min_spacing_to_set; 581 582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 584 mac->min_space_cfg); 585 586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 587 mac->min_space_cfg); 588 } 589 break; } 590 case HW_VAR_SHORTGI_DENSITY:{ 591 u8 density_to_set; 592 593 density_to_set = *((u8 *)val); 594 mac->min_space_cfg |= (density_to_set << 3); 595 596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 598 mac->min_space_cfg); 599 600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 601 mac->min_space_cfg); 602 603 break; } 604 case HW_VAR_AMPDU_FACTOR:{ 605 u32 ampdu_len = (*((u8 *)val)); 606 607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 608 if (ampdu_len < VHT_AGG_SIZE_128K) 609 ampdu_len = 610 (0x2000 << (*((u8 *)val))) - 1; 611 else 612 ampdu_len = 0x1ffff; 613 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 614 if (ampdu_len < HT_AGG_SIZE_64K) 615 ampdu_len = 616 (0x2000 << (*((u8 *)val))) - 1; 617 else 618 ampdu_len = 0xffff; 619 } 620 ampdu_len |= BIT(31); 621 622 rtl_write_dword(rtlpriv, 623 REG_AMPDU_MAX_LENGTH_8812, ampdu_len); 624 break; } 625 case HW_VAR_AC_PARAM:{ 626 u8 e_aci = *((u8 *)val); 627 628 rtl8821ae_dm_init_edca_turbo(hw); 629 if (rtlpci->acm_method != EACMWAY2_SW) 630 rtlpriv->cfg->ops->set_hw_reg(hw, 631 HW_VAR_ACM_CTRL, 632 (u8 *)(&e_aci)); 633 break; } 634 case HW_VAR_ACM_CTRL:{ 635 u8 e_aci = *((u8 *)val); 636 union aci_aifsn *p_aci_aifsn = 637 (union aci_aifsn *)(&mac->ac[0].aifs); 638 u8 acm = p_aci_aifsn->f.acm; 639 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 640 641 acm_ctrl = 642 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 643 644 if (acm) { 645 switch (e_aci) { 646 case AC0_BE: 647 acm_ctrl |= ACMHW_BEQEN; 648 break; 649 case AC2_VI: 650 acm_ctrl |= ACMHW_VIQEN; 651 break; 652 case AC3_VO: 653 acm_ctrl |= ACMHW_VOQEN; 654 break; 655 default: 656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 657 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 658 acm); 659 break; 660 } 661 } else { 662 switch (e_aci) { 663 case AC0_BE: 664 acm_ctrl &= (~ACMHW_BEQEN); 665 break; 666 case AC2_VI: 667 acm_ctrl &= (~ACMHW_VIQEN); 668 break; 669 case AC3_VO: 670 acm_ctrl &= (~ACMHW_VOQEN); 671 break; 672 default: 673 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 674 "switch case %#x not processed\n", 675 e_aci); 676 break; 677 } 678 } 679 680 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 681 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 682 acm_ctrl); 683 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 684 break; } 685 case HW_VAR_RCR: 686 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 687 rtlpci->receive_config = ((u32 *)(val))[0]; 688 break; 689 case HW_VAR_RETRY_LIMIT:{ 690 u8 retry_limit = ((u8 *)(val))[0]; 691 692 rtl_write_word(rtlpriv, REG_RL, 693 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 694 retry_limit << RETRY_LIMIT_LONG_SHIFT); 695 break; } 696 case HW_VAR_DUAL_TSF_RST: 697 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 698 break; 699 case HW_VAR_EFUSE_BYTES: 700 rtlefuse->efuse_usedbytes = *((u16 *)val); 701 break; 702 case HW_VAR_EFUSE_USAGE: 703 rtlefuse->efuse_usedpercentage = *((u8 *)val); 704 break; 705 case HW_VAR_IO_CMD: 706 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); 707 break; 708 case HW_VAR_SET_RPWM:{ 709 u8 rpwm_val; 710 711 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 712 udelay(1); 713 714 if (rpwm_val & BIT(7)) { 715 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 716 (*(u8 *)val)); 717 } else { 718 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 719 ((*(u8 *)val) | BIT(7))); 720 } 721 722 break; } 723 case HW_VAR_H2C_FW_PWRMODE: 724 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 725 break; 726 case HW_VAR_FW_PSMODE_STATUS: 727 ppsc->fw_current_inpsmode = *((bool *)val); 728 break; 729 case HW_VAR_INIT_RTS_RATE: 730 break; 731 case HW_VAR_RESUME_CLK_ON: 732 _rtl8821ae_set_fw_ps_rf_on(hw); 733 break; 734 case HW_VAR_FW_LPS_ACTION:{ 735 bool b_enter_fwlps = *((bool *)val); 736 737 if (b_enter_fwlps) 738 _rtl8821ae_fwlps_enter(hw); 739 else 740 _rtl8821ae_fwlps_leave(hw); 741 break; } 742 case HW_VAR_H2C_FW_JOINBSSRPT:{ 743 u8 mstatus = (*(u8 *)val); 744 745 if (mstatus == RT_MEDIA_CONNECT) { 746 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 747 NULL); 748 _rtl8821ae_download_rsvd_page(hw, false); 749 } 750 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus); 751 752 break; } 753 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 754 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 755 break; 756 case HW_VAR_AID:{ 757 u16 u2btmp; 758 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 759 u2btmp &= 0xC000; 760 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 761 mac->assoc_id)); 762 break; } 763 case HW_VAR_CORRECT_TSF:{ 764 u8 btype_ibss = ((u8 *)(val))[0]; 765 766 if (btype_ibss) 767 _rtl8821ae_stop_tx_beacon(hw); 768 769 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); 770 771 rtl_write_dword(rtlpriv, REG_TSFTR, 772 (u32)(mac->tsf & 0xffffffff)); 773 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 774 (u32)((mac->tsf >> 32) & 0xffffffff)); 775 776 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 777 778 if (btype_ibss) 779 _rtl8821ae_resume_tx_beacon(hw); 780 break; } 781 case HW_VAR_NAV_UPPER: { 782 u32 us_nav_upper = *(u32 *)val; 783 784 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) { 785 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING, 786 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", 787 us_nav_upper, HAL_92C_NAV_UPPER_UNIT); 788 break; 789 } 790 rtl_write_byte(rtlpriv, REG_NAV_UPPER, 791 ((u8)((us_nav_upper + 792 HAL_92C_NAV_UPPER_UNIT - 1) / 793 HAL_92C_NAV_UPPER_UNIT))); 794 break; } 795 case HW_VAR_KEEP_ALIVE: { 796 u8 array[2]; 797 array[0] = 0xff; 798 array[1] = *((u8 *)val); 799 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, 800 array); 801 break; } 802 default: 803 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 804 "switch case %#x not processed\n", variable); 805 break; 806 } 807 } 808 809 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 810 { 811 struct rtl_priv *rtlpriv = rtl_priv(hw); 812 bool status = true; 813 long count = 0; 814 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | 815 _LLT_OP(_LLT_WRITE_ACCESS); 816 817 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 818 819 do { 820 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 821 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 822 break; 823 824 if (count > POLLING_LLT_THRESHOLD) { 825 pr_err("Failed to polling write LLT done at address %d!\n", 826 address); 827 status = false; 828 break; 829 } 830 } while (++count); 831 832 return status; 833 } 834 835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw) 836 { 837 struct rtl_priv *rtlpriv = rtl_priv(hw); 838 unsigned short i; 839 u8 txpktbuf_bndy; 840 u32 rqpn; 841 u8 maxpage; 842 bool status; 843 844 maxpage = 255; 845 txpktbuf_bndy = 0xF7; 846 rqpn = 0x80e60808; 847 848 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 849 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1); 850 851 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 852 853 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 854 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 855 856 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 857 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 858 859 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 860 status = _rtl8821ae_llt_write(hw, i, i + 1); 861 if (!status) 862 return status; 863 } 864 865 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 866 if (!status) 867 return status; 868 869 for (i = txpktbuf_bndy; i < maxpage; i++) { 870 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 871 if (!status) 872 return status; 873 } 874 875 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy); 876 if (!status) 877 return status; 878 879 rtl_write_dword(rtlpriv, REG_RQPN, rqpn); 880 881 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00); 882 883 return true; 884 } 885 886 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw) 887 { 888 struct rtl_priv *rtlpriv = rtl_priv(hw); 889 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 890 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 891 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 892 893 if (rtlpriv->rtlhal.up_first_time) 894 return; 895 896 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 897 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 898 rtl8812ae_sw_led_on(hw, pled0); 899 else 900 rtl8821ae_sw_led_on(hw, pled0); 901 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 902 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 903 rtl8812ae_sw_led_on(hw, pled0); 904 else 905 rtl8821ae_sw_led_on(hw, pled0); 906 else 907 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 908 rtl8812ae_sw_led_off(hw, pled0); 909 else 910 rtl8821ae_sw_led_off(hw, pled0); 911 } 912 913 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw) 914 { 915 struct rtl_priv *rtlpriv = rtl_priv(hw); 916 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 917 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 918 919 u8 bytetmp = 0; 920 u16 wordtmp = 0; 921 bool mac_func_enable = rtlhal->mac_func_enable; 922 923 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 924 925 /*Auto Power Down to CHIP-off State*/ 926 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7)); 927 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 928 929 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 930 /* HW Power on sequence*/ 931 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, 932 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 933 RTL8812_NIC_ENABLE_FLOW)) { 934 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 935 "init 8812 MAC Fail as power on failure\n"); 936 return false; 937 } 938 } else { 939 /* HW Power on sequence */ 940 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, 941 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, 942 RTL8821A_NIC_ENABLE_FLOW)){ 943 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 944 "init 8821 MAC Fail as power on failure\n"); 945 return false; 946 } 947 } 948 949 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4); 950 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp); 951 952 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 953 bytetmp = 0xff; 954 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 955 mdelay(2); 956 957 bytetmp = 0xff; 958 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 959 mdelay(2); 960 961 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 962 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3); 963 if (bytetmp & BIT(0)) { 964 bytetmp = rtl_read_byte(rtlpriv, 0x7c); 965 bytetmp |= BIT(6); 966 rtl_write_byte(rtlpriv, 0x7c, bytetmp); 967 } 968 } 969 970 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 971 bytetmp &= ~BIT(4); 972 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp); 973 974 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 975 976 if (!mac_func_enable) { 977 if (!_rtl8821ae_llt_table_init(hw)) 978 return false; 979 } 980 981 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 982 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 983 984 /* Enable FW Beamformer Interrupt */ 985 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3); 986 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6)); 987 988 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 989 wordtmp &= 0xf; 990 wordtmp |= 0xF5B1; 991 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 992 993 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 994 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 995 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 996 /*low address*/ 997 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 998 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 999 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1000 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1001 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1002 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1003 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1004 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1005 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1006 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1007 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1008 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1009 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1010 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1011 rtl_write_dword(rtlpriv, REG_RX_DESA, 1012 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1013 1014 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 1015 1016 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 1017 1018 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0); 1019 1020 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3); 1021 _rtl8821ae_gen_refresh_led_state(hw); 1022 1023 return true; 1024 } 1025 1026 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw) 1027 { 1028 struct rtl_priv *rtlpriv = rtl_priv(hw); 1029 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1030 u32 reg_rrsr; 1031 1032 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 1033 1034 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 1035 /* ARFB table 9 for 11ac 5G 2SS */ 1036 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000); 1037 /* ARFB table 10 for 11ac 5G 1SS */ 1038 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000); 1039 /* ARFB table 11 for 11ac 24G 1SS */ 1040 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015); 1041 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000); 1042 /* ARFB table 12 for 11ac 24G 1SS */ 1043 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015); 1044 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000); 1045 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */ 1046 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00); 1047 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70); 1048 1049 /*Set retry limit*/ 1050 rtl_write_word(rtlpriv, REG_RL, 0x0707); 1051 1052 /* Set Data / Response auto rate fallack retry count*/ 1053 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 1054 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 1055 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 1056 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 1057 1058 rtlpci->reg_bcn_ctrl_val = 0x1d; 1059 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 1060 1061 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 1062 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1063 1064 /* AGGR_BK_TIME Reg51A 0x16 */ 1065 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 1066 1067 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 1068 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 1069 1070 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80); 1071 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1072 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F); 1073 } 1074 1075 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr) 1076 { 1077 u16 ret = 0; 1078 u8 tmp = 0, count = 0; 1079 1080 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6)); 1081 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1082 count = 0; 1083 while (tmp && count < 20) { 1084 udelay(10); 1085 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6); 1086 count++; 1087 } 1088 if (0 == tmp) 1089 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA); 1090 1091 return ret; 1092 } 1093 1094 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data) 1095 { 1096 u8 tmp = 0, count = 0; 1097 1098 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data); 1099 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5)); 1100 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1101 count = 0; 1102 while (tmp && count < 20) { 1103 udelay(10); 1104 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5); 1105 count++; 1106 } 1107 } 1108 1109 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr) 1110 { 1111 u16 read_addr = addr & 0xfffc; 1112 u8 tmp = 0, count = 0, ret = 0; 1113 1114 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr); 1115 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2); 1116 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1117 count = 0; 1118 while (tmp && count < 20) { 1119 udelay(10); 1120 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1121 count++; 1122 } 1123 if (0 == tmp) { 1124 read_addr = REG_DBI_RDATA + addr % 4; 1125 ret = rtl_read_byte(rtlpriv, read_addr); 1126 } 1127 return ret; 1128 } 1129 1130 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data) 1131 { 1132 u8 tmp = 0, count = 0; 1133 u16 wrtie_addr, remainder = addr % 4; 1134 1135 wrtie_addr = REG_DBI_WDATA + remainder; 1136 rtl_write_byte(rtlpriv, wrtie_addr, data); 1137 1138 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12)); 1139 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr); 1140 1141 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1); 1142 1143 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1144 count = 0; 1145 while (tmp && count < 20) { 1146 udelay(10); 1147 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG); 1148 count++; 1149 } 1150 } 1151 1152 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw) 1153 { 1154 struct rtl_priv *rtlpriv = rtl_priv(hw); 1155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1156 u8 tmp; 1157 1158 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1159 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544) 1160 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544); 1161 1162 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070) 1163 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070); 1164 } 1165 1166 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f); 1167 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7)); 1168 1169 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719); 1170 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4)); 1171 1172 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1173 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1174 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4)); 1175 } 1176 } 1177 1178 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw) 1179 { 1180 struct rtl_priv *rtlpriv = rtl_priv(hw); 1181 u8 sec_reg_value; 1182 u8 tmp; 1183 1184 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1185 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1186 rtlpriv->sec.pairwise_enc_algorithm, 1187 rtlpriv->sec.group_enc_algorithm); 1188 1189 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1190 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1191 "not open hw encryption\n"); 1192 return; 1193 } 1194 1195 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1196 1197 if (rtlpriv->sec.use_defaultkey) { 1198 sec_reg_value |= SCR_TXUSEDK; 1199 sec_reg_value |= SCR_RXUSEDK; 1200 } 1201 1202 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1203 1204 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1205 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1206 1207 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1208 "The SECR-value %x\n", sec_reg_value); 1209 1210 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1211 } 1212 1213 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */ 1214 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0 1215 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1 1216 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2 1217 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3 1218 /* ----------------------------------------------------------- */ 1219 1220 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw) 1221 { 1222 struct rtl_priv *rtlpriv = rtl_priv(hw); 1223 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1, 1224 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1225 MAC_ID_STATIC_FOR_BT_CLIENT_END}; 1226 1227 rtlpriv->cfg->ops->set_hw_reg(hw, 1228 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt); 1229 1230 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1231 "Initialize MacId media status: from %d to %d\n", 1232 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, 1233 MAC_ID_STATIC_FOR_BT_CLIENT_END); 1234 } 1235 1236 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw) 1237 { 1238 struct rtl_priv *rtlpriv = rtl_priv(hw); 1239 u8 tmp; 1240 1241 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1242 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1243 if (!(tmp & BIT(2))) { 1244 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2))); 1245 mdelay(100); 1246 } 1247 1248 /* read reg 0x350 Bit[25] if 1 : RX hang */ 1249 /* read reg 0x350 Bit[24] if 1 : TX hang */ 1250 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3); 1251 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1252 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1253 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n"); 1254 return true; 1255 } else { 1256 return false; 1257 } 1258 } 1259 1260 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw, 1261 bool mac_power_on, 1262 bool in_watchdog) 1263 { 1264 struct rtl_priv *rtlpriv = rtl_priv(hw); 1265 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1266 u8 tmp; 1267 bool release_mac_rx_pause; 1268 u8 backup_pcie_dma_pause; 1269 1270 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1271 1272 /* 1. Disable register write lock. 0x1c[1] = 0 */ 1273 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1274 tmp &= ~(BIT(1)); 1275 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1276 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1277 /* write 0xCC bit[2] = 1'b1 */ 1278 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1279 tmp |= BIT(2); 1280 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1281 } 1282 1283 /* 2. Check and pause TRX DMA */ 1284 /* write 0x284 bit[18] = 1'b1 */ 1285 /* write 0x301 = 0xFF */ 1286 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1287 if (tmp & BIT(2)) { 1288 /* Already pause before the function for another purpose. */ 1289 release_mac_rx_pause = false; 1290 } else { 1291 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1292 release_mac_rx_pause = true; 1293 } 1294 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1295 if (backup_pcie_dma_pause != 0xFF) 1296 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1297 1298 if (mac_power_on) { 1299 /* 3. reset TRX function */ 1300 /* write 0x100 = 0x00 */ 1301 rtl_write_byte(rtlpriv, REG_CR, 0); 1302 } 1303 1304 /* 4. Reset PCIe DMA. 0x3[0] = 0 */ 1305 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1306 tmp &= ~(BIT(0)); 1307 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1308 1309 /* 5. Enable PCIe DMA. 0x3[0] = 1 */ 1310 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1311 tmp |= BIT(0); 1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1313 1314 if (mac_power_on) { 1315 /* 6. enable TRX function */ 1316 /* write 0x100 = 0xFF */ 1317 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1318 1319 /* We should init LLT & RQPN and 1320 * prepare Tx/Rx descrptor address later 1321 * because MAC function is reset.*/ 1322 } 1323 1324 /* 7. Restore PCIe autoload down bit */ 1325 /* 8812AE does not has the defination. */ 1326 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1327 /* write 0xF8 bit[17] = 1'b1 */ 1328 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1329 tmp |= BIT(1); 1330 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1331 } 1332 1333 /* In MAC power on state, BB and RF maybe in ON state, 1334 * if we release TRx DMA here. 1335 * it will cause packets to be started to Tx/Rx, 1336 * so we release Tx/Rx DMA later.*/ 1337 if (!mac_power_on/* || in_watchdog*/) { 1338 /* 8. release TRX DMA */ 1339 /* write 0x284 bit[18] = 1'b0 */ 1340 /* write 0x301 = 0x00 */ 1341 if (release_mac_rx_pause) { 1342 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1343 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1344 tmp & (~BIT(2))); 1345 } 1346 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1347 backup_pcie_dma_pause); 1348 } 1349 1350 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1351 /* 9. lock system register */ 1352 /* write 0xCC bit[2] = 1'b0 */ 1353 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1354 tmp &= ~(BIT(2)); 1355 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1356 } 1357 return true; 1358 } 1359 1360 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw) 1361 { 1362 struct rtl_priv *rtlpriv = rtl_priv(hw); 1363 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1364 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1365 u8 fw_reason = 0; 1366 struct timeval ts; 1367 1368 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN); 1369 1370 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n", 1371 fw_reason); 1372 1373 ppsc->wakeup_reason = 0; 1374 1375 rtlhal->last_suspend_sec = ts.tv_sec; 1376 1377 switch (fw_reason) { 1378 case FW_WOW_V2_PTK_UPDATE_EVENT: 1379 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE; 1380 do_gettimeofday(&ts); 1381 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000; 1382 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1383 "It's a WOL PTK Key update event!\n"); 1384 break; 1385 case FW_WOW_V2_GTK_UPDATE_EVENT: 1386 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE; 1387 do_gettimeofday(&ts); 1388 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000; 1389 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1390 "It's a WOL GTK Key update event!\n"); 1391 break; 1392 case FW_WOW_V2_DISASSOC_EVENT: 1393 ppsc->wakeup_reason = WOL_REASON_DISASSOC; 1394 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1395 "It's a disassociation event!\n"); 1396 break; 1397 case FW_WOW_V2_DEAUTH_EVENT: 1398 ppsc->wakeup_reason = WOL_REASON_DEAUTH; 1399 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1400 "It's a deauth event!\n"); 1401 break; 1402 case FW_WOW_V2_FW_DISCONNECT_EVENT: 1403 ppsc->wakeup_reason = WOL_REASON_AP_LOST; 1404 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1405 "It's a Fw disconnect decision (AP lost) event!\n"); 1406 break; 1407 case FW_WOW_V2_MAGIC_PKT_EVENT: 1408 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT; 1409 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1410 "It's a magic packet event!\n"); 1411 break; 1412 case FW_WOW_V2_UNICAST_PKT_EVENT: 1413 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT; 1414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1415 "It's an unicast packet event!\n"); 1416 break; 1417 case FW_WOW_V2_PATTERN_PKT_EVENT: 1418 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT; 1419 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1420 "It's a pattern match event!\n"); 1421 break; 1422 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT: 1423 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH; 1424 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1425 "It's an RTD3 Ssid match event!\n"); 1426 break; 1427 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT: 1428 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT; 1429 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1430 "It's an RealWoW wake packet event!\n"); 1431 break; 1432 case FW_WOW_V2_REALWOW_V2_ACKLOST: 1433 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST; 1434 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1435 "It's an RealWoW ack lost event!\n"); 1436 break; 1437 default: 1438 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 1439 "WOL Read 0x1c7 = %02X, Unknown reason!\n", 1440 fw_reason); 1441 break; 1442 } 1443 } 1444 1445 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw) 1446 { 1447 struct rtl_priv *rtlpriv = rtl_priv(hw); 1448 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1449 1450 /*low address*/ 1451 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 1452 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32)); 1453 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 1454 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32)); 1455 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 1456 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 1457 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 1458 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 1459 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 1460 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 1461 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 1462 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 1463 rtl_write_dword(rtlpriv, REG_HQ_DESA, 1464 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32)); 1465 rtl_write_dword(rtlpriv, REG_RX_DESA, 1466 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32)); 1467 } 1468 1469 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 1470 { 1471 bool status = true; 1472 u32 i; 1473 u32 txpktbuf_bndy = boundary; 1474 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER; 1475 1476 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) { 1477 status = _rtl8821ae_llt_write(hw, i , i + 1); 1478 if (!status) 1479 return status; 1480 } 1481 1482 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 1483 if (!status) 1484 return status; 1485 1486 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) { 1487 status = _rtl8821ae_llt_write(hw, i, (i + 1)); 1488 if (!status) 1489 return status; 1490 } 1491 1492 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf, 1493 txpktbuf_bndy); 1494 if (!status) 1495 return status; 1496 1497 return status; 1498 } 1499 1500 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary, 1501 u16 npq_rqpn_value, u32 rqpn_val) 1502 { 1503 struct rtl_priv *rtlpriv = rtl_priv(hw); 1504 u8 tmp; 1505 bool ret = true; 1506 u16 count = 0, tmp16; 1507 bool support_remote_wakeup; 1508 1509 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1510 (u8 *)(&support_remote_wakeup)); 1511 1512 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1513 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n", 1514 boundary, npq_rqpn_value, rqpn_val); 1515 1516 /* stop PCIe DMA 1517 * 1. 0x301[7:0] = 0xFE */ 1518 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1519 1520 /* wait TXFF empty 1521 * 2. polling till 0x41A[15:0]=0x07FF */ 1522 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1523 while ((tmp16 & 0x07FF) != 0x07FF) { 1524 udelay(100); 1525 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY); 1526 count++; 1527 if ((count % 200) == 0) { 1528 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1529 "Tx queue is not empty for 20ms!\n"); 1530 } 1531 if (count >= 1000) { 1532 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1533 "Wait for Tx FIFO empty timeout!\n"); 1534 break; 1535 } 1536 } 1537 1538 /* TX pause 1539 * 3. reg 0x522=0xFF */ 1540 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1541 1542 /* Wait TX State Machine OK 1543 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */ 1544 count = 0; 1545 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) { 1546 udelay(100); 1547 count++; 1548 if (count >= 500) { 1549 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1550 "Wait for TX State Machine ready timeout !!\n"); 1551 break; 1552 } 1553 } 1554 1555 /* stop RX DMA path 1556 * 5. 0x284[18] = 1 1557 * 6. wait till 0x284[17] == 1 1558 * wait RX DMA idle */ 1559 count = 0; 1560 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1561 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1562 do { 1563 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1564 udelay(10); 1565 count++; 1566 } while (!(tmp & BIT(1)) && count < 100); 1567 1568 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1569 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n", 1570 count, tmp); 1571 1572 /* reset BB 1573 * 7. 0x02 [0] = 0 */ 1574 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1575 tmp &= ~(BIT(0)); 1576 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp); 1577 1578 /* Reset TRX MAC 1579 * 8. 0x100 = 0x00 1580 * Delay (1ms) */ 1581 rtl_write_byte(rtlpriv, REG_CR, 0x00); 1582 udelay(1000); 1583 1584 /* Disable MAC Security Engine 1585 * 9. 0x100 bit[9]=0 */ 1586 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1587 tmp &= ~(BIT(1)); 1588 rtl_write_byte(rtlpriv, REG_CR + 1, tmp); 1589 1590 /* To avoid DD-Tim Circuit hang 1591 * 10. 0x553 bit[5]=1 */ 1592 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST); 1593 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5))); 1594 1595 /* Enable MAC Security Engine 1596 * 11. 0x100 bit[9]=1 */ 1597 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1598 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1))); 1599 1600 /* Enable TRX MAC 1601 * 12. 0x100 = 0xFF 1602 * Delay (1ms) */ 1603 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1604 udelay(1000); 1605 1606 /* Enable BB 1607 * 13. 0x02 [0] = 1 */ 1608 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 1609 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0))); 1610 1611 /* beacon setting 1612 * 14,15. set beacon head page (reg 0x209 and 0x424) */ 1613 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary); 1614 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary); 1615 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary); 1616 1617 /* 16. WMAC_LBK_BF_HD 0x45D[7:0] 1618 * WMAC_LBK_BF_HD */ 1619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, 1620 (u8)boundary); 1621 1622 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary); 1623 1624 /* init LLT 1625 * 17. init LLT */ 1626 if (!_rtl8821ae_init_llt_table(hw, boundary)) { 1627 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 1628 "Failed to init LLT table!\n"); 1629 return false; 1630 } 1631 1632 /* reallocate RQPN 1633 * 18. reallocate RQPN and init LLT */ 1634 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value); 1635 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val); 1636 1637 /* release Tx pause 1638 * 19. 0x522=0x00 */ 1639 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1640 1641 /* enable PCIE DMA 1642 * 20. 0x301[7:0] = 0x00 1643 * 21. 0x284[18] = 0 */ 1644 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1645 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1646 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2))); 1647 1648 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n"); 1649 return ret; 1650 } 1651 1652 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw) 1653 { 1654 struct rtl_priv *rtlpriv = rtl_priv(hw); 1655 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1656 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 1657 1658 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 1659 /* Re-download normal Fw. */ 1660 rtl8821ae_set_fw_related_for_wowlan(hw, false); 1661 #endif 1662 1663 /* Re-Initialize LLT table. */ 1664 if (rtlhal->re_init_llt_table) { 1665 u32 rqpn = 0x80e70808; 1666 u8 rqpn_npq = 0, boundary = 0xF8; 1667 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 1668 rqpn = 0x80e90808; 1669 boundary = 0xFA; 1670 } 1671 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn)) 1672 rtlhal->re_init_llt_table = false; 1673 } 1674 1675 ppsc->rfpwr_state = ERFON; 1676 } 1677 1678 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw) 1679 { 1680 u8 tmp = 0; 1681 struct rtl_priv *rtlpriv = rtl_priv(hw); 1682 1683 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1684 1685 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160); 1686 if (!(tmp & (BIT(2) | BIT(3)))) { 1687 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD, 1688 "0x160(%#x)return!!\n", tmp); 1689 return; 1690 } 1691 1692 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b); 1693 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4))); 1694 1695 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718); 1696 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5)); 1697 1698 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1699 } 1700 1701 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw) 1702 { 1703 u8 tmp = 0; 1704 struct rtl_priv *rtlpriv = rtl_priv(hw); 1705 1706 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n"); 1707 1708 /* Check 0x98[10] */ 1709 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99); 1710 if (!(tmp & BIT(2))) { 1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1712 "<---0x99(%#x) return!!\n", tmp); 1713 return; 1714 } 1715 1716 /* LTR idle latency, 0x90 for 144us */ 1717 rtl_write_dword(rtlpriv, 0x798, 0x88908890); 1718 1719 /* LTR active latency, 0x3c for 60us */ 1720 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c); 1721 1722 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1723 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4))); 1724 1725 tmp = rtl_read_byte(rtlpriv, 0x7a4); 1726 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0)))); 1727 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0))); 1728 1729 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n"); 1730 } 1731 1732 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw) 1733 { 1734 struct rtl_priv *rtlpriv = rtl_priv(hw); 1735 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1736 bool init_finished = true; 1737 u8 tmp = 0; 1738 1739 /* Get Fw wake up reason. */ 1740 _rtl8821ae_get_wakeup_reason(hw); 1741 1742 /* Patch Pcie Rx DMA hang after S3/S4 several times. 1743 * The root cause has not be found. */ 1744 if (_rtl8821ae_check_pcie_dma_hang(hw)) 1745 _rtl8821ae_reset_pcie_interface_dma(hw, true, false); 1746 1747 /* Prepare Tx/Rx Desc Hw address. */ 1748 _rtl8821ae_init_trx_desc_hw_address(hw); 1749 1750 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */ 1751 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1752 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n"); 1753 1754 /* Check wake up event. 1755 * We should check wake packet bit before disable wowlan by H2C or 1756 * Fw will clear the bit. */ 1757 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3); 1758 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1759 "Read REG_FTISR 0x13f = %#X\n", tmp); 1760 1761 /* Set the WoWLAN related function control disable. */ 1762 rtl8821ae_set_fw_wowlan_mode(hw, false); 1763 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0); 1764 1765 if (rtlhal->hw_rof_enable) { 1766 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 1767 if (tmp & BIT(1)) { 1768 /* Clear GPIO9 ISR */ 1769 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 1770 init_finished = false; 1771 } else { 1772 init_finished = true; 1773 } 1774 } 1775 1776 if (init_finished) { 1777 _rtl8821ae_simple_initialize_adapter(hw); 1778 1779 /* Release Pcie Interface Tx DMA. */ 1780 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00); 1781 /* Release Pcie RX DMA */ 1782 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02); 1783 1784 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1785 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0)))); 1786 1787 _rtl8821ae_enable_l1off(hw); 1788 _rtl8821ae_enable_ltr(hw); 1789 } 1790 1791 return init_finished; 1792 } 1793 1794 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw) 1795 { 1796 /* BB OFDM RX Path_A */ 1797 rtl_set_bbreg(hw, 0x808, 0xff, 0x11); 1798 /* BB OFDM TX Path_A */ 1799 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111); 1800 /* BB CCK R/Rx Path_A */ 1801 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0); 1802 /* MCS support */ 1803 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4); 1804 /* RF Path_B HSSI OFF */ 1805 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4); 1806 /* RF Path_B Power Down */ 1807 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0); 1808 /* ADDA Path_B OFF */ 1809 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0); 1810 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0); 1811 } 1812 1813 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw) 1814 { 1815 struct rtl_priv *rtlpriv = rtl_priv(hw); 1816 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1817 u8 u1b_tmp; 1818 1819 rtlhal->mac_func_enable = false; 1820 1821 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1822 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1823 /* 1. Run LPS WL RFOFF flow */ 1824 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1825 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"); 1826 */ 1827 rtl_hal_pwrseqcmdparsing(rtlpriv, 1828 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1829 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW); 1830 } 1831 /* 2. 0x1F[7:0] = 0 */ 1832 /* turn off RF */ 1833 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */ 1834 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1835 rtlhal->fw_ready) { 1836 rtl8821ae_firmware_selfreset(hw); 1837 } 1838 1839 /* Reset MCU. Suggested by Filen. */ 1840 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1841 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1842 1843 /* g. MCUFWDL 0x80[1:0]=0 */ 1844 /* reset MCU ready status */ 1845 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1846 1847 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 1848 /* HW card disable configuration. */ 1849 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1850 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW); 1851 } else { 1852 /* HW card disable configuration. */ 1853 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1854 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW); 1855 } 1856 1857 /* Reset MCU IO Wrapper */ 1858 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1859 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1860 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1861 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1862 1863 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1864 /* lock ISO/CLK/Power control register */ 1865 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1866 } 1867 1868 int rtl8821ae_hw_init(struct ieee80211_hw *hw) 1869 { 1870 struct rtl_priv *rtlpriv = rtl_priv(hw); 1871 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1872 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1873 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1874 bool rtstatus = true; 1875 int err; 1876 u8 tmp_u1b; 1877 bool support_remote_wakeup; 1878 u32 nav_upper = WIFI_NAV_UPPER_US; 1879 1880 rtlhal->being_init_adapter = true; 1881 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 1882 (u8 *)(&support_remote_wakeup)); 1883 rtlpriv->intf_ops->disable_aspm(hw); 1884 1885 /*YP wowlan not considered*/ 1886 1887 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR); 1888 if (tmp_u1b != 0 && tmp_u1b != 0xEA) { 1889 rtlhal->mac_func_enable = true; 1890 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1891 "MAC has already power on.\n"); 1892 } else { 1893 rtlhal->mac_func_enable = false; 1894 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1895 } 1896 1897 if (support_remote_wakeup && 1898 rtlhal->wake_from_pnp_sleep && 1899 rtlhal->mac_func_enable) { 1900 if (_rtl8821ae_wowlan_initialize_adapter(hw)) { 1901 rtlhal->being_init_adapter = false; 1902 return 0; 1903 } 1904 } 1905 1906 if (_rtl8821ae_check_pcie_dma_hang(hw)) { 1907 _rtl8821ae_reset_pcie_interface_dma(hw, 1908 rtlhal->mac_func_enable, 1909 false); 1910 rtlhal->mac_func_enable = false; 1911 } 1912 1913 /* Reset MAC/BB/RF status if it is not powered off 1914 * before calling initialize Hw flow to prevent 1915 * from interface and MAC status mismatch. 1916 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */ 1917 if (rtlhal->mac_func_enable) { 1918 _rtl8821ae_poweroff_adapter(hw); 1919 rtlhal->mac_func_enable = false; 1920 } 1921 1922 rtstatus = _rtl8821ae_init_mac(hw); 1923 if (rtstatus != true) { 1924 pr_err("Init MAC failed\n"); 1925 err = 1; 1926 return err; 1927 } 1928 1929 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG); 1930 tmp_u1b &= 0x7F; 1931 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b); 1932 1933 err = rtl8821ae_download_fw(hw, false); 1934 if (err) { 1935 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1936 "Failed to download FW. Init HW without FW now\n"); 1937 err = 1; 1938 rtlhal->fw_ready = false; 1939 return err; 1940 } else { 1941 rtlhal->fw_ready = true; 1942 } 1943 ppsc->fw_current_inpsmode = false; 1944 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE; 1945 rtlhal->fw_clk_change_in_progress = false; 1946 rtlhal->allow_sw_to_change_hwclc = false; 1947 rtlhal->last_hmeboxnum = 0; 1948 1949 /*SIC_Init(Adapter); 1950 if(rtlhal->AMPDUBurstMode) 1951 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/ 1952 1953 rtl8821ae_phy_mac_config(hw); 1954 /* because last function modify RCR, so we update 1955 * rcr var here, or TP will unstable for receive_config 1956 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1957 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1958 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 1959 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1960 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/ 1961 rtl8821ae_phy_bb_config(hw); 1962 1963 rtl8821ae_phy_rf_config(hw); 1964 1965 if (rtlpriv->phy.rf_type == RF_1T1R && 1966 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 1967 _rtl8812ae_bb8812_config_1t(hw); 1968 1969 _rtl8821ae_hw_configure(hw); 1970 1971 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G); 1972 1973 /*set wireless mode*/ 1974 1975 rtlhal->mac_func_enable = true; 1976 1977 rtl_cam_reset_all_entry(hw); 1978 1979 rtl8821ae_enable_hw_security_config(hw); 1980 1981 ppsc->rfpwr_state = ERFON; 1982 1983 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1984 _rtl8821ae_enable_aspm_back_door(hw); 1985 rtlpriv->intf_ops->enable_aspm(hw); 1986 1987 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE && 1988 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5)) 1989 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302); 1990 1991 rtl8821ae_bt_hw_init(hw); 1992 rtlpriv->rtlhal.being_init_adapter = false; 1993 1994 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper); 1995 1996 /* rtl8821ae_dm_check_txpower_tracking(hw); */ 1997 /* rtl8821ae_phy_lc_calibrate(hw); */ 1998 if (support_remote_wakeup) 1999 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0); 2000 2001 /* Release Rx DMA*/ 2002 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2003 if (tmp_u1b & BIT(2)) { 2004 /* Release Rx DMA if needed*/ 2005 tmp_u1b &= ~BIT(2); 2006 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b); 2007 } 2008 2009 /* Release Tx/Rx PCIE DMA if*/ 2010 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0); 2011 2012 rtl8821ae_dm_init(hw); 2013 rtl8821ae_macid_initialize_mediastatus(hw); 2014 2015 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n"); 2016 return err; 2017 } 2018 2019 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw) 2020 { 2021 struct rtl_priv *rtlpriv = rtl_priv(hw); 2022 struct rtl_phy *rtlphy = &rtlpriv->phy; 2023 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2024 enum version_8821ae version = VERSION_UNKNOWN; 2025 u32 value32; 2026 2027 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 2028 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2029 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32); 2030 2031 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 2032 rtlphy->rf_type = RF_2T2R; 2033 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) 2034 rtlphy->rf_type = RF_1T1R; 2035 2036 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2037 "RF_Type is %x!!\n", rtlphy->rf_type); 2038 2039 if (value32 & TRP_VAUX_EN) { 2040 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2041 if (rtlphy->rf_type == RF_2T2R) 2042 version = VERSION_TEST_CHIP_2T2R_8812; 2043 else 2044 version = VERSION_TEST_CHIP_1T1R_8812; 2045 } else 2046 version = VERSION_TEST_CHIP_8821; 2047 } else { 2048 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 2049 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1; 2050 2051 if (rtlphy->rf_type == RF_2T2R) 2052 version = 2053 (enum version_8821ae)(CHIP_8812 2054 | NORMAL_CHIP | 2055 RF_TYPE_2T2R); 2056 else 2057 version = (enum version_8821ae)(CHIP_8812 2058 | NORMAL_CHIP); 2059 2060 version = (enum version_8821ae)(version | (rtl_id << 12)); 2061 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2062 u32 rtl_id = value32 & CHIP_VER_RTL_MASK; 2063 2064 version = (enum version_8821ae)(CHIP_8821 2065 | NORMAL_CHIP | rtl_id); 2066 } 2067 } 2068 2069 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) { 2070 /*WL_HWROF_EN.*/ 2071 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2072 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0); 2073 } 2074 2075 switch (version) { 2076 case VERSION_TEST_CHIP_1T1R_8812: 2077 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2078 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n"); 2079 break; 2080 case VERSION_TEST_CHIP_2T2R_8812: 2081 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2082 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n"); 2083 break; 2084 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812: 2085 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2086 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n"); 2087 break; 2088 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812: 2089 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2090 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n"); 2091 break; 2092 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT: 2093 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2094 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n"); 2095 break; 2096 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT: 2097 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2098 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n"); 2099 break; 2100 case VERSION_TEST_CHIP_8821: 2101 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2102 "Chip Version ID: VERSION_TEST_CHIP_8821\n"); 2103 break; 2104 case VERSION_NORMAL_TSMC_CHIP_8821: 2105 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2106 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n"); 2107 break; 2108 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT: 2109 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2110 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n"); 2111 break; 2112 default: 2113 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2114 "Chip Version ID: Unknown (0x%X)\n", version); 2115 break; 2116 } 2117 2118 return version; 2119 } 2120 2121 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw, 2122 enum nl80211_iftype type) 2123 { 2124 struct rtl_priv *rtlpriv = rtl_priv(hw); 2125 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 2126 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 2127 bt_msr &= 0xfc; 2128 2129 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 2130 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 2131 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 2132 2133 if (type == NL80211_IFTYPE_UNSPECIFIED || 2134 type == NL80211_IFTYPE_STATION) { 2135 _rtl8821ae_stop_tx_beacon(hw); 2136 _rtl8821ae_enable_bcn_sub_func(hw); 2137 } else if (type == NL80211_IFTYPE_ADHOC || 2138 type == NL80211_IFTYPE_AP) { 2139 _rtl8821ae_resume_tx_beacon(hw); 2140 _rtl8821ae_disable_bcn_sub_func(hw); 2141 } else { 2142 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2143 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 2144 type); 2145 } 2146 2147 switch (type) { 2148 case NL80211_IFTYPE_UNSPECIFIED: 2149 bt_msr |= MSR_NOLINK; 2150 ledaction = LED_CTL_LINK; 2151 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2152 "Set Network type to NO LINK!\n"); 2153 break; 2154 case NL80211_IFTYPE_ADHOC: 2155 bt_msr |= MSR_ADHOC; 2156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2157 "Set Network type to Ad Hoc!\n"); 2158 break; 2159 case NL80211_IFTYPE_STATION: 2160 bt_msr |= MSR_INFRA; 2161 ledaction = LED_CTL_LINK; 2162 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2163 "Set Network type to STA!\n"); 2164 break; 2165 case NL80211_IFTYPE_AP: 2166 bt_msr |= MSR_AP; 2167 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 2168 "Set Network type to AP!\n"); 2169 break; 2170 default: 2171 pr_err("Network type %d not support!\n", type); 2172 return 1; 2173 } 2174 2175 rtl_write_byte(rtlpriv, MSR, bt_msr); 2176 rtlpriv->cfg->ops->led_control(hw, ledaction); 2177 if ((bt_msr & MSR_MASK) == MSR_AP) 2178 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 2179 else 2180 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 2181 2182 return 0; 2183 } 2184 2185 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 2186 { 2187 struct rtl_priv *rtlpriv = rtl_priv(hw); 2188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2189 u32 reg_rcr = rtlpci->receive_config; 2190 2191 if (rtlpriv->psc.rfpwr_state != ERFON) 2192 return; 2193 2194 if (check_bssid) { 2195 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 2196 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 2197 (u8 *)(®_rcr)); 2198 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); 2199 } else if (!check_bssid) { 2200 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 2201 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0); 2202 rtlpriv->cfg->ops->set_hw_reg(hw, 2203 HW_VAR_RCR, (u8 *)(®_rcr)); 2204 } 2205 } 2206 2207 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 2208 { 2209 struct rtl_priv *rtlpriv = rtl_priv(hw); 2210 2211 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n"); 2212 2213 if (_rtl8821ae_set_media_status(hw, type)) 2214 return -EOPNOTSUPP; 2215 2216 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 2217 if (type != NL80211_IFTYPE_AP) 2218 rtl8821ae_set_check_bssid(hw, true); 2219 } else { 2220 rtl8821ae_set_check_bssid(hw, false); 2221 } 2222 2223 return 0; 2224 } 2225 2226 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 2227 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci) 2228 { 2229 struct rtl_priv *rtlpriv = rtl_priv(hw); 2230 rtl8821ae_dm_init_edca_turbo(hw); 2231 switch (aci) { 2232 case AC1_BK: 2233 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 2234 break; 2235 case AC0_BE: 2236 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 2237 break; 2238 case AC2_VI: 2239 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 2240 break; 2241 case AC3_VO: 2242 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 2243 break; 2244 default: 2245 WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci); 2246 break; 2247 } 2248 } 2249 2250 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw) 2251 { 2252 struct rtl_priv *rtlpriv = rtl_priv(hw); 2253 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR); 2254 2255 rtl_write_dword(rtlpriv, REG_HISR, tmp); 2256 2257 tmp = rtl_read_dword(rtlpriv, REG_HISRE); 2258 rtl_write_dword(rtlpriv, REG_HISRE, tmp); 2259 2260 tmp = rtl_read_dword(rtlpriv, REG_HSISR); 2261 rtl_write_dword(rtlpriv, REG_HSISR, tmp); 2262 } 2263 2264 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw) 2265 { 2266 struct rtl_priv *rtlpriv = rtl_priv(hw); 2267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2268 2269 if (rtlpci->int_clear) 2270 rtl8821ae_clear_interrupt(hw);/*clear it here first*/ 2271 2272 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 2273 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 2274 rtlpci->irq_enabled = true; 2275 /* there are some C2H CMDs have been sent before 2276 system interrupt is enabled, e.g., C2H, CPWM. 2277 *So we need to clear all C2H events that FW has 2278 notified, otherwise FW won't schedule any commands anymore. 2279 */ 2280 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */ 2281 /*enable system interrupt*/ 2282 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF); 2283 } 2284 2285 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw) 2286 { 2287 struct rtl_priv *rtlpriv = rtl_priv(hw); 2288 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2289 2290 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 2291 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 2292 rtlpci->irq_enabled = false; 2293 /*synchronize_irq(rtlpci->pdev->irq);*/ 2294 } 2295 2296 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw) 2297 { 2298 struct rtl_priv *rtlpriv = rtl_priv(hw); 2299 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2300 u16 cap_hdr; 2301 u8 cap_pointer; 2302 u8 cap_id = 0xff; 2303 u8 pmcs_reg; 2304 u8 cnt = 0; 2305 2306 /* Get the Capability pointer first, 2307 * the Capability Pointer is located at 2308 * offset 0x34 from the Function Header */ 2309 2310 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer); 2311 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2312 "PCI configuration 0x34 = 0x%2x\n", cap_pointer); 2313 2314 do { 2315 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr); 2316 cap_id = cap_hdr & 0xFF; 2317 2318 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2319 "in pci configuration, cap_pointer%x = %x\n", 2320 cap_pointer, cap_id); 2321 2322 if (cap_id == 0x01) { 2323 break; 2324 } else { 2325 /* point to next Capability */ 2326 cap_pointer = (cap_hdr >> 8) & 0xFF; 2327 /* 0: end of pci capability, 0xff: invalid value */ 2328 if (cap_pointer == 0x00 || cap_pointer == 0xff) { 2329 cap_id = 0xff; 2330 break; 2331 } 2332 } 2333 } while (cnt++ < 200); 2334 2335 if (cap_id == 0x01) { 2336 /* Get the PM CSR (Control/Status Register), 2337 * The PME_Status is located at PM Capatibility offset 5, bit 7 2338 */ 2339 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg); 2340 2341 if (pmcs_reg & BIT(7)) { 2342 /* PME event occured, clear the PM_Status by write 1 */ 2343 pmcs_reg = pmcs_reg | BIT(7); 2344 2345 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5, 2346 pmcs_reg); 2347 /* Read it back to check */ 2348 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, 2349 &pmcs_reg); 2350 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2351 "Clear PME status 0x%2x to 0x%2x\n", 2352 cap_pointer + 5, pmcs_reg); 2353 } else { 2354 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2355 "PME status(0x%2x) = 0x%2x\n", 2356 cap_pointer + 5, pmcs_reg); 2357 } 2358 } else { 2359 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING, 2360 "Cannot find PME Capability\n"); 2361 } 2362 } 2363 2364 void rtl8821ae_card_disable(struct ieee80211_hw *hw) 2365 { 2366 struct rtl_priv *rtlpriv = rtl_priv(hw); 2367 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2368 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); 2369 struct rtl_mac *mac = rtl_mac(rtlpriv); 2370 enum nl80211_iftype opmode; 2371 bool support_remote_wakeup; 2372 u8 tmp; 2373 u32 count = 0; 2374 2375 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 2376 (u8 *)(&support_remote_wakeup)); 2377 2378 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2379 2380 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION) 2381 || !rtlhal->enter_pnp_sleep) { 2382 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n"); 2383 mac->link_state = MAC80211_NOLINK; 2384 opmode = NL80211_IFTYPE_UNSPECIFIED; 2385 _rtl8821ae_set_media_status(hw, opmode); 2386 _rtl8821ae_poweroff_adapter(hw); 2387 } else { 2388 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n"); 2389 /* 3 <1> Prepare for configuring wowlan related infomations */ 2390 /* Clear Fw WoWLAN event. */ 2391 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0); 2392 2393 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1) 2394 rtl8821ae_set_fw_related_for_wowlan(hw, true); 2395 #endif 2396 /* Dynamically adjust Tx packet boundary 2397 * for download reserved page packet. 2398 * reserve 30 pages for rsvd page */ 2399 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d)) 2400 rtlhal->re_init_llt_table = true; 2401 2402 /* 3 <2> Set Fw releted H2C cmd. */ 2403 2404 /* Set WoWLAN related security information. */ 2405 rtl8821ae_set_fw_global_info_cmd(hw); 2406 2407 _rtl8821ae_download_rsvd_page(hw, true); 2408 2409 /* Just enable AOAC related functions when we connect to AP. */ 2410 printk("mac->link_state = %d\n", mac->link_state); 2411 if (mac->link_state >= MAC80211_LINKED && 2412 mac->opmode == NL80211_IFTYPE_STATION) { 2413 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 2414 rtl8821ae_set_fw_media_status_rpt_cmd(hw, 2415 RT_MEDIA_CONNECT); 2416 2417 rtl8821ae_set_fw_wowlan_mode(hw, true); 2418 /* Enable Fw Keep alive mechanism. */ 2419 rtl8821ae_set_fw_keep_alive_cmd(hw, true); 2420 2421 /* Enable disconnect decision control. */ 2422 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true); 2423 } 2424 2425 /* 3 <3> Hw Configutations */ 2426 2427 /* Wait untill Rx DMA Finished before host sleep. 2428 * FW Pause Rx DMA may happens when received packet doing dma. 2429 */ 2430 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2)); 2431 2432 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2433 count = 0; 2434 while (!(tmp & BIT(1)) && (count++ < 100)) { 2435 udelay(10); 2436 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 2437 } 2438 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2439 "Wait Rx DMA Finished before host sleep. count=%d\n", 2440 count); 2441 2442 /* reset trx ring */ 2443 rtlpriv->intf_ops->reset_trx_ring(hw); 2444 2445 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0); 2446 2447 _rtl8821ae_clear_pci_pme_status(hw); 2448 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 2449 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3)); 2450 /* prevent 8051 to be reset by PERST */ 2451 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20); 2452 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60); 2453 } 2454 2455 if (rtlpriv->rtlhal.driver_is_goingto_unload || 2456 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 2457 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 2458 /* For wowlan+LPS+32k. */ 2459 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) { 2460 /* Set the WoWLAN related function control enable. 2461 * It should be the last H2C cmd in the WoWLAN flow. */ 2462 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1); 2463 2464 /* Stop Pcie Interface Tx DMA. */ 2465 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 2466 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n"); 2467 2468 /* Wait for TxDMA idle. */ 2469 count = 0; 2470 do { 2471 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG); 2472 udelay(10); 2473 count++; 2474 } while ((tmp != 0) && (count < 100)); 2475 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2476 "Wait Tx DMA Finished before host sleep. count=%d\n", 2477 count); 2478 2479 if (rtlhal->hw_rof_enable) { 2480 printk("hw_rof_enable\n"); 2481 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3); 2482 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1)); 2483 } 2484 } 2485 /* after power off we should do iqk again */ 2486 rtlpriv->phy.iqk_initialized = false; 2487 } 2488 2489 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw, 2490 u32 *p_inta, u32 *p_intb) 2491 { 2492 struct rtl_priv *rtlpriv = rtl_priv(hw); 2493 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2494 2495 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 2496 rtl_write_dword(rtlpriv, ISR, *p_inta); 2497 2498 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 2499 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb); 2500 } 2501 2502 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw) 2503 { 2504 struct rtl_priv *rtlpriv = rtl_priv(hw); 2505 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2506 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2507 u16 bcn_interval, atim_window; 2508 2509 bcn_interval = mac->beacon_interval; 2510 atim_window = 2; /*FIX MERGE */ 2511 rtl8821ae_disable_interrupt(hw); 2512 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 2513 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2514 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 2515 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 2516 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 2517 rtl_write_byte(rtlpriv, 0x606, 0x30); 2518 rtlpci->reg_bcn_ctrl_val |= BIT(3); 2519 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 2520 rtl8821ae_enable_interrupt(hw); 2521 } 2522 2523 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw) 2524 { 2525 struct rtl_priv *rtlpriv = rtl_priv(hw); 2526 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2527 u16 bcn_interval = mac->beacon_interval; 2528 2529 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 2530 "beacon_interval:%d\n", bcn_interval); 2531 rtl8821ae_disable_interrupt(hw); 2532 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 2533 rtl8821ae_enable_interrupt(hw); 2534 } 2535 2536 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw, 2537 u32 add_msr, u32 rm_msr) 2538 { 2539 struct rtl_priv *rtlpriv = rtl_priv(hw); 2540 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2541 2542 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 2543 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 2544 2545 if (add_msr) 2546 rtlpci->irq_mask[0] |= add_msr; 2547 if (rm_msr) 2548 rtlpci->irq_mask[0] &= (~rm_msr); 2549 rtl8821ae_disable_interrupt(hw); 2550 rtl8821ae_enable_interrupt(hw); 2551 } 2552 2553 static u8 _rtl8821ae_get_chnl_group(u8 chnl) 2554 { 2555 u8 group = 0; 2556 2557 if (chnl <= 14) { 2558 if (1 <= chnl && chnl <= 2) 2559 group = 0; 2560 else if (3 <= chnl && chnl <= 5) 2561 group = 1; 2562 else if (6 <= chnl && chnl <= 8) 2563 group = 2; 2564 else if (9 <= chnl && chnl <= 11) 2565 group = 3; 2566 else /*if (12 <= chnl && chnl <= 14)*/ 2567 group = 4; 2568 } else { 2569 if (36 <= chnl && chnl <= 42) 2570 group = 0; 2571 else if (44 <= chnl && chnl <= 48) 2572 group = 1; 2573 else if (50 <= chnl && chnl <= 58) 2574 group = 2; 2575 else if (60 <= chnl && chnl <= 64) 2576 group = 3; 2577 else if (100 <= chnl && chnl <= 106) 2578 group = 4; 2579 else if (108 <= chnl && chnl <= 114) 2580 group = 5; 2581 else if (116 <= chnl && chnl <= 122) 2582 group = 6; 2583 else if (124 <= chnl && chnl <= 130) 2584 group = 7; 2585 else if (132 <= chnl && chnl <= 138) 2586 group = 8; 2587 else if (140 <= chnl && chnl <= 144) 2588 group = 9; 2589 else if (149 <= chnl && chnl <= 155) 2590 group = 10; 2591 else if (157 <= chnl && chnl <= 161) 2592 group = 11; 2593 else if (165 <= chnl && chnl <= 171) 2594 group = 12; 2595 else if (173 <= chnl && chnl <= 177) 2596 group = 13; 2597 else 2598 WARN_ONCE(true, 2599 "rtl8821ae: 5G, Channel %d in Group not found\n", 2600 chnl); 2601 } 2602 return group; 2603 } 2604 2605 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw, 2606 struct txpower_info_2g *pwrinfo24g, 2607 struct txpower_info_5g *pwrinfo5g, 2608 bool autoload_fail, 2609 u8 *hwinfo) 2610 { 2611 struct rtl_priv *rtlpriv = rtl_priv(hw); 2612 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0; 2613 2614 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2615 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n", 2616 (eeAddr+1), hwinfo[eeAddr+1]); 2617 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/ 2618 autoload_fail = true; 2619 2620 if (autoload_fail) { 2621 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2622 "auto load fail : Use Default value!\n"); 2623 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2624 /*2.4G default value*/ 2625 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2626 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D; 2627 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D; 2628 } 2629 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2630 if (TxCount == 0) { 2631 pwrinfo24g->bw20_diff[rfPath][0] = 0x02; 2632 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04; 2633 } else { 2634 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE; 2635 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE; 2636 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE; 2637 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE; 2638 } 2639 } 2640 /*5G default value*/ 2641 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 2642 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A; 2643 2644 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2645 if (TxCount == 0) { 2646 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04; 2647 pwrinfo5g->bw20_diff[rfPath][0] = 0x00; 2648 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE; 2649 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE; 2650 } else { 2651 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE; 2652 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE; 2653 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE; 2654 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE; 2655 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE; 2656 } 2657 } 2658 } 2659 return; 2660 } 2661 2662 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 2663 2664 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2665 /*2.4G default value*/ 2666 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 2667 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++]; 2668 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF) 2669 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D; 2670 } 2671 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 2672 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++]; 2673 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF) 2674 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D; 2675 } 2676 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2677 if (TxCount == 0) { 2678 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0; 2679 /*bit sign number to 8 bit sign number*/ 2680 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2681 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) 2682 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0; 2683 /*bit sign number to 8 bit sign number*/ 2684 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2685 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2686 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2687 2688 pwrinfo24g->cck_diff[rfPath][TxCount] = 0; 2689 eeAddr++; 2690 } else { 2691 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4; 2692 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3)) 2693 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0; 2694 2695 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2696 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) 2697 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0; 2698 2699 eeAddr++; 2700 2701 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2702 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2703 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2704 2705 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2706 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3)) 2707 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0; 2708 2709 eeAddr++; 2710 } 2711 } 2712 2713 /*5G default value*/ 2714 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 2715 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++]; 2716 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF) 2717 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE; 2718 } 2719 2720 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2721 if (TxCount == 0) { 2722 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0; 2723 2724 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4; 2725 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3)) 2726 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0; 2727 2728 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f); 2729 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2730 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2731 2732 eeAddr++; 2733 } else { 2734 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2735 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3)) 2736 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0; 2737 2738 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2739 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3)) 2740 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0; 2741 2742 eeAddr++; 2743 } 2744 } 2745 2746 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4; 2747 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f); 2748 2749 eeAddr++; 2750 2751 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f); 2752 2753 eeAddr++; 2754 2755 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) { 2756 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3)) 2757 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0; 2758 } 2759 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2760 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4; 2761 /* 4bit sign number to 8 bit sign number */ 2762 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3)) 2763 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0; 2764 /* 4bit sign number to 8 bit sign number */ 2765 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f); 2766 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3)) 2767 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0; 2768 2769 eeAddr++; 2770 } 2771 } 2772 } 2773 #if 0 2774 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2775 bool autoload_fail, 2776 u8 *hwinfo) 2777 { 2778 struct rtl_priv *rtlpriv = rtl_priv(hw); 2779 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2780 struct txpower_info_2g pwrinfo24g; 2781 struct txpower_info_5g pwrinfo5g; 2782 u8 rf_path, index; 2783 u8 i; 2784 2785 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2786 &pwrinfo5g, autoload_fail, hwinfo); 2787 2788 for (rf_path = 0; rf_path < 2; rf_path++) { 2789 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2790 index = _rtl8821ae_get_chnl_group(i + 1); 2791 2792 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2793 rtlefuse->txpwrlevel_cck[rf_path][i] = 2794 pwrinfo24g.index_cck_base[rf_path][5]; 2795 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2796 pwrinfo24g.index_bw40_base[rf_path][index]; 2797 } else { 2798 rtlefuse->txpwrlevel_cck[rf_path][i] = 2799 pwrinfo24g.index_cck_base[rf_path][index]; 2800 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2801 pwrinfo24g.index_bw40_base[rf_path][index]; 2802 } 2803 } 2804 2805 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2806 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2807 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2808 pwrinfo5g.index_bw40_base[rf_path][index]; 2809 } 2810 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2811 u8 upper, lower; 2812 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2813 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2814 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2815 2816 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2817 } 2818 for (i = 0; i < MAX_TX_COUNT; i++) { 2819 rtlefuse->txpwr_cckdiff[rf_path][i] = 2820 pwrinfo24g.cck_diff[rf_path][i]; 2821 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2822 pwrinfo24g.ofdm_diff[rf_path][i]; 2823 rtlefuse->txpwr_ht20diff[rf_path][i] = 2824 pwrinfo24g.bw20_diff[rf_path][i]; 2825 rtlefuse->txpwr_ht40diff[rf_path][i] = 2826 pwrinfo24g.bw40_diff[rf_path][i]; 2827 2828 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2829 pwrinfo5g.ofdm_diff[rf_path][i]; 2830 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2831 pwrinfo5g.bw20_diff[rf_path][i]; 2832 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2833 pwrinfo5g.bw40_diff[rf_path][i]; 2834 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2835 pwrinfo5g.bw80_diff[rf_path][i]; 2836 } 2837 } 2838 2839 if (!autoload_fail) { 2840 rtlefuse->eeprom_regulatory = 2841 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/ 2842 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2843 rtlefuse->eeprom_regulatory = 0; 2844 } else { 2845 rtlefuse->eeprom_regulatory = 0; 2846 } 2847 2848 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2849 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2850 } 2851 #endif 2852 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2853 bool autoload_fail, 2854 u8 *hwinfo) 2855 { 2856 struct rtl_priv *rtlpriv = rtl_priv(hw); 2857 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2858 struct txpower_info_2g pwrinfo24g; 2859 struct txpower_info_5g pwrinfo5g; 2860 u8 rf_path, index; 2861 u8 i; 2862 2863 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, 2864 &pwrinfo5g, autoload_fail, hwinfo); 2865 2866 for (rf_path = 0; rf_path < 2; rf_path++) { 2867 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) { 2868 index = _rtl8821ae_get_chnl_group(i + 1); 2869 2870 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2871 rtlefuse->txpwrlevel_cck[rf_path][i] = 2872 pwrinfo24g.index_cck_base[rf_path][5]; 2873 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2874 pwrinfo24g.index_bw40_base[rf_path][index]; 2875 } else { 2876 rtlefuse->txpwrlevel_cck[rf_path][i] = 2877 pwrinfo24g.index_cck_base[rf_path][index]; 2878 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 2879 pwrinfo24g.index_bw40_base[rf_path][index]; 2880 } 2881 } 2882 2883 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2884 index = _rtl8821ae_get_chnl_group(channel5g[i]); 2885 rtlefuse->txpwr_5g_bw40base[rf_path][i] = 2886 pwrinfo5g.index_bw40_base[rf_path][index]; 2887 } 2888 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2889 u8 upper, lower; 2890 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]); 2891 upper = pwrinfo5g.index_bw40_base[rf_path][index]; 2892 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1]; 2893 2894 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2; 2895 } 2896 for (i = 0; i < MAX_TX_COUNT; i++) { 2897 rtlefuse->txpwr_cckdiff[rf_path][i] = 2898 pwrinfo24g.cck_diff[rf_path][i]; 2899 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = 2900 pwrinfo24g.ofdm_diff[rf_path][i]; 2901 rtlefuse->txpwr_ht20diff[rf_path][i] = 2902 pwrinfo24g.bw20_diff[rf_path][i]; 2903 rtlefuse->txpwr_ht40diff[rf_path][i] = 2904 pwrinfo24g.bw40_diff[rf_path][i]; 2905 2906 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = 2907 pwrinfo5g.ofdm_diff[rf_path][i]; 2908 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = 2909 pwrinfo5g.bw20_diff[rf_path][i]; 2910 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = 2911 pwrinfo5g.bw40_diff[rf_path][i]; 2912 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = 2913 pwrinfo5g.bw80_diff[rf_path][i]; 2914 } 2915 } 2916 /*bit0~2*/ 2917 if (!autoload_fail) { 2918 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07; 2919 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF) 2920 rtlefuse->eeprom_regulatory = 0; 2921 } else { 2922 rtlefuse->eeprom_regulatory = 0; 2923 } 2924 2925 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2926 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 2927 } 2928 2929 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 2930 bool autoload_fail) 2931 { 2932 struct rtl_priv *rtlpriv = rtl_priv(hw); 2933 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2934 2935 if (!autoload_fail) { 2936 rtlhal->pa_type_2g = hwinfo[0xBC]; 2937 rtlhal->lna_type_2g = hwinfo[0xBD]; 2938 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 2939 rtlhal->pa_type_2g = 0; 2940 rtlhal->lna_type_2g = 0; 2941 } 2942 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) && 2943 (rtlhal->pa_type_2g & BIT(4))) ? 2944 1 : 0; 2945 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) && 2946 (rtlhal->lna_type_2g & BIT(3))) ? 2947 1 : 0; 2948 2949 rtlhal->pa_type_5g = hwinfo[0xBC]; 2950 rtlhal->lna_type_5g = hwinfo[0xBF]; 2951 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 2952 rtlhal->pa_type_5g = 0; 2953 rtlhal->lna_type_5g = 0; 2954 } 2955 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) && 2956 (rtlhal->pa_type_5g & BIT(0))) ? 2957 1 : 0; 2958 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) && 2959 (rtlhal->lna_type_5g & BIT(3))) ? 2960 1 : 0; 2961 } else { 2962 rtlhal->external_pa_2g = 0; 2963 rtlhal->external_lna_2g = 0; 2964 rtlhal->external_pa_5g = 0; 2965 rtlhal->external_lna_5g = 0; 2966 } 2967 } 2968 2969 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo, 2970 bool autoload_fail) 2971 { 2972 struct rtl_priv *rtlpriv = rtl_priv(hw); 2973 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 2974 2975 u8 ext_type_pa_2g_a = (hwinfo[0xBD] & BIT(2)) >> 2; /* 0xBD[2] */ 2976 u8 ext_type_pa_2g_b = (hwinfo[0xBD] & BIT(6)) >> 6; /* 0xBD[6] */ 2977 u8 ext_type_pa_5g_a = (hwinfo[0xBF] & BIT(2)) >> 2; /* 0xBF[2] */ 2978 u8 ext_type_pa_5g_b = (hwinfo[0xBF] & BIT(6)) >> 6; /* 0xBF[6] */ 2979 /* 0xBD[1:0] */ 2980 u8 ext_type_lna_2g_a = (hwinfo[0xBD] & (BIT(1) | BIT(0))) >> 0; 2981 /* 0xBD[5:4] */ 2982 u8 ext_type_lna_2g_b = (hwinfo[0xBD] & (BIT(5) | BIT(4))) >> 4; 2983 /* 0xBF[1:0] */ 2984 u8 ext_type_lna_5g_a = (hwinfo[0xBF] & (BIT(1) | BIT(0))) >> 0; 2985 /* 0xBF[5:4] */ 2986 u8 ext_type_lna_5g_b = (hwinfo[0xBF] & (BIT(5) | BIT(4))) >> 4; 2987 2988 _rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail); 2989 2990 /* [2.4G] Path A and B are both extPA */ 2991 if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4))) 2992 rtlhal->type_gpa = ext_type_pa_2g_b << 2 | ext_type_pa_2g_a; 2993 2994 /* [5G] Path A and B are both extPA */ 2995 if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0))) 2996 rtlhal->type_apa = ext_type_pa_5g_b << 2 | ext_type_pa_5g_a; 2997 2998 /* [2.4G] Path A and B are both extLNA */ 2999 if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 3000 rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a; 3001 3002 /* [5G] Path A and B are both extLNA */ 3003 if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3))) 3004 rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a; 3005 } 3006 3007 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo, 3008 bool autoload_fail) 3009 { 3010 struct rtl_priv *rtlpriv = rtl_priv(hw); 3011 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3012 3013 if (!autoload_fail) { 3014 rtlhal->pa_type_2g = hwinfo[0xBC]; 3015 rtlhal->lna_type_2g = hwinfo[0xBD]; 3016 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) { 3017 rtlhal->pa_type_2g = 0; 3018 rtlhal->lna_type_2g = 0; 3019 } 3020 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0; 3021 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0; 3022 3023 rtlhal->pa_type_5g = hwinfo[0xBC]; 3024 rtlhal->lna_type_5g = hwinfo[0xBF]; 3025 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) { 3026 rtlhal->pa_type_5g = 0; 3027 rtlhal->lna_type_5g = 0; 3028 } 3029 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0; 3030 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0; 3031 } else { 3032 rtlhal->external_pa_2g = 0; 3033 rtlhal->external_lna_2g = 0; 3034 rtlhal->external_pa_5g = 0; 3035 rtlhal->external_lna_5g = 0; 3036 } 3037 } 3038 3039 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo, 3040 bool autoload_fail) 3041 { 3042 struct rtl_priv *rtlpriv = rtl_priv(hw); 3043 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 3044 3045 if (!autoload_fail) { 3046 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) { 3047 if (rtlhal->external_lna_5g) { 3048 if (rtlhal->external_pa_5g) { 3049 if (rtlhal->external_lna_2g && 3050 rtlhal->external_pa_2g) 3051 rtlhal->rfe_type = 3; 3052 else 3053 rtlhal->rfe_type = 0; 3054 } else { 3055 rtlhal->rfe_type = 2; 3056 } 3057 } else { 3058 rtlhal->rfe_type = 4; 3059 } 3060 } else { 3061 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F; 3062 3063 if (rtlhal->rfe_type == 4 && 3064 (rtlhal->external_pa_5g || 3065 rtlhal->external_pa_2g || 3066 rtlhal->external_lna_5g || 3067 rtlhal->external_lna_2g)) { 3068 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) 3069 rtlhal->rfe_type = 2; 3070 } 3071 } 3072 } else { 3073 rtlhal->rfe_type = 0x04; 3074 } 3075 3076 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3077 "RFE Type: 0x%2x\n", rtlhal->rfe_type); 3078 } 3079 3080 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3081 bool auto_load_fail, u8 *hwinfo) 3082 { 3083 struct rtl_priv *rtlpriv = rtl_priv(hw); 3084 u8 value; 3085 3086 if (!auto_load_fail) { 3087 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION]; 3088 if (((value & 0xe0) >> 5) == 0x1) 3089 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3090 else 3091 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3092 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3093 3094 value = hwinfo[EEPROM_RF_BT_SETTING]; 3095 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3096 } else { 3097 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3098 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A; 3099 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3100 } 3101 /*move BT_InitHalVars() to init_sw_vars*/ 3102 } 3103 3104 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 3105 bool auto_load_fail, u8 *hwinfo) 3106 { 3107 struct rtl_priv *rtlpriv = rtl_priv(hw); 3108 u8 value; 3109 u32 tmpu_32; 3110 3111 if (!auto_load_fail) { 3112 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 3113 if (tmpu_32 & BIT(18)) 3114 rtlpriv->btcoexist.btc_info.btcoexist = 1; 3115 else 3116 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3117 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3118 3119 value = hwinfo[EEPROM_RF_BT_SETTING]; 3120 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1); 3121 } else { 3122 rtlpriv->btcoexist.btc_info.btcoexist = 0; 3123 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A; 3124 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; 3125 } 3126 /*move BT_InitHalVars() to init_sw_vars*/ 3127 } 3128 3129 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test) 3130 { 3131 struct rtl_priv *rtlpriv = rtl_priv(hw); 3132 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3133 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3134 int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID, 3135 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 3136 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 3137 COUNTRY_CODE_WORLD_WIDE_13}; 3138 u8 *hwinfo; 3139 3140 if (b_pseudo_test) { 3141 ;/* need add */ 3142 } 3143 3144 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 3145 if (!hwinfo) 3146 return; 3147 3148 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 3149 goto exit; 3150 3151 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 3152 hwinfo); 3153 3154 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { 3155 _rtl8812ae_read_amplifier_type(hw, hwinfo, 3156 rtlefuse->autoload_failflag); 3157 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw, 3158 rtlefuse->autoload_failflag, hwinfo); 3159 } else { 3160 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag); 3161 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw, 3162 rtlefuse->autoload_failflag, hwinfo); 3163 } 3164 3165 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag); 3166 /*board type*/ 3167 rtlefuse->board_type = ODM_BOARD_DEFAULT; 3168 if (rtlhal->external_lna_2g != 0) 3169 rtlefuse->board_type |= ODM_BOARD_EXT_LNA; 3170 if (rtlhal->external_lna_5g != 0) 3171 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G; 3172 if (rtlhal->external_pa_2g != 0) 3173 rtlefuse->board_type |= ODM_BOARD_EXT_PA; 3174 if (rtlhal->external_pa_5g != 0) 3175 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G; 3176 3177 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 3178 rtlefuse->board_type |= ODM_BOARD_BT; 3179 3180 rtlhal->board_type = rtlefuse->board_type; 3181 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3182 "board_type = 0x%x\n", rtlefuse->board_type); 3183 3184 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 3185 if (rtlefuse->eeprom_channelplan == 0xff) 3186 rtlefuse->eeprom_channelplan = 0x7F; 3187 3188 /* set channel plan from efuse */ 3189 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 3190 3191 /*parse xtal*/ 3192 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE]; 3193 if (rtlefuse->crystalcap == 0xFF) 3194 rtlefuse->crystalcap = 0x20; 3195 3196 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER]; 3197 if ((rtlefuse->eeprom_thermalmeter == 0xff) || 3198 rtlefuse->autoload_failflag) { 3199 rtlefuse->apk_thermalmeterignore = true; 3200 rtlefuse->eeprom_thermalmeter = 0xff; 3201 } 3202 3203 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 3204 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3205 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 3206 3207 if (!rtlefuse->autoload_failflag) { 3208 rtlefuse->antenna_div_cfg = 3209 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3; 3210 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff) 3211 rtlefuse->antenna_div_cfg = 0; 3212 3213 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 && 3214 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1) 3215 rtlefuse->antenna_div_cfg = 0; 3216 3217 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E]; 3218 if (rtlefuse->antenna_div_type == 0xff) 3219 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV; 3220 } else { 3221 rtlefuse->antenna_div_cfg = 0; 3222 rtlefuse->antenna_div_type = 0; 3223 } 3224 3225 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3226 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n", 3227 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type); 3228 3229 rtlpriv->ledctl.led_opendrain = true; 3230 3231 if (rtlhal->oem_id == RT_CID_DEFAULT) { 3232 switch (rtlefuse->eeprom_oemid) { 3233 case RT_CID_DEFAULT: 3234 break; 3235 case EEPROM_CID_TOSHIBA: 3236 rtlhal->oem_id = RT_CID_TOSHIBA; 3237 break; 3238 case EEPROM_CID_CCX: 3239 rtlhal->oem_id = RT_CID_CCX; 3240 break; 3241 case EEPROM_CID_QMI: 3242 rtlhal->oem_id = RT_CID_819X_QMI; 3243 break; 3244 case EEPROM_CID_WHQL: 3245 break; 3246 default: 3247 break; 3248 } 3249 } 3250 exit: 3251 kfree(hwinfo); 3252 } 3253 3254 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw) 3255 { 3256 struct rtl_priv *rtlpriv = rtl_priv(hw); 3257 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3258 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3259 3260 rtlpriv->ledctl.led_opendrain = true; 3261 switch (rtlhal->oem_id) { 3262 case RT_CID_819X_HP: 3263 rtlpriv->ledctl.led_opendrain = true; 3264 break; 3265 case RT_CID_819X_LENOVO: 3266 case RT_CID_DEFAULT: 3267 case RT_CID_TOSHIBA: 3268 case RT_CID_CCX: 3269 case RT_CID_819X_ACER: 3270 case RT_CID_WHQL: 3271 default: 3272 break; 3273 } 3274 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 3275 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 3276 }*/ 3277 3278 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw) 3279 { 3280 struct rtl_priv *rtlpriv = rtl_priv(hw); 3281 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3282 struct rtl_phy *rtlphy = &rtlpriv->phy; 3283 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3284 u8 tmp_u1b; 3285 3286 rtlhal->version = _rtl8821ae_read_chip_version(hw); 3287 if (get_rf_type(rtlphy) == RF_1T1R) 3288 rtlpriv->dm.rfpath_rxenable[0] = true; 3289 else 3290 rtlpriv->dm.rfpath_rxenable[0] = 3291 rtlpriv->dm.rfpath_rxenable[1] = true; 3292 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 3293 rtlhal->version); 3294 3295 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 3296 if (tmp_u1b & BIT(4)) { 3297 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 3298 rtlefuse->epromtype = EEPROM_93C46; 3299 } else { 3300 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 3301 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 3302 } 3303 3304 if (tmp_u1b & BIT(5)) { 3305 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 3306 rtlefuse->autoload_failflag = false; 3307 _rtl8821ae_read_adapter_info(hw, false); 3308 } else { 3309 pr_err("Autoload ERR!!\n"); 3310 } 3311 /*hal_ReadRFType_8812A()*/ 3312 /* _rtl8821ae_hal_customized_behavior(hw); */ 3313 } 3314 3315 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw, 3316 struct ieee80211_sta *sta) 3317 { 3318 struct rtl_priv *rtlpriv = rtl_priv(hw); 3319 struct rtl_phy *rtlphy = &rtlpriv->phy; 3320 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3321 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3322 u32 ratr_value; 3323 u8 ratr_index = 0; 3324 u8 b_nmode = mac->ht_enable; 3325 u8 mimo_ps = IEEE80211_SMPS_OFF; 3326 u16 shortgi_rate; 3327 u32 tmp_ratr_value; 3328 u8 curtxbw_40mhz = mac->bw_40; 3329 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3330 1 : 0; 3331 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3332 1 : 0; 3333 enum wireless_mode wirelessmode = mac->mode; 3334 3335 if (rtlhal->current_bandtype == BAND_ON_5G) 3336 ratr_value = sta->supp_rates[1] << 4; 3337 else 3338 ratr_value = sta->supp_rates[0]; 3339 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3340 ratr_value = 0xfff; 3341 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3342 sta->ht_cap.mcs.rx_mask[0] << 12); 3343 switch (wirelessmode) { 3344 case WIRELESS_MODE_B: 3345 if (ratr_value & 0x0000000c) 3346 ratr_value &= 0x0000000d; 3347 else 3348 ratr_value &= 0x0000000f; 3349 break; 3350 case WIRELESS_MODE_G: 3351 ratr_value &= 0x00000FF5; 3352 break; 3353 case WIRELESS_MODE_N_24G: 3354 case WIRELESS_MODE_N_5G: 3355 b_nmode = 1; 3356 if (mimo_ps == IEEE80211_SMPS_STATIC) { 3357 ratr_value &= 0x0007F005; 3358 } else { 3359 u32 ratr_mask; 3360 3361 if (get_rf_type(rtlphy) == RF_1T2R || 3362 get_rf_type(rtlphy) == RF_1T1R) 3363 ratr_mask = 0x000ff005; 3364 else 3365 ratr_mask = 0x0f0ff005; 3366 3367 ratr_value &= ratr_mask; 3368 } 3369 break; 3370 default: 3371 if (rtlphy->rf_type == RF_1T2R) 3372 ratr_value &= 0x000ff0ff; 3373 else 3374 ratr_value &= 0x0f0ff0ff; 3375 3376 break; 3377 } 3378 3379 if ((rtlpriv->btcoexist.bt_coexistence) && 3380 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 3381 (rtlpriv->btcoexist.bt_cur_state) && 3382 (rtlpriv->btcoexist.bt_ant_isolation) && 3383 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 3384 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 3385 ratr_value &= 0x0fffcfc0; 3386 else 3387 ratr_value &= 0x0FFFFFFF; 3388 3389 if (b_nmode && ((curtxbw_40mhz && 3390 b_curshortgi_40mhz) || (!curtxbw_40mhz && 3391 b_curshortgi_20mhz))) { 3392 ratr_value |= 0x10000000; 3393 tmp_ratr_value = (ratr_value >> 12); 3394 3395 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 3396 if ((1 << shortgi_rate) & tmp_ratr_value) 3397 break; 3398 } 3399 3400 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 3401 (shortgi_rate << 4) | (shortgi_rate); 3402 } 3403 3404 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 3405 3406 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3407 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 3408 } 3409 3410 static u8 _rtl8821ae_mrate_idx_to_arfr_id( 3411 struct ieee80211_hw *hw, u8 rate_index, 3412 enum wireless_mode wirelessmode) 3413 { 3414 struct rtl_priv *rtlpriv = rtl_priv(hw); 3415 struct rtl_phy *rtlphy = &rtlpriv->phy; 3416 u8 ret = 0; 3417 switch (rate_index) { 3418 case RATR_INX_WIRELESS_NGB: 3419 if (rtlphy->rf_type == RF_1T1R) 3420 ret = 1; 3421 else 3422 ret = 0; 3423 ; break; 3424 case RATR_INX_WIRELESS_N: 3425 case RATR_INX_WIRELESS_NG: 3426 if (rtlphy->rf_type == RF_1T1R) 3427 ret = 5; 3428 else 3429 ret = 4; 3430 ; break; 3431 case RATR_INX_WIRELESS_NB: 3432 if (rtlphy->rf_type == RF_1T1R) 3433 ret = 3; 3434 else 3435 ret = 2; 3436 ; break; 3437 case RATR_INX_WIRELESS_GB: 3438 ret = 6; 3439 break; 3440 case RATR_INX_WIRELESS_G: 3441 ret = 7; 3442 break; 3443 case RATR_INX_WIRELESS_B: 3444 ret = 8; 3445 break; 3446 case RATR_INX_WIRELESS_MC: 3447 if ((wirelessmode == WIRELESS_MODE_B) 3448 || (wirelessmode == WIRELESS_MODE_G) 3449 || (wirelessmode == WIRELESS_MODE_N_24G) 3450 || (wirelessmode == WIRELESS_MODE_AC_24G)) 3451 ret = 6; 3452 else 3453 ret = 7; 3454 case RATR_INX_WIRELESS_AC_5N: 3455 if (rtlphy->rf_type == RF_1T1R) 3456 ret = 10; 3457 else 3458 ret = 9; 3459 break; 3460 case RATR_INX_WIRELESS_AC_24N: 3461 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) { 3462 if (rtlphy->rf_type == RF_1T1R) 3463 ret = 10; 3464 else 3465 ret = 9; 3466 } else { 3467 if (rtlphy->rf_type == RF_1T1R) 3468 ret = 11; 3469 else 3470 ret = 12; 3471 } 3472 break; 3473 default: 3474 ret = 0; break; 3475 } 3476 return ret; 3477 } 3478 3479 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate) 3480 { 3481 u8 i, j, tmp_rate; 3482 u32 rate_bitmap = 0; 3483 3484 for (i = j = 0; i < 4; i += 2, j += 10) { 3485 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3; 3486 3487 switch (tmp_rate) { 3488 case 2: 3489 rate_bitmap = rate_bitmap | (0x03ff << j); 3490 break; 3491 case 1: 3492 rate_bitmap = rate_bitmap | (0x01ff << j); 3493 break; 3494 case 0: 3495 rate_bitmap = rate_bitmap | (0x00ff << j); 3496 break; 3497 default: 3498 break; 3499 } 3500 } 3501 3502 return rate_bitmap; 3503 } 3504 3505 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw, 3506 enum wireless_mode wirelessmode, 3507 u32 ratr_bitmap) 3508 { 3509 struct rtl_priv *rtlpriv = rtl_priv(hw); 3510 struct rtl_phy *rtlphy = &rtlpriv->phy; 3511 u32 ret_bitmap = ratr_bitmap; 3512 3513 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 3514 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) 3515 ret_bitmap = ratr_bitmap; 3516 else if (wirelessmode == WIRELESS_MODE_AC_5G 3517 || wirelessmode == WIRELESS_MODE_AC_24G) { 3518 if (rtlphy->rf_type == RF_1T1R) 3519 ret_bitmap = ratr_bitmap & (~BIT21); 3520 else 3521 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21)); 3522 } 3523 3524 return ret_bitmap; 3525 } 3526 3527 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode, 3528 u32 ratr_bitmap) 3529 { 3530 u8 ret = 0; 3531 if (wirelessmode < WIRELESS_MODE_N_24G) 3532 ret = 0; 3533 else if (wirelessmode == WIRELESS_MODE_AC_24G) { 3534 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */ 3535 ret = 3; 3536 else /* Mix, 1SS */ 3537 ret = 2; 3538 } else if (wirelessmode == WIRELESS_MODE_AC_5G) { 3539 ret = 1; 3540 } /* VHT */ 3541 3542 return ret << 4; 3543 } 3544 3545 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw, 3546 u8 mac_id, struct rtl_sta_info *sta_entry, 3547 enum wireless_mode wirelessmode) 3548 { 3549 u8 b_ldpc = 0; 3550 /*not support ldpc, do not open*/ 3551 return b_ldpc << 2; 3552 } 3553 3554 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw, 3555 enum wireless_mode wirelessmode, 3556 u32 ratr_bitmap) 3557 { 3558 struct rtl_priv *rtlpriv = rtl_priv(hw); 3559 struct rtl_phy *rtlphy = &rtlpriv->phy; 3560 u8 rf_type = RF_1T1R; 3561 3562 if (rtlphy->rf_type == RF_1T1R) 3563 rf_type = RF_1T1R; 3564 else if (wirelessmode == WIRELESS_MODE_AC_5G 3565 || wirelessmode == WIRELESS_MODE_AC_24G 3566 || wirelessmode == WIRELESS_MODE_AC_ONLY) { 3567 if (ratr_bitmap & 0xffc00000) 3568 rf_type = RF_2T2R; 3569 } else if (wirelessmode == WIRELESS_MODE_N_5G 3570 || wirelessmode == WIRELESS_MODE_N_24G) { 3571 if (ratr_bitmap & 0xfff00000) 3572 rf_type = RF_2T2R; 3573 } 3574 3575 return rf_type; 3576 } 3577 3578 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 3579 u8 mac_id) 3580 { 3581 bool b_short_gi = false; 3582 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 3583 1 : 0; 3584 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 3585 1 : 0; 3586 u8 b_curshortgi_80mhz = 0; 3587 b_curshortgi_80mhz = (sta->vht_cap.cap & 3588 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0; 3589 3590 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) 3591 b_short_gi = false; 3592 3593 if (b_curshortgi_40mhz || b_curshortgi_80mhz 3594 || b_curshortgi_20mhz) 3595 b_short_gi = true; 3596 3597 return b_short_gi; 3598 } 3599 3600 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw, 3601 struct ieee80211_sta *sta, u8 rssi_level) 3602 { 3603 struct rtl_priv *rtlpriv = rtl_priv(hw); 3604 struct rtl_phy *rtlphy = &rtlpriv->phy; 3605 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3606 struct rtl_sta_info *sta_entry = NULL; 3607 u32 ratr_bitmap; 3608 u8 ratr_index; 3609 enum wireless_mode wirelessmode = 0; 3610 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 3611 ? 1 : 0; 3612 bool b_shortgi = false; 3613 u8 rate_mask[7]; 3614 u8 macid = 0; 3615 u8 mimo_ps = IEEE80211_SMPS_OFF; 3616 u8 rf_type; 3617 3618 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 3619 wirelessmode = sta_entry->wireless_mode; 3620 3621 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3622 "wireless mode = 0x%x\n", wirelessmode); 3623 if (mac->opmode == NL80211_IFTYPE_STATION || 3624 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 3625 curtxbw_40mhz = mac->bw_40; 3626 } else if (mac->opmode == NL80211_IFTYPE_AP || 3627 mac->opmode == NL80211_IFTYPE_ADHOC) 3628 macid = sta->aid + 1; 3629 if (wirelessmode == WIRELESS_MODE_N_5G || 3630 wirelessmode == WIRELESS_MODE_AC_5G || 3631 wirelessmode == WIRELESS_MODE_A) 3632 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4; 3633 else 3634 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ]; 3635 3636 if (mac->opmode == NL80211_IFTYPE_ADHOC) 3637 ratr_bitmap = 0xfff; 3638 3639 if (wirelessmode == WIRELESS_MODE_N_24G 3640 || wirelessmode == WIRELESS_MODE_N_5G) 3641 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 3642 sta->ht_cap.mcs.rx_mask[0] << 12); 3643 else if (wirelessmode == WIRELESS_MODE_AC_24G 3644 || wirelessmode == WIRELESS_MODE_AC_5G 3645 || wirelessmode == WIRELESS_MODE_AC_ONLY) 3646 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht( 3647 sta->vht_cap.vht_mcs.rx_mcs_map) << 12; 3648 3649 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid); 3650 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap); 3651 3652 /*mac id owner*/ 3653 switch (wirelessmode) { 3654 case WIRELESS_MODE_B: 3655 ratr_index = RATR_INX_WIRELESS_B; 3656 if (ratr_bitmap & 0x0000000c) 3657 ratr_bitmap &= 0x0000000d; 3658 else 3659 ratr_bitmap &= 0x0000000f; 3660 break; 3661 case WIRELESS_MODE_G: 3662 ratr_index = RATR_INX_WIRELESS_GB; 3663 3664 if (rssi_level == 1) 3665 ratr_bitmap &= 0x00000f00; 3666 else if (rssi_level == 2) 3667 ratr_bitmap &= 0x00000ff0; 3668 else 3669 ratr_bitmap &= 0x00000ff5; 3670 break; 3671 case WIRELESS_MODE_A: 3672 ratr_index = RATR_INX_WIRELESS_G; 3673 ratr_bitmap &= 0x00000ff0; 3674 break; 3675 case WIRELESS_MODE_N_24G: 3676 case WIRELESS_MODE_N_5G: 3677 if (wirelessmode == WIRELESS_MODE_N_24G) 3678 ratr_index = RATR_INX_WIRELESS_NGB; 3679 else 3680 ratr_index = RATR_INX_WIRELESS_NG; 3681 3682 if (mimo_ps == IEEE80211_SMPS_STATIC 3683 || mimo_ps == IEEE80211_SMPS_DYNAMIC) { 3684 if (rssi_level == 1) 3685 ratr_bitmap &= 0x000f0000; 3686 else if (rssi_level == 2) 3687 ratr_bitmap &= 0x000ff000; 3688 else 3689 ratr_bitmap &= 0x000ff005; 3690 } else { 3691 if (rf_type == RF_1T1R) { 3692 if (curtxbw_40mhz) { 3693 if (rssi_level == 1) 3694 ratr_bitmap &= 0x000f0000; 3695 else if (rssi_level == 2) 3696 ratr_bitmap &= 0x000ff000; 3697 else 3698 ratr_bitmap &= 0x000ff015; 3699 } else { 3700 if (rssi_level == 1) 3701 ratr_bitmap &= 0x000f0000; 3702 else if (rssi_level == 2) 3703 ratr_bitmap &= 0x000ff000; 3704 else 3705 ratr_bitmap &= 0x000ff005; 3706 } 3707 } else { 3708 if (curtxbw_40mhz) { 3709 if (rssi_level == 1) 3710 ratr_bitmap &= 0x0fff0000; 3711 else if (rssi_level == 2) 3712 ratr_bitmap &= 0x0ffff000; 3713 else 3714 ratr_bitmap &= 0x0ffff015; 3715 } else { 3716 if (rssi_level == 1) 3717 ratr_bitmap &= 0x0fff0000; 3718 else if (rssi_level == 2) 3719 ratr_bitmap &= 0x0ffff000; 3720 else 3721 ratr_bitmap &= 0x0ffff005; 3722 } 3723 } 3724 } 3725 break; 3726 3727 case WIRELESS_MODE_AC_24G: 3728 ratr_index = RATR_INX_WIRELESS_AC_24N; 3729 if (rssi_level == 1) 3730 ratr_bitmap &= 0xfc3f0000; 3731 else if (rssi_level == 2) 3732 ratr_bitmap &= 0xfffff000; 3733 else 3734 ratr_bitmap &= 0xffffffff; 3735 break; 3736 3737 case WIRELESS_MODE_AC_5G: 3738 ratr_index = RATR_INX_WIRELESS_AC_5N; 3739 3740 if (rf_type == RF_1T1R) { 3741 if (rssi_level == 1) /*add by Gary for ac-series*/ 3742 ratr_bitmap &= 0x003f8000; 3743 else if (rssi_level == 2) 3744 ratr_bitmap &= 0x003ff000; 3745 else 3746 ratr_bitmap &= 0x003ff010; 3747 } else { 3748 if (rssi_level == 1) 3749 ratr_bitmap &= 0xfe3f8000; 3750 else if (rssi_level == 2) 3751 ratr_bitmap &= 0xfffff000; 3752 else 3753 ratr_bitmap &= 0xfffff010; 3754 } 3755 break; 3756 3757 default: 3758 ratr_index = RATR_INX_WIRELESS_NGB; 3759 3760 if (rf_type == RF_1T2R) 3761 ratr_bitmap &= 0x000ff0ff; 3762 else 3763 ratr_bitmap &= 0x0f8ff0ff; 3764 break; 3765 } 3766 3767 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode); 3768 sta_entry->ratr_index = ratr_index; 3769 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode, 3770 ratr_bitmap); 3771 3772 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD, 3773 "ratr_bitmap :%x\n", ratr_bitmap); 3774 3775 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) | 3776 (ratr_index << 28)); */ 3777 3778 rate_mask[0] = macid; 3779 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 3780 rate_mask[2] = rtlphy->current_chan_bw 3781 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap) 3782 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode); 3783 3784 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 3785 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 3786 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 3787 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 3788 3789 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 3790 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 3791 ratr_index, ratr_bitmap, 3792 rate_mask[0], rate_mask[1], 3793 rate_mask[2], rate_mask[3], 3794 rate_mask[4], rate_mask[5], 3795 rate_mask[6]); 3796 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask); 3797 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0); 3798 } 3799 3800 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw, 3801 struct ieee80211_sta *sta, u8 rssi_level) 3802 { 3803 struct rtl_priv *rtlpriv = rtl_priv(hw); 3804 if (rtlpriv->dm.useramask) 3805 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level); 3806 else 3807 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD, 3808 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/ 3809 rtl8821ae_update_hal_rate_table(hw, sta); 3810 } 3811 3812 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw) 3813 { 3814 struct rtl_priv *rtlpriv = rtl_priv(hw); 3815 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3816 u16 wireless_mode = mac->mode; 3817 u8 sifs_timer, r2t_sifs; 3818 3819 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 3820 (u8 *)&mac->slot_time); 3821 if (wireless_mode == WIRELESS_MODE_G) 3822 sifs_timer = 0x0a; 3823 else 3824 sifs_timer = 0x0e; 3825 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 3826 3827 r2t_sifs = 0xa; 3828 3829 if (wireless_mode == WIRELESS_MODE_AC_5G && 3830 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) && 3831 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) { 3832 if (mac->vendor == PEER_ATH) 3833 r2t_sifs = 0x8; 3834 else 3835 r2t_sifs = 0xa; 3836 } else if (wireless_mode == WIRELESS_MODE_AC_5G) { 3837 r2t_sifs = 0xa; 3838 } 3839 3840 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs); 3841 } 3842 3843 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 3844 { 3845 struct rtl_priv *rtlpriv = rtl_priv(hw); 3846 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3847 struct rtl_phy *rtlphy = &rtlpriv->phy; 3848 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 3849 u8 u1tmp = 0; 3850 bool b_actuallyset = false; 3851 3852 if (rtlpriv->rtlhal.being_init_adapter) 3853 return false; 3854 3855 if (ppsc->swrf_processing) 3856 return false; 3857 3858 spin_lock(&rtlpriv->locks.rf_ps_lock); 3859 if (ppsc->rfchange_inprogress) { 3860 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3861 return false; 3862 } else { 3863 ppsc->rfchange_inprogress = true; 3864 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3865 } 3866 3867 cur_rfstate = ppsc->rfpwr_state; 3868 3869 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 3870 rtl_read_byte(rtlpriv, 3871 REG_GPIO_IO_SEL_2) & ~(BIT(1))); 3872 3873 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 3874 3875 if (rtlphy->polarity_ctl) 3876 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 3877 else 3878 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 3879 3880 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 3881 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3882 "GPIOChangeRF - HW Radio ON, RF ON\n"); 3883 3884 e_rfpowerstate_toset = ERFON; 3885 ppsc->hwradiooff = false; 3886 b_actuallyset = true; 3887 } else if ((!ppsc->hwradiooff) 3888 && (e_rfpowerstate_toset == ERFOFF)) { 3889 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3890 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 3891 3892 e_rfpowerstate_toset = ERFOFF; 3893 ppsc->hwradiooff = true; 3894 b_actuallyset = true; 3895 } 3896 3897 if (b_actuallyset) { 3898 spin_lock(&rtlpriv->locks.rf_ps_lock); 3899 ppsc->rfchange_inprogress = false; 3900 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3901 } else { 3902 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 3903 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3904 3905 spin_lock(&rtlpriv->locks.rf_ps_lock); 3906 ppsc->rfchange_inprogress = false; 3907 spin_unlock(&rtlpriv->locks.rf_ps_lock); 3908 } 3909 3910 *valid = 1; 3911 return !ppsc->hwradiooff; 3912 } 3913 3914 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index, 3915 u8 *p_macaddr, bool is_group, u8 enc_algo, 3916 bool is_wepkey, bool clear_all) 3917 { 3918 struct rtl_priv *rtlpriv = rtl_priv(hw); 3919 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3920 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3921 u8 *macaddr = p_macaddr; 3922 u32 entry_id = 0; 3923 bool is_pairwise = false; 3924 3925 static u8 cam_const_addr[4][6] = { 3926 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 3927 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 3928 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 3929 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 3930 }; 3931 static u8 cam_const_broad[] = { 3932 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 3933 }; 3934 3935 if (clear_all) { 3936 u8 idx = 0; 3937 u8 cam_offset = 0; 3938 u8 clear_number = 5; 3939 3940 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 3941 3942 for (idx = 0; idx < clear_number; idx++) { 3943 rtl_cam_mark_invalid(hw, cam_offset + idx); 3944 rtl_cam_empty_entry(hw, cam_offset + idx); 3945 3946 if (idx < 5) { 3947 memset(rtlpriv->sec.key_buf[idx], 0, 3948 MAX_KEY_LEN); 3949 rtlpriv->sec.key_len[idx] = 0; 3950 } 3951 } 3952 } else { 3953 switch (enc_algo) { 3954 case WEP40_ENCRYPTION: 3955 enc_algo = CAM_WEP40; 3956 break; 3957 case WEP104_ENCRYPTION: 3958 enc_algo = CAM_WEP104; 3959 break; 3960 case TKIP_ENCRYPTION: 3961 enc_algo = CAM_TKIP; 3962 break; 3963 case AESCCMP_ENCRYPTION: 3964 enc_algo = CAM_AES; 3965 break; 3966 default: 3967 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 3968 "switch case %#x not processed\n", enc_algo); 3969 enc_algo = CAM_TKIP; 3970 break; 3971 } 3972 3973 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 3974 macaddr = cam_const_addr[key_index]; 3975 entry_id = key_index; 3976 } else { 3977 if (is_group) { 3978 macaddr = cam_const_broad; 3979 entry_id = key_index; 3980 } else { 3981 if (mac->opmode == NL80211_IFTYPE_AP) { 3982 entry_id = rtl_cam_get_free_entry(hw, p_macaddr); 3983 if (entry_id >= TOTAL_CAM_ENTRY) { 3984 pr_err("an not find free hwsecurity cam entry\n"); 3985 return; 3986 } 3987 } else { 3988 entry_id = CAM_PAIRWISE_KEY_POSITION; 3989 } 3990 3991 key_index = PAIRWISE_KEYIDX; 3992 is_pairwise = true; 3993 } 3994 } 3995 3996 if (rtlpriv->sec.key_len[key_index] == 0) { 3997 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 3998 "delete one entry, entry_id is %d\n", 3999 entry_id); 4000 if (mac->opmode == NL80211_IFTYPE_AP) 4001 rtl_cam_del_entry(hw, p_macaddr); 4002 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 4003 } else { 4004 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 4005 "add one entry\n"); 4006 if (is_pairwise) { 4007 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 4008 "set Pairwise key\n"); 4009 4010 rtl_cam_add_one_entry(hw, macaddr, key_index, 4011 entry_id, enc_algo, 4012 CAM_CONFIG_NO_USEDK, 4013 rtlpriv->sec.key_buf[key_index]); 4014 } else { 4015 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 4016 "set group key\n"); 4017 4018 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 4019 rtl_cam_add_one_entry(hw, 4020 rtlefuse->dev_addr, 4021 PAIRWISE_KEYIDX, 4022 CAM_PAIRWISE_KEY_POSITION, 4023 enc_algo, 4024 CAM_CONFIG_NO_USEDK, 4025 rtlpriv->sec.key_buf 4026 [entry_id]); 4027 } 4028 4029 rtl_cam_add_one_entry(hw, macaddr, key_index, 4030 entry_id, enc_algo, 4031 CAM_CONFIG_NO_USEDK, 4032 rtlpriv->sec.key_buf[entry_id]); 4033 } 4034 } 4035 } 4036 } 4037 4038 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw) 4039 { 4040 struct rtl_priv *rtlpriv = rtl_priv(hw); 4041 4042 /* 0:Low, 1:High, 2:From Efuse. */ 4043 rtlpriv->btcoexist.reg_bt_iso = 2; 4044 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 4045 rtlpriv->btcoexist.reg_bt_sco = 3; 4046 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 4047 rtlpriv->btcoexist.reg_bt_sco = 0; 4048 } 4049 4050 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw) 4051 { 4052 struct rtl_priv *rtlpriv = rtl_priv(hw); 4053 4054 if (rtlpriv->cfg->ops->get_btc_status()) 4055 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 4056 } 4057 4058 void rtl8821ae_suspend(struct ieee80211_hw *hw) 4059 { 4060 } 4061 4062 void rtl8821ae_resume(struct ieee80211_hw *hw) 4063 { 4064 } 4065 4066 /* Turn on AAP (RCR:bit 0) for promicuous mode. */ 4067 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw, 4068 bool allow_all_da, bool write_into_reg) 4069 { 4070 struct rtl_priv *rtlpriv = rtl_priv(hw); 4071 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 4072 4073 if (allow_all_da) /* Set BIT0 */ 4074 rtlpci->receive_config |= RCR_AAP; 4075 else /* Clear BIT0 */ 4076 rtlpci->receive_config &= ~RCR_AAP; 4077 4078 if (write_into_reg) 4079 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 4080 4081 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 4082 "receive_config=0x%08X, write_into_reg=%d\n", 4083 rtlpci->receive_config, write_into_reg); 4084 } 4085 4086 /* WKFMCAMAddAllEntry8812 */ 4087 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw, 4088 struct rtl_wow_pattern *rtl_pattern, 4089 u8 index) 4090 { 4091 struct rtl_priv *rtlpriv = rtl_priv(hw); 4092 u32 cam = 0; 4093 u8 addr = 0; 4094 u16 rxbuf_addr; 4095 u8 tmp, count = 0; 4096 u16 cam_start; 4097 u16 offset; 4098 4099 /* Count the WFCAM entry start offset. */ 4100 4101 /* RX page size = 128 byte */ 4102 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128; 4103 /* We should start from the boundry */ 4104 cam_start = offset * 128; 4105 4106 /* Enable Rx packet buffer access. */ 4107 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT); 4108 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) { 4109 /* Set Rx packet buffer offset. 4110 * RxBufer pointer increases 1, 4111 * we can access 8 bytes in Rx packet buffer. 4112 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE 4113 * RxBufer addr = (CAM start offset + 4114 * per entry offset of a WKFM CAM)/8 4115 * * index: The index of the wake up frame mask 4116 * * WKFMCAM_SIZE: the total size of one WKFM CAM 4117 * * per entry offset of a WKFM CAM: Addr*4 bytes 4118 */ 4119 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3; 4120 /* Set R/W start offset */ 4121 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr); 4122 4123 if (addr == 0) { 4124 cam = BIT(31) | rtl_pattern->crc; 4125 4126 if (rtl_pattern->type == UNICAST_PATTERN) 4127 cam |= BIT(24); 4128 else if (rtl_pattern->type == MULTICAST_PATTERN) 4129 cam |= BIT(25); 4130 else if (rtl_pattern->type == BROADCAST_PATTERN) 4131 cam |= BIT(26); 4132 4133 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4134 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4135 "WRITE entry[%d] 0x%x: %x\n", addr, 4136 REG_PKTBUF_DBG_DATA_L, cam); 4137 4138 /* Write to Rx packet buffer. */ 4139 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4140 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */ 4141 cam = rtl_pattern->mask[addr - 2]; 4142 4143 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam); 4144 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4145 "WRITE entry[%d] 0x%x: %x\n", addr, 4146 REG_PKTBUF_DBG_DATA_L, cam); 4147 4148 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01); 4149 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */ 4150 cam = rtl_pattern->mask[addr - 2]; 4151 4152 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam); 4153 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 4154 "WRITE entry[%d] 0x%x: %x\n", addr, 4155 REG_PKTBUF_DBG_DATA_H, cam); 4156 4157 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001); 4158 } 4159 4160 count = 0; 4161 do { 4162 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL); 4163 udelay(2); 4164 count++; 4165 } while (tmp && count < 100); 4166 4167 WARN_ONCE((count >= 100), 4168 "rtl8821ae: Write wake up frame mask FAIL %d value!\n", 4169 tmp); 4170 } 4171 /* Disable Rx packet buffer access. */ 4172 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, 4173 DISABLE_TRXPKT_BUF_ACCESS); 4174 } 4175