1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "dm.h"
15 #include "fw.h"
16 #include "led.h"
17 #include "hw.h"
18 #include "../pwrseqcmd.h"
19 #include "pwrseq.h"
20 #include "../btcoexist/rtl_btc.h"
21 
22 #define LLT_CONFIG	5
23 
24 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
25 {
26 	struct rtl_priv *rtlpriv = rtl_priv(hw);
27 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
28 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
29 	struct sk_buff_head free_list;
30 	unsigned long flags;
31 
32 	skb_queue_head_init(&free_list);
33 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
34 	while (skb_queue_len(&ring->queue)) {
35 		struct rtl_tx_desc *entry = &ring->desc[ring->idx];
36 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
37 
38 		dma_unmap_single(&rtlpci->pdev->dev,
39 				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
40 						true, HW_DESC_TXBUFF_ADDR),
41 				 skb->len, DMA_TO_DEVICE);
42 		__skb_queue_tail(&free_list, skb);
43 		ring->idx = (ring->idx + 1) % ring->entries;
44 	}
45 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
46 
47 	__skb_queue_purge(&free_list);
48 }
49 
50 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
51 					u8 set_bits, u8 clear_bits)
52 {
53 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
54 	struct rtl_priv *rtlpriv = rtl_priv(hw);
55 
56 	rtlpci->reg_bcn_ctrl_val |= set_bits;
57 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
58 
59 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
60 }
61 
62 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
63 {
64 	struct rtl_priv *rtlpriv = rtl_priv(hw);
65 	u8 tmp1byte;
66 
67 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
68 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
69 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
70 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
71 	tmp1byte &= ~(BIT(0));
72 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
73 }
74 
75 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
76 {
77 	struct rtl_priv *rtlpriv = rtl_priv(hw);
78 	u8 tmp1byte;
79 
80 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
81 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
82 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
83 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
84 	tmp1byte |= BIT(0);
85 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
86 }
87 
88 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
89 {
90 	_rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
91 }
92 
93 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
94 {
95 	_rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
96 }
97 
98 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
99 				       u8 rpwm_val, bool b_need_turn_off_ckk)
100 {
101 	struct rtl_priv *rtlpriv = rtl_priv(hw);
102 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
103 	bool b_support_remote_wake_up;
104 	u32 count = 0, isr_regaddr, content;
105 	bool b_schedule_timer = b_need_turn_off_ckk;
106 
107 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
108 					(u8 *)(&b_support_remote_wake_up));
109 
110 	if (!rtlhal->fw_ready)
111 		return;
112 	if (!rtlpriv->psc.fw_current_inpsmode)
113 		return;
114 
115 	while (1) {
116 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
117 		if (rtlhal->fw_clk_change_in_progress) {
118 			while (rtlhal->fw_clk_change_in_progress) {
119 				spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
120 				count++;
121 				udelay(100);
122 				if (count > 1000)
123 					goto change_done;
124 				spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
125 			}
126 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
127 		} else {
128 			rtlhal->fw_clk_change_in_progress = false;
129 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
130 			goto change_done;
131 		}
132 	}
133 change_done:
134 	if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
135 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
136 					(u8 *)(&rpwm_val));
137 		if (FW_PS_IS_ACK(rpwm_val)) {
138 			isr_regaddr = REG_HISR;
139 			content = rtl_read_dword(rtlpriv, isr_regaddr);
140 			while (!(content & IMR_CPWM) && (count < 500)) {
141 				udelay(50);
142 				count++;
143 				content = rtl_read_dword(rtlpriv, isr_regaddr);
144 			}
145 
146 			if (content & IMR_CPWM) {
147 				rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
148 				rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
149 				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
150 					"Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
151 					rtlhal->fw_ps_state);
152 			}
153 		}
154 
155 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
156 		rtlhal->fw_clk_change_in_progress = false;
157 		spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
158 		if (b_schedule_timer)
159 			mod_timer(&rtlpriv->works.fw_clockoff_timer,
160 				  jiffies + MSECS(10));
161 	} else  {
162 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
163 		rtlhal->fw_clk_change_in_progress = false;
164 		spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
165 	}
166 }
167 
168 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
169 					u8 rpwm_val)
170 {
171 	struct rtl_priv *rtlpriv = rtl_priv(hw);
172 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
173 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
174 	struct rtl8192_tx_ring *ring;
175 	enum rf_pwrstate rtstate;
176 	bool b_schedule_timer = false;
177 	u8 queue;
178 
179 	if (!rtlhal->fw_ready)
180 		return;
181 	if (!rtlpriv->psc.fw_current_inpsmode)
182 		return;
183 	if (!rtlhal->allow_sw_to_change_hwclc)
184 		return;
185 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
186 	if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
187 		return;
188 
189 	for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
190 		ring = &rtlpci->tx_ring[queue];
191 		if (skb_queue_len(&ring->queue)) {
192 			b_schedule_timer = true;
193 			break;
194 		}
195 	}
196 
197 	if (b_schedule_timer) {
198 		mod_timer(&rtlpriv->works.fw_clockoff_timer,
199 			  jiffies + MSECS(10));
200 		return;
201 	}
202 
203 	if (FW_PS_STATE(rtlhal->fw_ps_state) !=
204 		FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
205 		spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
206 		if (!rtlhal->fw_clk_change_in_progress) {
207 			rtlhal->fw_clk_change_in_progress = true;
208 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
209 			rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
210 			rtl_write_word(rtlpriv, REG_HISR, 0x0100);
211 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
212 						      (u8 *)(&rpwm_val));
213 			spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
214 			rtlhal->fw_clk_change_in_progress = false;
215 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
216 		} else {
217 			spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
218 			mod_timer(&rtlpriv->works.fw_clockoff_timer,
219 				  jiffies + MSECS(10));
220 		}
221 	}
222 }
223 
224 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
225 {
226 	u8 rpwm_val = 0;
227 
228 	rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
229 	_rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
230 }
231 
232 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
233 {
234 	struct rtl_priv *rtlpriv = rtl_priv(hw);
235 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
236 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
237 	bool fw_current_inps = false;
238 	u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
239 
240 	if (ppsc->low_power_enable) {
241 		rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
242 		_rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
243 		rtlhal->allow_sw_to_change_hwclc = false;
244 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
245 				(u8 *)(&fw_pwrmode));
246 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
247 				(u8 *)(&fw_current_inps));
248 	} else {
249 		rpwm_val = FW_PS_STATE_ALL_ON_8821AE;	/* RF on */
250 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
251 				(u8 *)(&rpwm_val));
252 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
253 				(u8 *)(&fw_pwrmode));
254 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
255 				(u8 *)(&fw_current_inps));
256 	}
257 }
258 
259 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
260 {
261 	struct rtl_priv *rtlpriv = rtl_priv(hw);
262 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
263 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
264 	bool fw_current_inps = true;
265 	u8 rpwm_val;
266 
267 	if (ppsc->low_power_enable) {
268 		rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE;	/* RF off */
269 		rtlpriv->cfg->ops->set_hw_reg(hw,
270 				HW_VAR_FW_PSMODE_STATUS,
271 				(u8 *)(&fw_current_inps));
272 		rtlpriv->cfg->ops->set_hw_reg(hw,
273 				HW_VAR_H2C_FW_PWRMODE,
274 				(u8 *)(&ppsc->fwctrl_psmode));
275 		rtlhal->allow_sw_to_change_hwclc = true;
276 		_rtl8821ae_set_fw_clock_off(hw, rpwm_val);
277 	} else {
278 		rpwm_val = FW_PS_STATE_RF_OFF_8821AE;	/* RF off */
279 		rtlpriv->cfg->ops->set_hw_reg(hw,
280 				HW_VAR_FW_PSMODE_STATUS,
281 				(u8 *)(&fw_current_inps));
282 		rtlpriv->cfg->ops->set_hw_reg(hw,
283 				HW_VAR_H2C_FW_PWRMODE,
284 				(u8 *)(&ppsc->fwctrl_psmode));
285 		rtlpriv->cfg->ops->set_hw_reg(hw,
286 				HW_VAR_SET_RPWM,
287 				(u8 *)(&rpwm_val));
288 	}
289 }
290 
291 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
292 					  bool dl_whole_packets)
293 {
294 	struct rtl_priv *rtlpriv = rtl_priv(hw);
295 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
296 	u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
297 	u8 count = 0, dlbcn_count = 0;
298 	bool send_beacon = false;
299 
300 	tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
301 	rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
302 
303 	_rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
304 	_rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
305 
306 	tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
307 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
308 		       tmp_reg422 & (~BIT(6)));
309 	if (tmp_reg422 & BIT(6))
310 		send_beacon = true;
311 
312 	do {
313 		bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
314 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
315 			       (bcnvalid_reg | BIT(0)));
316 		_rtl8821ae_return_beacon_queue_skb(hw);
317 
318 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
319 			rtl8812ae_set_fw_rsvdpagepkt(hw, false,
320 						     dl_whole_packets);
321 		else
322 			rtl8821ae_set_fw_rsvdpagepkt(hw, false,
323 						     dl_whole_packets);
324 
325 		bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
326 		count = 0;
327 		while (!(bcnvalid_reg & BIT(0)) && count < 20) {
328 			count++;
329 			udelay(10);
330 			bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
331 		}
332 		dlbcn_count++;
333 	} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
334 
335 	if (!(bcnvalid_reg & BIT(0)))
336 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
337 			"Download RSVD page failed!\n");
338 	if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
339 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
340 		_rtl8821ae_return_beacon_queue_skb(hw);
341 		if (send_beacon) {
342 			dlbcn_count = 0;
343 			do {
344 				rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
345 					       bcnvalid_reg | BIT(0));
346 
347 				_rtl8821ae_return_beacon_queue_skb(hw);
348 
349 				if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
350 					rtl8812ae_set_fw_rsvdpagepkt(hw, true,
351 								     false);
352 				else
353 					rtl8821ae_set_fw_rsvdpagepkt(hw, true,
354 								     false);
355 
356 				/* check rsvd page download OK. */
357 				bcnvalid_reg = rtl_read_byte(rtlpriv,
358 							     REG_TDECTRL + 2);
359 				count = 0;
360 				while (!(bcnvalid_reg & BIT(0)) && count < 20) {
361 					count++;
362 					udelay(10);
363 					bcnvalid_reg =
364 					  rtl_read_byte(rtlpriv,
365 							REG_TDECTRL + 2);
366 				}
367 				dlbcn_count++;
368 			} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
369 
370 			if (!(bcnvalid_reg & BIT(0)))
371 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
372 					"2 Download RSVD page failed!\n");
373 		}
374 	}
375 
376 	if (bcnvalid_reg & BIT(0))
377 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
378 
379 	_rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
380 	_rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
381 
382 	if (send_beacon)
383 		rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
384 
385 	if (!rtlhal->enter_pnp_sleep) {
386 		tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
387 		rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
388 	}
389 }
390 
391 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
392 {
393 	struct rtl_priv *rtlpriv = rtl_priv(hw);
394 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
395 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
396 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
397 
398 	switch (variable) {
399 	case HW_VAR_ETHER_ADDR:
400 		*((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
401 		*((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
402 		break;
403 	case HW_VAR_BSSID:
404 		*((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
405 		*((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
406 		break;
407 	case HW_VAR_MEDIA_STATUS:
408 		val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
409 		break;
410 	case HW_VAR_SLOT_TIME:
411 		*((u8 *)(val)) = mac->slot_time;
412 		break;
413 	case HW_VAR_BEACON_INTERVAL:
414 		*((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
415 		break;
416 	case HW_VAR_ATIM_WINDOW:
417 		*((u16 *)(val)) =  rtl_read_word(rtlpriv, REG_ATIMWND);
418 		break;
419 	case HW_VAR_RCR:
420 		*((u32 *)(val)) = rtlpci->receive_config;
421 		break;
422 	case HW_VAR_RF_STATE:
423 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
424 		break;
425 	case HW_VAR_FWLPS_RF_ON:{
426 		enum rf_pwrstate rfstate;
427 		u32 val_rcr;
428 
429 		rtlpriv->cfg->ops->get_hw_reg(hw,
430 					      HW_VAR_RF_STATE,
431 					      (u8 *)(&rfstate));
432 		if (rfstate == ERFOFF) {
433 			*((bool *)(val)) = true;
434 		} else {
435 			val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
436 			val_rcr &= 0x00070000;
437 			if (val_rcr)
438 				*((bool *)(val)) = false;
439 			else
440 				*((bool *)(val)) = true;
441 		}
442 		break; }
443 	case HW_VAR_FW_PSMODE_STATUS:
444 		*((bool *)(val)) = ppsc->fw_current_inpsmode;
445 		break;
446 	case HW_VAR_CORRECT_TSF:{
447 		u64 tsf;
448 		u32 *ptsf_low = (u32 *)&tsf;
449 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
450 
451 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
452 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
453 
454 		*((u64 *)(val)) = tsf;
455 
456 		break; }
457 	case HAL_DEF_WOWLAN:
458 		if (ppsc->wo_wlan_mode)
459 			*((bool *)(val)) = true;
460 		else
461 			*((bool *)(val)) = false;
462 		break;
463 	default:
464 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
465 			"switch case %#x not processed\n", variable);
466 		break;
467 	}
468 }
469 
470 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
471 {
472 	struct rtl_priv *rtlpriv = rtl_priv(hw);
473 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
474 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
475 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
476 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
477 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
478 	u8 idx;
479 
480 	switch (variable) {
481 	case HW_VAR_ETHER_ADDR:{
482 			for (idx = 0; idx < ETH_ALEN; idx++) {
483 				rtl_write_byte(rtlpriv, (REG_MACID + idx),
484 					       val[idx]);
485 			}
486 			break;
487 		}
488 	case HW_VAR_BASIC_RATE:{
489 			u16 b_rate_cfg = ((u16 *)val)[0];
490 			b_rate_cfg = b_rate_cfg & 0x15f;
491 			rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
492 			break;
493 		}
494 	case HW_VAR_BSSID:{
495 			for (idx = 0; idx < ETH_ALEN; idx++) {
496 				rtl_write_byte(rtlpriv, (REG_BSSID + idx),
497 					       val[idx]);
498 			}
499 			break;
500 		}
501 	case HW_VAR_SIFS:
502 		rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
503 		rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
504 
505 		rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
506 		rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
507 
508 		rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
509 		rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
510 		break;
511 	case HW_VAR_R2T_SIFS:
512 		rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
513 		break;
514 	case HW_VAR_SLOT_TIME:{
515 		u8 e_aci;
516 
517 		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
518 			"HW_VAR_SLOT_TIME %x\n", val[0]);
519 
520 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
521 
522 		for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
523 			rtlpriv->cfg->ops->set_hw_reg(hw,
524 						      HW_VAR_AC_PARAM,
525 						      (u8 *)(&e_aci));
526 		}
527 		break; }
528 	case HW_VAR_ACK_PREAMBLE:{
529 		u8 reg_tmp;
530 		u8 short_preamble = (bool)(*(u8 *)val);
531 
532 		reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
533 		if (short_preamble) {
534 			reg_tmp |= BIT(1);
535 			rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
536 				       reg_tmp);
537 		} else {
538 			reg_tmp &= (~BIT(1));
539 			rtl_write_byte(rtlpriv,
540 				REG_TRXPTCL_CTL + 2,
541 				reg_tmp);
542 		}
543 		break; }
544 	case HW_VAR_WPA_CONFIG:
545 		rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
546 		break;
547 	case HW_VAR_AMPDU_MIN_SPACE:{
548 		u8 min_spacing_to_set;
549 		u8 sec_min_space;
550 
551 		min_spacing_to_set = *((u8 *)val);
552 		if (min_spacing_to_set <= 7) {
553 			sec_min_space = 0;
554 
555 			if (min_spacing_to_set < sec_min_space)
556 				min_spacing_to_set = sec_min_space;
557 
558 			mac->min_space_cfg = ((mac->min_space_cfg &
559 					       0xf8) |
560 					      min_spacing_to_set);
561 
562 			*val = min_spacing_to_set;
563 
564 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
565 				"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
566 				mac->min_space_cfg);
567 
568 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
569 				       mac->min_space_cfg);
570 		}
571 		break; }
572 	case HW_VAR_SHORTGI_DENSITY:{
573 		u8 density_to_set;
574 
575 		density_to_set = *((u8 *)val);
576 		mac->min_space_cfg |= (density_to_set << 3);
577 
578 		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
579 			"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
580 			mac->min_space_cfg);
581 
582 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
583 			       mac->min_space_cfg);
584 
585 		break; }
586 	case HW_VAR_AMPDU_FACTOR:{
587 		u32	ampdu_len =  (*((u8 *)val));
588 
589 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
590 			if (ampdu_len < VHT_AGG_SIZE_128K)
591 				ampdu_len =
592 					(0x2000 << (*((u8 *)val))) - 1;
593 			else
594 				ampdu_len = 0x1ffff;
595 		} else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
596 			if (ampdu_len < HT_AGG_SIZE_64K)
597 				ampdu_len =
598 					(0x2000 << (*((u8 *)val))) - 1;
599 			else
600 				ampdu_len = 0xffff;
601 		}
602 		ampdu_len |= BIT(31);
603 
604 		rtl_write_dword(rtlpriv,
605 			REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
606 		break; }
607 	case HW_VAR_AC_PARAM:{
608 		u8 e_aci = *((u8 *)val);
609 
610 		rtl8821ae_dm_init_edca_turbo(hw);
611 		if (rtlpci->acm_method != EACMWAY2_SW)
612 			rtlpriv->cfg->ops->set_hw_reg(hw,
613 						      HW_VAR_ACM_CTRL,
614 						      (u8 *)(&e_aci));
615 		break; }
616 	case HW_VAR_ACM_CTRL:{
617 		u8 e_aci = *((u8 *)val);
618 		union aci_aifsn *p_aci_aifsn =
619 		    (union aci_aifsn *)(&mac->ac[0].aifs);
620 		u8 acm = p_aci_aifsn->f.acm;
621 		u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
622 
623 		acm_ctrl =
624 		    acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
625 
626 		if (acm) {
627 			switch (e_aci) {
628 			case AC0_BE:
629 				acm_ctrl |= ACMHW_BEQEN;
630 				break;
631 			case AC2_VI:
632 				acm_ctrl |= ACMHW_VIQEN;
633 				break;
634 			case AC3_VO:
635 				acm_ctrl |= ACMHW_VOQEN;
636 				break;
637 			default:
638 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
639 					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
640 					acm);
641 				break;
642 			}
643 		} else {
644 			switch (e_aci) {
645 			case AC0_BE:
646 				acm_ctrl &= (~ACMHW_BEQEN);
647 				break;
648 			case AC2_VI:
649 				acm_ctrl &= (~ACMHW_VIQEN);
650 				break;
651 			case AC3_VO:
652 				acm_ctrl &= (~ACMHW_VOQEN);
653 				break;
654 			default:
655 				rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
656 					"switch case %#x not processed\n",
657 					e_aci);
658 				break;
659 			}
660 		}
661 
662 		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
663 			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
664 			acm_ctrl);
665 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
666 		break; }
667 	case HW_VAR_RCR:
668 		rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
669 		rtlpci->receive_config = ((u32 *)(val))[0];
670 		break;
671 	case HW_VAR_RETRY_LIMIT:{
672 		u8 retry_limit = ((u8 *)(val))[0];
673 
674 		rtl_write_word(rtlpriv, REG_RL,
675 			       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
676 			       retry_limit << RETRY_LIMIT_LONG_SHIFT);
677 		break; }
678 	case HW_VAR_DUAL_TSF_RST:
679 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
680 		break;
681 	case HW_VAR_EFUSE_BYTES:
682 		rtlefuse->efuse_usedbytes = *((u16 *)val);
683 		break;
684 	case HW_VAR_EFUSE_USAGE:
685 		rtlefuse->efuse_usedpercentage = *((u8 *)val);
686 		break;
687 	case HW_VAR_IO_CMD:
688 		rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
689 		break;
690 	case HW_VAR_SET_RPWM:{
691 		u8 rpwm_val;
692 
693 		rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
694 		udelay(1);
695 
696 		if (rpwm_val & BIT(7)) {
697 			rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
698 				       (*(u8 *)val));
699 		} else {
700 			rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
701 				       ((*(u8 *)val) | BIT(7)));
702 		}
703 
704 		break; }
705 	case HW_VAR_H2C_FW_PWRMODE:
706 		rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
707 		break;
708 	case HW_VAR_FW_PSMODE_STATUS:
709 		ppsc->fw_current_inpsmode = *((bool *)val);
710 		break;
711 	case HW_VAR_INIT_RTS_RATE:
712 		break;
713 	case HW_VAR_RESUME_CLK_ON:
714 		_rtl8821ae_set_fw_ps_rf_on(hw);
715 		break;
716 	case HW_VAR_FW_LPS_ACTION:{
717 		bool b_enter_fwlps = *((bool *)val);
718 
719 		if (b_enter_fwlps)
720 			_rtl8821ae_fwlps_enter(hw);
721 		 else
722 			_rtl8821ae_fwlps_leave(hw);
723 		 break; }
724 	case HW_VAR_H2C_FW_JOINBSSRPT:{
725 		u8 mstatus = (*(u8 *)val);
726 
727 		if (mstatus == RT_MEDIA_CONNECT) {
728 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
729 						      NULL);
730 			_rtl8821ae_download_rsvd_page(hw, false);
731 		}
732 		rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
733 
734 		break; }
735 	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
736 		rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
737 		break;
738 	case HW_VAR_AID:{
739 		u16 u2btmp;
740 		u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
741 		u2btmp &= 0xC000;
742 		rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
743 			       mac->assoc_id));
744 		break; }
745 	case HW_VAR_CORRECT_TSF:{
746 		u8 btype_ibss = ((u8 *)(val))[0];
747 
748 		if (btype_ibss)
749 			_rtl8821ae_stop_tx_beacon(hw);
750 
751 		_rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
752 
753 		rtl_write_dword(rtlpriv, REG_TSFTR,
754 				(u32)(mac->tsf & 0xffffffff));
755 		rtl_write_dword(rtlpriv, REG_TSFTR + 4,
756 				(u32)((mac->tsf >> 32) & 0xffffffff));
757 
758 		_rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
759 
760 		if (btype_ibss)
761 			_rtl8821ae_resume_tx_beacon(hw);
762 		break; }
763 	case HW_VAR_NAV_UPPER: {
764 		u32	us_nav_upper = *(u32 *)val;
765 
766 		if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
767 			rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
768 				"The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
769 				us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
770 			break;
771 		}
772 		rtl_write_byte(rtlpriv, REG_NAV_UPPER,
773 			       ((u8)((us_nav_upper +
774 				HAL_92C_NAV_UPPER_UNIT - 1) /
775 				HAL_92C_NAV_UPPER_UNIT)));
776 		break; }
777 	case HW_VAR_KEEP_ALIVE: {
778 		u8 array[2];
779 		array[0] = 0xff;
780 		array[1] = *((u8 *)val);
781 		rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
782 				       array);
783 		break; }
784 	default:
785 		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
786 			"switch case %#x not processed\n", variable);
787 		break;
788 	}
789 }
790 
791 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
792 {
793 	struct rtl_priv *rtlpriv = rtl_priv(hw);
794 	bool status = true;
795 	long count = 0;
796 	u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
797 		    _LLT_OP(_LLT_WRITE_ACCESS);
798 
799 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
800 
801 	do {
802 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
803 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
804 			break;
805 
806 		if (count > POLLING_LLT_THRESHOLD) {
807 			pr_err("Failed to polling write LLT done at address %d!\n",
808 			       address);
809 			status = false;
810 			break;
811 		}
812 	} while (++count);
813 
814 	return status;
815 }
816 
817 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
818 {
819 	struct rtl_priv *rtlpriv = rtl_priv(hw);
820 	unsigned short i;
821 	u8 txpktbuf_bndy;
822 	u32 rqpn;
823 	u8 maxpage;
824 	bool status;
825 
826 	maxpage = 255;
827 	txpktbuf_bndy = 0xF7;
828 	rqpn = 0x80e60808;
829 
830 	rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
831 	rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
832 
833 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
834 
835 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
836 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
837 
838 	rtl_write_byte(rtlpriv, REG_PBP, 0x31);
839 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
840 
841 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
842 		status = _rtl8821ae_llt_write(hw, i, i + 1);
843 		if (!status)
844 			return status;
845 	}
846 
847 	status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
848 	if (!status)
849 		return status;
850 
851 	for (i = txpktbuf_bndy; i < maxpage; i++) {
852 		status = _rtl8821ae_llt_write(hw, i, (i + 1));
853 		if (!status)
854 			return status;
855 	}
856 
857 	status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
858 	if (!status)
859 		return status;
860 
861 	rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
862 
863 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
864 
865 	return true;
866 }
867 
868 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
869 {
870 	struct rtl_priv *rtlpriv = rtl_priv(hw);
871 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
872 	enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
873 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
874 
875 	if (rtlpriv->rtlhal.up_first_time)
876 		return;
877 
878 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
879 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
880 			rtl8812ae_sw_led_on(hw, pin0);
881 		else
882 			rtl8821ae_sw_led_on(hw, pin0);
883 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
884 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
885 			rtl8812ae_sw_led_on(hw, pin0);
886 		else
887 			rtl8821ae_sw_led_on(hw, pin0);
888 	else
889 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
890 			rtl8812ae_sw_led_off(hw, pin0);
891 		else
892 			rtl8821ae_sw_led_off(hw, pin0);
893 }
894 
895 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
896 {
897 	struct rtl_priv *rtlpriv = rtl_priv(hw);
898 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
899 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
900 
901 	u8 bytetmp = 0;
902 	u16 wordtmp = 0;
903 	bool mac_func_enable = rtlhal->mac_func_enable;
904 
905 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
906 
907 	/*Auto Power Down to CHIP-off State*/
908 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
909 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
910 
911 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
912 		/* HW Power on sequence*/
913 		if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
914 					      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
915 					      RTL8812_NIC_ENABLE_FLOW)) {
916 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
917 				"init 8812 MAC Fail as power on failure\n");
918 			return false;
919 		}
920 	} else {
921 		/* HW Power on sequence */
922 		if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
923 					      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
924 					      RTL8821A_NIC_ENABLE_FLOW)){
925 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
926 				"init 8821 MAC Fail as power on failure\n");
927 			return false;
928 		}
929 	}
930 
931 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
932 	rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
933 
934 	bytetmp = rtl_read_byte(rtlpriv, REG_CR);
935 	bytetmp = 0xff;
936 	rtl_write_byte(rtlpriv, REG_CR, bytetmp);
937 	mdelay(2);
938 
939 	bytetmp = 0xff;
940 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
941 	mdelay(2);
942 
943 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
944 		bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
945 		if (bytetmp & BIT(0)) {
946 			bytetmp = rtl_read_byte(rtlpriv, 0x7c);
947 			bytetmp |= BIT(6);
948 			rtl_write_byte(rtlpriv, 0x7c, bytetmp);
949 		}
950 	}
951 
952 	bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
953 	bytetmp &= ~BIT(4);
954 	rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
955 
956 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
957 
958 	if (!mac_func_enable) {
959 		if (!_rtl8821ae_llt_table_init(hw))
960 			return false;
961 	}
962 
963 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
964 	rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
965 
966 	/* Enable FW Beamformer Interrupt */
967 	bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
968 	rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
969 
970 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
971 	wordtmp &= 0xf;
972 	wordtmp |= 0xF5B1;
973 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
974 
975 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
976 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
977 	rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
978 	/*low address*/
979 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
980 			rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
981 	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
982 			rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
983 	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
984 			rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
985 	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
986 			rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
987 	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
988 			rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
989 	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
990 			rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
991 	rtl_write_dword(rtlpriv, REG_HQ_DESA,
992 			rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
993 	rtl_write_dword(rtlpriv, REG_RX_DESA,
994 			rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
995 
996 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
997 
998 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
999 
1000 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1001 
1002 	rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1003 	_rtl8821ae_gen_refresh_led_state(hw);
1004 
1005 	return true;
1006 }
1007 
1008 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1009 {
1010 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1011 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1012 	u32 reg_rrsr;
1013 
1014 	reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1015 
1016 	rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1017 	/* ARFB table 9 for 11ac 5G 2SS */
1018 	rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1019 	/* ARFB table 10 for 11ac 5G 1SS */
1020 	rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1021 	/* ARFB table 11 for 11ac 24G 1SS */
1022 	rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1023 	rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1024 	/* ARFB table 12 for 11ac 24G 1SS */
1025 	rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1026 	rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1027 	/* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1028 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1029 	rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1030 
1031 	/*Set retry limit*/
1032 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
1033 
1034 	/* Set Data / Response auto rate fallack retry count*/
1035 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1036 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1037 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1038 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1039 
1040 	rtlpci->reg_bcn_ctrl_val = 0x1d;
1041 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1042 
1043 	/* TBTT prohibit hold time. Suggested by designer TimChen. */
1044 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1045 
1046 	/* AGGR_BK_TIME Reg51A 0x16 */
1047 	rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1048 
1049 	/*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1050 	rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1051 
1052 	rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1053 	rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1054 	rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1055 }
1056 
1057 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1058 {
1059 	u16 ret = 0;
1060 	u8 tmp = 0, count = 0;
1061 
1062 	rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1063 	tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1064 	count = 0;
1065 	while (tmp && count < 20) {
1066 		udelay(10);
1067 		tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1068 		count++;
1069 	}
1070 	if (0 == tmp)
1071 		ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1072 
1073 	return ret;
1074 }
1075 
1076 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1077 {
1078 	u8 tmp = 0, count = 0;
1079 
1080 	rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1081 	rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1082 	tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1083 	count = 0;
1084 	while (tmp && count < 20) {
1085 		udelay(10);
1086 		tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1087 		count++;
1088 	}
1089 }
1090 
1091 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1092 {
1093 	u16 read_addr = addr & 0xfffc;
1094 	u8 tmp = 0, count = 0, ret = 0;
1095 
1096 	rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1097 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1098 	tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1099 	count = 0;
1100 	while (tmp && count < 20) {
1101 		udelay(10);
1102 		tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1103 		count++;
1104 	}
1105 	if (0 == tmp) {
1106 		read_addr = REG_DBI_RDATA + addr % 4;
1107 		ret = rtl_read_byte(rtlpriv, read_addr);
1108 	}
1109 	return ret;
1110 }
1111 
1112 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1113 {
1114 	u8 tmp = 0, count = 0;
1115 	u16 write_addr, remainder = addr % 4;
1116 
1117 	write_addr = REG_DBI_WDATA + remainder;
1118 	rtl_write_byte(rtlpriv, write_addr, data);
1119 
1120 	write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1121 	rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1122 
1123 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1124 
1125 	tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1126 	count = 0;
1127 	while (tmp && count < 20) {
1128 		udelay(10);
1129 		tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1130 		count++;
1131 	}
1132 }
1133 
1134 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1135 {
1136 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1137 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1138 	u8 tmp;
1139 
1140 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1141 		if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1142 			_rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1143 
1144 		if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1145 			_rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1146 	}
1147 
1148 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1149 	_rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1150 			     ASPM_L1_LATENCY << 3);
1151 
1152 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1153 	_rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1154 
1155 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1156 		tmp  = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1157 		_rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1158 	}
1159 }
1160 
1161 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1162 {
1163 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1164 	u8 sec_reg_value;
1165 	u8 tmp;
1166 
1167 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1168 		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1169 		rtlpriv->sec.pairwise_enc_algorithm,
1170 		rtlpriv->sec.group_enc_algorithm);
1171 
1172 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1173 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1174 			"not open hw encryption\n");
1175 		return;
1176 	}
1177 
1178 	sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1179 
1180 	if (rtlpriv->sec.use_defaultkey) {
1181 		sec_reg_value |= SCR_TXUSEDK;
1182 		sec_reg_value |= SCR_RXUSEDK;
1183 	}
1184 
1185 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1186 
1187 	tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1188 	rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1189 
1190 	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1191 		"The SECR-value %x\n", sec_reg_value);
1192 
1193 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1194 }
1195 
1196 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1197 #define MAC_ID_STATIC_FOR_DEFAULT_PORT				0
1198 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST		1
1199 #define MAC_ID_STATIC_FOR_BT_CLIENT_START				2
1200 #define MAC_ID_STATIC_FOR_BT_CLIENT_END				3
1201 /* ----------------------------------------------------------- */
1202 
1203 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1204 {
1205 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1206 	u8	media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1207 		MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1208 		MAC_ID_STATIC_FOR_BT_CLIENT_END};
1209 
1210 	rtlpriv->cfg->ops->set_hw_reg(hw,
1211 		HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1212 
1213 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1214 		"Initialize MacId media status: from %d to %d\n",
1215 		MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1216 		MAC_ID_STATIC_FOR_BT_CLIENT_END);
1217 }
1218 
1219 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1220 {
1221 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1222 	u8 tmp;
1223 
1224 	/* write reg 0x350 Bit[26]=1. Enable debug port. */
1225 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1226 	if (!(tmp & BIT(2))) {
1227 		rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1228 		mdelay(100);
1229 	}
1230 
1231 	/* read reg 0x350 Bit[25] if 1 : RX hang */
1232 	/* read reg 0x350 Bit[24] if 1 : TX hang */
1233 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1234 	if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1235 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1236 			"CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1237 		return true;
1238 	} else {
1239 		return false;
1240 	}
1241 }
1242 
1243 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1244 					 bool mac_power_on,
1245 					 bool in_watchdog)
1246 {
1247 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1249 	u8 tmp;
1250 	bool release_mac_rx_pause;
1251 	u8 backup_pcie_dma_pause;
1252 
1253 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1254 
1255 	/* 1. Disable register write lock. 0x1c[1] = 0 */
1256 	tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1257 	tmp &= ~(BIT(1));
1258 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1259 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1260 		/* write 0xCC bit[2] = 1'b1 */
1261 		tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1262 		tmp |= BIT(2);
1263 		rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1264 	}
1265 
1266 	/* 2. Check and pause TRX DMA */
1267 	/* write 0x284 bit[18] = 1'b1 */
1268 	/* write 0x301 = 0xFF */
1269 	tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1270 	if (tmp & BIT(2)) {
1271 		/* Already pause before the function for another purpose. */
1272 		release_mac_rx_pause = false;
1273 	} else {
1274 		rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1275 		release_mac_rx_pause = true;
1276 	}
1277 	backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1278 	if (backup_pcie_dma_pause != 0xFF)
1279 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1280 
1281 	if (mac_power_on) {
1282 		/* 3. reset TRX function */
1283 		/* write 0x100 = 0x00 */
1284 		rtl_write_byte(rtlpriv, REG_CR, 0);
1285 	}
1286 
1287 	/* 4. Reset PCIe DMA. 0x3[0] = 0 */
1288 	tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1289 	tmp &= ~(BIT(0));
1290 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1291 
1292 	/* 5. Enable PCIe DMA. 0x3[0] = 1 */
1293 	tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1294 	tmp |= BIT(0);
1295 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1296 
1297 	if (mac_power_on) {
1298 		/* 6. enable TRX function */
1299 		/* write 0x100 = 0xFF */
1300 		rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1301 
1302 		/* We should init LLT & RQPN and
1303 		 * prepare Tx/Rx descrptor address later
1304 		 * because MAC function is reset.*/
1305 	}
1306 
1307 	/* 7. Restore PCIe autoload down bit */
1308 	/* 8812AE does not has the defination. */
1309 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1310 		/* write 0xF8 bit[17] = 1'b1 */
1311 		tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1312 		tmp |= BIT(1);
1313 		rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1314 	}
1315 
1316 	/* In MAC power on state, BB and RF maybe in ON state,
1317 	 * if we release TRx DMA here.
1318 	 * it will cause packets to be started to Tx/Rx,
1319 	 * so we release Tx/Rx DMA later.*/
1320 	if (!mac_power_on/* || in_watchdog*/) {
1321 		/* 8. release TRX DMA */
1322 		/* write 0x284 bit[18] = 1'b0 */
1323 		/* write 0x301 = 0x00 */
1324 		if (release_mac_rx_pause) {
1325 			tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1326 			rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1327 				       tmp & (~BIT(2)));
1328 		}
1329 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1330 			       backup_pcie_dma_pause);
1331 	}
1332 
1333 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1334 		/* 9. lock system register */
1335 		/* write 0xCC bit[2] = 1'b0 */
1336 		tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1337 		tmp &= ~(BIT(2));
1338 		rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1339 	}
1340 	return true;
1341 }
1342 
1343 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1344 {
1345 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1346 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1347 	struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1348 	u8 fw_reason = 0;
1349 
1350 	fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1351 
1352 	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1353 		fw_reason);
1354 
1355 	ppsc->wakeup_reason = 0;
1356 
1357 	rtlhal->last_suspend_sec = ktime_get_real_seconds();
1358 
1359 	switch (fw_reason) {
1360 	case FW_WOW_V2_PTK_UPDATE_EVENT:
1361 		ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1362 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1363 			"It's a WOL PTK Key update event!\n");
1364 		break;
1365 	case FW_WOW_V2_GTK_UPDATE_EVENT:
1366 		ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1367 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1368 			"It's a WOL GTK Key update event!\n");
1369 		break;
1370 	case FW_WOW_V2_DISASSOC_EVENT:
1371 		ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1372 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1373 			"It's a disassociation event!\n");
1374 		break;
1375 	case FW_WOW_V2_DEAUTH_EVENT:
1376 		ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1377 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1378 			"It's a deauth event!\n");
1379 		break;
1380 	case FW_WOW_V2_FW_DISCONNECT_EVENT:
1381 		ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1382 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1383 			"It's a Fw disconnect decision (AP lost) event!\n");
1384 	break;
1385 	case FW_WOW_V2_MAGIC_PKT_EVENT:
1386 		ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1387 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1388 			"It's a magic packet event!\n");
1389 		break;
1390 	case FW_WOW_V2_UNICAST_PKT_EVENT:
1391 		ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1392 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1393 			"It's an unicast packet event!\n");
1394 		break;
1395 	case FW_WOW_V2_PATTERN_PKT_EVENT:
1396 		ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1397 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1398 			"It's a pattern match event!\n");
1399 		break;
1400 	case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1401 		ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1402 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1403 			"It's an RTD3 Ssid match event!\n");
1404 		break;
1405 	case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1406 		ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1407 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1408 			"It's an RealWoW wake packet event!\n");
1409 		break;
1410 	case FW_WOW_V2_REALWOW_V2_ACKLOST:
1411 		ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1412 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1413 			"It's an RealWoW ack lost event!\n");
1414 		break;
1415 	default:
1416 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1417 			"WOL Read 0x1c7 = %02X, Unknown reason!\n",
1418 			fw_reason);
1419 		break;
1420 	}
1421 }
1422 
1423 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1424 {
1425 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1426 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1427 
1428 	/*low address*/
1429 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1430 			rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1431 	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1432 			rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1433 	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1434 			rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1435 	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1436 			rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1437 	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1438 			rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1439 	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1440 			rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1441 	rtl_write_dword(rtlpriv, REG_HQ_DESA,
1442 			rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1443 	rtl_write_dword(rtlpriv, REG_RX_DESA,
1444 			rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1445 }
1446 
1447 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1448 {
1449 	bool status = true;
1450 	u32 i;
1451 	u32 txpktbuf_bndy = boundary;
1452 	u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1453 
1454 	for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1455 		status = _rtl8821ae_llt_write(hw, i , i + 1);
1456 		if (!status)
1457 			return status;
1458 	}
1459 
1460 	status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1461 	if (!status)
1462 		return status;
1463 
1464 	for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1465 		status = _rtl8821ae_llt_write(hw, i, (i + 1));
1466 		if (!status)
1467 			return status;
1468 	}
1469 
1470 	status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1471 				      txpktbuf_bndy);
1472 	if (!status)
1473 		return status;
1474 
1475 	return status;
1476 }
1477 
1478 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1479 			     u16 npq_rqpn_value, u32 rqpn_val)
1480 {
1481 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1482 	u8 tmp;
1483 	bool ret = true;
1484 	u16 count = 0, tmp16;
1485 	bool support_remote_wakeup;
1486 
1487 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1488 				      (u8 *)(&support_remote_wakeup));
1489 
1490 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1491 		"boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1492 		boundary, npq_rqpn_value, rqpn_val);
1493 
1494 	/* stop PCIe DMA
1495 	 * 1. 0x301[7:0] = 0xFE */
1496 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1497 
1498 	/* wait TXFF empty
1499 	 * 2. polling till 0x41A[15:0]=0x07FF */
1500 	tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1501 	while ((tmp16 & 0x07FF) != 0x07FF) {
1502 		udelay(100);
1503 		tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1504 		count++;
1505 		if ((count % 200) == 0) {
1506 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1507 				"Tx queue is not empty for 20ms!\n");
1508 		}
1509 		if (count >= 1000) {
1510 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1511 				"Wait for Tx FIFO empty timeout!\n");
1512 			break;
1513 		}
1514 	}
1515 
1516 	/* TX pause
1517 	 * 3. reg 0x522=0xFF */
1518 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1519 
1520 	/* Wait TX State Machine OK
1521 	 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1522 	count = 0;
1523 	while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1524 		udelay(100);
1525 		count++;
1526 		if (count >= 500) {
1527 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1528 				"Wait for TX State Machine ready timeout !!\n");
1529 			break;
1530 		}
1531 	}
1532 
1533 	/* stop RX DMA path
1534 	 * 5.	0x284[18] = 1
1535 	 * 6.	wait till 0x284[17] == 1
1536 	 * wait RX DMA idle */
1537 	count = 0;
1538 	tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1539 	rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1540 	do {
1541 		tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1542 		udelay(10);
1543 		count++;
1544 	} while (!(tmp & BIT(1)) && count < 100);
1545 
1546 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1547 		"Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1548 		count, tmp);
1549 
1550 	/* reset BB
1551 	 * 7.	0x02 [0] = 0 */
1552 	tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1553 	tmp &= ~(BIT(0));
1554 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1555 
1556 	/* Reset TRX MAC
1557 	 * 8.	 0x100 = 0x00
1558 	 * Delay (1ms) */
1559 	rtl_write_byte(rtlpriv, REG_CR, 0x00);
1560 	udelay(1000);
1561 
1562 	/* Disable MAC Security Engine
1563 	 * 9.	0x100 bit[9]=0 */
1564 	tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1565 	tmp &= ~(BIT(1));
1566 	rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1567 
1568 	/* To avoid DD-Tim Circuit hang
1569 	 * 10.	0x553 bit[5]=1 */
1570 	tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1571 	rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1572 
1573 	/* Enable MAC Security Engine
1574 	 * 11.	0x100 bit[9]=1 */
1575 	tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1576 	rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1577 
1578 	/* Enable TRX MAC
1579 	 * 12.	 0x100 = 0xFF
1580 	 *	Delay (1ms) */
1581 	rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1582 	udelay(1000);
1583 
1584 	/* Enable BB
1585 	 * 13.	0x02 [0] = 1 */
1586 	tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1587 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1588 
1589 	/* beacon setting
1590 	 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1591 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1592 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1593 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1594 
1595 	/* 16.	WMAC_LBK_BF_HD 0x45D[7:0]
1596 	 * WMAC_LBK_BF_HD */
1597 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1598 		       (u8)boundary);
1599 
1600 	rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1601 
1602 	/* init LLT
1603 	 * 17. init LLT */
1604 	if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1605 		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
1606 			"Failed to init LLT table!\n");
1607 		return false;
1608 	}
1609 
1610 	/* reallocate RQPN
1611 	 * 18. reallocate RQPN and init LLT */
1612 	rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1613 	rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1614 
1615 	/* release Tx pause
1616 	 * 19. 0x522=0x00 */
1617 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1618 
1619 	/* enable PCIE DMA
1620 	 * 20. 0x301[7:0] = 0x00
1621 	 * 21. 0x284[18] = 0 */
1622 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1623 	tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1624 	rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1625 
1626 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1627 	return ret;
1628 }
1629 
1630 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1631 {
1632 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1633 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1634 	struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1635 
1636 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1637 	/* Re-download normal Fw. */
1638 	rtl8821ae_set_fw_related_for_wowlan(hw, false);
1639 #endif
1640 
1641 	/* Re-Initialize LLT table. */
1642 	if (rtlhal->re_init_llt_table) {
1643 		u32 rqpn = 0x80e70808;
1644 		u8 rqpn_npq = 0, boundary = 0xF8;
1645 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1646 			rqpn = 0x80e90808;
1647 			boundary = 0xFA;
1648 		}
1649 		if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1650 			rtlhal->re_init_llt_table = false;
1651 	}
1652 
1653 	ppsc->rfpwr_state = ERFON;
1654 }
1655 
1656 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1657 {
1658 	u8 tmp  = 0;
1659 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1660 
1661 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1662 
1663 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1664 	if (!(tmp & (BIT(2) | BIT(3)))) {
1665 		rtl_dbg(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1666 			"0x160(%#x)return!!\n", tmp);
1667 		return;
1668 	}
1669 
1670 	tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1671 	_rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1672 
1673 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1674 	_rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1675 
1676 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1677 }
1678 
1679 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1680 {
1681 	u8 tmp  = 0;
1682 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1683 
1684 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1685 
1686 	/* Check 0x98[10] */
1687 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1688 	if (!(tmp & BIT(2))) {
1689 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1690 			"<---0x99(%#x) return!!\n", tmp);
1691 		return;
1692 	}
1693 
1694 	/* LTR idle latency, 0x90 for 144us */
1695 	rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1696 
1697 	/* LTR active latency, 0x3c for 60us */
1698 	rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1699 
1700 	tmp = rtl_read_byte(rtlpriv, 0x7a4);
1701 	rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1702 
1703 	tmp = rtl_read_byte(rtlpriv, 0x7a4);
1704 	rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1705 	rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1706 
1707 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1708 }
1709 
1710 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1711 {
1712 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1713 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1714 	bool init_finished = true;
1715 	u8 tmp = 0;
1716 
1717 	/* Get Fw wake up reason. */
1718 	_rtl8821ae_get_wakeup_reason(hw);
1719 
1720 	/* Patch Pcie Rx DMA hang after S3/S4 several times.
1721 	 * The root cause has not be found. */
1722 	if (_rtl8821ae_check_pcie_dma_hang(hw))
1723 		_rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1724 
1725 	/* Prepare Tx/Rx Desc Hw address. */
1726 	_rtl8821ae_init_trx_desc_hw_address(hw);
1727 
1728 	/* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1729 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1730 	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1731 
1732 	/* Check wake up event.
1733 	 * We should check wake packet bit before disable wowlan by H2C or
1734 	 * Fw will clear the bit. */
1735 	tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1736 	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1737 		"Read REG_FTISR 0x13f = %#X\n", tmp);
1738 
1739 	/* Set the WoWLAN related function control disable. */
1740 	rtl8821ae_set_fw_wowlan_mode(hw, false);
1741 	rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1742 
1743 	if (rtlhal->hw_rof_enable) {
1744 		tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1745 		if (tmp & BIT(1)) {
1746 			/* Clear GPIO9 ISR */
1747 			rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1748 			init_finished = false;
1749 		} else {
1750 			init_finished = true;
1751 		}
1752 	}
1753 
1754 	if (init_finished) {
1755 		_rtl8821ae_simple_initialize_adapter(hw);
1756 
1757 		/* Release Pcie Interface Tx DMA. */
1758 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1759 		/* Release Pcie RX DMA */
1760 		rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1761 
1762 		tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1763 		rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1764 
1765 		_rtl8821ae_enable_l1off(hw);
1766 		_rtl8821ae_enable_ltr(hw);
1767 	}
1768 
1769 	return init_finished;
1770 }
1771 
1772 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1773 {
1774 	/* BB OFDM RX Path_A */
1775 	rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1776 	/* BB OFDM TX Path_A */
1777 	rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1778 	/* BB CCK R/Rx Path_A */
1779 	rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1780 	/* MCS support */
1781 	rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1782 	/* RF Path_B HSSI OFF */
1783 	rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1784 	/* RF Path_B Power Down */
1785 	rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1786 	/* ADDA Path_B OFF */
1787 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1788 	rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1789 }
1790 
1791 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1792 {
1793 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1794 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1795 	u8 u1b_tmp;
1796 
1797 	rtlhal->mac_func_enable = false;
1798 
1799 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1800 		/* Combo (PCIe + USB) Card and PCIe-MF Card */
1801 		/* 1. Run LPS WL RFOFF flow */
1802 		/* rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1803 		"=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1804 		*/
1805 		rtl_hal_pwrseqcmdparsing(rtlpriv,
1806 			PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1807 			PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1808 	}
1809 	/* 2. 0x1F[7:0] = 0 */
1810 	/* turn off RF */
1811 	/* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1812 	if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1813 		rtlhal->fw_ready) {
1814 		rtl8821ae_firmware_selfreset(hw);
1815 	}
1816 
1817 	/* Reset MCU. Suggested by Filen. */
1818 	u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1819 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1820 
1821 	/* g.	MCUFWDL 0x80[1:0]=0	 */
1822 	/* reset MCU ready status */
1823 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1824 
1825 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1826 		/* HW card disable configuration. */
1827 		rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1828 			PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1829 	} else {
1830 		/* HW card disable configuration. */
1831 		rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1832 			PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1833 	}
1834 
1835 	/* Reset MCU IO Wrapper */
1836 	u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1837 	rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1838 	u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1839 	rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1840 
1841 	/* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1842 	/* lock ISO/CLK/Power control register */
1843 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1844 }
1845 
1846 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1847 {
1848 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1849 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1850 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1851 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1852 	bool rtstatus = true;
1853 	int err;
1854 	u8 tmp_u1b;
1855 	bool support_remote_wakeup;
1856 	u32 nav_upper = WIFI_NAV_UPPER_US;
1857 
1858 	rtlhal->being_init_adapter = true;
1859 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1860 				      (u8 *)(&support_remote_wakeup));
1861 	rtlpriv->intf_ops->disable_aspm(hw);
1862 
1863 	/*YP wowlan not considered*/
1864 
1865 	tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1866 	if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1867 		rtlhal->mac_func_enable = true;
1868 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1869 			"MAC has already power on.\n");
1870 	} else {
1871 		rtlhal->mac_func_enable = false;
1872 		rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1873 	}
1874 
1875 	if (support_remote_wakeup &&
1876 		rtlhal->wake_from_pnp_sleep &&
1877 		rtlhal->mac_func_enable) {
1878 		if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1879 			rtlhal->being_init_adapter = false;
1880 			return 0;
1881 		}
1882 	}
1883 
1884 	if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1885 		_rtl8821ae_reset_pcie_interface_dma(hw,
1886 						    rtlhal->mac_func_enable,
1887 						    false);
1888 		rtlhal->mac_func_enable = false;
1889 	}
1890 
1891 	/* Reset MAC/BB/RF status if it is not powered off
1892 	 * before calling initialize Hw flow to prevent
1893 	 * from interface and MAC status mismatch.
1894 	 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1895 	if (rtlhal->mac_func_enable) {
1896 		_rtl8821ae_poweroff_adapter(hw);
1897 		rtlhal->mac_func_enable = false;
1898 	}
1899 
1900 	rtstatus = _rtl8821ae_init_mac(hw);
1901 	if (!rtstatus) {
1902 		pr_err("Init MAC failed\n");
1903 		err = 1;
1904 		return err;
1905 	}
1906 
1907 	tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1908 	tmp_u1b &= 0x7F;
1909 	rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1910 
1911 	err = rtl8821ae_download_fw(hw, false);
1912 	if (err) {
1913 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1914 			"Failed to download FW. Init HW without FW now\n");
1915 		err = 1;
1916 		rtlhal->fw_ready = false;
1917 		return err;
1918 	} else {
1919 		rtlhal->fw_ready = true;
1920 	}
1921 	ppsc->fw_current_inpsmode = false;
1922 	rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1923 	rtlhal->fw_clk_change_in_progress = false;
1924 	rtlhal->allow_sw_to_change_hwclc = false;
1925 	rtlhal->last_hmeboxnum = 0;
1926 
1927 	/*SIC_Init(Adapter);
1928 	if(rtlhal->AMPDUBurstMode)
1929 		rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812,  0x7F);*/
1930 
1931 	rtl8821ae_phy_mac_config(hw);
1932 	/* because last function modify RCR, so we update
1933 	 * rcr var here, or TP will unstable for receive_config
1934 	 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1935 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1936 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1937 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1938 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1939 	rtl8821ae_phy_bb_config(hw);
1940 
1941 	rtl8821ae_phy_rf_config(hw);
1942 
1943 	if (rtlpriv->phy.rf_type == RF_1T1R &&
1944 		rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1945 		_rtl8812ae_bb8812_config_1t(hw);
1946 
1947 	_rtl8821ae_hw_configure(hw);
1948 
1949 	rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1950 
1951 	/*set wireless mode*/
1952 
1953 	rtlhal->mac_func_enable = true;
1954 
1955 	rtl_cam_reset_all_entry(hw);
1956 
1957 	rtl8821ae_enable_hw_security_config(hw);
1958 
1959 	ppsc->rfpwr_state = ERFON;
1960 
1961 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1962 	_rtl8821ae_enable_aspm_back_door(hw);
1963 	rtlpriv->intf_ops->enable_aspm(hw);
1964 
1965 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1966 	    (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1967 		rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1968 
1969 	rtl8821ae_bt_hw_init(hw);
1970 	rtlpriv->rtlhal.being_init_adapter = false;
1971 
1972 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1973 
1974 	/* rtl8821ae_dm_check_txpower_tracking(hw); */
1975 	/* rtl8821ae_phy_lc_calibrate(hw); */
1976 	if (support_remote_wakeup)
1977 		rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
1978 
1979 	/* Release Rx DMA*/
1980 	tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1981 	if (tmp_u1b & BIT(2)) {
1982 		/* Release Rx DMA if needed*/
1983 		tmp_u1b &= ~BIT(2);
1984 		rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1985 	}
1986 
1987 	/* Release Tx/Rx PCIE DMA if*/
1988 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1989 
1990 	rtl8821ae_dm_init(hw);
1991 	rtl8821ae_macid_initialize_mediastatus(hw);
1992 
1993 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s() <====\n", __func__);
1994 	return err;
1995 }
1996 
1997 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
1998 {
1999 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2000 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2001 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2002 	enum version_8821ae version = VERSION_UNKNOWN;
2003 	u32 value32;
2004 
2005 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2006 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2007 		"ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2008 
2009 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2010 		rtlphy->rf_type = RF_2T2R;
2011 	else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2012 		rtlphy->rf_type = RF_1T1R;
2013 
2014 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2015 		"RF_Type is %x!!\n", rtlphy->rf_type);
2016 
2017 	if (value32 & TRP_VAUX_EN) {
2018 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2019 			if (rtlphy->rf_type == RF_2T2R)
2020 				version = VERSION_TEST_CHIP_2T2R_8812;
2021 			else
2022 				version = VERSION_TEST_CHIP_1T1R_8812;
2023 		} else
2024 			version = VERSION_TEST_CHIP_8821;
2025 	} else {
2026 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2027 			u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2028 
2029 			if (rtlphy->rf_type == RF_2T2R)
2030 				version =
2031 					(enum version_8821ae)(CHIP_8812
2032 					| NORMAL_CHIP |
2033 					RF_TYPE_2T2R);
2034 			else
2035 				version = (enum version_8821ae)(CHIP_8812
2036 					| NORMAL_CHIP);
2037 
2038 			version = (enum version_8821ae)(version | (rtl_id << 12));
2039 		} else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2040 			u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2041 
2042 			version = (enum version_8821ae)(CHIP_8821
2043 				| NORMAL_CHIP | rtl_id);
2044 		}
2045 	}
2046 
2047 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2048 		/*WL_HWROF_EN.*/
2049 		value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2050 		rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2051 	}
2052 
2053 	switch (version) {
2054 	case VERSION_TEST_CHIP_1T1R_8812:
2055 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2056 			"Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2057 		break;
2058 	case VERSION_TEST_CHIP_2T2R_8812:
2059 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2060 			"Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2061 		break;
2062 	case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2063 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2064 			"Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2065 		break;
2066 	case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2067 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2068 			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2069 		break;
2070 	case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2071 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2072 			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2073 		break;
2074 	case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2075 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2076 			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2077 		break;
2078 	case VERSION_TEST_CHIP_8821:
2079 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2080 			"Chip Version ID: VERSION_TEST_CHIP_8821\n");
2081 		break;
2082 	case VERSION_NORMAL_TSMC_CHIP_8821:
2083 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2084 			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2085 		break;
2086 	case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2087 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2088 			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2089 		break;
2090 	default:
2091 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2092 			"Chip Version ID: Unknown (0x%X)\n", version);
2093 		break;
2094 	}
2095 
2096 	return version;
2097 }
2098 
2099 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2100 				     enum nl80211_iftype type)
2101 {
2102 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2103 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2104 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2105 	bt_msr &= 0xfc;
2106 
2107 	rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2108 	rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
2109 		"clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2110 
2111 	if (type == NL80211_IFTYPE_UNSPECIFIED ||
2112 	    type == NL80211_IFTYPE_STATION) {
2113 		_rtl8821ae_stop_tx_beacon(hw);
2114 		_rtl8821ae_enable_bcn_sub_func(hw);
2115 	} else if (type == NL80211_IFTYPE_ADHOC ||
2116 		type == NL80211_IFTYPE_AP) {
2117 		_rtl8821ae_resume_tx_beacon(hw);
2118 		_rtl8821ae_disable_bcn_sub_func(hw);
2119 	} else {
2120 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2121 			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2122 			type);
2123 	}
2124 
2125 	switch (type) {
2126 	case NL80211_IFTYPE_UNSPECIFIED:
2127 		bt_msr |= MSR_NOLINK;
2128 		ledaction = LED_CTL_LINK;
2129 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2130 			"Set Network type to NO LINK!\n");
2131 		break;
2132 	case NL80211_IFTYPE_ADHOC:
2133 		bt_msr |= MSR_ADHOC;
2134 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2135 			"Set Network type to Ad Hoc!\n");
2136 		break;
2137 	case NL80211_IFTYPE_STATION:
2138 		bt_msr |= MSR_INFRA;
2139 		ledaction = LED_CTL_LINK;
2140 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2141 			"Set Network type to STA!\n");
2142 		break;
2143 	case NL80211_IFTYPE_AP:
2144 		bt_msr |= MSR_AP;
2145 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2146 			"Set Network type to AP!\n");
2147 		break;
2148 	default:
2149 		pr_err("Network type %d not support!\n", type);
2150 		return 1;
2151 	}
2152 
2153 	rtl_write_byte(rtlpriv, MSR, bt_msr);
2154 	rtlpriv->cfg->ops->led_control(hw, ledaction);
2155 	if ((bt_msr & MSR_MASK) == MSR_AP)
2156 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2157 	else
2158 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2159 
2160 	return 0;
2161 }
2162 
2163 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2164 {
2165 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2166 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2167 	u32 reg_rcr = rtlpci->receive_config;
2168 
2169 	if (rtlpriv->psc.rfpwr_state != ERFON)
2170 		return;
2171 
2172 	if (check_bssid) {
2173 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2174 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2175 					      (u8 *)(&reg_rcr));
2176 		_rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2177 	} else if (!check_bssid) {
2178 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2179 		_rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2180 		rtlpriv->cfg->ops->set_hw_reg(hw,
2181 			HW_VAR_RCR, (u8 *)(&reg_rcr));
2182 	}
2183 }
2184 
2185 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2186 {
2187 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2188 
2189 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s!\n", __func__);
2190 
2191 	if (_rtl8821ae_set_media_status(hw, type))
2192 		return -EOPNOTSUPP;
2193 
2194 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2195 		if (type != NL80211_IFTYPE_AP)
2196 			rtl8821ae_set_check_bssid(hw, true);
2197 	} else {
2198 		rtl8821ae_set_check_bssid(hw, false);
2199 	}
2200 
2201 	return 0;
2202 }
2203 
2204 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2205 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2206 {
2207 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2208 	rtl8821ae_dm_init_edca_turbo(hw);
2209 	switch (aci) {
2210 	case AC1_BK:
2211 		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2212 		break;
2213 	case AC0_BE:
2214 		/* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2215 		break;
2216 	case AC2_VI:
2217 		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2218 		break;
2219 	case AC3_VO:
2220 		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2221 		break;
2222 	default:
2223 		WARN_ONCE(true, "rtl8821ae: invalid aci: %d !\n", aci);
2224 		break;
2225 	}
2226 }
2227 
2228 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2229 {
2230 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2231 	u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2232 
2233 	rtl_write_dword(rtlpriv, REG_HISR, tmp);
2234 
2235 	tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2236 	rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2237 
2238 	tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2239 	rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2240 }
2241 
2242 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2243 {
2244 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2245 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2246 
2247 	if (rtlpci->int_clear)
2248 		rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2249 
2250 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2251 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2252 	rtlpci->irq_enabled = true;
2253 	/* there are some C2H CMDs have been sent before
2254 	system interrupt is enabled, e.g., C2H, CPWM.
2255 	*So we need to clear all C2H events that FW has
2256 	notified, otherwise FW won't schedule any commands anymore.
2257 	*/
2258 	/* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2259 	/*enable system interrupt*/
2260 	rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2261 }
2262 
2263 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2264 {
2265 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2266 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2267 
2268 	rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2269 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2270 	rtlpci->irq_enabled = false;
2271 	/*synchronize_irq(rtlpci->pdev->irq);*/
2272 }
2273 
2274 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2275 {
2276 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2277 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2278 	u16 cap_hdr;
2279 	u8 cap_pointer;
2280 	u8 cap_id = 0xff;
2281 	u8 pmcs_reg;
2282 	u8 cnt = 0;
2283 
2284 	/* Get the Capability pointer first,
2285 	 * the Capability Pointer is located at
2286 	 * offset 0x34 from the Function Header */
2287 
2288 	pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2289 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2290 		"PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2291 
2292 	do {
2293 		pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2294 		cap_id = cap_hdr & 0xFF;
2295 
2296 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2297 			"in pci configuration, cap_pointer%x = %x\n",
2298 			cap_pointer, cap_id);
2299 
2300 		if (cap_id == 0x01) {
2301 			break;
2302 		} else {
2303 			/* point to next Capability */
2304 			cap_pointer = (cap_hdr >> 8) & 0xFF;
2305 			/* 0: end of pci capability, 0xff: invalid value */
2306 			if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2307 				cap_id = 0xff;
2308 				break;
2309 			}
2310 		}
2311 	} while (cnt++ < 200);
2312 
2313 	if (cap_id == 0x01) {
2314 		/* Get the PM CSR (Control/Status Register),
2315 		 * The PME_Status is located at PM Capatibility offset 5, bit 7
2316 		 */
2317 		pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2318 
2319 		if (pmcs_reg & BIT(7)) {
2320 			/* PME event occured, clear the PM_Status by write 1 */
2321 			pmcs_reg = pmcs_reg | BIT(7);
2322 
2323 			pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2324 					      pmcs_reg);
2325 			/* Read it back to check */
2326 			pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2327 					     &pmcs_reg);
2328 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2329 				"Clear PME status 0x%2x to 0x%2x\n",
2330 				cap_pointer + 5, pmcs_reg);
2331 		} else {
2332 			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2333 				"PME status(0x%2x) = 0x%2x\n",
2334 				cap_pointer + 5, pmcs_reg);
2335 		}
2336 	} else {
2337 		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
2338 			"Cannot find PME Capability\n");
2339 	}
2340 }
2341 
2342 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2343 {
2344 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2345 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2346 	struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2347 	struct rtl_mac *mac = rtl_mac(rtlpriv);
2348 	enum nl80211_iftype opmode;
2349 	bool support_remote_wakeup;
2350 	u8 tmp;
2351 	u32 count = 0;
2352 
2353 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2354 				      (u8 *)(&support_remote_wakeup));
2355 
2356 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2357 
2358 	if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2359 	    || !rtlhal->enter_pnp_sleep) {
2360 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2361 		mac->link_state = MAC80211_NOLINK;
2362 		opmode = NL80211_IFTYPE_UNSPECIFIED;
2363 		_rtl8821ae_set_media_status(hw, opmode);
2364 		_rtl8821ae_poweroff_adapter(hw);
2365 	} else {
2366 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2367 		/* 3 <1> Prepare for configuring wowlan related infomations */
2368 		/* Clear Fw WoWLAN event. */
2369 		rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2370 
2371 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2372 		rtl8821ae_set_fw_related_for_wowlan(hw, true);
2373 #endif
2374 		/* Dynamically adjust Tx packet boundary
2375 		 * for download reserved page packet.
2376 		 * reserve 30 pages for rsvd page */
2377 		if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2378 			rtlhal->re_init_llt_table = true;
2379 
2380 		/* 3 <2> Set Fw releted H2C cmd. */
2381 
2382 		/* Set WoWLAN related security information. */
2383 		rtl8821ae_set_fw_global_info_cmd(hw);
2384 
2385 		_rtl8821ae_download_rsvd_page(hw, true);
2386 
2387 		/* Just enable AOAC related functions when we connect to AP. */
2388 		printk("mac->link_state = %d\n", mac->link_state);
2389 		if (mac->link_state >= MAC80211_LINKED &&
2390 		    mac->opmode == NL80211_IFTYPE_STATION) {
2391 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2392 			rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2393 							      RT_MEDIA_CONNECT);
2394 
2395 			rtl8821ae_set_fw_wowlan_mode(hw, true);
2396 			/* Enable Fw Keep alive mechanism. */
2397 			rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2398 
2399 			/* Enable disconnect decision control. */
2400 			rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2401 		}
2402 
2403 		/* 3 <3> Hw Configutations */
2404 
2405 		/* Wait untill Rx DMA Finished before host sleep.
2406 		 * FW Pause Rx DMA may happens when received packet doing dma.
2407 		 */
2408 		rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2409 
2410 		tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2411 		count = 0;
2412 		while (!(tmp & BIT(1)) && (count++ < 100)) {
2413 			udelay(10);
2414 			tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2415 		}
2416 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2417 			"Wait Rx DMA Finished before host sleep. count=%d\n",
2418 			count);
2419 
2420 		/* reset trx ring */
2421 		rtlpriv->intf_ops->reset_trx_ring(hw);
2422 
2423 		rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2424 
2425 		_rtl8821ae_clear_pci_pme_status(hw);
2426 		tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2427 		rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2428 		/* prevent 8051 to be reset by PERST */
2429 		rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2430 		rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2431 	}
2432 
2433 	if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2434 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2435 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2436 	/* For wowlan+LPS+32k. */
2437 	if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2438 		/* Set the WoWLAN related function control enable.
2439 		 * It should be the last H2C cmd in the WoWLAN flow. */
2440 		rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2441 
2442 		/* Stop Pcie Interface Tx DMA. */
2443 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2444 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2445 
2446 		/* Wait for TxDMA idle. */
2447 		count = 0;
2448 		do {
2449 			tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2450 			udelay(10);
2451 			count++;
2452 		} while ((tmp != 0) && (count < 100));
2453 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2454 			"Wait Tx DMA Finished before host sleep. count=%d\n",
2455 			count);
2456 
2457 		if (rtlhal->hw_rof_enable) {
2458 			printk("hw_rof_enable\n");
2459 			tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2460 			rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2461 		}
2462 	}
2463 	/* after power off we should do iqk again */
2464 	rtlpriv->phy.iqk_initialized = false;
2465 }
2466 
2467 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2468 				    struct rtl_int *intvec)
2469 {
2470 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2471 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2472 
2473 	intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2474 	rtl_write_dword(rtlpriv, ISR, intvec->inta);
2475 
2476 	intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2477 	rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
2478 }
2479 
2480 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2481 {
2482 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2483 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2484 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2485 	u16 bcn_interval, atim_window;
2486 
2487 	bcn_interval = mac->beacon_interval;
2488 	atim_window = 2;	/*FIX MERGE */
2489 	rtl8821ae_disable_interrupt(hw);
2490 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2491 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2492 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2493 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2494 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2495 	rtl_write_byte(rtlpriv, 0x606, 0x30);
2496 	rtlpci->reg_bcn_ctrl_val |= BIT(3);
2497 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2498 	rtl8821ae_enable_interrupt(hw);
2499 }
2500 
2501 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2502 {
2503 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2504 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2505 	u16 bcn_interval = mac->beacon_interval;
2506 
2507 	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
2508 		"beacon_interval:%d\n", bcn_interval);
2509 	rtl8821ae_disable_interrupt(hw);
2510 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2511 	rtl8821ae_enable_interrupt(hw);
2512 }
2513 
2514 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2515 				   u32 add_msr, u32 rm_msr)
2516 {
2517 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2518 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2519 
2520 	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
2521 		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2522 
2523 	if (add_msr)
2524 		rtlpci->irq_mask[0] |= add_msr;
2525 	if (rm_msr)
2526 		rtlpci->irq_mask[0] &= (~rm_msr);
2527 	rtl8821ae_disable_interrupt(hw);
2528 	rtl8821ae_enable_interrupt(hw);
2529 }
2530 
2531 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2532 {
2533 	u8 group = 0;
2534 
2535 	if (chnl <= 14) {
2536 		if (1 <= chnl && chnl <= 2)
2537 			group = 0;
2538 	else if (3 <= chnl && chnl <= 5)
2539 			group = 1;
2540 	else if (6 <= chnl && chnl <= 8)
2541 			group = 2;
2542 	else if (9 <= chnl && chnl <= 11)
2543 			group = 3;
2544 	else /*if (12 <= chnl && chnl <= 14)*/
2545 			group = 4;
2546 	} else {
2547 		if (36 <= chnl && chnl <= 42)
2548 			group = 0;
2549 	else if (44 <= chnl && chnl <= 48)
2550 			group = 1;
2551 	else if (50 <= chnl && chnl <= 58)
2552 			group = 2;
2553 	else if (60 <= chnl && chnl <= 64)
2554 			group = 3;
2555 	else if (100 <= chnl && chnl <= 106)
2556 			group = 4;
2557 	else if (108 <= chnl && chnl <= 114)
2558 			group = 5;
2559 	else if (116 <= chnl && chnl <= 122)
2560 			group = 6;
2561 	else if (124 <= chnl && chnl <= 130)
2562 			group = 7;
2563 	else if (132 <= chnl && chnl <= 138)
2564 			group = 8;
2565 	else if (140 <= chnl && chnl <= 144)
2566 			group = 9;
2567 	else if (149 <= chnl && chnl <= 155)
2568 			group = 10;
2569 	else if (157 <= chnl && chnl <= 161)
2570 			group = 11;
2571 	else if (165 <= chnl && chnl <= 171)
2572 			group = 12;
2573 	else if (173 <= chnl && chnl <= 177)
2574 			group = 13;
2575 	else
2576 		WARN_ONCE(true,
2577 			  "rtl8821ae: 5G, Channel %d in Group not found\n",
2578 			  chnl);
2579 	}
2580 	return group;
2581 }
2582 
2583 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2584 	struct txpower_info_2g *pwrinfo24g,
2585 	struct txpower_info_5g *pwrinfo5g,
2586 	bool autoload_fail,
2587 	u8 *hwinfo)
2588 {
2589 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2590 	u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0;
2591 
2592 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2593 		"hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2594 		(eeaddr + 1), hwinfo[eeaddr + 1]);
2595 	if (hwinfo[eeaddr + 1] == 0xFF)  /*YJ,add,120316*/
2596 		autoload_fail = true;
2597 
2598 	if (autoload_fail) {
2599 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2600 			"auto load fail : Use Default value!\n");
2601 		for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
2602 			/*2.4G default value*/
2603 			for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2604 				pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2605 				pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
2606 			}
2607 			for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2608 				if (txcount == 0) {
2609 					pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
2610 					pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
2611 				} else {
2612 					pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE;
2613 					pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE;
2614 					pwrinfo24g->cck_diff[rfpath][txcount] =	0xFE;
2615 					pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE;
2616 				}
2617 			}
2618 			/*5G default value*/
2619 			for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2620 				pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A;
2621 
2622 			for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2623 				if (txcount == 0) {
2624 					pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
2625 					pwrinfo5g->bw20_diff[rfpath][0] = 0x00;
2626 					pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2627 					pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
2628 				} else {
2629 					pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE;
2630 					pwrinfo5g->bw20_diff[rfpath][0] = 0xFE;
2631 					pwrinfo5g->bw40_diff[rfpath][0] = 0xFE;
2632 					pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2633 					pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
2634 				}
2635 			}
2636 		}
2637 		return;
2638 	}
2639 
2640 	rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2641 
2642 	for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
2643 		/*2.4G default value*/
2644 		for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2645 			pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++];
2646 			if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
2647 				pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2648 		}
2649 		for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2650 			pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2651 			if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
2652 				pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
2653 		}
2654 		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2655 			if (txcount == 0) {
2656 				pwrinfo24g->bw40_diff[rfpath][txcount] = 0;
2657 				/*bit sign number to 8 bit sign number*/
2658 				pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2659 				if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2660 					pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
2661 				/*bit sign number to 8 bit sign number*/
2662 				pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2663 				if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2664 					pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
2665 
2666 				pwrinfo24g->cck_diff[rfpath][txcount] = 0;
2667 				eeaddr++;
2668 			} else {
2669 				pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2670 				if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3))
2671 					pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0;
2672 
2673 				pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2674 				if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2675 					pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
2676 
2677 				eeaddr++;
2678 
2679 				pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2680 				if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2681 					pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
2682 
2683 				pwrinfo24g->cck_diff[rfpath][txcount] =	(hwinfo[eeaddr] & 0x0f);
2684 				if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3))
2685 					pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0;
2686 
2687 				eeaddr++;
2688 			}
2689 		}
2690 
2691 		/*5G default value*/
2692 		for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2693 			pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2694 			if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
2695 				pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE;
2696 		}
2697 
2698 		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2699 			if (txcount == 0) {
2700 				pwrinfo5g->bw40_diff[rfpath][txcount] = 0;
2701 
2702 				pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4;
2703 				if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2704 					pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
2705 
2706 				pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f);
2707 				if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2708 					pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
2709 
2710 				eeaddr++;
2711 			} else {
2712 				pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2713 				if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3))
2714 					pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0;
2715 
2716 				pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2717 				if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2718 					pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
2719 
2720 				eeaddr++;
2721 			}
2722 		}
2723 
2724 		pwrinfo5g->ofdm_diff[rfpath][1] =	(hwinfo[eeaddr] & 0xf0) >> 4;
2725 		pwrinfo5g->ofdm_diff[rfpath][2] =	(hwinfo[eeaddr] & 0x0f);
2726 
2727 		eeaddr++;
2728 
2729 		pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f);
2730 
2731 		eeaddr++;
2732 
2733 		for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) {
2734 			if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2735 				pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
2736 		}
2737 		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2738 			pwrinfo5g->bw80_diff[rfpath][txcount] =	(hwinfo[eeaddr] & 0xf0) >> 4;
2739 			/* 4bit sign number to 8 bit sign number */
2740 			if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3))
2741 				pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0;
2742 			/* 4bit sign number to 8 bit sign number */
2743 			pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2744 			if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3))
2745 				pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0;
2746 
2747 			eeaddr++;
2748 		}
2749 	}
2750 }
2751 #if 0
2752 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2753 						 bool autoload_fail,
2754 						 u8 *hwinfo)
2755 {
2756 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2757 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2758 	struct txpower_info_2g pwrinfo24g;
2759 	struct txpower_info_5g pwrinfo5g;
2760 	u8 rf_path, index;
2761 	u8 i;
2762 
2763 	_rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2764 					&pwrinfo5g, autoload_fail, hwinfo);
2765 
2766 	for (rf_path = 0; rf_path < 2; rf_path++) {
2767 		for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2768 			index = _rtl8821ae_get_chnl_group(i + 1);
2769 
2770 			if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2771 				rtlefuse->txpwrlevel_cck[rf_path][i] =
2772 					pwrinfo24g.index_cck_base[rf_path][5];
2773 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2774 					pwrinfo24g.index_bw40_base[rf_path][index];
2775 			} else {
2776 				rtlefuse->txpwrlevel_cck[rf_path][i] =
2777 					pwrinfo24g.index_cck_base[rf_path][index];
2778 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2779 					pwrinfo24g.index_bw40_base[rf_path][index];
2780 			}
2781 		}
2782 
2783 		for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2784 			index = _rtl8821ae_get_chnl_group(channel5g[i]);
2785 			rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2786 					pwrinfo5g.index_bw40_base[rf_path][index];
2787 		}
2788 		for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2789 			u8 upper, lower;
2790 			index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2791 			upper = pwrinfo5g.index_bw40_base[rf_path][index];
2792 			lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2793 
2794 			rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2795 		}
2796 		for (i = 0; i < MAX_TX_COUNT; i++) {
2797 			rtlefuse->txpwr_cckdiff[rf_path][i] =
2798 				pwrinfo24g.cck_diff[rf_path][i];
2799 			rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2800 				pwrinfo24g.ofdm_diff[rf_path][i];
2801 			rtlefuse->txpwr_ht20diff[rf_path][i] =
2802 				pwrinfo24g.bw20_diff[rf_path][i];
2803 			rtlefuse->txpwr_ht40diff[rf_path][i] =
2804 				pwrinfo24g.bw40_diff[rf_path][i];
2805 
2806 			rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2807 				pwrinfo5g.ofdm_diff[rf_path][i];
2808 			rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2809 				pwrinfo5g.bw20_diff[rf_path][i];
2810 			rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2811 				pwrinfo5g.bw40_diff[rf_path][i];
2812 			rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2813 				pwrinfo5g.bw80_diff[rf_path][i];
2814 		}
2815 	}
2816 
2817 	if (!autoload_fail) {
2818 		rtlefuse->eeprom_regulatory =
2819 			hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2820 		if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2821 			rtlefuse->eeprom_regulatory = 0;
2822 	} else {
2823 		rtlefuse->eeprom_regulatory = 0;
2824 	}
2825 
2826 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2827 	"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2828 }
2829 #endif
2830 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2831 						 bool autoload_fail,
2832 						 u8 *hwinfo)
2833 {
2834 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2835 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2836 	struct txpower_info_2g pwrinfo24g;
2837 	struct txpower_info_5g pwrinfo5g;
2838 	u8 rf_path, index;
2839 	u8 i;
2840 
2841 	_rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2842 		&pwrinfo5g, autoload_fail, hwinfo);
2843 
2844 	for (rf_path = 0; rf_path < 2; rf_path++) {
2845 		for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2846 			index = _rtl8821ae_get_chnl_group(i + 1);
2847 
2848 			if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2849 				rtlefuse->txpwrlevel_cck[rf_path][i] =
2850 					pwrinfo24g.index_cck_base[rf_path][5];
2851 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2852 					pwrinfo24g.index_bw40_base[rf_path][index];
2853 			} else {
2854 				rtlefuse->txpwrlevel_cck[rf_path][i] =
2855 					pwrinfo24g.index_cck_base[rf_path][index];
2856 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2857 					pwrinfo24g.index_bw40_base[rf_path][index];
2858 			}
2859 		}
2860 
2861 		for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2862 			index = _rtl8821ae_get_chnl_group(channel5g[i]);
2863 			rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2864 				pwrinfo5g.index_bw40_base[rf_path][index];
2865 		}
2866 		for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2867 			u8 upper, lower;
2868 			index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2869 			upper = pwrinfo5g.index_bw40_base[rf_path][index];
2870 			lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2871 
2872 			rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2873 		}
2874 		for (i = 0; i < MAX_TX_COUNT; i++) {
2875 			rtlefuse->txpwr_cckdiff[rf_path][i] =
2876 				pwrinfo24g.cck_diff[rf_path][i];
2877 			rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2878 				pwrinfo24g.ofdm_diff[rf_path][i];
2879 			rtlefuse->txpwr_ht20diff[rf_path][i] =
2880 				pwrinfo24g.bw20_diff[rf_path][i];
2881 			rtlefuse->txpwr_ht40diff[rf_path][i] =
2882 				pwrinfo24g.bw40_diff[rf_path][i];
2883 
2884 			rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2885 				pwrinfo5g.ofdm_diff[rf_path][i];
2886 			rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2887 				pwrinfo5g.bw20_diff[rf_path][i];
2888 			rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2889 				pwrinfo5g.bw40_diff[rf_path][i];
2890 			rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2891 				pwrinfo5g.bw80_diff[rf_path][i];
2892 		}
2893 	}
2894 	/*bit0~2*/
2895 	if (!autoload_fail) {
2896 		rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2897 		if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2898 			rtlefuse->eeprom_regulatory = 0;
2899 	} else {
2900 		rtlefuse->eeprom_regulatory = 0;
2901 	}
2902 
2903 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2904 	"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2905 }
2906 
2907 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2908 				    bool autoload_fail)
2909 {
2910 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2911 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2912 
2913 	if (!autoload_fail) {
2914 		rtlhal->pa_type_2g = hwinfo[0XBC];
2915 		rtlhal->lna_type_2g = hwinfo[0XBD];
2916 		if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2917 			rtlhal->pa_type_2g = 0;
2918 			rtlhal->lna_type_2g = 0;
2919 		}
2920 		rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2921 					  (rtlhal->pa_type_2g & BIT(4))) ?
2922 					 1 : 0;
2923 		rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2924 					   (rtlhal->lna_type_2g & BIT(3))) ?
2925 					  1 : 0;
2926 
2927 		rtlhal->pa_type_5g = hwinfo[0XBC];
2928 		rtlhal->lna_type_5g = hwinfo[0XBF];
2929 		if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2930 			rtlhal->pa_type_5g = 0;
2931 			rtlhal->lna_type_5g = 0;
2932 		}
2933 		rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2934 					  (rtlhal->pa_type_5g & BIT(0))) ?
2935 					 1 : 0;
2936 		rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2937 					   (rtlhal->lna_type_5g & BIT(3))) ?
2938 					  1 : 0;
2939 	} else {
2940 		rtlhal->external_pa_2g  = 0;
2941 		rtlhal->external_lna_2g = 0;
2942 		rtlhal->external_pa_5g  = 0;
2943 		rtlhal->external_lna_5g = 0;
2944 	}
2945 }
2946 
2947 static void _rtl8812ae_read_amplifier_type(struct ieee80211_hw *hw, u8 *hwinfo,
2948 					   bool autoload_fail)
2949 {
2950 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2951 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2952 
2953 	u8 ext_type_pa_2g_a  = (hwinfo[0XBD] & BIT(2))      >> 2; /* 0XBD[2] */
2954 	u8 ext_type_pa_2g_b  = (hwinfo[0XBD] & BIT(6))      >> 6; /* 0XBD[6] */
2955 	u8 ext_type_pa_5g_a  = (hwinfo[0XBF] & BIT(2))      >> 2; /* 0XBF[2] */
2956 	u8 ext_type_pa_5g_b  = (hwinfo[0XBF] & BIT(6))      >> 6; /* 0XBF[6] */
2957 	/* 0XBD[1:0] */
2958 	u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0;
2959 	/* 0XBD[5:4] */
2960 	u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4;
2961 	/* 0XBF[1:0] */
2962 	u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0;
2963 	/* 0XBF[5:4] */
2964 	u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4;
2965 
2966 	_rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
2967 
2968 	/* [2.4G] Path A and B are both extPA */
2969 	if ((rtlhal->pa_type_2g & (BIT(5) | BIT(4))) == (BIT(5) | BIT(4)))
2970 		rtlhal->type_gpa  = ext_type_pa_2g_b  << 2 | ext_type_pa_2g_a;
2971 
2972 	/* [5G] Path A and B are both extPA */
2973 	if ((rtlhal->pa_type_5g & (BIT(1) | BIT(0))) == (BIT(1) | BIT(0)))
2974 		rtlhal->type_apa  = ext_type_pa_5g_b  << 2 | ext_type_pa_5g_a;
2975 
2976 	/* [2.4G] Path A and B are both extLNA */
2977 	if ((rtlhal->lna_type_2g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2978 		rtlhal->type_glna = ext_type_lna_2g_b << 2 | ext_type_lna_2g_a;
2979 
2980 	/* [5G] Path A and B are both extLNA */
2981 	if ((rtlhal->lna_type_5g & (BIT(7) | BIT(3))) == (BIT(7) | BIT(3)))
2982 		rtlhal->type_alna = ext_type_lna_5g_b << 2 | ext_type_lna_5g_a;
2983 }
2984 
2985 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2986 				    bool autoload_fail)
2987 {
2988 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2989 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2990 
2991 	if (!autoload_fail) {
2992 		rtlhal->pa_type_2g = hwinfo[0XBC];
2993 		rtlhal->lna_type_2g = hwinfo[0XBD];
2994 		if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2995 			rtlhal->pa_type_2g = 0;
2996 			rtlhal->lna_type_2g = 0;
2997 		}
2998 		rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2999 		rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3000 
3001 		rtlhal->pa_type_5g = hwinfo[0XBC];
3002 		rtlhal->lna_type_5g = hwinfo[0XBF];
3003 		if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3004 			rtlhal->pa_type_5g = 0;
3005 			rtlhal->lna_type_5g = 0;
3006 		}
3007 		rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3008 		rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3009 	} else {
3010 		rtlhal->external_pa_2g  = 0;
3011 		rtlhal->external_lna_2g = 0;
3012 		rtlhal->external_pa_5g  = 0;
3013 		rtlhal->external_lna_5g = 0;
3014 	}
3015 }
3016 
3017 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3018 			      bool autoload_fail)
3019 {
3020 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3021 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3022 
3023 	if (!autoload_fail) {
3024 		if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3025 			if (rtlhal->external_lna_5g) {
3026 				if (rtlhal->external_pa_5g) {
3027 					if (rtlhal->external_lna_2g &&
3028 					    rtlhal->external_pa_2g)
3029 						rtlhal->rfe_type = 3;
3030 					else
3031 						rtlhal->rfe_type = 0;
3032 				} else {
3033 					rtlhal->rfe_type = 2;
3034 				}
3035 			} else {
3036 				rtlhal->rfe_type = 4;
3037 			}
3038 		} else {
3039 			rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3040 
3041 			if (rtlhal->rfe_type == 4 &&
3042 			    (rtlhal->external_pa_5g ||
3043 			     rtlhal->external_pa_2g ||
3044 			     rtlhal->external_lna_5g ||
3045 			     rtlhal->external_lna_2g)) {
3046 				if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3047 					rtlhal->rfe_type = 2;
3048 			}
3049 		}
3050 	} else {
3051 		rtlhal->rfe_type = 0x04;
3052 	}
3053 
3054 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3055 		"RFE Type: 0x%2x\n", rtlhal->rfe_type);
3056 }
3057 
3058 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3059 					      bool auto_load_fail, u8 *hwinfo)
3060 {
3061 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3062 	u8 value;
3063 
3064 	if (!auto_load_fail) {
3065 		value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3066 		if (((value & 0xe0) >> 5) == 0x1)
3067 			rtlpriv->btcoexist.btc_info.btcoexist = 1;
3068 		else
3069 			rtlpriv->btcoexist.btc_info.btcoexist = 0;
3070 		rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3071 
3072 		value = hwinfo[EEPROM_RF_BT_SETTING];
3073 		rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3074 	} else {
3075 		rtlpriv->btcoexist.btc_info.btcoexist = 0;
3076 		rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3077 		rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3078 	}
3079 	/*move BT_InitHalVars() to init_sw_vars*/
3080 }
3081 
3082 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3083 					      bool auto_load_fail, u8 *hwinfo)
3084 {
3085 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3086 	u8 value;
3087 	u32 tmpu_32;
3088 
3089 	if (!auto_load_fail) {
3090 		tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3091 		if (tmpu_32 & BIT(18))
3092 			rtlpriv->btcoexist.btc_info.btcoexist = 1;
3093 		else
3094 			rtlpriv->btcoexist.btc_info.btcoexist = 0;
3095 		rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3096 
3097 		value = hwinfo[EEPROM_RF_BT_SETTING];
3098 		rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3099 	} else {
3100 		rtlpriv->btcoexist.btc_info.btcoexist = 0;
3101 		rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3102 		rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3103 	}
3104 	/*move BT_InitHalVars() to init_sw_vars*/
3105 }
3106 
3107 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3108 {
3109 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3110 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3111 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3112 	int params[] = {RTL_EEPROM_ID, EEPROM_VID, EEPROM_DID,
3113 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
3114 			EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
3115 			COUNTRY_CODE_WORLD_WIDE_13};
3116 	u8 *hwinfo;
3117 
3118 	if (b_pseudo_test) {
3119 		;/* need add */
3120 	}
3121 
3122 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
3123 	if (!hwinfo)
3124 		return;
3125 
3126 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
3127 		goto exit;
3128 
3129 	_rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3130 					       hwinfo);
3131 
3132 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3133 		_rtl8812ae_read_amplifier_type(hw, hwinfo,
3134 					       rtlefuse->autoload_failflag);
3135 		_rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3136 				rtlefuse->autoload_failflag, hwinfo);
3137 	} else {
3138 		_rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3139 		_rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3140 				rtlefuse->autoload_failflag, hwinfo);
3141 	}
3142 
3143 	_rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3144 	/*board type*/
3145 	rtlefuse->board_type = ODM_BOARD_DEFAULT;
3146 	if (rtlhal->external_lna_2g != 0)
3147 		rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3148 	if (rtlhal->external_lna_5g != 0)
3149 		rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3150 	if (rtlhal->external_pa_2g != 0)
3151 		rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3152 	if (rtlhal->external_pa_5g != 0)
3153 		rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3154 
3155 	if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3156 		rtlefuse->board_type |= ODM_BOARD_BT;
3157 
3158 	rtlhal->board_type = rtlefuse->board_type;
3159 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3160 		"board_type = 0x%x\n", rtlefuse->board_type);
3161 
3162 	rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3163 	if (rtlefuse->eeprom_channelplan == 0xff)
3164 		rtlefuse->eeprom_channelplan = 0x7F;
3165 
3166 	/* set channel plan from efuse */
3167 	rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3168 
3169 	/*parse xtal*/
3170 	rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3171 	if (rtlefuse->crystalcap == 0xFF)
3172 		rtlefuse->crystalcap = 0x20;
3173 
3174 	rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3175 	if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3176 	    rtlefuse->autoload_failflag) {
3177 		rtlefuse->apk_thermalmeterignore = true;
3178 		rtlefuse->eeprom_thermalmeter = 0xff;
3179 	}
3180 
3181 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3182 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3183 		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3184 
3185 	if (!rtlefuse->autoload_failflag) {
3186 		rtlefuse->antenna_div_cfg =
3187 		  (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3188 		if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3189 			rtlefuse->antenna_div_cfg = 0;
3190 
3191 		if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3192 		    rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3193 			rtlefuse->antenna_div_cfg = 0;
3194 
3195 		rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3196 		if (rtlefuse->antenna_div_type == 0xff)
3197 			rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3198 	} else {
3199 		rtlefuse->antenna_div_cfg = 0;
3200 		rtlefuse->antenna_div_type = 0;
3201 	}
3202 
3203 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3204 		"SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3205 		rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3206 
3207 	rtlpriv->ledctl.led_opendrain = true;
3208 
3209 	if (rtlhal->oem_id == RT_CID_DEFAULT) {
3210 		switch (rtlefuse->eeprom_oemid) {
3211 		case RT_CID_DEFAULT:
3212 			break;
3213 		case EEPROM_CID_TOSHIBA:
3214 			rtlhal->oem_id = RT_CID_TOSHIBA;
3215 			break;
3216 		case EEPROM_CID_CCX:
3217 			rtlhal->oem_id = RT_CID_CCX;
3218 			break;
3219 		case EEPROM_CID_QMI:
3220 			rtlhal->oem_id = RT_CID_819X_QMI;
3221 			break;
3222 		case EEPROM_CID_WHQL:
3223 			break;
3224 		default:
3225 			break;
3226 		}
3227 	}
3228 exit:
3229 	kfree(hwinfo);
3230 }
3231 
3232 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3233 {
3234 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3235 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3236 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3237 
3238 	rtlpriv->ledctl.led_opendrain = true;
3239 	switch (rtlhal->oem_id) {
3240 	case RT_CID_819X_HP:
3241 		rtlpriv->ledctl.led_opendrain = true;
3242 		break;
3243 	case RT_CID_819X_LENOVO:
3244 	case RT_CID_DEFAULT:
3245 	case RT_CID_TOSHIBA:
3246 	case RT_CID_CCX:
3247 	case RT_CID_819X_ACER:
3248 	case RT_CID_WHQL:
3249 	default:
3250 		break;
3251 	}
3252 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
3253 		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3254 }*/
3255 
3256 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3257 {
3258 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3259 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3260 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3261 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3262 	u8 tmp_u1b;
3263 
3264 	rtlhal->version = _rtl8821ae_read_chip_version(hw);
3265 	if (get_rf_type(rtlphy) == RF_1T1R)
3266 		rtlpriv->dm.rfpath_rxenable[0] = true;
3267 	else
3268 		rtlpriv->dm.rfpath_rxenable[0] =
3269 		    rtlpriv->dm.rfpath_rxenable[1] = true;
3270 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3271 		rtlhal->version);
3272 
3273 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3274 	if (tmp_u1b & BIT(4)) {
3275 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3276 		rtlefuse->epromtype = EEPROM_93C46;
3277 	} else {
3278 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3279 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3280 	}
3281 
3282 	if (tmp_u1b & BIT(5)) {
3283 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3284 		rtlefuse->autoload_failflag = false;
3285 		_rtl8821ae_read_adapter_info(hw, false);
3286 	} else {
3287 		pr_err("Autoload ERR!!\n");
3288 	}
3289 	/*hal_ReadRFType_8812A()*/
3290 	/* _rtl8821ae_hal_customized_behavior(hw); */
3291 }
3292 
3293 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3294 		struct ieee80211_sta *sta)
3295 {
3296 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3297 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3298 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3299 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3300 	u32 ratr_value;
3301 	u8 ratr_index = 0;
3302 	u8 b_nmode = mac->ht_enable;
3303 	u8 mimo_ps = IEEE80211_SMPS_OFF;
3304 	u16 shortgi_rate;
3305 	u32 tmp_ratr_value;
3306 	u8 curtxbw_40mhz = mac->bw_40;
3307 	u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3308 				1 : 0;
3309 	u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3310 				1 : 0;
3311 	enum wireless_mode wirelessmode = mac->mode;
3312 
3313 	if (rtlhal->current_bandtype == BAND_ON_5G)
3314 		ratr_value = sta->deflink.supp_rates[1] << 4;
3315 	else
3316 		ratr_value = sta->deflink.supp_rates[0];
3317 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
3318 		ratr_value = 0xfff;
3319 	ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
3320 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
3321 	switch (wirelessmode) {
3322 	case WIRELESS_MODE_B:
3323 		if (ratr_value & 0x0000000c)
3324 			ratr_value &= 0x0000000d;
3325 		else
3326 			ratr_value &= 0x0000000f;
3327 		break;
3328 	case WIRELESS_MODE_G:
3329 		ratr_value &= 0x00000FF5;
3330 		break;
3331 	case WIRELESS_MODE_N_24G:
3332 	case WIRELESS_MODE_N_5G:
3333 		b_nmode = 1;
3334 		if (mimo_ps == IEEE80211_SMPS_STATIC) {
3335 			ratr_value &= 0x0007F005;
3336 		} else {
3337 			u32 ratr_mask;
3338 
3339 			if (get_rf_type(rtlphy) == RF_1T2R ||
3340 			    get_rf_type(rtlphy) == RF_1T1R)
3341 				ratr_mask = 0x000ff005;
3342 			else
3343 				ratr_mask = 0x0f0ff005;
3344 
3345 			ratr_value &= ratr_mask;
3346 		}
3347 		break;
3348 	default:
3349 		if (rtlphy->rf_type == RF_1T2R)
3350 			ratr_value &= 0x000ff0ff;
3351 		else
3352 			ratr_value &= 0x0f0ff0ff;
3353 
3354 		break;
3355 	}
3356 
3357 	if ((rtlpriv->btcoexist.bt_coexistence) &&
3358 	     (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3359 	     (rtlpriv->btcoexist.bt_cur_state) &&
3360 	     (rtlpriv->btcoexist.bt_ant_isolation) &&
3361 	     ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3362 	     (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3363 		ratr_value &= 0x0fffcfc0;
3364 	else
3365 		ratr_value &= 0x0FFFFFFF;
3366 
3367 	if (b_nmode && ((curtxbw_40mhz &&
3368 			 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3369 						 b_curshortgi_20mhz))) {
3370 		ratr_value |= 0x10000000;
3371 		tmp_ratr_value = (ratr_value >> 12);
3372 
3373 		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3374 			if ((1 << shortgi_rate) & tmp_ratr_value)
3375 				break;
3376 		}
3377 
3378 		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3379 		    (shortgi_rate << 4) | (shortgi_rate);
3380 	}
3381 
3382 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3383 
3384 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3385 		"%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3386 }
3387 
3388 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3389 {
3390 	u8 i, j, tmp_rate;
3391 	u32 rate_bitmap = 0;
3392 
3393 	for (i = j = 0; i < 4; i += 2, j += 10) {
3394 		tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3395 
3396 		switch (tmp_rate) {
3397 		case 2:
3398 			rate_bitmap = rate_bitmap | (0x03ff << j);
3399 			break;
3400 		case 1:
3401 			rate_bitmap = rate_bitmap | (0x01ff << j);
3402 			break;
3403 		case 0:
3404 			rate_bitmap = rate_bitmap | (0x00ff << j);
3405 			break;
3406 		default:
3407 			break;
3408 		}
3409 	}
3410 
3411 	return rate_bitmap;
3412 }
3413 
3414 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3415 					     enum wireless_mode wirelessmode,
3416 					     u32 ratr_bitmap)
3417 {
3418 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3419 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3420 	u32 ret_bitmap = ratr_bitmap;
3421 
3422 	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3423 		|| rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3424 		ret_bitmap = ratr_bitmap;
3425 	else if (wirelessmode == WIRELESS_MODE_AC_5G
3426 		|| wirelessmode == WIRELESS_MODE_AC_24G) {
3427 		if (rtlphy->rf_type == RF_1T1R)
3428 			ret_bitmap = ratr_bitmap & (~BIT21);
3429 		else
3430 			ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3431 	}
3432 
3433 	return ret_bitmap;
3434 }
3435 
3436 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3437 			u32 ratr_bitmap)
3438 {
3439 	u8 ret = 0;
3440 	if (wirelessmode < WIRELESS_MODE_N_24G)
3441 		ret =  0;
3442 	else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3443 		if (ratr_bitmap & 0xfff00000)	/* Mix , 2SS */
3444 			ret = 3;
3445 		else					/* Mix, 1SS */
3446 			ret = 2;
3447 	} else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3448 			ret = 1;
3449 	} /* VHT */
3450 
3451 	return ret << 4;
3452 }
3453 
3454 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3455 			     u8 mac_id, struct rtl_sta_info *sta_entry,
3456 			     enum wireless_mode wirelessmode)
3457 {
3458 	u8 b_ldpc = 0;
3459 	/*not support ldpc, do not open*/
3460 	return b_ldpc << 2;
3461 }
3462 
3463 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3464 			  enum wireless_mode wirelessmode,
3465 			  u32 ratr_bitmap)
3466 {
3467 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3468 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3469 	u8 rf_type = RF_1T1R;
3470 
3471 	if (rtlphy->rf_type == RF_1T1R)
3472 		rf_type = RF_1T1R;
3473 	else if (wirelessmode == WIRELESS_MODE_AC_5G
3474 		|| wirelessmode == WIRELESS_MODE_AC_24G
3475 		|| wirelessmode == WIRELESS_MODE_AC_ONLY) {
3476 		if (ratr_bitmap & 0xffc00000)
3477 			rf_type = RF_2T2R;
3478 	} else if (wirelessmode == WIRELESS_MODE_N_5G
3479 		|| wirelessmode == WIRELESS_MODE_N_24G) {
3480 		if (ratr_bitmap & 0xfff00000)
3481 			rf_type = RF_2T2R;
3482 	}
3483 
3484 	return rf_type;
3485 }
3486 
3487 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3488 			      u8 mac_id)
3489 {
3490 	bool b_short_gi = false;
3491 	u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3492 				1 : 0;
3493 	u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3494 				1 : 0;
3495 	u8 b_curshortgi_80mhz = 0;
3496 	b_curshortgi_80mhz = (sta->deflink.vht_cap.cap &
3497 			      IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3498 
3499 	if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3500 			b_short_gi = false;
3501 
3502 	if (b_curshortgi_40mhz || b_curshortgi_80mhz
3503 		|| b_curshortgi_20mhz)
3504 		b_short_gi = true;
3505 
3506 	return b_short_gi;
3507 }
3508 
3509 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3510 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3511 {
3512 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3513 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3514 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3515 	struct rtl_sta_info *sta_entry = NULL;
3516 	u32 ratr_bitmap;
3517 	u8 ratr_index;
3518 	enum wireless_mode wirelessmode = 0;
3519 	u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3520 				? 1 : 0;
3521 	bool b_shortgi = false;
3522 	u8 rate_mask[7];
3523 	u8 macid = 0;
3524 	u8 mimo_ps = IEEE80211_SMPS_OFF;
3525 	u8 rf_type;
3526 
3527 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3528 	wirelessmode = sta_entry->wireless_mode;
3529 
3530 	rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3531 		"wireless mode = 0x%x\n", wirelessmode);
3532 	if (mac->opmode == NL80211_IFTYPE_STATION ||
3533 		mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3534 		curtxbw_40mhz = mac->bw_40;
3535 	} else if (mac->opmode == NL80211_IFTYPE_AP ||
3536 		mac->opmode == NL80211_IFTYPE_ADHOC)
3537 		macid = sta->aid + 1;
3538 	if (wirelessmode == WIRELESS_MODE_N_5G ||
3539 	    wirelessmode == WIRELESS_MODE_AC_5G ||
3540 	    wirelessmode == WIRELESS_MODE_A)
3541 		ratr_bitmap = sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
3542 	else
3543 		ratr_bitmap = sta->deflink.supp_rates[NL80211_BAND_2GHZ];
3544 
3545 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
3546 		ratr_bitmap = 0xfff;
3547 
3548 	if (wirelessmode == WIRELESS_MODE_N_24G
3549 		|| wirelessmode == WIRELESS_MODE_N_5G)
3550 		ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
3551 				sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
3552 	else if (wirelessmode == WIRELESS_MODE_AC_24G
3553 		|| wirelessmode == WIRELESS_MODE_AC_5G
3554 		|| wirelessmode == WIRELESS_MODE_AC_ONLY)
3555 		ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3556 				sta->deflink.vht_cap.vht_mcs.rx_mcs_map) << 12;
3557 
3558 	b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3559 	rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3560 
3561 /*mac id owner*/
3562 	switch (wirelessmode) {
3563 	case WIRELESS_MODE_B:
3564 		ratr_index = RATR_INX_WIRELESS_B;
3565 		if (ratr_bitmap & 0x0000000c)
3566 			ratr_bitmap &= 0x0000000d;
3567 		else
3568 			ratr_bitmap &= 0x0000000f;
3569 		break;
3570 	case WIRELESS_MODE_G:
3571 		ratr_index = RATR_INX_WIRELESS_GB;
3572 
3573 		if (rssi_level == 1)
3574 			ratr_bitmap &= 0x00000f00;
3575 		else if (rssi_level == 2)
3576 			ratr_bitmap &= 0x00000ff0;
3577 		else
3578 			ratr_bitmap &= 0x00000ff5;
3579 		break;
3580 	case WIRELESS_MODE_A:
3581 		ratr_index = RATR_INX_WIRELESS_G;
3582 		ratr_bitmap &= 0x00000ff0;
3583 		break;
3584 	case WIRELESS_MODE_N_24G:
3585 	case WIRELESS_MODE_N_5G:
3586 		if (wirelessmode == WIRELESS_MODE_N_24G)
3587 			ratr_index = RATR_INX_WIRELESS_NGB;
3588 		else
3589 			ratr_index = RATR_INX_WIRELESS_NG;
3590 
3591 		if (mimo_ps == IEEE80211_SMPS_STATIC
3592 			|| mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3593 			if (rssi_level == 1)
3594 				ratr_bitmap &= 0x000f0000;
3595 			else if (rssi_level == 2)
3596 				ratr_bitmap &= 0x000ff000;
3597 			else
3598 				ratr_bitmap &= 0x000ff005;
3599 		} else {
3600 			if (rf_type == RF_1T1R) {
3601 				if (curtxbw_40mhz) {
3602 					if (rssi_level == 1)
3603 						ratr_bitmap &= 0x000f0000;
3604 					else if (rssi_level == 2)
3605 						ratr_bitmap &= 0x000ff000;
3606 					else
3607 						ratr_bitmap &= 0x000ff015;
3608 				} else {
3609 					if (rssi_level == 1)
3610 						ratr_bitmap &= 0x000f0000;
3611 					else if (rssi_level == 2)
3612 						ratr_bitmap &= 0x000ff000;
3613 					else
3614 						ratr_bitmap &= 0x000ff005;
3615 				}
3616 			} else {
3617 				if (curtxbw_40mhz) {
3618 					if (rssi_level == 1)
3619 						ratr_bitmap &= 0x0fff0000;
3620 					else if (rssi_level == 2)
3621 						ratr_bitmap &= 0x0ffff000;
3622 					else
3623 						ratr_bitmap &= 0x0ffff015;
3624 				} else {
3625 					if (rssi_level == 1)
3626 						ratr_bitmap &= 0x0fff0000;
3627 					else if (rssi_level == 2)
3628 						ratr_bitmap &= 0x0ffff000;
3629 					else
3630 						ratr_bitmap &= 0x0ffff005;
3631 				}
3632 			}
3633 		}
3634 		break;
3635 
3636 	case WIRELESS_MODE_AC_24G:
3637 		ratr_index = RATR_INX_WIRELESS_AC_24N;
3638 		if (rssi_level == 1)
3639 			ratr_bitmap &= 0xfc3f0000;
3640 		else if (rssi_level == 2)
3641 			ratr_bitmap &= 0xfffff000;
3642 		else
3643 			ratr_bitmap &= 0xffffffff;
3644 		break;
3645 
3646 	case WIRELESS_MODE_AC_5G:
3647 		ratr_index = RATR_INX_WIRELESS_AC_5N;
3648 
3649 		if (rf_type == RF_1T1R) {
3650 			if (rssi_level == 1)	/*add by Gary for ac-series*/
3651 				ratr_bitmap &= 0x003f8000;
3652 			else if (rssi_level == 2)
3653 				ratr_bitmap &= 0x003ff000;
3654 			else
3655 				ratr_bitmap &= 0x003ff010;
3656 		} else {
3657 			if (rssi_level == 1)
3658 				ratr_bitmap &= 0xfe3f8000;
3659 			else if (rssi_level == 2)
3660 				ratr_bitmap &= 0xfffff000;
3661 			else
3662 				ratr_bitmap &= 0xfffff010;
3663 		}
3664 		break;
3665 
3666 	default:
3667 		ratr_index = RATR_INX_WIRELESS_NGB;
3668 
3669 		if (rf_type == RF_1T2R)
3670 			ratr_bitmap &= 0x000ff0ff;
3671 		else
3672 			ratr_bitmap &= 0x0f8ff0ff;
3673 		break;
3674 	}
3675 
3676 	ratr_index = rtl_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3677 	sta_entry->ratr_index = ratr_index;
3678 	ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3679 							ratr_bitmap);
3680 
3681 	rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3682 		"ratr_bitmap :%x\n", ratr_bitmap);
3683 
3684 	/* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3685 				       (ratr_index << 28)); */
3686 
3687 	rate_mask[0] = macid;
3688 	rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3689 	rate_mask[2] = rtlphy->current_chan_bw | ((!update_bw) << 3)
3690 			   | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3691 			   | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3692 
3693 	rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3694 	rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3695 	rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3696 	rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3697 
3698 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3699 		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3700 		ratr_index, ratr_bitmap,
3701 		rate_mask[0], rate_mask[1],
3702 		 rate_mask[2], rate_mask[3],
3703 		 rate_mask[4], rate_mask[5],
3704 		 rate_mask[6]);
3705 	rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3706 	_rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3707 }
3708 
3709 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3710 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
3711 {
3712 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3713 	if (rtlpriv->dm.useramask)
3714 		rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
3715 	else
3716 		/*rtl_dbg(rtlpriv, COMP_RATR,DBG_LOUD,
3717 			   "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
3718 		rtl8821ae_update_hal_rate_table(hw, sta);
3719 }
3720 
3721 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3722 {
3723 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3724 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3725 	u16 wireless_mode = mac->mode;
3726 	u8 sifs_timer, r2t_sifs;
3727 
3728 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3729 				      (u8 *)&mac->slot_time);
3730 	if (wireless_mode == WIRELESS_MODE_G)
3731 		sifs_timer = 0x0a;
3732 	else
3733 		sifs_timer = 0x0e;
3734 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3735 
3736 	r2t_sifs = 0xa;
3737 
3738 	if (wireless_mode == WIRELESS_MODE_AC_5G &&
3739 	    (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3740 	    (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3741 		if (mac->vendor == PEER_ATH)
3742 			r2t_sifs = 0x8;
3743 		else
3744 			r2t_sifs = 0xa;
3745 	} else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3746 		r2t_sifs = 0xa;
3747 	}
3748 
3749 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3750 }
3751 
3752 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3753 {
3754 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3755 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3756 	struct rtl_phy *rtlphy = &rtlpriv->phy;
3757 	enum rf_pwrstate e_rfpowerstate_toset;
3758 	u8 u1tmp = 0;
3759 	bool b_actuallyset = false;
3760 
3761 	if (rtlpriv->rtlhal.being_init_adapter)
3762 		return false;
3763 
3764 	if (ppsc->swrf_processing)
3765 		return false;
3766 
3767 	spin_lock(&rtlpriv->locks.rf_ps_lock);
3768 	if (ppsc->rfchange_inprogress) {
3769 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
3770 		return false;
3771 	} else {
3772 		ppsc->rfchange_inprogress = true;
3773 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
3774 	}
3775 
3776 	rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3777 			rtl_read_byte(rtlpriv,
3778 					REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3779 
3780 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3781 
3782 	if (rtlphy->polarity_ctl)
3783 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3784 	else
3785 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3786 
3787 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3788 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3789 			"GPIOChangeRF  - HW Radio ON, RF ON\n");
3790 
3791 		e_rfpowerstate_toset = ERFON;
3792 		ppsc->hwradiooff = false;
3793 		b_actuallyset = true;
3794 	} else if ((!ppsc->hwradiooff)
3795 		   && (e_rfpowerstate_toset == ERFOFF)) {
3796 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3797 			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3798 
3799 		e_rfpowerstate_toset = ERFOFF;
3800 		ppsc->hwradiooff = true;
3801 		b_actuallyset = true;
3802 	}
3803 
3804 	if (b_actuallyset) {
3805 		spin_lock(&rtlpriv->locks.rf_ps_lock);
3806 		ppsc->rfchange_inprogress = false;
3807 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
3808 	} else {
3809 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3810 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3811 
3812 		spin_lock(&rtlpriv->locks.rf_ps_lock);
3813 		ppsc->rfchange_inprogress = false;
3814 		spin_unlock(&rtlpriv->locks.rf_ps_lock);
3815 	}
3816 
3817 	*valid = 1;
3818 	return !ppsc->hwradiooff;
3819 }
3820 
3821 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3822 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
3823 		     bool is_wepkey, bool clear_all)
3824 {
3825 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3826 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3827 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3828 	u8 *macaddr = p_macaddr;
3829 	u32 entry_id = 0;
3830 	bool is_pairwise = false;
3831 
3832 	static u8 cam_const_addr[4][6] = {
3833 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3834 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3835 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3836 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3837 	};
3838 	static u8 cam_const_broad[] = {
3839 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3840 	};
3841 
3842 	if (clear_all) {
3843 		u8 idx = 0;
3844 		u8 cam_offset = 0;
3845 		u8 clear_number = 5;
3846 
3847 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3848 
3849 		for (idx = 0; idx < clear_number; idx++) {
3850 			rtl_cam_mark_invalid(hw, cam_offset + idx);
3851 			rtl_cam_empty_entry(hw, cam_offset + idx);
3852 
3853 			if (idx < 5) {
3854 				memset(rtlpriv->sec.key_buf[idx], 0,
3855 				       MAX_KEY_LEN);
3856 				rtlpriv->sec.key_len[idx] = 0;
3857 			}
3858 		}
3859 	} else {
3860 		switch (enc_algo) {
3861 		case WEP40_ENCRYPTION:
3862 			enc_algo = CAM_WEP40;
3863 			break;
3864 		case WEP104_ENCRYPTION:
3865 			enc_algo = CAM_WEP104;
3866 			break;
3867 		case TKIP_ENCRYPTION:
3868 			enc_algo = CAM_TKIP;
3869 			break;
3870 		case AESCCMP_ENCRYPTION:
3871 			enc_algo = CAM_AES;
3872 			break;
3873 		default:
3874 			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3875 				"switch case %#x not processed\n", enc_algo);
3876 			enc_algo = CAM_TKIP;
3877 			break;
3878 		}
3879 
3880 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3881 			macaddr = cam_const_addr[key_index];
3882 			entry_id = key_index;
3883 		} else {
3884 			if (is_group) {
3885 				macaddr = cam_const_broad;
3886 				entry_id = key_index;
3887 			} else {
3888 				if (mac->opmode == NL80211_IFTYPE_AP) {
3889 					entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3890 					if (entry_id >=  TOTAL_CAM_ENTRY) {
3891 						pr_err("an not find free hwsecurity cam entry\n");
3892 						return;
3893 					}
3894 				} else {
3895 					entry_id = CAM_PAIRWISE_KEY_POSITION;
3896 				}
3897 
3898 				key_index = PAIRWISE_KEYIDX;
3899 				is_pairwise = true;
3900 			}
3901 		}
3902 
3903 		if (rtlpriv->sec.key_len[key_index] == 0) {
3904 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3905 				"delete one entry, entry_id is %d\n",
3906 				entry_id);
3907 			if (mac->opmode == NL80211_IFTYPE_AP)
3908 				rtl_cam_del_entry(hw, p_macaddr);
3909 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3910 		} else {
3911 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3912 				"add one entry\n");
3913 			if (is_pairwise) {
3914 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3915 					"set Pairwise key\n");
3916 
3917 				rtl_cam_add_one_entry(hw, macaddr, key_index,
3918 						      entry_id, enc_algo,
3919 						      CAM_CONFIG_NO_USEDK,
3920 						      rtlpriv->sec.key_buf[key_index]);
3921 			} else {
3922 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3923 					"set group key\n");
3924 
3925 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3926 					rtl_cam_add_one_entry(hw,
3927 							rtlefuse->dev_addr,
3928 							PAIRWISE_KEYIDX,
3929 							CAM_PAIRWISE_KEY_POSITION,
3930 							enc_algo,
3931 							CAM_CONFIG_NO_USEDK,
3932 							rtlpriv->sec.key_buf
3933 							[entry_id]);
3934 				}
3935 
3936 				rtl_cam_add_one_entry(hw, macaddr, key_index,
3937 						entry_id, enc_algo,
3938 						CAM_CONFIG_NO_USEDK,
3939 						rtlpriv->sec.key_buf[entry_id]);
3940 			}
3941 		}
3942 	}
3943 }
3944 
3945 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
3946 {
3947 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3948 
3949 	/* 0:Low, 1:High, 2:From Efuse. */
3950 	rtlpriv->btcoexist.reg_bt_iso = 2;
3951 	/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3952 	rtlpriv->btcoexist.reg_bt_sco = 3;
3953 	/* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3954 	rtlpriv->btcoexist.reg_bt_sco = 0;
3955 }
3956 
3957 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
3958 {
3959 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3960 
3961 	if (rtlpriv->cfg->ops->get_btc_status())
3962 		rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3963 }
3964 
3965 void rtl8821ae_suspend(struct ieee80211_hw *hw)
3966 {
3967 }
3968 
3969 void rtl8821ae_resume(struct ieee80211_hw *hw)
3970 {
3971 }
3972 
3973 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
3974 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3975 	bool allow_all_da, bool write_into_reg)
3976 {
3977 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3978 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3979 
3980 	if (allow_all_da) /* Set BIT0 */
3981 		rtlpci->receive_config |= RCR_AAP;
3982 	else /* Clear BIT0 */
3983 		rtlpci->receive_config &= ~RCR_AAP;
3984 
3985 	if (write_into_reg)
3986 		rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
3987 
3988 	rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
3989 		"receive_config=0x%08X, write_into_reg=%d\n",
3990 		rtlpci->receive_config, write_into_reg);
3991 }
3992 
3993 /* WKFMCAMAddAllEntry8812 */
3994 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
3995 				  struct rtl_wow_pattern *rtl_pattern,
3996 				  u8 index)
3997 {
3998 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3999 	u32 cam = 0;
4000 	u8 addr = 0;
4001 	u16 rxbuf_addr;
4002 	u8 tmp, count = 0;
4003 	u16 cam_start;
4004 	u16 offset;
4005 
4006 	/* Count the WFCAM entry start offset. */
4007 
4008 	/* RX page size = 128 byte */
4009 	offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4010 	/* We should start from the boundry */
4011 	cam_start = offset * 128;
4012 
4013 	/* Enable Rx packet buffer access. */
4014 	rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4015 	for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4016 		/* Set Rx packet buffer offset.
4017 		 * RXBufer pointer increases 1,
4018 		 * we can access 8 bytes in Rx packet buffer.
4019 		 * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4020 		 * RXBufer addr = (CAM start offset +
4021 		 *                 per entry offset of a WKFM CAM)/8
4022 		 *	* index: The index of the wake up frame mask
4023 		 *	* WKFMCAM_SIZE: the total size of one WKFM CAM
4024 		 *	* per entry offset of a WKFM CAM: Addr*4 bytes
4025 		 */
4026 		rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4027 		/* Set R/W start offset */
4028 		rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4029 
4030 		if (addr == 0) {
4031 			cam = BIT(31) | rtl_pattern->crc;
4032 
4033 			if (rtl_pattern->type == UNICAST_PATTERN)
4034 				cam |= BIT(24);
4035 			else if (rtl_pattern->type == MULTICAST_PATTERN)
4036 				cam |= BIT(25);
4037 			else if (rtl_pattern->type == BROADCAST_PATTERN)
4038 				cam |= BIT(26);
4039 
4040 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4041 			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4042 				"WRITE entry[%d] 0x%x: %x\n", addr,
4043 				REG_PKTBUF_DBG_DATA_L, cam);
4044 
4045 			/* Write to Rx packet buffer. */
4046 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4047 		} else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4048 			cam = rtl_pattern->mask[addr - 2];
4049 
4050 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4051 			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4052 				"WRITE entry[%d] 0x%x: %x\n", addr,
4053 				REG_PKTBUF_DBG_DATA_L, cam);
4054 
4055 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4056 		} else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4057 			cam = rtl_pattern->mask[addr - 2];
4058 
4059 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4060 			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4061 				"WRITE entry[%d] 0x%x: %x\n", addr,
4062 				REG_PKTBUF_DBG_DATA_H, cam);
4063 
4064 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4065 		}
4066 
4067 		count = 0;
4068 		do {
4069 			tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4070 			udelay(2);
4071 			count++;
4072 		} while (tmp && count < 100);
4073 
4074 		WARN_ONCE((count >= 100),
4075 			  "rtl8821ae: Write wake up frame mask FAIL %d value!\n",
4076 			  tmp);
4077 	}
4078 	/* Disable Rx packet buffer access. */
4079 	rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4080 		       DISABLE_TRXPKT_BUF_ACCESS);
4081 }
4082