1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3 4 #ifndef __RTL8723BE_PHY_H__ 5 #define __RTL8723BE_PHY_H__ 6 7 /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence 8 * will be wrong. 9 */ 10 #define MAX_TX_COUNT 4 11 #define TX_1S 0 12 #define TX_2S 1 13 #define TX_3S 2 14 #define TX_4S 3 15 16 #define MAX_POWER_INDEX 0x3F 17 18 #define MAX_PRECMD_CNT 16 19 #define MAX_RFDEPENDCMD_CNT 16 20 #define MAX_POSTCMD_CNT 16 21 22 #define MAX_DOZE_WAITING_TIMES_9x 64 23 24 #define RT_CANNOT_IO(hw) false 25 #define HIGHPOWER_RADIOA_ARRAYLEN 22 26 27 #define TARGET_CHNL_NUM_2G_5G 59 28 29 #define IQK_ADDA_REG_NUM 16 30 #define IQK_BB_REG_NUM 9 31 #define MAX_TOLERANCE 5 32 #define IQK_DELAY_TIME 10 33 #define index_mapping_NUM 15 34 35 #define APK_BB_REG_NUM 5 36 #define APK_AFE_REG_NUM 16 37 #define APK_CURVE_REG_NUM 4 38 #define PATH_NUM 1 39 40 #define LOOP_LIMIT 5 41 #define MAX_STALL_TIME 50 42 #define ANTENNADIVERSITYVALUE 0x80 43 #define MAX_TXPWR_IDX_NMODE_92S 63 44 #define RESET_CNT_LIMIT 3 45 46 #define IQK_ADDA_REG_NUM 16 47 #define IQK_MAC_REG_NUM 4 48 49 #define RF6052_MAX_PATH 2 50 51 #define CT_OFFSET_MAC_ADDR 0X16 52 53 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A 54 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60 55 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66 56 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69 57 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C 58 59 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F 60 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72 61 62 #define CT_OFFSET_CHANNEL_PLAH 0x75 63 #define CT_OFFSET_THERMAL_METER 0x78 64 #define CT_OFFSET_RF_OPTION 0x79 65 #define CT_OFFSET_VERSION 0x7E 66 #define CT_OFFSET_CUSTOMER_ID 0x7F 67 68 #define RTL92C_MAX_PATH_NUM 2 69 70 enum baseband_config_type { 71 BASEBAND_CONFIG_PHY_REG = 0, 72 BASEBAND_CONFIG_AGC_TAB = 1, 73 }; 74 75 enum ant_div_type { 76 NO_ANTDIV = 0xFF, 77 CG_TRX_HW_ANTDIV = 0x01, 78 CGCS_RX_HW_ANTDIV = 0x02, 79 FIXED_HW_ANTDIV = 0x03, 80 CG_TRX_SMART_ANTDIV = 0x04, 81 CGCS_RX_SW_ANTDIV = 0x05, 82 83 }; 84 85 u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, 86 enum radio_path rfpath, 87 u32 regaddr, u32 bitmask); 88 void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, 89 enum radio_path rfpath, 90 u32 regaddr, u32 bitmask, u32 data); 91 bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw); 92 bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw); 93 bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw); 94 void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 95 void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw, 96 u8 channel); 97 void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw, 98 u8 operation); 99 void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 100 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw, 101 enum nl80211_channel_type ch_type); 102 void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw); 103 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw); 104 void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, 105 bool b_recovery); 106 void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw); 107 void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 108 bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 109 enum radio_path rfpath); 110 bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 111 bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw, 112 enum rf_pwrstate rfpwr_state); 113 #endif 114