1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * Larry Finger <Larry.Finger@lwfinger.net> 22 * 23 *****************************************************************************/ 24 25 #ifndef __RTL8723BE__FW__H__ 26 #define __RTL8723BE__FW__H__ 27 28 #define FW_8192C_SIZE 0x8000 29 #define FW_8192C_START_ADDRESS 0x1000 30 #define FW_8192C_END_ADDRESS 0x5FFF 31 #define FW_8192C_PAGE_SIZE 4096 32 #define FW_8192C_POLLING_DELAY 5 33 34 #define USE_OLD_WOWLAN_DEBUG_FW 0 35 36 #define H2C_PWEMODE_LENGTH 7 37 38 /* Fw PS state for RPWM. 39 *BIT[2:0] = HW state 40 *BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state 41 *BIT[4] = sub-state 42 */ 43 #define FW_PS_RF_ON BIT(2) 44 #define FW_PS_REGISTER_ACTIVE BIT(3) 45 46 #define FW_PS_ACK BIT(6) 47 #define FW_PS_TOGGLE BIT(7) 48 49 /* 8723BE RPWM value*/ 50 /* BIT[0] = 1: 32k, 0: 40M*/ 51 #define FW_PS_CLOCK_OFF BIT(0) /* 32k*/ 52 #define FW_PS_CLOCK_ON 0 /*40M*/ 53 54 #define FW_PS_STATE_MASK (0x0F) 55 #define FW_PS_STATE_HW_MASK (0x07) 56 /*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/ 57 #define FW_PS_STATE_INT_MASK (0x3F) 58 59 #define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x)) 60 61 /* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/ 62 #define FW_PS_STATE_ALL_ON (FW_PS_CLOCK_ON) 63 /* (FW_PS_RF_ON)*/ 64 #define FW_PS_STATE_RF_ON (FW_PS_CLOCK_ON) 65 /* 0x0*/ 66 #define FW_PS_STATE_RF_OFF (FW_PS_CLOCK_ON) 67 /* (FW_PS_STATE_RF_OFF)*/ 68 #define FW_PS_STATE_RF_OFF_LOW_PWR (FW_PS_CLOCK_OFF) 69 70 71 /* For 8723BE H2C PwrMode Cmd ID 5.*/ 72 #define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE)) 73 #define FW_PWR_STATE_RF_OFF 0 74 75 #define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK) 76 77 #define IS_IN_LOW_POWER_STATE(__fwpsstate) \ 78 (FW_PS_STATE(__fwpsstate) == FW_PS_CLOCK_OFF) 79 80 #define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE)) 81 #define FW_PWR_STATE_RF_OFF 0 82 83 enum rtl8723b_h2c_cmd { 84 H2C_8723B_RSVDPAGE = 0, 85 H2C_8723B_MSRRPT = 1, 86 H2C_8723B_SCAN = 2, 87 H2C_8723B_KEEP_ALIVE_CTRL = 3, 88 H2C_8723B_DISCONNECT_DECISION = 4, 89 H2C_8723B_BCN_RSVDPAGE = 9, 90 H2C_8723B_PROBERSP_RSVDPAGE = 10, 91 92 H2C_8723B_SETPWRMODE = 0x20, 93 H2C_8723B_PS_LPS_PARA = 0x23, 94 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 95 96 H2C_8723B_RA_MASK = 0x40, 97 H2C_RSSIBE_REPORT = 0x42, 98 /*Not defined CTW CMD for P2P yet*/ 99 H2C_8723B_P2P_PS_CTW_CMD, 100 MAX_8723B_H2CCMD 101 }; 102 103 enum rtl8723b_c2h_evt { 104 C2H_8723B_DBG = 0, 105 C2H_8723B_LB = 1, 106 C2H_8723B_TXBF = 2, 107 C2H_8723B_TX_REPORT = 3, 108 C2H_8723B_BT_INFO = 9, 109 C2H_8723B_BT_MP = 11, 110 MAX_8723B_C2HEVENT 111 }; 112 113 #define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0)) 114 115 116 #define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \ 117 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val) 118 #define SET_H2CCMD_PWRMODE_PARM_RLBM(__ph2ccmd, __val) \ 119 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 4, __val) 120 #define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \ 121 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 4, 4, __val) 122 #define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__ph2ccmd, __val) \ 123 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val) 124 #define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__ph2ccmd, __val) \ 125 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+3, 0, 8, __val) 126 #define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__ph2ccmd, __val) \ 127 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+4, 0, 8, __val) 128 #define SET_H2CCMD_PWRMODE_PARM_BYTE5(__ph2ccmd, __val) \ 129 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 5, 0, 8, __val) 130 #define GET_88E_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd) \ 131 LE_BITS_TO_1BYTE(__ph2ccmd, 0, 8) 132 133 #define SET_H2CCMD_MSRRPT_PARM_OPMODE(__ph2ccmd, __val) \ 134 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val) 135 #define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__ph2ccmd, __val) \ 136 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val) 137 138 #define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \ 139 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val) 140 #define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \ 141 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val) 142 #define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \ 143 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val) 144 #define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__ph2ccmd, __val) \ 145 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 3, 0, 8, __val) 146 #define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__ph2ccmd, __val) \ 147 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 4, 0, 8, __val) 148 149 150 void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, 151 u32 cmd_len, u8 *p_cmdbuffer); 152 void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode); 153 void rtl8723be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus); 154 void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished); 155 void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state); 156 void rtl8723be_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len); 157 void rtl8723be_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id, 158 u8 c2h_cmd_len, u8 *tmp_buf); 159 #endif 160