1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../core.h" 28 #include "../pci.h" 29 #include "reg.h" 30 #include "def.h" 31 #include "phy.h" 32 #include "dm.h" 33 #include "fw.h" 34 #include "../rtl8723com/fw_common.h" 35 #include "hw.h" 36 #include "sw.h" 37 #include "trx.h" 38 #include "led.h" 39 #include "table.h" 40 #include "hal_btc.h" 41 #include "../btcoexist/rtl_btc.h" 42 #include "../rtl8723com/phy_common.h" 43 44 #include <linux/vmalloc.h> 45 #include <linux/module.h> 46 47 static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw) 48 { 49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 50 51 /*close ASPM for AMD defaultly */ 52 rtlpci->const_amdpci_aspm = 0; 53 54 /** 55 * ASPM PS mode. 56 * 0 - Disable ASPM, 57 * 1 - Enable ASPM without Clock Req, 58 * 2 - Enable ASPM with Clock Req, 59 * 3 - Alwyas Enable ASPM with Clock Req, 60 * 4 - Always Enable ASPM without Clock Req. 61 * set defult to RTL8192CE:3 RTL8192E:2 62 */ 63 rtlpci->const_pci_aspm = 3; 64 65 /*Setting for PCI-E device */ 66 rtlpci->const_devicepci_aspm_setting = 0x03; 67 68 /*Setting for PCI-E bridge */ 69 rtlpci->const_hostpci_aspm_setting = 0x02; 70 71 /** 72 * In Hw/Sw Radio Off situation. 73 * 0 - Default, 74 * 1 - From ASPM setting without low Mac Pwr, 75 * 2 - From ASPM setting with low Mac Pwr, 76 * 3 - Bus D3 77 * set default to RTL8192CE:0 RTL8192SE:2 78 */ 79 rtlpci->const_hwsw_rfoff_d3 = 0; 80 81 /** 82 * This setting works for those device with 83 * backdoor ASPM setting such as EPHY setting. 84 * 0 - Not support ASPM, 85 * 1 - Support ASPM, 86 * 2 - According to chipset. 87 */ 88 rtlpci->const_support_pciaspm = 1; 89 } 90 91 int rtl8723e_init_sw_vars(struct ieee80211_hw *hw) 92 { 93 struct rtl_priv *rtlpriv = rtl_priv(hw); 94 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 95 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 96 int err = 0; 97 98 rtl8723e_bt_reg_init(hw); 99 100 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer(); 101 102 rtlpriv->dm.dm_initialgain_enable = 1; 103 rtlpriv->dm.dm_flag = 0; 104 rtlpriv->dm.disable_framebursting = 0; 105 rtlpriv->dm.thermalvalue = 0; 106 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 107 108 /* compatible 5G band 88ce just 2.4G band & smsp */ 109 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 110 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 111 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 112 113 rtlpci->receive_config = (RCR_APPFCS | 114 RCR_APP_MIC | 115 RCR_APP_ICV | 116 RCR_APP_PHYST_RXFF | 117 RCR_HTC_LOC_CTRL | 118 RCR_AMF | 119 RCR_ACF | 120 RCR_ADF | 121 RCR_AICV | 122 RCR_AB | 123 RCR_AM | 124 RCR_APM | 125 0); 126 127 rtlpci->irq_mask[0] = 128 (u32) (PHIMR_ROK | 129 PHIMR_RDU | 130 PHIMR_VODOK | 131 PHIMR_VIDOK | 132 PHIMR_BEDOK | 133 PHIMR_BKDOK | 134 PHIMR_MGNTDOK | 135 PHIMR_HIGHDOK | 136 PHIMR_C2HCMD | 137 PHIMR_HISRE_IND | 138 PHIMR_TSF_BIT32_TOGGLE | 139 PHIMR_TXBCNOK | 140 PHIMR_PSTIMEOUT | 141 0); 142 143 rtlpci->irq_mask[1] = 144 (u32)(PHIMR_RXFOVW | 145 0); 146 147 /* for debug level */ 148 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 149 /* for LPS & IPS */ 150 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 151 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 152 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 153 if (rtlpriv->cfg->mod_params->disable_watchdog) 154 pr_info("watchdog disabled\n"); 155 rtlpriv->psc.reg_fwctrl_lps = 3; 156 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 157 rtl8723e_init_aspm_vars(hw); 158 159 if (rtlpriv->psc.reg_fwctrl_lps == 1) 160 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 161 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 162 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 163 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 164 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 165 166 /* for firmware buf */ 167 rtlpriv->rtlhal.pfirmware = vzalloc(0x6000); 168 if (!rtlpriv->rtlhal.pfirmware) { 169 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 170 "Can't alloc buffer for fw.\n"); 171 return 1; 172 } 173 174 if (IS_VENDOR_8723_A_CUT(rtlhal->version)) 175 rtlpriv->cfg->fw_name = "rtlwifi/rtl8723fw.bin"; 176 else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) 177 rtlpriv->cfg->fw_name = "rtlwifi/rtl8723fw_B.bin"; 178 179 rtlpriv->max_fw_size = 0x6000; 180 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name); 181 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 182 rtlpriv->io.dev, GFP_KERNEL, hw, 183 rtl_fw_cb); 184 if (err) { 185 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 186 "Failed to request firmware!\n"); 187 return 1; 188 } 189 return 0; 190 } 191 192 void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw) 193 { 194 struct rtl_priv *rtlpriv = rtl_priv(hw); 195 196 if (rtlpriv->rtlhal.pfirmware) { 197 vfree(rtlpriv->rtlhal.pfirmware); 198 rtlpriv->rtlhal.pfirmware = NULL; 199 } 200 } 201 202 /* get bt coexist status */ 203 bool rtl8723e_get_btc_status(void) 204 { 205 return true; 206 } 207 208 static bool is_fw_header(struct rtlwifi_firmware_header *hdr) 209 { 210 return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x2300; 211 } 212 213 static struct rtl_hal_ops rtl8723e_hal_ops = { 214 .init_sw_vars = rtl8723e_init_sw_vars, 215 .deinit_sw_vars = rtl8723e_deinit_sw_vars, 216 .read_eeprom_info = rtl8723e_read_eeprom_info, 217 .interrupt_recognized = rtl8723e_interrupt_recognized, 218 .hw_init = rtl8723e_hw_init, 219 .hw_disable = rtl8723e_card_disable, 220 .hw_suspend = rtl8723e_suspend, 221 .hw_resume = rtl8723e_resume, 222 .enable_interrupt = rtl8723e_enable_interrupt, 223 .disable_interrupt = rtl8723e_disable_interrupt, 224 .set_network_type = rtl8723e_set_network_type, 225 .set_chk_bssid = rtl8723e_set_check_bssid, 226 .set_qos = rtl8723e_set_qos, 227 .set_bcn_reg = rtl8723e_set_beacon_related_registers, 228 .set_bcn_intv = rtl8723e_set_beacon_interval, 229 .update_interrupt_mask = rtl8723e_update_interrupt_mask, 230 .get_hw_reg = rtl8723e_get_hw_reg, 231 .set_hw_reg = rtl8723e_set_hw_reg, 232 .update_rate_tbl = rtl8723e_update_hal_rate_tbl, 233 .fill_tx_desc = rtl8723e_tx_fill_desc, 234 .fill_tx_cmddesc = rtl8723e_tx_fill_cmddesc, 235 .query_rx_desc = rtl8723e_rx_query_desc, 236 .set_channel_access = rtl8723e_update_channel_access_setting, 237 .radio_onoff_checking = rtl8723e_gpio_radio_on_off_checking, 238 .set_bw_mode = rtl8723e_phy_set_bw_mode, 239 .switch_channel = rtl8723e_phy_sw_chnl, 240 .dm_watchdog = rtl8723e_dm_watchdog, 241 .scan_operation_backup = rtl8723e_phy_scan_operation_backup, 242 .set_rf_power_state = rtl8723e_phy_set_rf_power_state, 243 .led_control = rtl8723e_led_control, 244 .set_desc = rtl8723e_set_desc, 245 .get_desc = rtl8723e_get_desc, 246 .is_tx_desc_closed = rtl8723e_is_tx_desc_closed, 247 .tx_polling = rtl8723e_tx_polling, 248 .enable_hw_sec = rtl8723e_enable_hw_security_config, 249 .set_key = rtl8723e_set_key, 250 .init_sw_leds = rtl8723e_init_sw_leds, 251 .get_bbreg = rtl8723_phy_query_bb_reg, 252 .set_bbreg = rtl8723_phy_set_bb_reg, 253 .get_rfreg = rtl8723e_phy_query_rf_reg, 254 .set_rfreg = rtl8723e_phy_set_rf_reg, 255 .c2h_command_handle = rtl_8723e_c2h_command_handle, 256 .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify, 257 .bt_coex_off_before_lps = 258 rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps, 259 .get_btc_status = rtl8723e_get_btc_status, 260 .rx_command_packet = rtl8723e_rx_command_packet, 261 .is_fw_header = is_fw_header, 262 }; 263 264 static struct rtl_mod_params rtl8723e_mod_params = { 265 .sw_crypto = false, 266 .inactiveps = true, 267 .swctrl_lps = false, 268 .fwctrl_lps = true, 269 .debug = DBG_EMERG, 270 }; 271 272 static struct rtl_hal_cfg rtl8723e_hal_cfg = { 273 .bar_id = 2, 274 .write_readback = true, 275 .name = "rtl8723e_pci", 276 .fw_name = "rtlwifi/rtl8723efw.bin", 277 .ops = &rtl8723e_hal_ops, 278 .mod_params = &rtl8723e_mod_params, 279 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 280 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 281 .maps[SYS_CLK] = REG_SYS_CLKR, 282 .maps[MAC_RCR_AM] = AM, 283 .maps[MAC_RCR_AB] = AB, 284 .maps[MAC_RCR_ACRC32] = ACRC32, 285 .maps[MAC_RCR_ACF] = ACF, 286 .maps[MAC_RCR_AAP] = AAP, 287 .maps[MAC_HIMR] = REG_HIMR, 288 .maps[MAC_HIMRE] = REG_HIMRE, 289 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 290 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 291 .maps[EFUSE_CLK] = 0, 292 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 293 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 294 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 295 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 296 .maps[EFUSE_ANA8M] = ANA8M, 297 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 298 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 299 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 300 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 301 302 .maps[RWCAM] = REG_CAMCMD, 303 .maps[WCAMI] = REG_CAMWRITE, 304 .maps[RCAMO] = REG_CAMREAD, 305 .maps[CAMDBG] = REG_CAMDBG, 306 .maps[SECR] = REG_SECCFG, 307 .maps[SEC_CAM_NONE] = CAM_NONE, 308 .maps[SEC_CAM_WEP40] = CAM_WEP40, 309 .maps[SEC_CAM_TKIP] = CAM_TKIP, 310 .maps[SEC_CAM_AES] = CAM_AES, 311 .maps[SEC_CAM_WEP104] = CAM_WEP104, 312 313 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 314 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 315 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 316 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 317 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 318 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 319 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 320 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 321 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 322 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 323 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 324 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 325 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 326 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 327 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 328 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 329 330 .maps[RTL_IMR_TXFOVW] = PHIMR_TXFOVW, 331 .maps[RTL_IMR_PSTIMEOUT] = PHIMR_PSTIMEOUT, 332 .maps[RTL_IMR_BCNINT] = PHIMR_BCNDMAINT0, 333 .maps[RTL_IMR_RXFOVW] = PHIMR_RXFOVW, 334 .maps[RTL_IMR_RDU] = PHIMR_RDU, 335 .maps[RTL_IMR_ATIMEND] = PHIMR_ATIMEND_E, 336 .maps[RTL_IMR_BDOK] = PHIMR_BCNDOK0, 337 .maps[RTL_IMR_MGNTDOK] = PHIMR_MGNTDOK, 338 .maps[RTL_IMR_TBDER] = PHIMR_TXBCNERR, 339 .maps[RTL_IMR_HIGHDOK] = PHIMR_HIGHDOK, 340 .maps[RTL_IMR_TBDOK] = PHIMR_TXBCNOK, 341 .maps[RTL_IMR_BKDOK] = PHIMR_BKDOK, 342 .maps[RTL_IMR_BEDOK] = PHIMR_BEDOK, 343 .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK, 344 .maps[RTL_IMR_VODOK] = PHIMR_VODOK, 345 .maps[RTL_IMR_ROK] = PHIMR_ROK, 346 .maps[RTL_IBSS_INT_MASKS] = 347 (PHIMR_BCNDMAINT0 | PHIMR_TXBCNOK | PHIMR_TXBCNERR), 348 .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD, 349 350 351 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, 352 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M, 353 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M, 354 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M, 355 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M, 356 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M, 357 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M, 358 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M, 359 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M, 360 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M, 361 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M, 362 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M, 363 364 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7, 365 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, 366 }; 367 368 static struct pci_device_id rtl8723e_pci_ids[] = { 369 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723e_hal_cfg)}, 370 {}, 371 }; 372 373 MODULE_DEVICE_TABLE(pci, rtl8723e_pci_ids); 374 375 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 376 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 377 MODULE_LICENSE("GPL"); 378 MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless"); 379 MODULE_FIRMWARE("rtlwifi/rtl8723efw.bin"); 380 381 module_param_named(swenc, rtl8723e_mod_params.sw_crypto, bool, 0444); 382 module_param_named(debug, rtl8723e_mod_params.debug, int, 0444); 383 module_param_named(ips, rtl8723e_mod_params.inactiveps, bool, 0444); 384 module_param_named(swlps, rtl8723e_mod_params.swctrl_lps, bool, 0444); 385 module_param_named(fwlps, rtl8723e_mod_params.fwctrl_lps, bool, 0444); 386 module_param_named(disable_watchdog, rtl8723e_mod_params.disable_watchdog, 387 bool, 0444); 388 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 389 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 390 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 391 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 392 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 393 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n"); 394 395 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 396 397 static struct pci_driver rtl8723e_driver = { 398 .name = KBUILD_MODNAME, 399 .id_table = rtl8723e_pci_ids, 400 .probe = rtl_pci_probe, 401 .remove = rtl_pci_disconnect, 402 .driver.pm = &rtlwifi_pm_ops, 403 }; 404 405 module_pci_driver(rtl8723e_driver); 406