1f1d2b4d3SLarry Finger /****************************************************************************** 2f1d2b4d3SLarry Finger * 3f1d2b4d3SLarry Finger * Copyright(c) 2009-2012 Realtek Corporation. 4f1d2b4d3SLarry Finger * 5f1d2b4d3SLarry Finger * This program is free software; you can redistribute it and/or modify it 6f1d2b4d3SLarry Finger * under the terms of version 2 of the GNU General Public License as 7f1d2b4d3SLarry Finger * published by the Free Software Foundation. 8f1d2b4d3SLarry Finger * 9f1d2b4d3SLarry Finger * This program is distributed in the hope that it will be useful, but WITHOUT 10f1d2b4d3SLarry Finger * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11f1d2b4d3SLarry Finger * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12f1d2b4d3SLarry Finger * more details. 13f1d2b4d3SLarry Finger * 14f1d2b4d3SLarry Finger * The full GNU General Public License is included in this distribution in the 15f1d2b4d3SLarry Finger * file called LICENSE. 16f1d2b4d3SLarry Finger * 17f1d2b4d3SLarry Finger * Contact Information: 18f1d2b4d3SLarry Finger * wlanfae <wlanfae@realtek.com> 19f1d2b4d3SLarry Finger * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20f1d2b4d3SLarry Finger * Hsinchu 300, Taiwan. 21f1d2b4d3SLarry Finger * 22f1d2b4d3SLarry Finger * Larry Finger <Larry.Finger@lwfinger.net> 23f1d2b4d3SLarry Finger * 24f1d2b4d3SLarry Finger *****************************************************************************/ 25f1d2b4d3SLarry Finger 26f1d2b4d3SLarry Finger #ifndef __RTL8723E_PWRSEQ_H__ 27f1d2b4d3SLarry Finger #define __RTL8723E_PWRSEQ_H__ 28f1d2b4d3SLarry Finger 29f1d2b4d3SLarry Finger #include "../pwrseqcmd.h" 30f1d2b4d3SLarry Finger /* 31f1d2b4d3SLarry Finger * Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd 32f1d2b4d3SLarry Finger * There are 6 HW Power States: 33f1d2b4d3SLarry Finger * 0: POFF--Power Off 34f1d2b4d3SLarry Finger * 1: PDN--Power Down 35f1d2b4d3SLarry Finger * 2: CARDEMU--Card Emulation 36f1d2b4d3SLarry Finger * 3: ACT--Active Mode 37f1d2b4d3SLarry Finger * 4: LPS--Low Power State 38f1d2b4d3SLarry Finger * 5: SUS--Suspend 39f1d2b4d3SLarry Finger * 40f1d2b4d3SLarry Finger * The transision from different states are defined below 41f1d2b4d3SLarry Finger * TRANS_CARDEMU_TO_ACT 42f1d2b4d3SLarry Finger * TRANS_ACT_TO_CARDEMU 43f1d2b4d3SLarry Finger * TRANS_CARDEMU_TO_SUS 44f1d2b4d3SLarry Finger * TRANS_SUS_TO_CARDEMU 45f1d2b4d3SLarry Finger * TRANS_CARDEMU_TO_PDN 46f1d2b4d3SLarry Finger * TRANS_ACT_TO_LPS 47f1d2b4d3SLarry Finger * TRANS_LPS_TO_ACT 48f1d2b4d3SLarry Finger * 49f1d2b4d3SLarry Finger * TRANS_END 50f1d2b4d3SLarry Finger */ 51f1d2b4d3SLarry Finger 52f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 10 53f1d2b4d3SLarry Finger #define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 10 54f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 10 55f1d2b4d3SLarry Finger #define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 10 56f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 10 57f1d2b4d3SLarry Finger #define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 10 58f1d2b4d3SLarry Finger #define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15 59f1d2b4d3SLarry Finger #define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15 60f1d2b4d3SLarry Finger #define RTL8723A_TRANS_END_STEPS 1 61f1d2b4d3SLarry Finger 62f1d2b4d3SLarry Finger /* format */ 63f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/ 64f1d2b4d3SLarry Finger 65f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_ACT \ 66f1d2b4d3SLarry Finger /* disable SW LPS 0x04[10]=0*/ \ 67f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 68f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\ 69f1d2b4d3SLarry Finger /* wait till 0x04[17] = 1 power ready*/ \ 70f1d2b4d3SLarry Finger {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 71f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\ 72f1d2b4d3SLarry Finger /* release WLON reset 0x04[16]=1*/ \ 73f1d2b4d3SLarry Finger {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 74f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\ 75f1d2b4d3SLarry Finger /* disable HWPDN 0x04[15]=0*/ \ 76f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 77f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\ 78f1d2b4d3SLarry Finger /* disable WL suspend*/ \ 79f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 80f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\ 81f1d2b4d3SLarry Finger /* polling until return 0*/ \ 82f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 83f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\ 84f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 85f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, 86f1d2b4d3SLarry Finger 87f1d2b4d3SLarry Finger /* format */ 88f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 89f1d2b4d3SLarry Finger 90f1d2b4d3SLarry Finger #define RTL8723A_TRANS_ACT_TO_CARDEMU \ 91f1d2b4d3SLarry Finger /*0x1F[7:0] = 0 turn off RF*/ \ 92f1d2b4d3SLarry Finger {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 93f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ 94f1d2b4d3SLarry Finger {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 95f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\ 96f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 97f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 98f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 99f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, 100f1d2b4d3SLarry Finger 101f1d2b4d3SLarry Finger /* format */ 102f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/ 103f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_SUS \ 104f1d2b4d3SLarry Finger /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 105f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\ 106f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, \ 107f1d2b4d3SLarry Finger BIT(4)|BIT(3), (BIT(4)|BIT(3))},\ 108f1d2b4d3SLarry Finger /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 109f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \ 110f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK,\ 111f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, \ 112f1d2b4d3SLarry Finger PWR_CMD_WRITE, \ 113f1d2b4d3SLarry Finger BIT(3)|BIT(4), BIT(3)}, \ 114f1d2b4d3SLarry Finger /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 115f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 116f1d2b4d3SLarry Finger PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \ 117f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(3)|BIT(4), \ 118f1d2b4d3SLarry Finger BIT(3)|BIT(4)}, \ 119f1d2b4d3SLarry Finger /*Set SDIO suspend local register*/ \ 120f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 121f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 122f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 123f1d2b4d3SLarry Finger /*wait power state to suspend*/ \ 124f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 125f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 126f1d2b4d3SLarry Finger PWR_CMD_POLLING, BIT(1), 0}, 127f1d2b4d3SLarry Finger 128f1d2b4d3SLarry Finger /* format */ 129f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 130f1d2b4d3SLarry Finger 131f1d2b4d3SLarry Finger #define RTL8723A_TRANS_SUS_TO_CARDEMU \ 132f1d2b4d3SLarry Finger /*Set SDIO suspend local register*/ \ 133f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 134f1d2b4d3SLarry Finger PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\ 135f1d2b4d3SLarry Finger /*wait power state to suspend*/ \ 136f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\ 137f1d2b4d3SLarry Finger PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\ 138f1d2b4d3SLarry Finger /*0x04[12:11] = 2b'01enable WL suspend*/ \ 139f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 140f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, 141f1d2b4d3SLarry Finger 142f1d2b4d3SLarry Finger /* format */ 143f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 144f1d2b4d3SLarry Finger 145f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \ 146f1d2b4d3SLarry Finger /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 147f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 148f1d2b4d3SLarry Finger PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \ 149f1d2b4d3SLarry Finger PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ 150f1d2b4d3SLarry Finger /*0x04[10] = 1, enable SW LPS*/ \ 151f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 152f1d2b4d3SLarry Finger PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\ 153f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(2), BIT(2)}, \ 154f1d2b4d3SLarry Finger /*Set SDIO suspend local register*/ \ 155f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 156f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 157f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 158f1d2b4d3SLarry Finger /*wait power state to suspend*/ \ 159f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 160f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 161f1d2b4d3SLarry Finger PWR_CMD_POLLING, BIT(1), 0}, 162f1d2b4d3SLarry Finger 163f1d2b4d3SLarry Finger /* format */ 164f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 165f1d2b4d3SLarry Finger 166f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\ 167f1d2b4d3SLarry Finger /*Set SDIO suspend local register*/ \ 168f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 169f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 170f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(0), 0}, \ 171f1d2b4d3SLarry Finger /*wait power state to suspend*/ \ 172f1d2b4d3SLarry Finger {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 173f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 174f1d2b4d3SLarry Finger PWR_CMD_POLLING, BIT(1), BIT(1)},\ 175f1d2b4d3SLarry Finger /*0x04[12:11] = 2b'00enable WL suspend*/ \ 176f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 177f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 178f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\ 179f1d2b4d3SLarry Finger /*PCIe DMA start*/ \ 180f1d2b4d3SLarry Finger {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 181f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 182f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0}, 183f1d2b4d3SLarry Finger 184f1d2b4d3SLarry Finger /* format */ 185f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 186f1d2b4d3SLarry Finger #define RTL8723A_TRANS_CARDEMU_TO_PDN \ 187f1d2b4d3SLarry Finger {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 188f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 189f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\ 190f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 191f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 192f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/ 193f1d2b4d3SLarry Finger 194f1d2b4d3SLarry Finger /* format */ 195f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 196f1d2b4d3SLarry Finger #define RTL8723A_TRANS_PDN_TO_CARDEMU \ 197f1d2b4d3SLarry Finger {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 198f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 199f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/ 200f1d2b4d3SLarry Finger 201f1d2b4d3SLarry Finger /* format */ 202f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 203f1d2b4d3SLarry Finger 204f1d2b4d3SLarry Finger #define RTL8723A_TRANS_ACT_TO_LPS \ 205f1d2b4d3SLarry Finger {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 206f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 207f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ 208f1d2b4d3SLarry Finger {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 209f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 210f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \ 211f1d2b4d3SLarry Finger /*Should be zero if no packet is transmitting*/ \ 212f1d2b4d3SLarry Finger {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 213f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 214f1d2b4d3SLarry Finger PWR_CMD_POLLING, 0xFF, 0},\ 215f1d2b4d3SLarry Finger /*Should be zero if no packet is transmitting*/ \ 216f1d2b4d3SLarry Finger {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 217f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 218f1d2b4d3SLarry Finger PWR_CMD_POLLING, 0xFF, 0},\ 219f1d2b4d3SLarry Finger /*Should be zero if no packet is transmitting*/ \ 220f1d2b4d3SLarry Finger {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 221f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 222f1d2b4d3SLarry Finger PWR_CMD_POLLING, 0xFF, 0},\ 223f1d2b4d3SLarry Finger /*Should be zero if no packet is transmitting*/ \ 224f1d2b4d3SLarry Finger {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 225f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 226f1d2b4d3SLarry Finger PWR_CMD_POLLING, 0xFF, 0},\ 227f1d2b4d3SLarry Finger /*CCK and OFDM are disabled,and clock are gated*/ \ 228f1d2b4d3SLarry Finger {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 229f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 230f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(0), 0},\ 231f1d2b4d3SLarry Finger {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 232f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 233f1d2b4d3SLarry Finger PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\ 234f1d2b4d3SLarry Finger {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 235f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 236f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \ 237f1d2b4d3SLarry Finger {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 238f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 239f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ 240f1d2b4d3SLarry Finger {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 241f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 242f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \ 243f1d2b4d3SLarry Finger /*Respond TxOK to scheduler*/ \ 244f1d2b4d3SLarry Finger {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 245f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 246f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(5), BIT(5)},\ 247f1d2b4d3SLarry Finger 248f1d2b4d3SLarry Finger #define RTL8723A_TRANS_LPS_TO_ACT\ 249f1d2b4d3SLarry Finger /* format */ \ 250f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ \ 251f1d2b4d3SLarry Finger {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 252f1d2b4d3SLarry Finger PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\ 253f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ 254f1d2b4d3SLarry Finger {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 255f1d2b4d3SLarry Finger PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\ 256f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ 257f1d2b4d3SLarry Finger {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 258f1d2b4d3SLarry Finger PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\ 259f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ 260f1d2b4d3SLarry Finger {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 261f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 262f1d2b4d3SLarry Finger PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ 263f1d2b4d3SLarry Finger /*. 0x08[4] = 0 switch TSF to 40M*/\ 264f1d2b4d3SLarry Finger {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 265f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 266f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(4), 0}, \ 267f1d2b4d3SLarry Finger /*Polling 0x109[7]=0 TSF in 40M*/\ 268f1d2b4d3SLarry Finger {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 269f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 270f1d2b4d3SLarry Finger PWR_CMD_POLLING, BIT(7), 0}, \ 271f1d2b4d3SLarry Finger /*. 0x29[7:6] = 2b'00 enable BB clock*/\ 272f1d2b4d3SLarry Finger {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 273f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 274f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\ 275f1d2b4d3SLarry Finger /*. 0x101[1] = 1*/\ 276f1d2b4d3SLarry Finger {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 277f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 278f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(1), BIT(1)},\ 279f1d2b4d3SLarry Finger /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ 280f1d2b4d3SLarry Finger {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 281f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 282f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0xFF},\ 283f1d2b4d3SLarry Finger /*. 0x02[1:0] = 2b'11 enable BB macro*/\ 284f1d2b4d3SLarry Finger {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 285f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 286f1d2b4d3SLarry Finger PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\ 287f1d2b4d3SLarry Finger {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 288f1d2b4d3SLarry Finger PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\ 289f1d2b4d3SLarry Finger PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ 290f1d2b4d3SLarry Finger 291f1d2b4d3SLarry Finger /* format */ 292f1d2b4d3SLarry Finger /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ 293f1d2b4d3SLarry Finger 294f1d2b4d3SLarry Finger #define RTL8723A_TRANS_END \ 295f1d2b4d3SLarry Finger {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 296f1d2b4d3SLarry Finger 0, PWR_CMD_END, 0, 0} 297f1d2b4d3SLarry Finger 298f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_power_on_flow 299f1d2b4d3SLarry Finger [RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + 300f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 301f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_radio_off_flow 302f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + 303f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 304f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_card_disable_flow 305f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + 306f1d2b4d3SLarry Finger RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + 307f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 308f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_card_enable_flow 309f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + 310f1d2b4d3SLarry Finger RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + 311f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 312f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_suspend_flow 313f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + 314f1d2b4d3SLarry Finger RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + 315f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 316f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_resume_flow 317f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + 318f1d2b4d3SLarry Finger RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + 319f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 320f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow 321f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + 322f1d2b4d3SLarry Finger RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + 323f1d2b4d3SLarry Finger RTL8723A_TRANS_END_STEPS]; 324f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow 325f1d2b4d3SLarry Finger [RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS]; 326f1d2b4d3SLarry Finger extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow 327f1d2b4d3SLarry Finger [RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS]; 328f1d2b4d3SLarry Finger 329f1d2b4d3SLarry Finger /* RTL8723 Power Configuration CMDs for PCIe interface */ 330f1d2b4d3SLarry Finger #define Rtl8723_NIC_PWR_ON_FLOW rtl8723A_power_on_flow 331f1d2b4d3SLarry Finger #define Rtl8723_NIC_RF_OFF_FLOW rtl8723A_radio_off_flow 332f1d2b4d3SLarry Finger #define Rtl8723_NIC_DISABLE_FLOW rtl8723A_card_disable_flow 333f1d2b4d3SLarry Finger #define Rtl8723_NIC_ENABLE_FLOW rtl8723A_card_enable_flow 334f1d2b4d3SLarry Finger #define Rtl8723_NIC_SUSPEND_FLOW rtl8723A_suspend_flow 335f1d2b4d3SLarry Finger #define Rtl8723_NIC_RESUME_FLOW rtl8723A_resume_flow 336f1d2b4d3SLarry Finger #define Rtl8723_NIC_PDN_FLOW rtl8723A_hwpdn_flow 337f1d2b4d3SLarry Finger #define Rtl8723_NIC_LPS_ENTER_FLOW rtl8723A_enter_lps_flow 338f1d2b4d3SLarry Finger #define Rtl8723_NIC_LPS_LEAVE_FLOW rtl8723A_leave_lps_flow 339f1d2b4d3SLarry Finger 340f1d2b4d3SLarry Finger #endif 341