1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../pci.h" 28 #include "../ps.h" 29 #include "reg.h" 30 #include "def.h" 31 #include "phy.h" 32 #include "rf.h" 33 #include "dm.h" 34 #include "table.h" 35 #include "../rtl8723com/phy_common.h" 36 37 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw, 38 enum radio_path rfpath, u32 offset, 39 u32 data); 40 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw); 41 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 42 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 43 u8 configtype); 44 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 45 u8 configtype); 46 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 47 u8 channel, u8 *stage, u8 *step, 48 u32 *delay); 49 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw, 50 enum wireless_mode wirelessmode, 51 long power_indbm); 52 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw); 53 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw); 54 55 u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw, 56 enum radio_path rfpath, 57 u32 regaddr, u32 bitmask) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u32 original_value = 0, readback_value, bitshift; 61 struct rtl_phy *rtlphy = &rtlpriv->phy; 62 unsigned long flags; 63 64 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 65 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 66 regaddr, rfpath, bitmask); 67 68 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 69 70 if (rtlphy->rf_mode != RF_OP_BY_FW) { 71 original_value = rtl8723_phy_rf_serial_read(hw, 72 rfpath, regaddr); 73 } 74 75 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 76 readback_value = (original_value & bitmask) >> bitshift; 77 78 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 79 80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 81 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 82 regaddr, rfpath, bitmask, original_value); 83 84 return readback_value; 85 } 86 87 void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw, 88 enum radio_path rfpath, 89 u32 regaddr, u32 bitmask, u32 data) 90 { 91 struct rtl_priv *rtlpriv = rtl_priv(hw); 92 struct rtl_phy *rtlphy = &rtlpriv->phy; 93 u32 original_value = 0, bitshift; 94 unsigned long flags; 95 96 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 97 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 98 regaddr, bitmask, data, rfpath); 99 100 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 101 102 if (rtlphy->rf_mode != RF_OP_BY_FW) { 103 if (bitmask != RFREG_OFFSET_MASK) { 104 original_value = rtl8723_phy_rf_serial_read(hw, 105 rfpath, 106 regaddr); 107 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 108 data = 109 ((original_value & (~bitmask)) | 110 (data << bitshift)); 111 } 112 113 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data); 114 } else { 115 if (bitmask != RFREG_OFFSET_MASK) { 116 bitshift = rtl8723_phy_calculate_bit_shift(bitmask); 117 data = 118 ((original_value & (~bitmask)) | 119 (data << bitshift)); 120 } 121 _rtl8723e_phy_fw_rf_serial_write(hw, rfpath, regaddr, data); 122 } 123 124 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 125 126 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 127 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 128 regaddr, bitmask, data, rfpath); 129 130 } 131 132 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw, 133 enum radio_path rfpath, u32 offset, 134 u32 data) 135 { 136 WARN_ONCE(true, "rtl8723ae: _rtl8723e_phy_fw_rf_serial_write deprecated!\n"); 137 } 138 139 static void _rtl8723e_phy_bb_config_1t(struct ieee80211_hw *hw) 140 { 141 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); 142 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); 143 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); 144 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); 145 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); 146 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); 147 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); 148 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); 149 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); 150 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); 151 } 152 153 bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw) 154 { 155 struct rtl_priv *rtlpriv = rtl_priv(hw); 156 bool rtstatus = _rtl8723e_phy_config_mac_with_headerfile(hw); 157 rtl_write_byte(rtlpriv, 0x04CA, 0x0A); 158 return rtstatus; 159 } 160 161 bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw) 162 { 163 bool rtstatus = true; 164 struct rtl_priv *rtlpriv = rtl_priv(hw); 165 u8 tmpu1b; 166 u8 b_reg_hwparafile = 1; 167 168 rtl8723_phy_init_bb_rf_reg_def(hw); 169 170 /* 1. 0x28[1] = 1 */ 171 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL); 172 udelay(2); 173 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1))); 174 udelay(2); 175 /* 2. 0x29[7:0] = 0xFF */ 176 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff); 177 udelay(2); 178 179 /* 3. 0x02[1:0] = 2b'11 */ 180 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 181 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 182 (tmpu1b | FEN_BB_GLB_RSTN | FEN_BBRSTB)); 183 184 /* 4. 0x25[6] = 0 */ 185 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1); 186 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b & (~BIT(6)))); 187 188 /* 5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09. */ 189 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2); 190 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b & (~BIT(4)))); 191 192 /* 6. 0x1f[7:0] = 0x07 */ 193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07); 194 195 if (b_reg_hwparafile == 1) 196 rtstatus = _rtl8723e_phy_bb8192c_config_parafile(hw); 197 return rtstatus; 198 } 199 200 bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw) 201 { 202 return rtl8723e_phy_rf6052_config(hw); 203 } 204 205 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw) 206 { 207 struct rtl_priv *rtlpriv = rtl_priv(hw); 208 struct rtl_phy *rtlphy = &rtlpriv->phy; 209 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 210 bool rtstatus; 211 212 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n"); 213 rtstatus = _rtl8723e_phy_config_bb_with_headerfile(hw, 214 BASEBAND_CONFIG_PHY_REG); 215 if (rtstatus != true) { 216 pr_err("Write BB Reg Fail!!\n"); 217 return false; 218 } 219 220 if (rtlphy->rf_type == RF_1T2R) { 221 _rtl8723e_phy_bb_config_1t(hw); 222 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); 223 } 224 if (rtlefuse->autoload_failflag == false) { 225 rtlphy->pwrgroup_cnt = 0; 226 rtstatus = _rtl8723e_phy_config_bb_with_pgheaderfile(hw, 227 BASEBAND_CONFIG_PHY_REG); 228 } 229 if (rtstatus != true) { 230 pr_err("BB_PG Reg Fail!!\n"); 231 return false; 232 } 233 rtstatus = 234 _rtl8723e_phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB); 235 if (rtstatus != true) { 236 pr_err("AGC Table Fail\n"); 237 return false; 238 } 239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 240 RFPGA0_XA_HSSIPARAMETER2, 241 0x200)); 242 243 return true; 244 } 245 246 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 247 { 248 struct rtl_priv *rtlpriv = rtl_priv(hw); 249 u32 i; 250 u32 arraylength; 251 u32 *ptrarray; 252 253 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n"); 254 arraylength = RTL8723E_MACARRAYLENGTH; 255 ptrarray = RTL8723EMAC_ARRAY; 256 257 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 258 "Img:RTL8192CEMAC_2T_ARRAY\n"); 259 for (i = 0; i < arraylength; i = i + 2) 260 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 261 return true; 262 } 263 264 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 265 u8 configtype) 266 { 267 int i; 268 u32 *phy_regarray_table; 269 u32 *agctab_array_table; 270 u16 phy_reg_arraylen, agctab_arraylen; 271 struct rtl_priv *rtlpriv = rtl_priv(hw); 272 273 agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH; 274 agctab_array_table = RTL8723EAGCTAB_1TARRAY; 275 phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH; 276 phy_regarray_table = RTL8723EPHY_REG_1TARRAY; 277 if (configtype == BASEBAND_CONFIG_PHY_REG) { 278 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 279 if (phy_regarray_table[i] == 0xfe) 280 mdelay(50); 281 else if (phy_regarray_table[i] == 0xfd) 282 mdelay(5); 283 else if (phy_regarray_table[i] == 0xfc) 284 mdelay(1); 285 else if (phy_regarray_table[i] == 0xfb) 286 udelay(50); 287 else if (phy_regarray_table[i] == 0xfa) 288 udelay(5); 289 else if (phy_regarray_table[i] == 0xf9) 290 udelay(1); 291 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 292 phy_regarray_table[i + 1]); 293 udelay(1); 294 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 295 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 296 phy_regarray_table[i], 297 phy_regarray_table[i + 1]); 298 } 299 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 300 for (i = 0; i < agctab_arraylen; i = i + 2) { 301 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, 302 agctab_array_table[i + 1]); 303 udelay(1); 304 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 305 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 306 agctab_array_table[i], 307 agctab_array_table[i + 1]); 308 } 309 } 310 return true; 311 } 312 313 static void store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 314 u32 regaddr, u32 bitmask, 315 u32 data) 316 { 317 struct rtl_priv *rtlpriv = rtl_priv(hw); 318 struct rtl_phy *rtlphy = &rtlpriv->phy; 319 320 if (regaddr == RTXAGC_A_RATE18_06) { 321 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] = 322 data; 323 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 324 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", 325 rtlphy->pwrgroup_cnt, 326 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 327 pwrgroup_cnt][0]); 328 } 329 if (regaddr == RTXAGC_A_RATE54_24) { 330 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] = 331 data; 332 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 333 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", 334 rtlphy->pwrgroup_cnt, 335 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 336 pwrgroup_cnt][1]); 337 } 338 if (regaddr == RTXAGC_A_CCK1_MCS32) { 339 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] = 340 data; 341 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 342 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", 343 rtlphy->pwrgroup_cnt, 344 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 345 pwrgroup_cnt][6]); 346 } 347 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { 348 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] = 349 data; 350 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 351 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", 352 rtlphy->pwrgroup_cnt, 353 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 354 pwrgroup_cnt][7]); 355 } 356 if (regaddr == RTXAGC_A_MCS03_MCS00) { 357 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] = 358 data; 359 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 360 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", 361 rtlphy->pwrgroup_cnt, 362 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 363 pwrgroup_cnt][2]); 364 } 365 if (regaddr == RTXAGC_A_MCS07_MCS04) { 366 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] = 367 data; 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 369 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", 370 rtlphy->pwrgroup_cnt, 371 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 372 pwrgroup_cnt][3]); 373 } 374 if (regaddr == RTXAGC_A_MCS11_MCS08) { 375 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] = 376 data; 377 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 378 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", 379 rtlphy->pwrgroup_cnt, 380 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 381 pwrgroup_cnt][4]); 382 } 383 if (regaddr == RTXAGC_A_MCS15_MCS12) { 384 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] = 385 data; 386 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 387 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", 388 rtlphy->pwrgroup_cnt, 389 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 390 pwrgroup_cnt][5]); 391 } 392 if (regaddr == RTXAGC_B_RATE18_06) { 393 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] = 394 data; 395 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 396 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", 397 rtlphy->pwrgroup_cnt, 398 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 399 pwrgroup_cnt][8]); 400 } 401 if (regaddr == RTXAGC_B_RATE54_24) { 402 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] = 403 data; 404 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 405 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", 406 rtlphy->pwrgroup_cnt, 407 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 408 pwrgroup_cnt][9]); 409 } 410 if (regaddr == RTXAGC_B_CCK1_55_MCS32) { 411 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] = 412 data; 413 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 414 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", 415 rtlphy->pwrgroup_cnt, 416 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 417 pwrgroup_cnt][14]); 418 } 419 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { 420 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] = 421 data; 422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 423 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", 424 rtlphy->pwrgroup_cnt, 425 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 426 pwrgroup_cnt][15]); 427 } 428 if (regaddr == RTXAGC_B_MCS03_MCS00) { 429 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] = 430 data; 431 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 432 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", 433 rtlphy->pwrgroup_cnt, 434 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 435 pwrgroup_cnt][10]); 436 } 437 if (regaddr == RTXAGC_B_MCS07_MCS04) { 438 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] = 439 data; 440 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 441 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", 442 rtlphy->pwrgroup_cnt, 443 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 444 pwrgroup_cnt][11]); 445 } 446 if (regaddr == RTXAGC_B_MCS11_MCS08) { 447 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] = 448 data; 449 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 450 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", 451 rtlphy->pwrgroup_cnt, 452 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 453 pwrgroup_cnt][12]); 454 } 455 if (regaddr == RTXAGC_B_MCS15_MCS12) { 456 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] = 457 data; 458 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 459 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", 460 rtlphy->pwrgroup_cnt, 461 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> 462 pwrgroup_cnt][13]); 463 464 rtlphy->pwrgroup_cnt++; 465 } 466 } 467 468 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 469 u8 configtype) 470 { 471 struct rtl_priv *rtlpriv = rtl_priv(hw); 472 int i; 473 u32 *phy_regarray_table_pg; 474 u16 phy_regarray_pg_len; 475 476 phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH; 477 phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG; 478 479 if (configtype == BASEBAND_CONFIG_PHY_REG) { 480 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 481 if (phy_regarray_table_pg[i] == 0xfe) 482 mdelay(50); 483 else if (phy_regarray_table_pg[i] == 0xfd) 484 mdelay(5); 485 else if (phy_regarray_table_pg[i] == 0xfc) 486 mdelay(1); 487 else if (phy_regarray_table_pg[i] == 0xfb) 488 udelay(50); 489 else if (phy_regarray_table_pg[i] == 0xfa) 490 udelay(5); 491 else if (phy_regarray_table_pg[i] == 0xf9) 492 udelay(1); 493 494 store_pwrindex_diffrate_offset(hw, 495 phy_regarray_table_pg[i], 496 phy_regarray_table_pg[i + 1], 497 phy_regarray_table_pg[i + 2]); 498 } 499 } else { 500 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 501 "configtype != BaseBand_Config_PHY_REG\n"); 502 } 503 return true; 504 } 505 506 bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 507 enum radio_path rfpath) 508 { 509 int i; 510 bool rtstatus = true; 511 u32 *radioa_array_table; 512 u16 radioa_arraylen; 513 514 radioa_arraylen = RTL8723ERADIOA_1TARRAYLENGTH; 515 radioa_array_table = RTL8723E_RADIOA_1TARRAY; 516 517 rtstatus = true; 518 519 switch (rfpath) { 520 case RF90_PATH_A: 521 for (i = 0; i < radioa_arraylen; i = i + 2) { 522 if (radioa_array_table[i] == 0xfe) { 523 mdelay(50); 524 } else if (radioa_array_table[i] == 0xfd) { 525 mdelay(5); 526 } else if (radioa_array_table[i] == 0xfc) { 527 mdelay(1); 528 } else if (radioa_array_table[i] == 0xfb) { 529 udelay(50); 530 } else if (radioa_array_table[i] == 0xfa) { 531 udelay(5); 532 } else if (radioa_array_table[i] == 0xf9) { 533 udelay(1); 534 } else { 535 rtl_set_rfreg(hw, rfpath, radioa_array_table[i], 536 RFREG_OFFSET_MASK, 537 radioa_array_table[i + 1]); 538 udelay(1); 539 } 540 } 541 break; 542 case RF90_PATH_B: 543 case RF90_PATH_C: 544 case RF90_PATH_D: 545 break; 546 } 547 return true; 548 } 549 550 void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 551 { 552 struct rtl_priv *rtlpriv = rtl_priv(hw); 553 struct rtl_phy *rtlphy = &rtlpriv->phy; 554 555 rtlphy->default_initialgain[0] = 556 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 557 rtlphy->default_initialgain[1] = 558 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 559 rtlphy->default_initialgain[2] = 560 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 561 rtlphy->default_initialgain[3] = 562 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 563 564 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 565 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 566 rtlphy->default_initialgain[0], 567 rtlphy->default_initialgain[1], 568 rtlphy->default_initialgain[2], 569 rtlphy->default_initialgain[3]); 570 571 rtlphy->framesync = (u8) rtl_get_bbreg(hw, 572 ROFDM0_RXDETECTOR3, MASKBYTE0); 573 rtlphy->framesync_c34 = rtl_get_bbreg(hw, 574 ROFDM0_RXDETECTOR2, MASKDWORD); 575 576 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 577 "Default framesync (0x%x) = 0x%x\n", 578 ROFDM0_RXDETECTOR3, rtlphy->framesync); 579 } 580 581 void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 582 { 583 struct rtl_priv *rtlpriv = rtl_priv(hw); 584 struct rtl_phy *rtlphy = &rtlpriv->phy; 585 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 586 u8 txpwr_level; 587 long txpwr_dbm; 588 589 txpwr_level = rtlphy->cur_cck_txpwridx; 590 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, 591 WIRELESS_MODE_B, txpwr_level); 592 txpwr_level = rtlphy->cur_ofdm24g_txpwridx + 593 rtlefuse->legacy_ht_txpowerdiff; 594 if (rtl8723_phy_txpwr_idx_to_dbm(hw, 595 WIRELESS_MODE_G, 596 txpwr_level) > txpwr_dbm) 597 txpwr_dbm = 598 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 599 txpwr_level); 600 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 601 if (rtl8723_phy_txpwr_idx_to_dbm(hw, 602 WIRELESS_MODE_N_24G, 603 txpwr_level) > txpwr_dbm) 604 txpwr_dbm = 605 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 606 txpwr_level); 607 *powerlevel = txpwr_dbm; 608 } 609 610 static void _rtl8723e_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 611 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 612 { 613 struct rtl_priv *rtlpriv = rtl_priv(hw); 614 struct rtl_phy *rtlphy = &rtlpriv->phy; 615 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 616 u8 index = (channel - 1); 617 618 cckpowerlevel[RF90_PATH_A] = 619 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; 620 cckpowerlevel[RF90_PATH_B] = 621 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; 622 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) { 623 ofdmpowerlevel[RF90_PATH_A] = 624 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; 625 ofdmpowerlevel[RF90_PATH_B] = 626 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; 627 } else if (get_rf_type(rtlphy) == RF_2T2R) { 628 ofdmpowerlevel[RF90_PATH_A] = 629 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; 630 ofdmpowerlevel[RF90_PATH_B] = 631 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; 632 } 633 } 634 635 static void _rtl8723e_ccxpower_index_check(struct ieee80211_hw *hw, 636 u8 channel, u8 *cckpowerlevel, 637 u8 *ofdmpowerlevel) 638 { 639 struct rtl_priv *rtlpriv = rtl_priv(hw); 640 struct rtl_phy *rtlphy = &rtlpriv->phy; 641 642 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 643 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 644 645 } 646 647 void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 648 { 649 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 650 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 651 652 if (rtlefuse->txpwr_fromeprom == false) 653 return; 654 _rtl8723e_get_txpower_index(hw, channel, 655 &cckpowerlevel[0], &ofdmpowerlevel[0]); 656 _rtl8723e_ccxpower_index_check(hw, 657 channel, &cckpowerlevel[0], 658 &ofdmpowerlevel[0]); 659 rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 660 rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); 661 } 662 663 bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm) 664 { 665 struct rtl_priv *rtlpriv = rtl_priv(hw); 666 struct rtl_phy *rtlphy = &rtlpriv->phy; 667 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 668 u8 idx; 669 u8 rf_path; 670 u8 ccktxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw, 671 WIRELESS_MODE_B, 672 power_indbm); 673 u8 ofdmtxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw, 674 WIRELESS_MODE_N_24G, 675 power_indbm); 676 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0) 677 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff; 678 else 679 ofdmtxpwridx = 0; 680 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE, 681 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n", 682 power_indbm, ccktxpwridx, ofdmtxpwridx); 683 for (idx = 0; idx < 14; idx++) { 684 for (rf_path = 0; rf_path < 2; rf_path++) { 685 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx; 686 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] = 687 ofdmtxpwridx; 688 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] = 689 ofdmtxpwridx; 690 } 691 } 692 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); 693 return true; 694 } 695 696 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw, 697 enum wireless_mode wirelessmode, 698 long power_indbm) 699 { 700 u8 txpwridx; 701 long offset; 702 703 switch (wirelessmode) { 704 case WIRELESS_MODE_B: 705 offset = -7; 706 break; 707 case WIRELESS_MODE_G: 708 case WIRELESS_MODE_N_24G: 709 offset = -8; 710 break; 711 default: 712 offset = -8; 713 break; 714 } 715 716 if ((power_indbm - offset) > 0) 717 txpwridx = (u8)((power_indbm - offset) * 2); 718 else 719 txpwridx = 0; 720 721 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S) 722 txpwridx = MAX_TXPWR_IDX_NMODE_92S; 723 724 return txpwridx; 725 } 726 727 void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) 728 { 729 struct rtl_priv *rtlpriv = rtl_priv(hw); 730 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 731 enum io_type iotype; 732 733 if (!is_hal_stop(rtlhal)) { 734 switch (operation) { 735 case SCAN_OPT_BACKUP_BAND0: 736 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 737 rtlpriv->cfg->ops->set_hw_reg(hw, 738 HW_VAR_IO_CMD, 739 (u8 *)&iotype); 740 741 break; 742 case SCAN_OPT_RESTORE: 743 iotype = IO_CMD_RESUME_DM_BY_SCAN; 744 rtlpriv->cfg->ops->set_hw_reg(hw, 745 HW_VAR_IO_CMD, 746 (u8 *)&iotype); 747 break; 748 default: 749 pr_err("Unknown Scan Backup operation.\n"); 750 break; 751 } 752 } 753 } 754 755 void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 756 { 757 struct rtl_priv *rtlpriv = rtl_priv(hw); 758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 759 struct rtl_phy *rtlphy = &rtlpriv->phy; 760 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 761 u8 reg_bw_opmode; 762 u8 reg_prsr_rsc; 763 764 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 765 "Switch to %s bandwidth\n", 766 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 767 "20MHz" : "40MHz"); 768 769 if (is_hal_stop(rtlhal)) { 770 rtlphy->set_bwmode_inprogress = false; 771 return; 772 } 773 774 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 775 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 776 777 switch (rtlphy->current_chan_bw) { 778 case HT_CHANNEL_WIDTH_20: 779 reg_bw_opmode |= BW_OPMODE_20MHZ; 780 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 781 break; 782 case HT_CHANNEL_WIDTH_20_40: 783 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 784 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 785 reg_prsr_rsc = 786 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); 787 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 788 break; 789 default: 790 pr_err("unknown bandwidth: %#X\n", 791 rtlphy->current_chan_bw); 792 break; 793 } 794 795 switch (rtlphy->current_chan_bw) { 796 case HT_CHANNEL_WIDTH_20: 797 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 798 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 799 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 800 break; 801 case HT_CHANNEL_WIDTH_20_40: 802 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 803 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 804 805 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 806 (mac->cur_40_prime_sc >> 1)); 807 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 808 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); 809 810 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 811 (mac->cur_40_prime_sc == 812 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 813 break; 814 default: 815 pr_err("unknown bandwidth: %#X\n", 816 rtlphy->current_chan_bw); 817 break; 818 } 819 rtl8723e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 820 rtlphy->set_bwmode_inprogress = false; 821 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 822 } 823 824 void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw, 825 enum nl80211_channel_type ch_type) 826 { 827 struct rtl_priv *rtlpriv = rtl_priv(hw); 828 struct rtl_phy *rtlphy = &rtlpriv->phy; 829 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 830 u8 tmp_bw = rtlphy->current_chan_bw; 831 832 if (rtlphy->set_bwmode_inprogress) 833 return; 834 rtlphy->set_bwmode_inprogress = true; 835 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 836 rtl8723e_phy_set_bw_mode_callback(hw); 837 } else { 838 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 839 "false driver sleep or unload\n"); 840 rtlphy->set_bwmode_inprogress = false; 841 rtlphy->current_chan_bw = tmp_bw; 842 } 843 } 844 845 void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw) 846 { 847 struct rtl_priv *rtlpriv = rtl_priv(hw); 848 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 849 struct rtl_phy *rtlphy = &rtlpriv->phy; 850 u32 delay; 851 852 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 853 "switch to channel%d\n", rtlphy->current_channel); 854 if (is_hal_stop(rtlhal)) 855 return; 856 do { 857 if (!rtlphy->sw_chnl_inprogress) 858 break; 859 if (!_rtl8723e_phy_sw_chnl_step_by_step 860 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, 861 &rtlphy->sw_chnl_step, &delay)) { 862 if (delay > 0) 863 mdelay(delay); 864 else 865 continue; 866 } else { 867 rtlphy->sw_chnl_inprogress = false; 868 } 869 break; 870 } while (true); 871 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 872 } 873 874 u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw) 875 { 876 struct rtl_priv *rtlpriv = rtl_priv(hw); 877 struct rtl_phy *rtlphy = &rtlpriv->phy; 878 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 879 880 if (rtlphy->sw_chnl_inprogress) 881 return 0; 882 if (rtlphy->set_bwmode_inprogress) 883 return 0; 884 WARN_ONCE((rtlphy->current_channel > 14), 885 "rtl8723ae: WIRELESS_MODE_G but channel>14"); 886 rtlphy->sw_chnl_inprogress = true; 887 rtlphy->sw_chnl_stage = 0; 888 rtlphy->sw_chnl_step = 0; 889 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 890 rtl8723e_phy_sw_chnl_callback(hw); 891 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 892 "sw_chnl_inprogress false schedule workitem\n"); 893 rtlphy->sw_chnl_inprogress = false; 894 } else { 895 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 896 "sw_chnl_inprogress false driver sleep or unload\n"); 897 rtlphy->sw_chnl_inprogress = false; 898 } 899 return 1; 900 } 901 902 static void _rtl8723e_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel) 903 { 904 struct rtl_priv *rtlpriv = rtl_priv(hw); 905 struct rtl_phy *rtlphy = &rtlpriv->phy; 906 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 907 908 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { 909 if (channel == 6 && rtlphy->current_chan_bw == 910 HT_CHANNEL_WIDTH_20) 911 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, 912 MASKDWORD, 0x00255); 913 else{ 914 u32 backuprf0x1a = (u32)rtl_get_rfreg(hw, 915 RF90_PATH_A, RF_RX_G1, 916 RFREG_OFFSET_MASK); 917 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, 918 MASKDWORD, backuprf0x1a); 919 } 920 } 921 } 922 923 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 924 u8 channel, u8 *stage, u8 *step, 925 u32 *delay) 926 { 927 struct rtl_priv *rtlpriv = rtl_priv(hw); 928 struct rtl_phy *rtlphy = &rtlpriv->phy; 929 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 930 u32 precommoncmdcnt; 931 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 932 u32 postcommoncmdcnt; 933 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 934 u32 rfdependcmdcnt; 935 struct swchnlcmd *currentcmd = NULL; 936 u8 rfpath; 937 u8 num_total_rfpath = rtlphy->num_total_rfpath; 938 939 precommoncmdcnt = 0; 940 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 941 MAX_PRECMD_CNT, 942 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 943 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 944 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 945 946 postcommoncmdcnt = 0; 947 948 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 949 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 950 951 rfdependcmdcnt = 0; 952 953 WARN_ONCE((channel < 1 || channel > 14), 954 "rtl8723ae: illegal channel for Zebra: %d\n", channel); 955 956 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 957 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 958 RF_CHNLBW, channel, 10); 959 960 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 961 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 962 0); 963 964 do { 965 switch (*stage) { 966 case 0: 967 currentcmd = &precommoncmd[*step]; 968 break; 969 case 1: 970 currentcmd = &rfdependcmd[*step]; 971 break; 972 case 2: 973 currentcmd = &postcommoncmd[*step]; 974 break; 975 default: 976 pr_err("Invalid 'stage' = %d, Check it!\n", 977 *stage); 978 return true; 979 } 980 981 if (currentcmd->cmdid == CMDID_END) { 982 if ((*stage) == 2) { 983 return true; 984 } else { 985 (*stage)++; 986 (*step) = 0; 987 continue; 988 } 989 } 990 991 switch (currentcmd->cmdid) { 992 case CMDID_SET_TXPOWEROWER_LEVEL: 993 rtl8723e_phy_set_txpower_level(hw, channel); 994 break; 995 case CMDID_WRITEPORT_ULONG: 996 rtl_write_dword(rtlpriv, currentcmd->para1, 997 currentcmd->para2); 998 break; 999 case CMDID_WRITEPORT_USHORT: 1000 rtl_write_word(rtlpriv, currentcmd->para1, 1001 (u16) currentcmd->para2); 1002 break; 1003 case CMDID_WRITEPORT_UCHAR: 1004 rtl_write_byte(rtlpriv, currentcmd->para1, 1005 (u8) currentcmd->para2); 1006 break; 1007 case CMDID_RF_WRITEREG: 1008 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 1009 rtlphy->rfreg_chnlval[rfpath] = 1010 ((rtlphy->rfreg_chnlval[rfpath] & 1011 0xfffffc00) | currentcmd->para2); 1012 1013 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1014 currentcmd->para1, 1015 RFREG_OFFSET_MASK, 1016 rtlphy->rfreg_chnlval[rfpath]); 1017 } 1018 _rtl8723e_phy_sw_rf_seting(hw, channel); 1019 break; 1020 default: 1021 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1022 "switch case %#x not processed\n", 1023 currentcmd->cmdid); 1024 break; 1025 } 1026 1027 break; 1028 } while (true); 1029 1030 (*delay) = currentcmd->msdelay; 1031 (*step)++; 1032 return false; 1033 } 1034 1035 static u8 _rtl8723e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1036 { 1037 u32 reg_eac, reg_e94, reg_e9c, reg_ea4; 1038 u8 result = 0x00; 1039 1040 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); 1041 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); 1042 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); 1043 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 1044 config_pathb ? 0x28160202 : 0x28160502); 1045 1046 if (config_pathb) { 1047 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); 1048 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); 1049 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); 1050 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); 1051 } 1052 1053 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); 1054 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1055 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1056 1057 mdelay(IQK_DELAY_TIME); 1058 1059 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1060 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1061 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1062 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1063 1064 if (!(reg_eac & BIT(28)) && 1065 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1066 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1067 result |= 0x01; 1068 else 1069 return result; 1070 1071 if (!(reg_eac & BIT(27)) && 1072 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && 1073 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) 1074 result |= 0x02; 1075 return result; 1076 } 1077 1078 static u8 _rtl8723e_phy_path_b_iqk(struct ieee80211_hw *hw) 1079 { 1080 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1081 u8 result = 0x00; 1082 1083 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1084 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1085 mdelay(IQK_DELAY_TIME); 1086 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1087 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1088 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1089 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1090 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1091 1092 if (!(reg_eac & BIT(31)) && 1093 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && 1094 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) 1095 result |= 0x01; 1096 else 1097 return result; 1098 if (!(reg_eac & BIT(30)) && 1099 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && 1100 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) 1101 result |= 0x02; 1102 return result; 1103 } 1104 1105 static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw, 1106 long result[][8], u8 c1, u8 c2) 1107 { 1108 u32 i, j, diff, simularity_bitmap, bound; 1109 1110 u8 final_candidate[2] = { 0xFF, 0xFF }; 1111 bool bresult = true; 1112 1113 bound = 4; 1114 1115 simularity_bitmap = 0; 1116 1117 for (i = 0; i < bound; i++) { 1118 diff = (result[c1][i] > result[c2][i]) ? 1119 (result[c1][i] - result[c2][i]) : 1120 (result[c2][i] - result[c1][i]); 1121 1122 if (diff > MAX_TOLERANCE) { 1123 if ((i == 2 || i == 6) && !simularity_bitmap) { 1124 if (result[c1][i] + result[c1][i + 1] == 0) 1125 final_candidate[(i / 4)] = c2; 1126 else if (result[c2][i] + result[c2][i + 1] == 0) 1127 final_candidate[(i / 4)] = c1; 1128 else 1129 simularity_bitmap = simularity_bitmap | 1130 (1 << i); 1131 } else 1132 simularity_bitmap = 1133 simularity_bitmap | (1 << i); 1134 } 1135 } 1136 1137 if (simularity_bitmap == 0) { 1138 for (i = 0; i < (bound / 4); i++) { 1139 if (final_candidate[i] != 0xFF) { 1140 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 1141 result[3][j] = 1142 result[final_candidate[i]][j]; 1143 bresult = false; 1144 } 1145 } 1146 return bresult; 1147 } else if (!(simularity_bitmap & 0x0F)) { 1148 for (i = 0; i < 4; i++) 1149 result[3][i] = result[c1][i]; 1150 return false; 1151 } else { 1152 return false; 1153 } 1154 1155 } 1156 1157 static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, 1158 long result[][8], u8 t, bool is2t) 1159 { 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 struct rtl_phy *rtlphy = &rtlpriv->phy; 1162 u32 i; 1163 u8 patha_ok, pathb_ok; 1164 u32 adda_reg[IQK_ADDA_REG_NUM] = { 1165 0x85c, 0xe6c, 0xe70, 0xe74, 1166 0xe78, 0xe7c, 0xe80, 0xe84, 1167 0xe88, 0xe8c, 0xed0, 0xed4, 1168 0xed8, 0xedc, 0xee0, 0xeec 1169 }; 1170 1171 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1172 0x522, 0x550, 0x551, 0x040 1173 }; 1174 1175 const u32 retrycount = 2; 1176 1177 u32 bbvalue; 1178 1179 if (t == 0) { 1180 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); 1181 1182 rtl8723_save_adda_registers(hw, adda_reg, 1183 rtlphy->adda_backup, 16); 1184 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg, 1185 rtlphy->iqk_mac_backup); 1186 } 1187 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t); 1188 if (t == 0) { 1189 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1190 RFPGA0_XA_HSSIPARAMETER1, 1191 BIT(8)); 1192 } 1193 1194 if (!rtlphy->rfpi_enable) 1195 rtl8723_phy_pi_mode_switch(hw, true); 1196 if (t == 0) { 1197 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); 1198 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); 1199 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); 1200 } 1201 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); 1202 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); 1203 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); 1204 if (is2t) { 1205 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1206 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); 1207 } 1208 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg, 1209 rtlphy->iqk_mac_backup); 1210 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); 1211 if (is2t) 1212 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); 1213 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1214 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1215 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1216 for (i = 0; i < retrycount; i++) { 1217 patha_ok = _rtl8723e_phy_path_a_iqk(hw, is2t); 1218 if (patha_ok == 0x03) { 1219 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1220 0x3FF0000) >> 16; 1221 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1222 0x3FF0000) >> 16; 1223 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1224 0x3FF0000) >> 16; 1225 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1226 0x3FF0000) >> 16; 1227 break; 1228 } else if (i == (retrycount - 1) && patha_ok == 0x01) 1229 1230 result[t][0] = (rtl_get_bbreg(hw, 0xe94, 1231 MASKDWORD) & 0x3FF0000) >> 1232 16; 1233 result[t][1] = 1234 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; 1235 1236 } 1237 1238 if (is2t) { 1239 rtl8723_phy_path_a_standby(hw); 1240 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t); 1241 for (i = 0; i < retrycount; i++) { 1242 pathb_ok = _rtl8723e_phy_path_b_iqk(hw); 1243 if (pathb_ok == 0x03) { 1244 result[t][4] = (rtl_get_bbreg(hw, 1245 0xeb4, 1246 MASKDWORD) & 1247 0x3FF0000) >> 16; 1248 result[t][5] = 1249 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1250 0x3FF0000) >> 16; 1251 result[t][6] = 1252 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 1253 0x3FF0000) >> 16; 1254 result[t][7] = 1255 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 1256 0x3FF0000) >> 16; 1257 break; 1258 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1259 result[t][4] = (rtl_get_bbreg(hw, 1260 0xeb4, 1261 MASKDWORD) & 1262 0x3FF0000) >> 16; 1263 } 1264 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1265 0x3FF0000) >> 16; 1266 } 1267 } 1268 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); 1269 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); 1270 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); 1271 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1272 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); 1273 if (is2t) 1274 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); 1275 if (t != 0) { 1276 if (!rtlphy->rfpi_enable) 1277 rtl8723_phy_pi_mode_switch(hw, false); 1278 rtl8723_phy_reload_adda_registers(hw, adda_reg, 1279 rtlphy->adda_backup, 16); 1280 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg, 1281 rtlphy->iqk_mac_backup); 1282 } 1283 } 1284 1285 static void _rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 1286 { 1287 u8 tmpreg; 1288 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 1289 struct rtl_priv *rtlpriv = rtl_priv(hw); 1290 1291 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 1292 1293 if ((tmpreg & 0x70) != 0) 1294 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 1295 else 1296 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1297 1298 if ((tmpreg & 0x70) != 0) { 1299 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); 1300 1301 if (is2t) 1302 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, 1303 MASK12BITS); 1304 1305 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, 1306 (rf_a_mode & 0x8FFFF) | 0x10000); 1307 1308 if (is2t) 1309 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 1310 (rf_b_mode & 0x8FFFF) | 0x10000); 1311 } 1312 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); 1313 1314 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); 1315 1316 mdelay(100); 1317 1318 if ((tmpreg & 0x70) != 0) { 1319 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 1320 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); 1321 1322 if (is2t) 1323 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 1324 rf_b_mode); 1325 } else { 1326 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1327 } 1328 } 1329 1330 static void _rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, 1331 bool bmain, bool is2t) 1332 { 1333 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1334 1335 if (is_hal_stop(rtlhal)) { 1336 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); 1337 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); 1338 } 1339 if (is2t) { 1340 if (bmain) 1341 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1342 BIT(5) | BIT(6), 0x1); 1343 else 1344 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1345 BIT(5) | BIT(6), 0x2); 1346 } else { 1347 if (bmain) 1348 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); 1349 else 1350 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); 1351 1352 } 1353 1354 } 1355 1356 #undef IQK_ADDA_REG_NUM 1357 #undef IQK_DELAY_TIME 1358 1359 void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 1360 { 1361 struct rtl_priv *rtlpriv = rtl_priv(hw); 1362 struct rtl_phy *rtlphy = &rtlpriv->phy; 1363 1364 long result[4][8]; 1365 u8 i, final_candidate; 1366 bool b_patha_ok, b_pathb_ok; 1367 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, 1368 reg_ecc, reg_tmp = 0; 1369 bool is12simular, is13simular, is23simular; 1370 u32 iqk_bb_reg[10] = { 1371 ROFDM0_XARXIQIMBALANCE, 1372 ROFDM0_XBRXIQIMBALANCE, 1373 ROFDM0_ECCATHRESHOLD, 1374 ROFDM0_AGCRSSITABLE, 1375 ROFDM0_XATXIQIMBALANCE, 1376 ROFDM0_XBTXIQIMBALANCE, 1377 ROFDM0_XCTXIQIMBALANCE, 1378 ROFDM0_XCTXAFE, 1379 ROFDM0_XDTXAFE, 1380 ROFDM0_RXIQEXTANTA 1381 }; 1382 1383 if (b_recovery) { 1384 rtl8723_phy_reload_adda_registers(hw, 1385 iqk_bb_reg, 1386 rtlphy->iqk_bb_backup, 10); 1387 return; 1388 } 1389 for (i = 0; i < 8; i++) { 1390 result[0][i] = 0; 1391 result[1][i] = 0; 1392 result[2][i] = 0; 1393 result[3][i] = 0; 1394 } 1395 final_candidate = 0xff; 1396 b_patha_ok = false; 1397 b_pathb_ok = false; 1398 is12simular = false; 1399 is23simular = false; 1400 is13simular = false; 1401 for (i = 0; i < 3; i++) { 1402 _rtl8723e_phy_iq_calibrate(hw, result, i, false); 1403 if (i == 1) { 1404 is12simular = 1405 _rtl8723e_phy_simularity_compare(hw, result, 0, 1); 1406 if (is12simular) { 1407 final_candidate = 0; 1408 break; 1409 } 1410 } 1411 if (i == 2) { 1412 is13simular = 1413 _rtl8723e_phy_simularity_compare(hw, result, 0, 2); 1414 if (is13simular) { 1415 final_candidate = 0; 1416 break; 1417 } 1418 is23simular = 1419 _rtl8723e_phy_simularity_compare(hw, result, 1, 2); 1420 if (is23simular) 1421 final_candidate = 1; 1422 else { 1423 for (i = 0; i < 8; i++) 1424 reg_tmp += result[3][i]; 1425 1426 if (reg_tmp != 0) 1427 final_candidate = 3; 1428 else 1429 final_candidate = 0xFF; 1430 } 1431 } 1432 } 1433 for (i = 0; i < 4; i++) { 1434 reg_e94 = result[i][0]; 1435 reg_e9c = result[i][1]; 1436 reg_ea4 = result[i][2]; 1437 reg_eac = result[i][3]; 1438 reg_eb4 = result[i][4]; 1439 reg_ebc = result[i][5]; 1440 reg_ec4 = result[i][6]; 1441 reg_ecc = result[i][7]; 1442 } 1443 if (final_candidate != 0xff) { 1444 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; 1445 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1]; 1446 reg_ea4 = result[final_candidate][2]; 1447 reg_eac = result[final_candidate][3]; 1448 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4]; 1449 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5]; 1450 reg_ec4 = result[final_candidate][6]; 1451 reg_ecc = result[final_candidate][7]; 1452 b_patha_ok = true; 1453 b_pathb_ok = true; 1454 } else { 1455 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; 1456 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; 1457 } 1458 if (reg_e94 != 0) 1459 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, 1460 final_candidate, 1461 (reg_ea4 == 0)); 1462 rtl8723_save_adda_registers(hw, iqk_bb_reg, 1463 rtlphy->iqk_bb_backup, 10); 1464 } 1465 1466 void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw) 1467 { 1468 _rtl8723e_phy_lc_calibrate(hw, false); 1469 } 1470 1471 void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 1472 { 1473 _rtl8723e_phy_set_rfpath_switch(hw, bmain, false); 1474 } 1475 1476 bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 1477 { 1478 struct rtl_priv *rtlpriv = rtl_priv(hw); 1479 struct rtl_phy *rtlphy = &rtlpriv->phy; 1480 bool postprocessing = false; 1481 1482 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1483 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 1484 iotype, rtlphy->set_io_inprogress); 1485 do { 1486 switch (iotype) { 1487 case IO_CMD_RESUME_DM_BY_SCAN: 1488 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1489 "[IO CMD] Resume DM after scan.\n"); 1490 postprocessing = true; 1491 break; 1492 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 1493 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1494 "[IO CMD] Pause DM before scan.\n"); 1495 postprocessing = true; 1496 break; 1497 default: 1498 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1499 "switch case %#x not processed\n", iotype); 1500 break; 1501 } 1502 } while (false); 1503 if (postprocessing && !rtlphy->set_io_inprogress) { 1504 rtlphy->set_io_inprogress = true; 1505 rtlphy->current_io_type = iotype; 1506 } else { 1507 return false; 1508 } 1509 rtl8723e_phy_set_io(hw); 1510 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 1511 return true; 1512 } 1513 1514 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw) 1515 { 1516 struct rtl_priv *rtlpriv = rtl_priv(hw); 1517 struct rtl_phy *rtlphy = &rtlpriv->phy; 1518 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 1519 1520 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1521 "--->Cmd(%#x), set_io_inprogress(%d)\n", 1522 rtlphy->current_io_type, rtlphy->set_io_inprogress); 1523 switch (rtlphy->current_io_type) { 1524 case IO_CMD_RESUME_DM_BY_SCAN: 1525 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 1526 rtl8723e_dm_write_dig(hw); 1527 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); 1528 break; 1529 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 1530 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 1531 dm_digtable->cur_igvalue = 0x17; 1532 rtl8723e_dm_write_dig(hw); 1533 break; 1534 default: 1535 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1536 "switch case %#x not processed\n", 1537 rtlphy->current_io_type); 1538 break; 1539 } 1540 rtlphy->set_io_inprogress = false; 1541 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1542 "(%#x)\n", rtlphy->current_io_type); 1543 } 1544 1545 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw) 1546 { 1547 struct rtl_priv *rtlpriv = rtl_priv(hw); 1548 1549 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 1550 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 1551 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 1552 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1553 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 1554 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1555 } 1556 1557 static void _rtl8723e_phy_set_rf_sleep(struct ieee80211_hw *hw) 1558 { 1559 u32 u4b_tmp; 1560 u8 delay = 5; 1561 struct rtl_priv *rtlpriv = rtl_priv(hw); 1562 1563 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1564 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1565 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1566 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 1567 while (u4b_tmp != 0 && delay > 0) { 1568 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 1569 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1570 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1571 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 1572 delay--; 1573 } 1574 if (delay == 0) { 1575 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 1576 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1577 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 1578 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1579 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 1580 "Switch RF timeout !!!.\n"); 1581 return; 1582 } 1583 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1584 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 1585 } 1586 1587 static bool _rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw, 1588 enum rf_pwrstate rfpwr_state) 1589 { 1590 struct rtl_priv *rtlpriv = rtl_priv(hw); 1591 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1592 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1593 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1594 bool bresult = true; 1595 u8 i, queue_id; 1596 struct rtl8192_tx_ring *ring = NULL; 1597 1598 switch (rfpwr_state) { 1599 case ERFON: 1600 if ((ppsc->rfpwr_state == ERFOFF) && 1601 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 1602 bool rtstatus; 1603 u32 initializecount = 0; 1604 1605 do { 1606 initializecount++; 1607 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1608 "IPS Set eRf nic enable\n"); 1609 rtstatus = rtl_ps_enable_nic(hw); 1610 } while (!rtstatus && (initializecount < 10)); 1611 RT_CLEAR_PS_LEVEL(ppsc, 1612 RT_RF_OFF_LEVL_HALT_NIC); 1613 } else { 1614 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1615 "Set ERFON sleeped:%d ms\n", 1616 jiffies_to_msecs(jiffies - 1617 ppsc-> 1618 last_sleep_jiffies)); 1619 ppsc->last_awake_jiffies = jiffies; 1620 rtl8723e_phy_set_rf_on(hw); 1621 } 1622 if (mac->link_state == MAC80211_LINKED) { 1623 rtlpriv->cfg->ops->led_control(hw, 1624 LED_CTL_LINK); 1625 } else { 1626 rtlpriv->cfg->ops->led_control(hw, 1627 LED_CTL_NO_LINK); 1628 } 1629 break; 1630 case ERFOFF: 1631 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 1632 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1633 "IPS Set eRf nic disable\n"); 1634 rtl_ps_disable_nic(hw); 1635 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1636 } else { 1637 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 1638 rtlpriv->cfg->ops->led_control(hw, 1639 LED_CTL_NO_LINK); 1640 } else { 1641 rtlpriv->cfg->ops->led_control(hw, 1642 LED_CTL_POWER_OFF); 1643 } 1644 } 1645 break; 1646 case ERFSLEEP: 1647 if (ppsc->rfpwr_state == ERFOFF) 1648 break; 1649 for (queue_id = 0, i = 0; 1650 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 1651 ring = &pcipriv->dev.tx_ring[queue_id]; 1652 if (queue_id == BEACON_QUEUE || 1653 skb_queue_len(&ring->queue) == 0) { 1654 queue_id++; 1655 continue; 1656 } else { 1657 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1658 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 1659 (i + 1), queue_id, 1660 skb_queue_len(&ring->queue)); 1661 1662 udelay(10); 1663 i++; 1664 } 1665 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 1666 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1667 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 1668 MAX_DOZE_WAITING_TIMES_9x, 1669 queue_id, 1670 skb_queue_len(&ring->queue)); 1671 break; 1672 } 1673 } 1674 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1675 "Set ERFSLEEP awaked:%d ms\n", 1676 jiffies_to_msecs(jiffies - 1677 ppsc->last_awake_jiffies)); 1678 ppsc->last_sleep_jiffies = jiffies; 1679 _rtl8723e_phy_set_rf_sleep(hw); 1680 break; 1681 default: 1682 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 1683 "switch case %#x not processed\n", rfpwr_state); 1684 bresult = false; 1685 break; 1686 } 1687 if (bresult) 1688 ppsc->rfpwr_state = rfpwr_state; 1689 return bresult; 1690 } 1691 1692 bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw, 1693 enum rf_pwrstate rfpwr_state) 1694 { 1695 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1696 1697 bool bresult = false; 1698 1699 if (rfpwr_state == ppsc->rfpwr_state) 1700 return bresult; 1701 bresult = _rtl8723e_phy_set_rf_power_state(hw, rfpwr_state); 1702 return bresult; 1703 } 1704