1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "../rtl8723com/phy_common.h" 37 #include "dm.h" 38 #include "../rtl8723com/dm_common.h" 39 #include "fw.h" 40 #include "../rtl8723com/fw_common.h" 41 #include "led.h" 42 #include "hw.h" 43 #include "../pwrseqcmd.h" 44 #include "pwrseq.h" 45 #include "btc.h" 46 47 #define LLT_CONFIG 5 48 49 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 50 u8 set_bits, u8 clear_bits) 51 { 52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 53 struct rtl_priv *rtlpriv = rtl_priv(hw); 54 55 rtlpci->reg_bcn_ctrl_val |= set_bits; 56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 57 58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 59 } 60 61 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw) 62 { 63 struct rtl_priv *rtlpriv = rtl_priv(hw); 64 u8 tmp1byte; 65 66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 70 tmp1byte &= ~(BIT(0)); 71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 72 } 73 74 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw) 75 { 76 struct rtl_priv *rtlpriv = rtl_priv(hw); 77 u8 tmp1byte; 78 79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 83 tmp1byte |= BIT(1); 84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 85 } 86 87 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw) 88 { 89 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); 90 } 91 92 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw) 93 { 94 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); 95 } 96 97 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 98 { 99 struct rtl_priv *rtlpriv = rtl_priv(hw); 100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 102 103 switch (variable) { 104 case HW_VAR_RCR: 105 *((u32 *)(val)) = rtlpci->receive_config; 106 break; 107 case HW_VAR_RF_STATE: 108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 109 break; 110 case HW_VAR_FWLPS_RF_ON:{ 111 enum rf_pwrstate rfstate; 112 u32 val_rcr; 113 114 rtlpriv->cfg->ops->get_hw_reg(hw, 115 HW_VAR_RF_STATE, 116 (u8 *)(&rfstate)); 117 if (rfstate == ERFOFF) { 118 *((bool *)(val)) = true; 119 } else { 120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 121 val_rcr &= 0x00070000; 122 if (val_rcr) 123 *((bool *)(val)) = false; 124 else 125 *((bool *)(val)) = true; 126 } 127 break; 128 } 129 case HW_VAR_FW_PSMODE_STATUS: 130 *((bool *)(val)) = ppsc->fw_current_inpsmode; 131 break; 132 case HW_VAR_CORRECT_TSF:{ 133 u64 tsf; 134 u32 *ptsf_low = (u32 *)&tsf; 135 u32 *ptsf_high = ((u32 *)&tsf) + 1; 136 137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 139 140 *((u64 *)(val)) = tsf; 141 142 break; 143 } 144 case HAL_DEF_WOWLAN: 145 break; 146 default: 147 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 148 "switch case %#x not processed\n", variable); 149 break; 150 } 151 } 152 153 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 154 { 155 struct rtl_priv *rtlpriv = rtl_priv(hw); 156 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 157 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 158 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 159 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 160 u8 idx; 161 162 switch (variable) { 163 case HW_VAR_ETHER_ADDR:{ 164 for (idx = 0; idx < ETH_ALEN; idx++) { 165 rtl_write_byte(rtlpriv, (REG_MACID + idx), 166 val[idx]); 167 } 168 break; 169 } 170 case HW_VAR_BASIC_RATE:{ 171 u16 b_rate_cfg = ((u16 *)val)[0]; 172 u8 rate_index = 0; 173 174 b_rate_cfg = b_rate_cfg & 0x15f; 175 b_rate_cfg |= 0x01; 176 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 177 rtl_write_byte(rtlpriv, REG_RRSR + 1, 178 (b_rate_cfg >> 8) & 0xff); 179 while (b_rate_cfg > 0x1) { 180 b_rate_cfg = (b_rate_cfg >> 1); 181 rate_index++; 182 } 183 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 184 rate_index); 185 break; 186 } 187 case HW_VAR_BSSID:{ 188 for (idx = 0; idx < ETH_ALEN; idx++) { 189 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 190 val[idx]); 191 } 192 break; 193 } 194 case HW_VAR_SIFS:{ 195 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 196 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 197 198 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 199 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 200 201 if (!mac->ht_enable) 202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 203 0x0e0e); 204 else 205 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 206 *((u16 *)val)); 207 break; 208 } 209 case HW_VAR_SLOT_TIME:{ 210 u8 e_aci; 211 212 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 213 "HW_VAR_SLOT_TIME %x\n", val[0]); 214 215 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 216 217 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 218 rtlpriv->cfg->ops->set_hw_reg(hw, 219 HW_VAR_AC_PARAM, 220 (u8 *)(&e_aci)); 221 } 222 break; 223 } 224 case HW_VAR_ACK_PREAMBLE:{ 225 u8 reg_tmp; 226 u8 short_preamble = (bool)(*(u8 *)val); 227 228 reg_tmp = (mac->cur_40_prime_sc) << 5; 229 if (short_preamble) 230 reg_tmp |= 0x80; 231 232 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 233 break; 234 } 235 case HW_VAR_AMPDU_MIN_SPACE:{ 236 u8 min_spacing_to_set; 237 u8 sec_min_space; 238 239 min_spacing_to_set = *((u8 *)val); 240 if (min_spacing_to_set <= 7) { 241 sec_min_space = 0; 242 243 if (min_spacing_to_set < sec_min_space) 244 min_spacing_to_set = sec_min_space; 245 246 mac->min_space_cfg = ((mac->min_space_cfg & 247 0xf8) | 248 min_spacing_to_set); 249 250 *val = min_spacing_to_set; 251 252 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 253 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 254 mac->min_space_cfg); 255 256 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 257 mac->min_space_cfg); 258 } 259 break; 260 } 261 case HW_VAR_SHORTGI_DENSITY:{ 262 u8 density_to_set; 263 264 density_to_set = *((u8 *)val); 265 mac->min_space_cfg |= (density_to_set << 3); 266 267 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 268 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 269 mac->min_space_cfg); 270 271 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 272 mac->min_space_cfg); 273 274 break; 275 } 276 case HW_VAR_AMPDU_FACTOR:{ 277 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 278 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 279 u8 factor_toset; 280 u8 *p_regtoset = NULL; 281 u8 index = 0; 282 283 if ((rtlpriv->btcoexist.bt_coexistence) && 284 (rtlpriv->btcoexist.bt_coexist_type == 285 BT_CSR_BC4)) 286 p_regtoset = regtoset_bt; 287 else 288 p_regtoset = regtoset_normal; 289 290 factor_toset = *((u8 *)val); 291 if (factor_toset <= 3) { 292 factor_toset = (1 << (factor_toset + 2)); 293 if (factor_toset > 0xf) 294 factor_toset = 0xf; 295 296 for (index = 0; index < 4; index++) { 297 if ((p_regtoset[index] & 0xf0) > 298 (factor_toset << 4)) 299 p_regtoset[index] = 300 (p_regtoset[index] & 0x0f) | 301 (factor_toset << 4); 302 303 if ((p_regtoset[index] & 0x0f) > 304 factor_toset) 305 p_regtoset[index] = 306 (p_regtoset[index] & 0xf0) | 307 (factor_toset); 308 309 rtl_write_byte(rtlpriv, 310 (REG_AGGLEN_LMT + index), 311 p_regtoset[index]); 312 } 313 314 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 315 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 316 factor_toset); 317 } 318 break; 319 } 320 case HW_VAR_AC_PARAM:{ 321 u8 e_aci = *((u8 *)val); 322 323 rtl8723_dm_init_edca_turbo(hw); 324 325 if (rtlpci->acm_method != EACMWAY2_SW) 326 rtlpriv->cfg->ops->set_hw_reg(hw, 327 HW_VAR_ACM_CTRL, 328 (u8 *)(&e_aci)); 329 break; 330 } 331 case HW_VAR_ACM_CTRL:{ 332 u8 e_aci = *((u8 *)val); 333 union aci_aifsn *p_aci_aifsn = 334 (union aci_aifsn *)(&mac->ac[0].aifs); 335 u8 acm = p_aci_aifsn->f.acm; 336 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 337 338 acm_ctrl = 339 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 340 341 if (acm) { 342 switch (e_aci) { 343 case AC0_BE: 344 acm_ctrl |= ACMHW_BEQEN; 345 break; 346 case AC2_VI: 347 acm_ctrl |= ACMHW_VIQEN; 348 break; 349 case AC3_VO: 350 acm_ctrl |= ACMHW_VOQEN; 351 break; 352 default: 353 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 354 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 355 acm); 356 break; 357 } 358 } else { 359 switch (e_aci) { 360 case AC0_BE: 361 acm_ctrl &= (~ACMHW_BEQEN); 362 break; 363 case AC2_VI: 364 acm_ctrl &= (~ACMHW_VIQEN); 365 break; 366 case AC3_VO: 367 acm_ctrl &= (~ACMHW_VOQEN); 368 break; 369 default: 370 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 371 "switch case %#x not processed\n", 372 e_aci); 373 break; 374 } 375 } 376 377 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 378 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 379 acm_ctrl); 380 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 381 break; 382 } 383 case HW_VAR_RCR:{ 384 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 385 rtlpci->receive_config = ((u32 *)(val))[0]; 386 break; 387 } 388 case HW_VAR_RETRY_LIMIT:{ 389 u8 retry_limit = ((u8 *)(val))[0]; 390 391 rtl_write_word(rtlpriv, REG_RL, 392 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 393 retry_limit << RETRY_LIMIT_LONG_SHIFT); 394 break; 395 } 396 case HW_VAR_DUAL_TSF_RST: 397 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 398 break; 399 case HW_VAR_EFUSE_BYTES: 400 rtlefuse->efuse_usedbytes = *((u16 *)val); 401 break; 402 case HW_VAR_EFUSE_USAGE: 403 rtlefuse->efuse_usedpercentage = *((u8 *)val); 404 break; 405 case HW_VAR_IO_CMD: 406 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val)); 407 break; 408 case HW_VAR_WPA_CONFIG: 409 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 410 break; 411 case HW_VAR_SET_RPWM:{ 412 u8 rpwm_val; 413 414 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 415 udelay(1); 416 417 if (rpwm_val & BIT(7)) { 418 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 419 (*(u8 *)val)); 420 } else { 421 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 422 ((*(u8 *)val) | BIT(7))); 423 } 424 425 break; 426 } 427 case HW_VAR_H2C_FW_PWRMODE:{ 428 u8 psmode = (*(u8 *)val); 429 430 if (psmode != FW_PS_ACTIVE_MODE) 431 rtl8723e_dm_rf_saving(hw, true); 432 433 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 434 break; 435 } 436 case HW_VAR_FW_PSMODE_STATUS: 437 ppsc->fw_current_inpsmode = *((bool *)val); 438 break; 439 case HW_VAR_H2C_FW_JOINBSSRPT:{ 440 u8 mstatus = (*(u8 *)val); 441 u8 tmp_regcr, tmp_reg422; 442 bool b_recover = false; 443 444 if (mstatus == RT_MEDIA_CONNECT) { 445 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 446 NULL); 447 448 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 449 rtl_write_byte(rtlpriv, REG_CR + 1, 450 (tmp_regcr | BIT(0))); 451 452 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); 453 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); 454 455 tmp_reg422 = 456 rtl_read_byte(rtlpriv, 457 REG_FWHW_TXQ_CTRL + 2); 458 if (tmp_reg422 & BIT(6)) 459 b_recover = true; 460 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 461 tmp_reg422 & (~BIT(6))); 462 463 rtl8723e_set_fw_rsvdpagepkt(hw, 0); 464 465 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); 466 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); 467 468 if (b_recover) { 469 rtl_write_byte(rtlpriv, 470 REG_FWHW_TXQ_CTRL + 2, 471 tmp_reg422); 472 } 473 474 rtl_write_byte(rtlpriv, REG_CR + 1, 475 (tmp_regcr & ~(BIT(0)))); 476 } 477 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); 478 479 break; 480 } 481 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{ 482 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 483 break; 484 } 485 case HW_VAR_AID:{ 486 u16 u2btmp; 487 488 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 489 u2btmp &= 0xC000; 490 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 491 (u2btmp | mac->assoc_id)); 492 493 break; 494 } 495 case HW_VAR_CORRECT_TSF:{ 496 u8 btype_ibss = ((u8 *)(val))[0]; 497 498 if (btype_ibss) 499 _rtl8723e_stop_tx_beacon(hw); 500 501 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); 502 503 rtl_write_dword(rtlpriv, REG_TSFTR, 504 (u32)(mac->tsf & 0xffffffff)); 505 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 506 (u32)((mac->tsf >> 32) & 0xffffffff)); 507 508 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); 509 510 if (btype_ibss) 511 _rtl8723e_resume_tx_beacon(hw); 512 513 break; 514 } 515 case HW_VAR_FW_LPS_ACTION:{ 516 bool b_enter_fwlps = *((bool *)val); 517 u8 rpwm_val, fw_pwrmode; 518 bool fw_current_inps; 519 520 if (b_enter_fwlps) { 521 rpwm_val = 0x02; /* RF off */ 522 fw_current_inps = true; 523 rtlpriv->cfg->ops->set_hw_reg(hw, 524 HW_VAR_FW_PSMODE_STATUS, 525 (u8 *)(&fw_current_inps)); 526 rtlpriv->cfg->ops->set_hw_reg(hw, 527 HW_VAR_H2C_FW_PWRMODE, 528 (u8 *)(&ppsc->fwctrl_psmode)); 529 530 rtlpriv->cfg->ops->set_hw_reg(hw, 531 HW_VAR_SET_RPWM, 532 (u8 *)(&rpwm_val)); 533 } else { 534 rpwm_val = 0x0C; /* RF on */ 535 fw_pwrmode = FW_PS_ACTIVE_MODE; 536 fw_current_inps = false; 537 rtlpriv->cfg->ops->set_hw_reg(hw, 538 HW_VAR_SET_RPWM, 539 (u8 *)(&rpwm_val)); 540 rtlpriv->cfg->ops->set_hw_reg(hw, 541 HW_VAR_H2C_FW_PWRMODE, 542 (u8 *)(&fw_pwrmode)); 543 544 rtlpriv->cfg->ops->set_hw_reg(hw, 545 HW_VAR_FW_PSMODE_STATUS, 546 (u8 *)(&fw_current_inps)); 547 } 548 break; 549 } 550 default: 551 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 552 "switch case %#x not processed\n", variable); 553 break; 554 } 555 } 556 557 static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 558 { 559 struct rtl_priv *rtlpriv = rtl_priv(hw); 560 bool status = true; 561 long count = 0; 562 u32 value = _LLT_INIT_ADDR(address) | 563 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 564 565 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 566 567 do { 568 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 569 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 570 break; 571 572 if (count > POLLING_LLT_THRESHOLD) { 573 pr_err("Failed to polling write LLT done at address %d!\n", 574 address); 575 status = false; 576 break; 577 } 578 } while (++count); 579 580 return status; 581 } 582 583 static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw) 584 { 585 struct rtl_priv *rtlpriv = rtl_priv(hw); 586 unsigned short i; 587 u8 txpktbuf_bndy; 588 u8 maxpage; 589 bool status; 590 u8 ubyte; 591 592 #if LLT_CONFIG == 1 593 maxpage = 255; 594 txpktbuf_bndy = 252; 595 #elif LLT_CONFIG == 2 596 maxpage = 127; 597 txpktbuf_bndy = 124; 598 #elif LLT_CONFIG == 3 599 maxpage = 255; 600 txpktbuf_bndy = 174; 601 #elif LLT_CONFIG == 4 602 maxpage = 255; 603 txpktbuf_bndy = 246; 604 #elif LLT_CONFIG == 5 605 maxpage = 255; 606 txpktbuf_bndy = 246; 607 #endif 608 609 rtl_write_byte(rtlpriv, REG_CR, 0x8B); 610 611 #if LLT_CONFIG == 1 612 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 613 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 614 #elif LLT_CONFIG == 2 615 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 616 #elif LLT_CONFIG == 3 617 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 618 #elif LLT_CONFIG == 4 619 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 620 #elif LLT_CONFIG == 5 621 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 622 623 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29); 624 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03); 625 #endif 626 627 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 628 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 629 630 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 631 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 632 633 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 634 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 635 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 636 637 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 638 status = _rtl8723e_llt_write(hw, i, i + 1); 639 if (true != status) 640 return status; 641 } 642 643 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 644 if (true != status) 645 return status; 646 647 for (i = txpktbuf_bndy; i < maxpage; i++) { 648 status = _rtl8723e_llt_write(hw, i, (i + 1)); 649 if (true != status) 650 return status; 651 } 652 653 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy); 654 if (true != status) 655 return status; 656 657 rtl_write_byte(rtlpriv, REG_CR, 0xff); 658 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3); 659 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7)); 660 661 return true; 662 } 663 664 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw) 665 { 666 struct rtl_priv *rtlpriv = rtl_priv(hw); 667 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 668 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 669 670 if (rtlpriv->rtlhal.up_first_time) 671 return; 672 673 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 674 rtl8723e_sw_led_on(hw, pled0); 675 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 676 rtl8723e_sw_led_on(hw, pled0); 677 else 678 rtl8723e_sw_led_off(hw, pled0); 679 } 680 681 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw) 682 { 683 struct rtl_priv *rtlpriv = rtl_priv(hw); 684 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 685 686 unsigned char bytetmp; 687 unsigned short wordtmp; 688 u16 retry = 0; 689 u16 tmpu2b; 690 bool mac_func_enable; 691 692 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 693 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 694 if (bytetmp == 0xFF) 695 mac_func_enable = true; 696 else 697 mac_func_enable = false; 698 699 /* HW Power on sequence */ 700 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 701 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW)) 702 return false; 703 704 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2); 705 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4)); 706 707 /* eMAC time out function enable, 0x369[7]=1 */ 708 bytetmp = rtl_read_byte(rtlpriv, 0x369); 709 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7)); 710 711 /* ePHY reg 0x1e bit[4]=1 using MDIO interface, 712 * we should do this before Enabling ASPM backdoor. 713 */ 714 do { 715 rtl_write_word(rtlpriv, 0x358, 0x5e); 716 udelay(100); 717 rtl_write_word(rtlpriv, 0x356, 0xc280); 718 rtl_write_word(rtlpriv, 0x354, 0xc290); 719 rtl_write_word(rtlpriv, 0x358, 0x3e); 720 udelay(100); 721 rtl_write_word(rtlpriv, 0x358, 0x5e); 722 udelay(100); 723 tmpu2b = rtl_read_word(rtlpriv, 0x356); 724 retry++; 725 } while (tmpu2b != 0xc290 && retry < 100); 726 727 if (retry >= 100) { 728 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 729 "InitMAC(): ePHY configure fail!!!\n"); 730 return false; 731 } 732 733 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 734 rtl_write_word(rtlpriv, REG_CR + 1, 0x06); 735 736 if (!mac_func_enable) { 737 if (!_rtl8723e_llt_table_init(hw)) 738 return false; 739 } 740 741 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 742 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 743 744 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 745 746 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 747 wordtmp &= 0xf; 748 wordtmp |= 0xF771; 749 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 750 751 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 752 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 753 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 754 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 755 756 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 757 758 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 759 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 760 DMA_BIT_MASK(32)); 761 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 762 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 763 DMA_BIT_MASK(32)); 764 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 765 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 766 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 767 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 768 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 769 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 770 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 771 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 772 rtl_write_dword(rtlpriv, REG_HQ_DESA, 773 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 774 DMA_BIT_MASK(32)); 775 rtl_write_dword(rtlpriv, REG_RX_DESA, 776 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 777 DMA_BIT_MASK(32)); 778 779 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74); 780 781 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 782 783 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 784 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 785 do { 786 retry++; 787 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 788 } while ((retry < 200) && (bytetmp & BIT(7))); 789 790 _rtl8723e_gen_refresh_led_state(hw); 791 792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 793 794 return true; 795 } 796 797 static void _rtl8723e_hw_configure(struct ieee80211_hw *hw) 798 { 799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 800 struct rtl_priv *rtlpriv = rtl_priv(hw); 801 u8 reg_bw_opmode; 802 u32 reg_prsr; 803 804 reg_bw_opmode = BW_OPMODE_20MHZ; 805 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 806 807 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 808 809 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 810 811 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 812 813 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 814 815 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 816 817 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 818 819 rtl_write_word(rtlpriv, REG_RL, 0x0707); 820 821 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 822 823 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 824 825 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 826 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 827 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 828 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 829 830 if ((rtlpriv->btcoexist.bt_coexistence) && 831 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 832 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 833 else 834 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 835 836 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 837 838 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 839 840 rtlpci->reg_bcn_ctrl_val = 0x1f; 841 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 842 843 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 844 845 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 846 847 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 848 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 849 850 if ((rtlpriv->btcoexist.bt_coexistence) && 851 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) { 852 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 853 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 854 } else { 855 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 856 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 857 } 858 859 if ((rtlpriv->btcoexist.bt_coexistence) && 860 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 861 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 862 else 863 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 864 865 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 866 867 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 868 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 869 870 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 871 872 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 873 874 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 875 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 876 877 rtl_write_dword(rtlpriv, 0x394, 0x1); 878 } 879 880 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw) 881 { 882 struct rtl_priv *rtlpriv = rtl_priv(hw); 883 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 884 885 rtl_write_byte(rtlpriv, 0x34b, 0x93); 886 rtl_write_word(rtlpriv, 0x350, 0x870c); 887 rtl_write_byte(rtlpriv, 0x352, 0x1); 888 889 if (ppsc->support_backdoor) 890 rtl_write_byte(rtlpriv, 0x349, 0x1b); 891 else 892 rtl_write_byte(rtlpriv, 0x349, 0x03); 893 894 rtl_write_word(rtlpriv, 0x350, 0x2718); 895 rtl_write_byte(rtlpriv, 0x352, 0x1); 896 } 897 898 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw) 899 { 900 struct rtl_priv *rtlpriv = rtl_priv(hw); 901 u8 sec_reg_value; 902 903 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 904 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 905 rtlpriv->sec.pairwise_enc_algorithm, 906 rtlpriv->sec.group_enc_algorithm); 907 908 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 909 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 910 "not open hw encryption\n"); 911 return; 912 } 913 914 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 915 916 if (rtlpriv->sec.use_defaultkey) { 917 sec_reg_value |= SCR_TXUSEDK; 918 sec_reg_value |= SCR_RXUSEDK; 919 } 920 921 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 922 923 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 924 925 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 926 "The SECR-value %x\n", sec_reg_value); 927 928 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 929 930 } 931 932 int rtl8723e_hw_init(struct ieee80211_hw *hw) 933 { 934 struct rtl_priv *rtlpriv = rtl_priv(hw); 935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 936 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 937 struct rtl_phy *rtlphy = &(rtlpriv->phy); 938 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 939 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 940 bool rtstatus = true; 941 int err; 942 u8 tmp_u1b; 943 unsigned long flags; 944 945 rtlpriv->rtlhal.being_init_adapter = true; 946 /* As this function can take a very long time (up to 350 ms) 947 * and can be called with irqs disabled, reenable the irqs 948 * to let the other devices continue being serviced. 949 * 950 * It is safe doing so since our own interrupts will only be enabled 951 * in a subsequent step. 952 */ 953 local_save_flags(flags); 954 local_irq_enable(); 955 rtlhal->fw_ready = false; 956 957 rtlpriv->intf_ops->disable_aspm(hw); 958 rtstatus = _rtl8712e_init_mac(hw); 959 if (rtstatus != true) { 960 pr_err("Init MAC failed\n"); 961 err = 1; 962 goto exit; 963 } 964 965 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT); 966 if (err) { 967 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 968 "Failed to download FW. Init HW without FW now..\n"); 969 err = 1; 970 goto exit; 971 } 972 rtlhal->fw_ready = true; 973 974 rtlhal->last_hmeboxnum = 0; 975 rtl8723e_phy_mac_config(hw); 976 /* because last function modify RCR, so we update 977 * rcr var here, or TP will unstable for receive_config 978 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx 979 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 980 */ 981 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 982 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 983 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 984 985 rtl8723e_phy_bb_config(hw); 986 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 987 rtl8723e_phy_rf_config(hw); 988 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) { 989 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 990 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 991 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { 992 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 993 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 994 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 995 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 996 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 997 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 998 } 999 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1000 RF_CHNLBW, RFREG_OFFSET_MASK); 1001 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1002 RF_CHNLBW, RFREG_OFFSET_MASK); 1003 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1004 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1005 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1006 _rtl8723e_hw_configure(hw); 1007 rtl_cam_reset_all_entry(hw); 1008 rtl8723e_enable_hw_security_config(hw); 1009 1010 ppsc->rfpwr_state = ERFON; 1011 1012 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1013 _rtl8723e_enable_aspm_back_door(hw); 1014 rtlpriv->intf_ops->enable_aspm(hw); 1015 1016 rtl8723e_bt_hw_init(hw); 1017 1018 if (ppsc->rfpwr_state == ERFON) { 1019 rtl8723e_phy_set_rfpath_switch(hw, 1); 1020 if (rtlphy->iqk_initialized) { 1021 rtl8723e_phy_iq_calibrate(hw, true); 1022 } else { 1023 rtl8723e_phy_iq_calibrate(hw, false); 1024 rtlphy->iqk_initialized = true; 1025 } 1026 1027 rtl8723e_dm_check_txpower_tracking(hw); 1028 rtl8723e_phy_lc_calibrate(hw); 1029 } 1030 1031 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1032 if (!(tmp_u1b & BIT(0))) { 1033 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1034 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1035 } 1036 1037 if (!(tmp_u1b & BIT(4))) { 1038 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1039 tmp_u1b &= 0x0F; 1040 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1041 udelay(10); 1042 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1043 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1044 } 1045 rtl8723e_dm_init(hw); 1046 exit: 1047 local_irq_restore(flags); 1048 rtlpriv->rtlhal.being_init_adapter = false; 1049 return err; 1050 } 1051 1052 static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw) 1053 { 1054 struct rtl_priv *rtlpriv = rtl_priv(hw); 1055 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1056 enum version_8723e version = 0x0000; 1057 u32 value32; 1058 1059 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1060 if (value32 & TRP_VAUX_EN) { 1061 version = (enum version_8723e)(version | 1062 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1063 /* RTL8723 with BT function. */ 1064 version = (enum version_8723e)(version | 1065 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1066 1067 } else { 1068 /* Normal mass production chip. */ 1069 version = (enum version_8723e) NORMAL_CHIP; 1070 version = (enum version_8723e)(version | 1071 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1072 /* RTL8723 with BT function. */ 1073 version = (enum version_8723e)(version | 1074 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1075 if (IS_CHIP_VENDOR_UMC(version)) 1076 version = (enum version_8723e)(version | 1077 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */ 1078 if (IS_8723_SERIES(version)) { 1079 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS); 1080 /* ROM code version. */ 1081 version = (enum version_8723e)(version | 1082 ((value32 & RF_RL_ID)>>20)); 1083 } 1084 } 1085 1086 if (IS_8723_SERIES(version)) { 1087 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 1088 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ? 1089 RT_POLARITY_HIGH_ACT : 1090 RT_POLARITY_LOW_ACT); 1091 } 1092 switch (version) { 1093 case VERSION_TEST_UMC_CHIP_8723: 1094 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1095 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n"); 1096 break; 1097 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT: 1098 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1099 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n"); 1100 break; 1101 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT: 1102 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1103 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n"); 1104 break; 1105 default: 1106 pr_err("Chip Version ID: Unknown. Bug?\n"); 1107 break; 1108 } 1109 1110 if (IS_8723_SERIES(version)) 1111 rtlphy->rf_type = RF_1T1R; 1112 1113 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1114 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R"); 1115 1116 return version; 1117 } 1118 1119 static int _rtl8723e_set_media_status(struct ieee80211_hw *hw, 1120 enum nl80211_iftype type) 1121 { 1122 struct rtl_priv *rtlpriv = rtl_priv(hw); 1123 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1124 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1125 u8 mode = MSR_NOLINK; 1126 1127 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 1128 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 1129 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 1130 1131 switch (type) { 1132 case NL80211_IFTYPE_UNSPECIFIED: 1133 mode = MSR_NOLINK; 1134 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1135 "Set Network type to NO LINK!\n"); 1136 break; 1137 case NL80211_IFTYPE_ADHOC: 1138 mode = MSR_ADHOC; 1139 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1140 "Set Network type to Ad Hoc!\n"); 1141 break; 1142 case NL80211_IFTYPE_STATION: 1143 mode = MSR_INFRA; 1144 ledaction = LED_CTL_LINK; 1145 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1146 "Set Network type to STA!\n"); 1147 break; 1148 case NL80211_IFTYPE_AP: 1149 mode = MSR_AP; 1150 ledaction = LED_CTL_LINK; 1151 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1152 "Set Network type to AP!\n"); 1153 break; 1154 default: 1155 pr_err("Network type %d not support!\n", type); 1156 return 1; 1157 break; 1158 } 1159 1160 /* MSR_INFRA == Link in infrastructure network; 1161 * MSR_ADHOC == Link in ad hoc network; 1162 * Therefore, check link state is necessary. 1163 * 1164 * MSR_AP == AP mode; link state is not cared here. 1165 */ 1166 if (mode != MSR_AP && 1167 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1168 mode = MSR_NOLINK; 1169 ledaction = LED_CTL_NO_LINK; 1170 } 1171 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1172 _rtl8723e_stop_tx_beacon(hw); 1173 _rtl8723e_enable_bcn_sub_func(hw); 1174 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1175 _rtl8723e_resume_tx_beacon(hw); 1176 _rtl8723e_disable_bcn_sub_func(hw); 1177 } else { 1178 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1179 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1180 mode); 1181 } 1182 1183 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1184 rtlpriv->cfg->ops->led_control(hw, ledaction); 1185 if (mode == MSR_AP) 1186 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1187 else 1188 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1189 return 0; 1190 } 1191 1192 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1193 { 1194 struct rtl_priv *rtlpriv = rtl_priv(hw); 1195 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1196 u32 reg_rcr = rtlpci->receive_config; 1197 1198 if (rtlpriv->psc.rfpwr_state != ERFON) 1199 return; 1200 1201 if (check_bssid) { 1202 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1203 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1204 (u8 *)(®_rcr)); 1205 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1206 } else if (!check_bssid) { 1207 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1208 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); 1209 rtlpriv->cfg->ops->set_hw_reg(hw, 1210 HW_VAR_RCR, (u8 *)(®_rcr)); 1211 } 1212 } 1213 1214 int rtl8723e_set_network_type(struct ieee80211_hw *hw, 1215 enum nl80211_iftype type) 1216 { 1217 struct rtl_priv *rtlpriv = rtl_priv(hw); 1218 1219 if (_rtl8723e_set_media_status(hw, type)) 1220 return -EOPNOTSUPP; 1221 1222 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1223 if (type != NL80211_IFTYPE_AP) 1224 rtl8723e_set_check_bssid(hw, true); 1225 } else { 1226 rtl8723e_set_check_bssid(hw, false); 1227 } 1228 1229 return 0; 1230 } 1231 1232 /* don't set REG_EDCA_BE_PARAM here 1233 * because mac80211 will send pkt when scan 1234 */ 1235 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci) 1236 { 1237 struct rtl_priv *rtlpriv = rtl_priv(hw); 1238 1239 rtl8723_dm_init_edca_turbo(hw); 1240 switch (aci) { 1241 case AC1_BK: 1242 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1243 break; 1244 case AC0_BE: 1245 break; 1246 case AC2_VI: 1247 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1248 break; 1249 case AC3_VO: 1250 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1251 break; 1252 default: 1253 WARN_ONCE(true, "rtl8723ae: invalid aci: %d !\n", aci); 1254 break; 1255 } 1256 } 1257 1258 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw) 1259 { 1260 struct rtl_priv *rtlpriv = rtl_priv(hw); 1261 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1262 1263 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1264 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1265 rtlpci->irq_enabled = true; 1266 } 1267 1268 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw) 1269 { 1270 struct rtl_priv *rtlpriv = rtl_priv(hw); 1271 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1272 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED); 1273 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED); 1274 rtlpci->irq_enabled = false; 1275 /*synchronize_irq(rtlpci->pdev->irq);*/ 1276 } 1277 1278 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw) 1279 { 1280 struct rtl_priv *rtlpriv = rtl_priv(hw); 1281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1282 u8 u1b_tmp; 1283 1284 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1285 /* 1. Run LPS WL RFOFF flow */ 1286 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1287 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW); 1288 1289 /* 2. 0x1F[7:0] = 0 */ 1290 /* turn off RF */ 1291 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1292 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1293 rtlhal->fw_ready) { 1294 rtl8723ae_firmware_selfreset(hw); 1295 } 1296 1297 /* Reset MCU. Suggested by Filen. */ 1298 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1299 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1300 1301 /* g. MCUFWDL 0x80[1:0]=0 */ 1302 /* reset MCU ready status */ 1303 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1304 1305 /* HW card disable configuration. */ 1306 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1307 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW); 1308 1309 /* Reset MCU IO Wrapper */ 1310 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1311 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1312 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1313 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1314 1315 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1316 /* lock ISO/CLK/Power control register */ 1317 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1318 } 1319 1320 void rtl8723e_card_disable(struct ieee80211_hw *hw) 1321 { 1322 struct rtl_priv *rtlpriv = rtl_priv(hw); 1323 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1324 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1325 enum nl80211_iftype opmode; 1326 1327 mac->link_state = MAC80211_NOLINK; 1328 opmode = NL80211_IFTYPE_UNSPECIFIED; 1329 _rtl8723e_set_media_status(hw, opmode); 1330 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1331 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1332 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1333 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1334 _rtl8723e_poweroff_adapter(hw); 1335 1336 /* after power off we should do iqk again */ 1337 rtlpriv->phy.iqk_initialized = false; 1338 } 1339 1340 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw, 1341 struct rtl_int *intvec) 1342 { 1343 struct rtl_priv *rtlpriv = rtl_priv(hw); 1344 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1345 1346 intvec->inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0]; 1347 rtl_write_dword(rtlpriv, 0x3a0, intvec->inta); 1348 } 1349 1350 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw) 1351 { 1352 1353 struct rtl_priv *rtlpriv = rtl_priv(hw); 1354 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1355 u16 bcn_interval, atim_window; 1356 1357 bcn_interval = mac->beacon_interval; 1358 atim_window = 2; /*FIX MERGE */ 1359 rtl8723e_disable_interrupt(hw); 1360 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1361 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1362 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1363 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1364 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1365 rtl_write_byte(rtlpriv, 0x606, 0x30); 1366 rtl8723e_enable_interrupt(hw); 1367 } 1368 1369 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw) 1370 { 1371 struct rtl_priv *rtlpriv = rtl_priv(hw); 1372 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1373 u16 bcn_interval = mac->beacon_interval; 1374 1375 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1376 "beacon_interval:%d\n", bcn_interval); 1377 rtl8723e_disable_interrupt(hw); 1378 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1379 rtl8723e_enable_interrupt(hw); 1380 } 1381 1382 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw, 1383 u32 add_msr, u32 rm_msr) 1384 { 1385 struct rtl_priv *rtlpriv = rtl_priv(hw); 1386 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1387 1388 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1389 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1390 1391 if (add_msr) 1392 rtlpci->irq_mask[0] |= add_msr; 1393 if (rm_msr) 1394 rtlpci->irq_mask[0] &= (~rm_msr); 1395 rtl8723e_disable_interrupt(hw); 1396 rtl8723e_enable_interrupt(hw); 1397 } 1398 1399 static u8 _rtl8723e_get_chnl_group(u8 chnl) 1400 { 1401 u8 group; 1402 1403 if (chnl < 3) 1404 group = 0; 1405 else if (chnl < 9) 1406 group = 1; 1407 else 1408 group = 2; 1409 return group; 1410 } 1411 1412 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1413 bool autoload_fail, 1414 u8 *hwinfo) 1415 { 1416 struct rtl_priv *rtlpriv = rtl_priv(hw); 1417 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1418 u8 rf_path, index, tempval; 1419 u16 i; 1420 1421 for (rf_path = 0; rf_path < 1; rf_path++) { 1422 for (i = 0; i < 3; i++) { 1423 if (!autoload_fail) { 1424 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1425 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1426 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1427 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i]; 1428 } else { 1429 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1430 EEPROM_DEFAULT_TXPOWERLEVEL; 1431 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1432 EEPROM_DEFAULT_TXPOWERLEVEL; 1433 } 1434 } 1435 } 1436 1437 for (i = 0; i < 3; i++) { 1438 if (!autoload_fail) 1439 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1440 else 1441 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1442 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1443 (tempval & 0xf); 1444 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1445 ((tempval & 0xf0) >> 4); 1446 } 1447 1448 for (rf_path = 0; rf_path < 2; rf_path++) 1449 for (i = 0; i < 3; i++) 1450 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1451 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 1452 i, rtlefuse->eeprom_chnlarea_txpwr_cck 1453 [rf_path][i]); 1454 for (rf_path = 0; rf_path < 2; rf_path++) 1455 for (i = 0; i < 3; i++) 1456 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1457 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1458 rf_path, i, 1459 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1460 [rf_path][i]); 1461 for (rf_path = 0; rf_path < 2; rf_path++) 1462 for (i = 0; i < 3; i++) 1463 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1464 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1465 rf_path, i, 1466 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1467 [rf_path][i]); 1468 1469 for (rf_path = 0; rf_path < 2; rf_path++) { 1470 for (i = 0; i < 14; i++) { 1471 index = _rtl8723e_get_chnl_group((u8)i); 1472 1473 rtlefuse->txpwrlevel_cck[rf_path][i] = 1474 rtlefuse->eeprom_chnlarea_txpwr_cck 1475 [rf_path][index]; 1476 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1477 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1478 [rf_path][index]; 1479 1480 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1481 [rf_path][index] - 1482 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1483 [rf_path][index]) > 0) { 1484 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1485 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1486 [rf_path][index] - 1487 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1488 [rf_path][index]; 1489 } else { 1490 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1491 } 1492 } 1493 1494 for (i = 0; i < 14; i++) { 1495 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1496 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1497 rf_path, i, 1498 rtlefuse->txpwrlevel_cck[rf_path][i], 1499 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1500 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1501 } 1502 } 1503 1504 for (i = 0; i < 3; i++) { 1505 if (!autoload_fail) { 1506 rtlefuse->eeprom_pwrlimit_ht40[i] = 1507 hwinfo[EEPROM_TXPWR_GROUP + i]; 1508 rtlefuse->eeprom_pwrlimit_ht20[i] = 1509 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1510 } else { 1511 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1512 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1513 } 1514 } 1515 1516 for (rf_path = 0; rf_path < 2; rf_path++) { 1517 for (i = 0; i < 14; i++) { 1518 index = _rtl8723e_get_chnl_group((u8)i); 1519 1520 if (rf_path == RF90_PATH_A) { 1521 rtlefuse->pwrgroup_ht20[rf_path][i] = 1522 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf); 1523 rtlefuse->pwrgroup_ht40[rf_path][i] = 1524 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf); 1525 } else if (rf_path == RF90_PATH_B) { 1526 rtlefuse->pwrgroup_ht20[rf_path][i] = 1527 ((rtlefuse->eeprom_pwrlimit_ht20[index] & 1528 0xf0) >> 4); 1529 rtlefuse->pwrgroup_ht40[rf_path][i] = 1530 ((rtlefuse->eeprom_pwrlimit_ht40[index] & 1531 0xf0) >> 4); 1532 } 1533 1534 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1535 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i, 1536 rtlefuse->pwrgroup_ht20[rf_path][i]); 1537 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1538 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i, 1539 rtlefuse->pwrgroup_ht40[rf_path][i]); 1540 } 1541 } 1542 1543 for (i = 0; i < 14; i++) { 1544 index = _rtl8723e_get_chnl_group((u8)i); 1545 1546 if (!autoload_fail) 1547 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1548 else 1549 tempval = EEPROM_DEFAULT_HT20_DIFF; 1550 1551 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1552 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1553 ((tempval >> 4) & 0xF); 1554 1555 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1556 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1557 1558 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1559 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1560 1561 index = _rtl8723e_get_chnl_group((u8)i); 1562 1563 if (!autoload_fail) 1564 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1565 else 1566 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1567 1568 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1569 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1570 ((tempval >> 4) & 0xF); 1571 } 1572 1573 rtlefuse->legacy_ht_txpowerdiff = 1574 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1575 1576 for (i = 0; i < 14; i++) 1577 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1578 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1579 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1580 for (i = 0; i < 14; i++) 1581 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1582 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 1583 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1584 for (i = 0; i < 14; i++) 1585 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1586 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1587 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1588 for (i = 0; i < 14; i++) 1589 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1590 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 1591 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1592 1593 if (!autoload_fail) 1594 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1595 else 1596 rtlefuse->eeprom_regulatory = 0; 1597 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1598 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1599 1600 if (!autoload_fail) 1601 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1602 else 1603 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1604 1605 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1606 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1607 rtlefuse->eeprom_tssi[RF90_PATH_A], 1608 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1609 1610 if (!autoload_fail) 1611 tempval = hwinfo[EEPROM_THERMAL_METER]; 1612 else 1613 tempval = EEPROM_DEFAULT_THERMALMETER; 1614 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1615 1616 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1617 rtlefuse->apk_thermalmeterignore = true; 1618 1619 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1620 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1621 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1622 } 1623 1624 static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw, 1625 bool b_pseudo_test) 1626 { 1627 struct rtl_priv *rtlpriv = rtl_priv(hw); 1628 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1629 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1630 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1631 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1632 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1633 COUNTRY_CODE_WORLD_WIDE_13}; 1634 u8 *hwinfo; 1635 1636 if (b_pseudo_test) { 1637 /* need add */ 1638 return; 1639 } 1640 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1641 if (!hwinfo) 1642 return; 1643 1644 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1645 goto exit; 1646 1647 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 1648 hwinfo); 1649 1650 rtl8723e_read_bt_coexist_info_from_hwpg(hw, 1651 rtlefuse->autoload_failflag, hwinfo); 1652 1653 if (rtlhal->oem_id != RT_CID_DEFAULT) 1654 goto exit; 1655 1656 switch (rtlefuse->eeprom_oemid) { 1657 case EEPROM_CID_DEFAULT: 1658 switch (rtlefuse->eeprom_did) { 1659 case 0x8176: 1660 switch (rtlefuse->eeprom_svid) { 1661 case 0x10EC: 1662 switch (rtlefuse->eeprom_smid) { 1663 case 0x6151 ... 0x6152: 1664 case 0x6154 ... 0x6155: 1665 case 0x6177 ... 0x6180: 1666 case 0x7151 ... 0x7152: 1667 case 0x7154 ... 0x7155: 1668 case 0x7177 ... 0x7180: 1669 case 0x8151 ... 0x8152: 1670 case 0x8154 ... 0x8155: 1671 case 0x8181 ... 0x8182: 1672 case 0x8184 ... 0x8185: 1673 case 0x9151 ... 0x9152: 1674 case 0x9154 ... 0x9155: 1675 case 0x9181 ... 0x9182: 1676 case 0x9184 ... 0x9185: 1677 rtlhal->oem_id = RT_CID_TOSHIBA; 1678 break; 1679 case 0x6191 ... 0x6193: 1680 case 0x7191 ... 0x7193: 1681 case 0x8191 ... 0x8193: 1682 case 0x9191 ... 0x9193: 1683 rtlhal->oem_id = RT_CID_819X_SAMSUNG; 1684 break; 1685 case 0x8197: 1686 case 0x9196: 1687 rtlhal->oem_id = RT_CID_819X_CLEVO; 1688 break; 1689 case 0x8203: 1690 rtlhal->oem_id = RT_CID_819X_PRONETS; 1691 break; 1692 case 0x8195: 1693 case 0x9195: 1694 case 0x7194: 1695 case 0x8200 ... 0x8202: 1696 case 0x9200: 1697 rtlhal->oem_id = RT_CID_819X_LENOVO; 1698 break; 1699 } 1700 case 0x1025: 1701 rtlhal->oem_id = RT_CID_819X_ACER; 1702 break; 1703 case 0x1028: 1704 switch (rtlefuse->eeprom_smid) { 1705 case 0x8194: 1706 case 0x8198: 1707 case 0x9197 ... 0x9198: 1708 rtlhal->oem_id = RT_CID_819X_DELL; 1709 break; 1710 } 1711 break; 1712 case 0x103C: 1713 switch (rtlefuse->eeprom_smid) { 1714 case 0x1629: 1715 rtlhal->oem_id = RT_CID_819X_HP; 1716 } 1717 break; 1718 case 0x1A32: 1719 switch (rtlefuse->eeprom_smid) { 1720 case 0x2315: 1721 rtlhal->oem_id = RT_CID_819X_QMI; 1722 break; 1723 } 1724 break; 1725 case 0x1043: 1726 switch (rtlefuse->eeprom_smid) { 1727 case 0x84B5: 1728 rtlhal->oem_id = 1729 RT_CID_819X_EDIMAX_ASUS; 1730 } 1731 break; 1732 } 1733 break; 1734 case 0x8178: 1735 switch (rtlefuse->eeprom_svid) { 1736 case 0x10ec: 1737 switch (rtlefuse->eeprom_smid) { 1738 case 0x6181 ... 0x6182: 1739 case 0x6184 ... 0x6185: 1740 case 0x7181 ... 0x7182: 1741 case 0x7184 ... 0x7185: 1742 case 0x8181 ... 0x8182: 1743 case 0x8184 ... 0x8185: 1744 case 0x9181 ... 0x9182: 1745 case 0x9184 ... 0x9185: 1746 rtlhal->oem_id = RT_CID_TOSHIBA; 1747 break; 1748 case 0x8186: 1749 rtlhal->oem_id = 1750 RT_CID_819X_PRONETS; 1751 break; 1752 } 1753 break; 1754 case 0x1025: 1755 rtlhal->oem_id = RT_CID_819X_ACER; 1756 break; 1757 case 0x1043: 1758 switch (rtlefuse->eeprom_smid) { 1759 case 0x8486: 1760 rtlhal->oem_id = 1761 RT_CID_819X_EDIMAX_ASUS; 1762 } 1763 break; 1764 } 1765 break; 1766 } 1767 break; 1768 case EEPROM_CID_TOSHIBA: 1769 rtlhal->oem_id = RT_CID_TOSHIBA; 1770 break; 1771 case EEPROM_CID_CCX: 1772 rtlhal->oem_id = RT_CID_CCX; 1773 break; 1774 case EEPROM_CID_QMI: 1775 rtlhal->oem_id = RT_CID_819X_QMI; 1776 break; 1777 case EEPROM_CID_WHQL: 1778 break; 1779 default: 1780 rtlhal->oem_id = RT_CID_DEFAULT; 1781 break; 1782 } 1783 exit: 1784 kfree(hwinfo); 1785 } 1786 1787 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw) 1788 { 1789 struct rtl_priv *rtlpriv = rtl_priv(hw); 1790 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1791 1792 rtlpriv->ledctl.led_opendrain = true; 1793 switch (rtlhal->oem_id) { 1794 case RT_CID_819X_HP: 1795 rtlpriv->ledctl.led_opendrain = true; 1796 break; 1797 case RT_CID_819X_LENOVO: 1798 case RT_CID_DEFAULT: 1799 case RT_CID_TOSHIBA: 1800 case RT_CID_CCX: 1801 case RT_CID_819X_ACER: 1802 case RT_CID_WHQL: 1803 default: 1804 break; 1805 } 1806 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1807 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1808 } 1809 1810 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw) 1811 { 1812 struct rtl_priv *rtlpriv = rtl_priv(hw); 1813 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1814 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1815 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1816 u8 tmp_u1b; 1817 u32 value32; 1818 1819 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]); 1820 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 1821 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32); 1822 1823 rtlhal->version = _rtl8723e_read_chip_version(hw); 1824 1825 if (get_rf_type(rtlphy) == RF_1T1R) 1826 rtlpriv->dm.rfpath_rxenable[0] = true; 1827 else 1828 rtlpriv->dm.rfpath_rxenable[0] = 1829 rtlpriv->dm.rfpath_rxenable[1] = true; 1830 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1831 rtlhal->version); 1832 1833 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1834 if (tmp_u1b & BIT(4)) { 1835 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1836 rtlefuse->epromtype = EEPROM_93C46; 1837 } else { 1838 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1839 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1840 } 1841 if (tmp_u1b & BIT(5)) { 1842 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1843 rtlefuse->autoload_failflag = false; 1844 _rtl8723e_read_adapter_info(hw, false); 1845 } else { 1846 rtlefuse->autoload_failflag = true; 1847 _rtl8723e_read_adapter_info(hw, false); 1848 pr_err("Autoload ERR!!\n"); 1849 } 1850 _rtl8723e_hal_customized_behavior(hw); 1851 } 1852 1853 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw, 1854 struct ieee80211_sta *sta) 1855 { 1856 struct rtl_priv *rtlpriv = rtl_priv(hw); 1857 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1858 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1859 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1860 u32 ratr_value; 1861 u8 ratr_index = 0; 1862 u8 b_nmode = mac->ht_enable; 1863 u16 shortgi_rate; 1864 u32 tmp_ratr_value; 1865 u8 curtxbw_40mhz = mac->bw_40; 1866 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1867 1 : 0; 1868 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1869 1 : 0; 1870 enum wireless_mode wirelessmode = mac->mode; 1871 u32 ratr_mask; 1872 1873 if (rtlhal->current_bandtype == BAND_ON_5G) 1874 ratr_value = sta->supp_rates[1] << 4; 1875 else 1876 ratr_value = sta->supp_rates[0]; 1877 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1878 ratr_value = 0xfff; 1879 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1880 sta->ht_cap.mcs.rx_mask[0] << 12); 1881 switch (wirelessmode) { 1882 case WIRELESS_MODE_B: 1883 if (ratr_value & 0x0000000c) 1884 ratr_value &= 0x0000000d; 1885 else 1886 ratr_value &= 0x0000000f; 1887 break; 1888 case WIRELESS_MODE_G: 1889 ratr_value &= 0x00000FF5; 1890 break; 1891 case WIRELESS_MODE_N_24G: 1892 case WIRELESS_MODE_N_5G: 1893 b_nmode = 1; 1894 if (get_rf_type(rtlphy) == RF_1T2R || 1895 get_rf_type(rtlphy) == RF_1T1R) 1896 ratr_mask = 0x000ff005; 1897 else 1898 ratr_mask = 0x0f0ff005; 1899 1900 ratr_value &= ratr_mask; 1901 break; 1902 default: 1903 if (rtlphy->rf_type == RF_1T2R) 1904 ratr_value &= 0x000ff0ff; 1905 else 1906 ratr_value &= 0x0f0ff0ff; 1907 1908 break; 1909 } 1910 1911 if ((rtlpriv->btcoexist.bt_coexistence) && 1912 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 1913 (rtlpriv->btcoexist.bt_cur_state) && 1914 (rtlpriv->btcoexist.bt_ant_isolation) && 1915 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 1916 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 1917 ratr_value &= 0x0fffcfc0; 1918 else 1919 ratr_value &= 0x0FFFFFFF; 1920 1921 if (b_nmode && 1922 ((curtxbw_40mhz && curshortgi_40mhz) || 1923 (!curtxbw_40mhz && curshortgi_20mhz))) { 1924 ratr_value |= 0x10000000; 1925 tmp_ratr_value = (ratr_value >> 12); 1926 1927 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1928 if ((1 << shortgi_rate) & tmp_ratr_value) 1929 break; 1930 } 1931 1932 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1933 (shortgi_rate << 4) | (shortgi_rate); 1934 } 1935 1936 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1937 1938 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1939 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 1940 } 1941 1942 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw, 1943 struct ieee80211_sta *sta, 1944 u8 rssi_level, bool update_bw) 1945 { 1946 struct rtl_priv *rtlpriv = rtl_priv(hw); 1947 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1948 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1949 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1950 struct rtl_sta_info *sta_entry = NULL; 1951 u32 ratr_bitmap; 1952 u8 ratr_index; 1953 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 1954 ? 1 : 0; 1955 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1956 1 : 0; 1957 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1958 1 : 0; 1959 enum wireless_mode wirelessmode = 0; 1960 bool shortgi = false; 1961 u8 rate_mask[5]; 1962 u8 macid = 0; 1963 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 1964 1965 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1966 wirelessmode = sta_entry->wireless_mode; 1967 if (mac->opmode == NL80211_IFTYPE_STATION) 1968 curtxbw_40mhz = mac->bw_40; 1969 else if (mac->opmode == NL80211_IFTYPE_AP || 1970 mac->opmode == NL80211_IFTYPE_ADHOC) 1971 macid = sta->aid + 1; 1972 1973 if (rtlhal->current_bandtype == BAND_ON_5G) 1974 ratr_bitmap = sta->supp_rates[1] << 4; 1975 else 1976 ratr_bitmap = sta->supp_rates[0]; 1977 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1978 ratr_bitmap = 0xfff; 1979 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1980 sta->ht_cap.mcs.rx_mask[0] << 12); 1981 switch (wirelessmode) { 1982 case WIRELESS_MODE_B: 1983 ratr_index = RATR_INX_WIRELESS_B; 1984 if (ratr_bitmap & 0x0000000c) 1985 ratr_bitmap &= 0x0000000d; 1986 else 1987 ratr_bitmap &= 0x0000000f; 1988 break; 1989 case WIRELESS_MODE_G: 1990 ratr_index = RATR_INX_WIRELESS_GB; 1991 1992 if (rssi_level == 1) 1993 ratr_bitmap &= 0x00000f00; 1994 else if (rssi_level == 2) 1995 ratr_bitmap &= 0x00000ff0; 1996 else 1997 ratr_bitmap &= 0x00000ff5; 1998 break; 1999 case WIRELESS_MODE_A: 2000 ratr_index = RATR_INX_WIRELESS_G; 2001 ratr_bitmap &= 0x00000ff0; 2002 break; 2003 case WIRELESS_MODE_N_24G: 2004 case WIRELESS_MODE_N_5G: 2005 ratr_index = RATR_INX_WIRELESS_NGB; 2006 if (rtlphy->rf_type == RF_1T2R || 2007 rtlphy->rf_type == RF_1T1R) { 2008 if (curtxbw_40mhz) { 2009 if (rssi_level == 1) 2010 ratr_bitmap &= 0x000f0000; 2011 else if (rssi_level == 2) 2012 ratr_bitmap &= 0x000ff000; 2013 else 2014 ratr_bitmap &= 0x000ff015; 2015 } else { 2016 if (rssi_level == 1) 2017 ratr_bitmap &= 0x000f0000; 2018 else if (rssi_level == 2) 2019 ratr_bitmap &= 0x000ff000; 2020 else 2021 ratr_bitmap &= 0x000ff005; 2022 } 2023 } else { 2024 if (curtxbw_40mhz) { 2025 if (rssi_level == 1) 2026 ratr_bitmap &= 0x0f0f0000; 2027 else if (rssi_level == 2) 2028 ratr_bitmap &= 0x0f0ff000; 2029 else 2030 ratr_bitmap &= 0x0f0ff015; 2031 } else { 2032 if (rssi_level == 1) 2033 ratr_bitmap &= 0x0f0f0000; 2034 else if (rssi_level == 2) 2035 ratr_bitmap &= 0x0f0ff000; 2036 else 2037 ratr_bitmap &= 0x0f0ff005; 2038 } 2039 } 2040 2041 if ((curtxbw_40mhz && curshortgi_40mhz) || 2042 (!curtxbw_40mhz && curshortgi_20mhz)) { 2043 if (macid == 0) 2044 shortgi = true; 2045 else if (macid == 1) 2046 shortgi = false; 2047 } 2048 break; 2049 default: 2050 ratr_index = RATR_INX_WIRELESS_NGB; 2051 2052 if (rtlphy->rf_type == RF_1T2R) 2053 ratr_bitmap &= 0x000ff0ff; 2054 else 2055 ratr_bitmap &= 0x0f0ff0ff; 2056 break; 2057 } 2058 sta_entry->ratr_index = ratr_index; 2059 2060 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2061 "ratr_bitmap :%x\n", ratr_bitmap); 2062 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2063 (ratr_index << 28); 2064 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2065 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2066 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n", 2067 ratr_index, ratr_bitmap, 2068 rate_mask[0], rate_mask[1], 2069 rate_mask[2], rate_mask[3], 2070 rate_mask[4]); 2071 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2072 } 2073 2074 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw, 2075 struct ieee80211_sta *sta, u8 rssi_level, 2076 bool update_bw) 2077 { 2078 struct rtl_priv *rtlpriv = rtl_priv(hw); 2079 2080 if (rtlpriv->dm.useramask) 2081 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2082 else 2083 rtl8723e_update_hal_rate_table(hw, sta); 2084 } 2085 2086 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw) 2087 { 2088 struct rtl_priv *rtlpriv = rtl_priv(hw); 2089 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2090 u16 sifs_timer; 2091 2092 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); 2093 if (!mac->ht_enable) 2094 sifs_timer = 0x0a0a; 2095 else 2096 sifs_timer = 0x1010; 2097 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2098 } 2099 2100 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2101 { 2102 struct rtl_priv *rtlpriv = rtl_priv(hw); 2103 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2104 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2105 enum rf_pwrstate e_rfpowerstate_toset; 2106 u8 u1tmp; 2107 bool b_actuallyset = false; 2108 2109 if (rtlpriv->rtlhal.being_init_adapter) 2110 return false; 2111 2112 if (ppsc->swrf_processing) 2113 return false; 2114 2115 spin_lock(&rtlpriv->locks.rf_ps_lock); 2116 if (ppsc->rfchange_inprogress) { 2117 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2118 return false; 2119 } else { 2120 ppsc->rfchange_inprogress = true; 2121 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2122 } 2123 2124 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 2125 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1))); 2126 2127 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 2128 2129 if (rtlphy->polarity_ctl) 2130 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 2131 else 2132 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 2133 2134 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2135 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2136 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2137 2138 e_rfpowerstate_toset = ERFON; 2139 ppsc->hwradiooff = false; 2140 b_actuallyset = true; 2141 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2142 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2143 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2144 2145 e_rfpowerstate_toset = ERFOFF; 2146 ppsc->hwradiooff = true; 2147 b_actuallyset = true; 2148 } 2149 2150 if (b_actuallyset) { 2151 spin_lock(&rtlpriv->locks.rf_ps_lock); 2152 ppsc->rfchange_inprogress = false; 2153 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2154 } else { 2155 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2156 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2157 2158 spin_lock(&rtlpriv->locks.rf_ps_lock); 2159 ppsc->rfchange_inprogress = false; 2160 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2161 } 2162 2163 *valid = 1; 2164 return !ppsc->hwradiooff; 2165 2166 } 2167 2168 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index, 2169 u8 *p_macaddr, bool is_group, u8 enc_algo, 2170 bool is_wepkey, bool clear_all) 2171 { 2172 struct rtl_priv *rtlpriv = rtl_priv(hw); 2173 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2174 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2175 u8 *macaddr = p_macaddr; 2176 u32 entry_id = 0; 2177 bool is_pairwise = false; 2178 2179 static u8 cam_const_addr[4][6] = { 2180 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2181 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2182 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2183 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2184 }; 2185 static u8 cam_const_broad[] = { 2186 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2187 }; 2188 2189 if (clear_all) { 2190 u8 idx = 0; 2191 u8 cam_offset = 0; 2192 u8 clear_number = 5; 2193 2194 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2195 2196 for (idx = 0; idx < clear_number; idx++) { 2197 rtl_cam_mark_invalid(hw, cam_offset + idx); 2198 rtl_cam_empty_entry(hw, cam_offset + idx); 2199 2200 if (idx < 5) { 2201 memset(rtlpriv->sec.key_buf[idx], 0, 2202 MAX_KEY_LEN); 2203 rtlpriv->sec.key_len[idx] = 0; 2204 } 2205 } 2206 2207 } else { 2208 switch (enc_algo) { 2209 case WEP40_ENCRYPTION: 2210 enc_algo = CAM_WEP40; 2211 break; 2212 case WEP104_ENCRYPTION: 2213 enc_algo = CAM_WEP104; 2214 break; 2215 case TKIP_ENCRYPTION: 2216 enc_algo = CAM_TKIP; 2217 break; 2218 case AESCCMP_ENCRYPTION: 2219 enc_algo = CAM_AES; 2220 break; 2221 default: 2222 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 2223 "switch case %#x not processed\n", enc_algo); 2224 enc_algo = CAM_TKIP; 2225 break; 2226 } 2227 2228 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2229 macaddr = cam_const_addr[key_index]; 2230 entry_id = key_index; 2231 } else { 2232 if (is_group) { 2233 macaddr = cam_const_broad; 2234 entry_id = key_index; 2235 } else { 2236 if (mac->opmode == NL80211_IFTYPE_AP) { 2237 entry_id = 2238 rtl_cam_get_free_entry(hw, p_macaddr); 2239 if (entry_id >= TOTAL_CAM_ENTRY) { 2240 pr_err("Can not find free hw security cam entry\n"); 2241 return; 2242 } 2243 } else { 2244 entry_id = CAM_PAIRWISE_KEY_POSITION; 2245 } 2246 2247 key_index = PAIRWISE_KEYIDX; 2248 is_pairwise = true; 2249 } 2250 } 2251 2252 if (rtlpriv->sec.key_len[key_index] == 0) { 2253 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2254 "delete one entry, entry_id is %d\n", 2255 entry_id); 2256 if (mac->opmode == NL80211_IFTYPE_AP) 2257 rtl_cam_del_entry(hw, p_macaddr); 2258 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2259 } else { 2260 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2261 "add one entry\n"); 2262 if (is_pairwise) { 2263 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2264 "set Pairwise key\n"); 2265 2266 rtl_cam_add_one_entry(hw, macaddr, key_index, 2267 entry_id, enc_algo, 2268 CAM_CONFIG_NO_USEDK, 2269 rtlpriv->sec.key_buf[key_index]); 2270 } else { 2271 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2272 "set group key\n"); 2273 2274 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2275 rtl_cam_add_one_entry(hw, 2276 rtlefuse->dev_addr, 2277 PAIRWISE_KEYIDX, 2278 CAM_PAIRWISE_KEY_POSITION, 2279 enc_algo, 2280 CAM_CONFIG_NO_USEDK, 2281 rtlpriv->sec.key_buf 2282 [entry_id]); 2283 } 2284 2285 rtl_cam_add_one_entry(hw, macaddr, key_index, 2286 entry_id, enc_algo, 2287 CAM_CONFIG_NO_USEDK, 2288 rtlpriv->sec.key_buf[entry_id]); 2289 } 2290 2291 } 2292 } 2293 } 2294 2295 static void rtl8723e_bt_var_init(struct ieee80211_hw *hw) 2296 { 2297 struct rtl_priv *rtlpriv = rtl_priv(hw); 2298 2299 rtlpriv->btcoexist.bt_coexistence = 2300 rtlpriv->btcoexist.eeprom_bt_coexist; 2301 rtlpriv->btcoexist.bt_ant_num = 2302 rtlpriv->btcoexist.eeprom_bt_ant_num; 2303 rtlpriv->btcoexist.bt_coexist_type = 2304 rtlpriv->btcoexist.eeprom_bt_type; 2305 2306 rtlpriv->btcoexist.bt_ant_isolation = 2307 rtlpriv->btcoexist.eeprom_bt_ant_isol; 2308 2309 rtlpriv->btcoexist.bt_radio_shared_type = 2310 rtlpriv->btcoexist.eeprom_bt_radio_shared; 2311 2312 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2313 "BT Coexistence = 0x%x\n", 2314 rtlpriv->btcoexist.bt_coexistence); 2315 2316 if (rtlpriv->btcoexist.bt_coexistence) { 2317 rtlpriv->btcoexist.bt_busy_traffic = false; 2318 rtlpriv->btcoexist.bt_traffic_mode_set = false; 2319 rtlpriv->btcoexist.bt_non_traffic_mode_set = false; 2320 2321 rtlpriv->btcoexist.cstate = 0; 2322 rtlpriv->btcoexist.previous_state = 0; 2323 2324 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) { 2325 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2326 "BlueTooth BT_Ant_Num = Antx2\n"); 2327 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) { 2328 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2329 "BlueTooth BT_Ant_Num = Antx1\n"); 2330 } 2331 switch (rtlpriv->btcoexist.bt_coexist_type) { 2332 case BT_2WIRE: 2333 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2334 "BlueTooth BT_CoexistType = BT_2Wire\n"); 2335 break; 2336 case BT_ISSC_3WIRE: 2337 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2338 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n"); 2339 break; 2340 case BT_ACCEL: 2341 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2342 "BlueTooth BT_CoexistType = BT_ACCEL\n"); 2343 break; 2344 case BT_CSR_BC4: 2345 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2346 "BlueTooth BT_CoexistType = BT_CSR_BC4\n"); 2347 break; 2348 case BT_CSR_BC8: 2349 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2350 "BlueTooth BT_CoexistType = BT_CSR_BC8\n"); 2351 break; 2352 case BT_RTL8756: 2353 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2354 "BlueTooth BT_CoexistType = BT_RTL8756\n"); 2355 break; 2356 default: 2357 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2358 "BlueTooth BT_CoexistType = Unknown\n"); 2359 break; 2360 } 2361 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2362 "BlueTooth BT_Ant_isolation = %d\n", 2363 rtlpriv->btcoexist.bt_ant_isolation); 2364 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2365 "BT_RadioSharedType = 0x%x\n", 2366 rtlpriv->btcoexist.bt_radio_shared_type); 2367 rtlpriv->btcoexist.bt_active_zero_cnt = 0; 2368 rtlpriv->btcoexist.cur_bt_disabled = false; 2369 rtlpriv->btcoexist.pre_bt_disabled = false; 2370 } 2371 } 2372 2373 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2374 bool auto_load_fail, u8 *hwinfo) 2375 { 2376 struct rtl_priv *rtlpriv = rtl_priv(hw); 2377 u8 value; 2378 u32 tmpu_32; 2379 2380 if (!auto_load_fail) { 2381 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2382 if (tmpu_32 & BIT(18)) 2383 rtlpriv->btcoexist.eeprom_bt_coexist = 1; 2384 else 2385 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2386 value = hwinfo[RF_OPTION4]; 2387 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A; 2388 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1); 2389 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); 2390 rtlpriv->btcoexist.eeprom_bt_radio_shared = 2391 ((value & 0x20) >> 5); 2392 } else { 2393 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2394 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A; 2395 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2; 2396 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; 2397 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2398 } 2399 2400 rtl8723e_bt_var_init(hw); 2401 } 2402 2403 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw) 2404 { 2405 struct rtl_priv *rtlpriv = rtl_priv(hw); 2406 2407 /* 0:Low, 1:High, 2:From Efuse. */ 2408 rtlpriv->btcoexist.reg_bt_iso = 2; 2409 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2410 rtlpriv->btcoexist.reg_bt_sco = 3; 2411 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2412 rtlpriv->btcoexist.reg_bt_sco = 0; 2413 } 2414 2415 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw) 2416 { 2417 struct rtl_priv *rtlpriv = rtl_priv(hw); 2418 2419 if (rtlpriv->cfg->ops->get_btc_status()) 2420 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2421 } 2422 2423 void rtl8723e_suspend(struct ieee80211_hw *hw) 2424 { 2425 } 2426 2427 void rtl8723e_resume(struct ieee80211_hw *hw) 2428 { 2429 } 2430